1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <clk/sunxi.h>
12#include <dt-bindings/clock/sun8i-v3s-ccu.h>
13#include <dt-bindings/reset/sun8i-v3s-ccu.h>
14#include <linux/bitops.h>
15
16static struct ccu_clk_gate v3s_gates[] = {
17	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
18	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
19	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
20	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
21	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
22
23	[CLK_BUS_TCON0]		= GATE(0x064, BIT(4)),
24	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
25
26	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
27
28	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
29	[CLK_BUS_I2C1]		= GATE(0x06c, BIT(1)),
30	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
31	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
32	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
33
34	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
35
36	[CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
37
38	[CLK_DE]		= GATE(0x104, BIT(31)),
39	[CLK_TCON0]		= GATE(0x118, BIT(31)),
40};
41
42static struct ccu_reset v3s_resets[] = {
43	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
44
45	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
46	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
47	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
48	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
49	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
50
51	[RST_BUS_TCON0]		= RESET(0x2c4, BIT(4)),
52	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
53
54	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
55	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
56	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
57	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
58	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
59};
60
61const struct ccu_desc v3s_ccu_desc = {
62	.gates = v3s_gates,
63	.resets = v3s_resets,
64	.num_gates = ARRAY_SIZE(v3s_gates),
65	.num_resets = ARRAY_SIZE(v3s_resets),
66};
67