1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <clk/sunxi.h>
12#include <dt-bindings/clock/sun8i-h3-ccu.h>
13#include <dt-bindings/reset/sun8i-h3-ccu.h>
14#include <linux/bitops.h>
15
16static struct ccu_clk_gate h3_gates[] = {
17	[CLK_PLL_PERIPH0]	= GATE(0x028, BIT(31)),
18
19	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
20	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
21	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
22	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
23	[CLK_BUS_EMAC]		= GATE(0x060, BIT(17)),
24	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
25	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
26	[CLK_BUS_OTG]		= GATE(0x060, BIT(23)),
27	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(24)),
28	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(25)),
29	[CLK_BUS_EHCI2]		= GATE(0x060, BIT(26)),
30	[CLK_BUS_EHCI3]		= GATE(0x060, BIT(27)),
31	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(28)),
32	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(29)),
33	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(30)),
34	[CLK_BUS_OHCI3]		= GATE(0x060, BIT(31)),
35
36	[CLK_BUS_TCON0]		= GATE(0x064, BIT(3)),
37	[CLK_BUS_TCON1]		= GATE(0x064, BIT(4)),
38	[CLK_BUS_HDMI]		= GATE(0x064, BIT(11)),
39	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
40
41	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
42
43	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
44	[CLK_BUS_I2C1]		= GATE(0x06c, BIT(1)),
45	[CLK_BUS_I2C2]		= GATE(0x06c, BIT(2)),
46	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
47	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
48	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
49	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
50
51	[CLK_BUS_EPHY]		= GATE(0x070, BIT(0)),
52
53	[CLK_NAND]		= GATE(0x080, BIT(31)),
54	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
55	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
56
57	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
58	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
59	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),
60	[CLK_USB_PHY3]		= GATE(0x0cc, BIT(11)),
61	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
62	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
63	[CLK_USB_OHCI2]		= GATE(0x0cc, BIT(18)),
64	[CLK_USB_OHCI3]		= GATE(0x0cc, BIT(19)),
65
66	[CLK_DE]		= GATE(0x104, BIT(31)),
67	[CLK_TCON0]		= GATE(0x118, BIT(31)),
68
69	[CLK_HDMI]		= GATE(0x150, BIT(31)),
70	[CLK_HDMI_DDC]		= GATE(0x154, BIT(31)),
71};
72
73static struct ccu_reset h3_resets[] = {
74	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
75	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
76	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
77	[RST_USB_PHY3]		= RESET(0x0cc, BIT(3)),
78
79	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
80	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
81	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
82	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
83	[RST_BUS_EMAC]		= RESET(0x2c0, BIT(17)),
84	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
85	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
86	[RST_BUS_OTG]		= RESET(0x2c0, BIT(23)),
87	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(24)),
88	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(25)),
89	[RST_BUS_EHCI2]		= RESET(0x2c0, BIT(26)),
90	[RST_BUS_EHCI3]		= RESET(0x2c0, BIT(27)),
91	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(28)),
92	[RST_BUS_OHCI1]		= RESET(0x2c0, BIT(29)),
93	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(30)),
94	[RST_BUS_OHCI3]		= RESET(0x2c0, BIT(31)),
95
96	[RST_BUS_TCON0]		= RESET(0x2c4, BIT(3)),
97	[RST_BUS_TCON1]		= RESET(0x2c4, BIT(4)),
98	[RST_BUS_HDMI0]		= RESET(0x2c4, BIT(10)),
99	[RST_BUS_HDMI1]		= RESET(0x2c4, BIT(11)),
100	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
101
102	[RST_BUS_EPHY]		= RESET(0x2c8, BIT(2)),
103
104	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
105	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
106	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),
107	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
108	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
109	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
110	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
111};
112
113const struct ccu_desc h3_ccu_desc = {
114	.gates = h3_gates,
115	.resets = h3_resets,
116	.num_gates = ARRAY_SIZE(h3_gates),
117	.num_resets = ARRAY_SIZE(h3_resets),
118};
119