1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2018 Amarula Solutions. 4 * Author: Jagan Teki <jagan@amarulasolutions.com> 5 */ 6 7#include <common.h> 8#include <clk-uclass.h> 9#include <dm.h> 10#include <errno.h> 11#include <clk/sunxi.h> 12#include <dt-bindings/clock/sun50i-a64-ccu.h> 13#include <dt-bindings/reset/sun50i-a64-ccu.h> 14#include <linux/bitops.h> 15 16static const struct ccu_clk_gate a64_gates[] = { 17 [CLK_PLL_PERIPH0] = GATE(0x028, BIT(31)), 18 19 [CLK_BUS_MIPI_DSI] = GATE(0x060, BIT(1)), 20 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), 21 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), 22 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), 23 [CLK_BUS_NAND] = GATE(0x060, BIT(13)), 24 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), 25 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), 26 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), 27 [CLK_BUS_OTG] = GATE(0x060, BIT(23)), 28 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)), 29 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)), 30 [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)), 31 [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)), 32 33 [CLK_BUS_TCON0] = GATE(0x064, BIT(3)), 34 [CLK_BUS_TCON1] = GATE(0x064, BIT(4)), 35 [CLK_BUS_HDMI] = GATE(0x064, BIT(11)), 36 [CLK_BUS_DE] = GATE(0x064, BIT(12)), 37 38 [CLK_BUS_PIO] = GATE(0x068, BIT(5)), 39 40 [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), 41 [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), 42 [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), 43 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), 44 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), 45 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), 46 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)), 47 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)), 48 49 [CLK_NAND] = GATE(0x080, BIT(31)), 50 [CLK_SPI0] = GATE(0x0a0, BIT(31)), 51 [CLK_SPI1] = GATE(0x0a4, BIT(31)), 52 53 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), 54 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), 55 [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)), 56 [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)), 57 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)), 58 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)), 59 60 [CLK_DE] = GATE(0x104, BIT(31)), 61 [CLK_TCON0] = GATE(0x118, BIT(31)), 62 [CLK_TCON1] = GATE(0x11c, BIT(31)), 63 64 [CLK_HDMI] = GATE(0x150, BIT(31)), 65 [CLK_HDMI_DDC] = GATE(0x154, BIT(31)), 66 67 [CLK_DSI_DPHY] = GATE(0x168, BIT(15)), 68}; 69 70static const struct ccu_reset a64_resets[] = { 71 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), 72 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), 73 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)), 74 75 [RST_BUS_MIPI_DSI] = RESET(0x2c0, BIT(1)), 76 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), 77 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), 78 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), 79 [RST_BUS_NAND] = RESET(0x2c0, BIT(13)), 80 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)), 81 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), 82 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)), 83 [RST_BUS_OTG] = RESET(0x2c0, BIT(23)), 84 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)), 85 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)), 86 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)), 87 [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)), 88 89 [RST_BUS_TCON0] = RESET(0x2c4, BIT(3)), 90 [RST_BUS_TCON1] = RESET(0x2c4, BIT(4)), 91 [RST_BUS_HDMI0] = RESET(0x2c4, BIT(10)), 92 [RST_BUS_HDMI1] = RESET(0x2c4, BIT(11)), 93 [RST_BUS_DE] = RESET(0x2c4, BIT(12)), 94 95 [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), 96 [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), 97 [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), 98 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), 99 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), 100 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), 101 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)), 102 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)), 103}; 104 105const struct ccu_desc a64_ccu_desc = { 106 .gates = a64_gates, 107 .resets = a64_resets, 108 .num_gates = ARRAY_SIZE(a64_gates), 109 .num_resets = ARRAY_SIZE(a64_resets), 110}; 111