1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright 2019 NXP 4 * Peng Fan <peng.fan@nxp.com> 5 */ 6 7#include <common.h> 8#include <clk.h> 9#include <clk-uclass.h> 10#include <dm.h> 11#include <log.h> 12#include <asm/arch/clock.h> 13#include <asm/arch/imx-regs.h> 14#include <dt-bindings/clock/imx8mm-clock.h> 15 16#include "clk.h" 17 18static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", }; 19static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; 20static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; 21static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; 22static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; 23static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; 24 25static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", 26 "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; 27 28static const char *imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", 29 "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", }; 30 31#ifndef CONFIG_SPL_BUILD 32static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", 33 "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; 34 35static const char *imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", 36 "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", }; 37 38static const char *imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", 39 "clk_ext3", "clk_ext4", "video_pll1_out", }; 40 41static const char *imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m", 42 "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", }; 43#endif 44 45static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", 46 "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", }; 47 48static const char *imx8mm_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m", 49 "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; 50 51static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", 52 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; 53 54static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", 55 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; 56 57static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", 58 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; 59 60static const char *imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", 61 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; 62 63static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", 64 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; 65 66static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", 67 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; 68 69#if CONFIG_IS_ENABLED(PCIE_DW_IMX) 70static const char *imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m", 71 "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", }; 72 73static const char *imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2", 74 "clk_ext3", "clk_ext4", "sys_pll1_400m", }; 75 76static const char *imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out", 77 "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", }; 78#endif 79 80#ifndef CONFIG_SPL_BUILD 81static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", 82 "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; 83 84static const char *imx8mm_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", 85 "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; 86 87static const char *imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", 88 "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; 89 90static const char *imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", 91 "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; 92#endif 93 94static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out", 95 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; 96 97static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", 98 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", }; 99 100#if CONFIG_IS_ENABLED(NXP_FSPI) 101static const char *imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m", 102 "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; 103#endif 104 105static const char *imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", 106 "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; 107 108static const char *imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", 109 "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; 110 111#if CONFIG_IS_ENABLED(DM_SPI) 112static const char *imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", 113 "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; 114 115static const char *imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", 116 "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; 117 118static const char *imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", 119 "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; 120#endif 121 122static int imx8mm_clk_probe(struct udevice *dev) 123{ 124 void __iomem *base; 125 126 base = (void *)ANATOP_BASE_ADDR; 127 128 clk_dm(IMX8MM_DRAM_PLL_REF_SEL, 129 imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, 130 pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); 131 clk_dm(IMX8MM_ARM_PLL_REF_SEL, 132 imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, 133 pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); 134 clk_dm(IMX8MM_SYS_PLL1_REF_SEL, 135 imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, 136 pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); 137 clk_dm(IMX8MM_SYS_PLL2_REF_SEL, 138 imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, 139 pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); 140 clk_dm(IMX8MM_SYS_PLL3_REF_SEL, 141 imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, 142 pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); 143 144 clk_dm(IMX8MM_DRAM_PLL, 145 imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", 146 base + 0x50, &imx_1443x_dram_pll)); 147 clk_dm(IMX8MM_ARM_PLL, 148 imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", 149 base + 0x84, &imx_1416x_pll)); 150 clk_dm(IMX8MM_SYS_PLL1, 151 imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", 152 base + 0x94, &imx_1416x_pll)); 153 clk_dm(IMX8MM_SYS_PLL2, 154 imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", 155 base + 0x104, &imx_1416x_pll)); 156 clk_dm(IMX8MM_SYS_PLL3, 157 imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", 158 base + 0x114, &imx_1416x_pll)); 159 160 /* PLL bypass out */ 161 clk_dm(IMX8MM_DRAM_PLL_BYPASS, 162 imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, 163 dram_pll_bypass_sels, 164 ARRAY_SIZE(dram_pll_bypass_sels), 165 CLK_SET_RATE_PARENT)); 166 clk_dm(IMX8MM_ARM_PLL_BYPASS, 167 imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, 168 arm_pll_bypass_sels, 169 ARRAY_SIZE(arm_pll_bypass_sels), 170 CLK_SET_RATE_PARENT)); 171 clk_dm(IMX8MM_SYS_PLL1_BYPASS, 172 imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, 173 sys_pll1_bypass_sels, 174 ARRAY_SIZE(sys_pll1_bypass_sels), 175 CLK_SET_RATE_PARENT)); 176 clk_dm(IMX8MM_SYS_PLL2_BYPASS, 177 imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, 178 sys_pll2_bypass_sels, 179 ARRAY_SIZE(sys_pll2_bypass_sels), 180 CLK_SET_RATE_PARENT)); 181 clk_dm(IMX8MM_SYS_PLL3_BYPASS, 182 imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, 183 sys_pll3_bypass_sels, 184 ARRAY_SIZE(sys_pll3_bypass_sels), 185 CLK_SET_RATE_PARENT)); 186 187 /* PLL out gate */ 188 clk_dm(IMX8MM_DRAM_PLL_OUT, 189 imx_clk_gate("dram_pll_out", "dram_pll_bypass", 190 base + 0x50, 13)); 191 clk_dm(IMX8MM_ARM_PLL_OUT, 192 imx_clk_gate("arm_pll_out", "arm_pll_bypass", 193 base + 0x84, 11)); 194 clk_dm(IMX8MM_SYS_PLL1_OUT, 195 imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", 196 base + 0x94, 11)); 197 clk_dm(IMX8MM_SYS_PLL2_OUT, 198 imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", 199 base + 0x104, 11)); 200 clk_dm(IMX8MM_SYS_PLL3_OUT, 201 imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", 202 base + 0x114, 11)); 203 204 /* SYS PLL fixed output */ 205 clk_dm(IMX8MM_SYS_PLL1_40M, 206 imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20)); 207 clk_dm(IMX8MM_SYS_PLL1_80M, 208 imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10)); 209 clk_dm(IMX8MM_SYS_PLL1_100M, 210 imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8)); 211 clk_dm(IMX8MM_SYS_PLL1_133M, 212 imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6)); 213 clk_dm(IMX8MM_SYS_PLL1_160M, 214 imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5)); 215 clk_dm(IMX8MM_SYS_PLL1_200M, 216 imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4)); 217 clk_dm(IMX8MM_SYS_PLL1_266M, 218 imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3)); 219 clk_dm(IMX8MM_SYS_PLL1_400M, 220 imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2)); 221 clk_dm(IMX8MM_SYS_PLL1_800M, 222 imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1)); 223 224 clk_dm(IMX8MM_SYS_PLL2_50M, 225 imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20)); 226 clk_dm(IMX8MM_SYS_PLL2_100M, 227 imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10)); 228 clk_dm(IMX8MM_SYS_PLL2_125M, 229 imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8)); 230 clk_dm(IMX8MM_SYS_PLL2_166M, 231 imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6)); 232 clk_dm(IMX8MM_SYS_PLL2_200M, 233 imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5)); 234 clk_dm(IMX8MM_SYS_PLL2_250M, 235 imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4)); 236 clk_dm(IMX8MM_SYS_PLL2_333M, 237 imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3)); 238 clk_dm(IMX8MM_SYS_PLL2_500M, 239 imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2)); 240 clk_dm(IMX8MM_SYS_PLL2_1000M, 241 imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); 242 243 base = dev_read_addr_ptr(dev); 244 if (!base) 245 return -EINVAL; 246 247 clk_dm(IMX8MM_CLK_A53_SRC, 248 imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, 249 imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels))); 250 clk_dm(IMX8MM_CLK_A53_CG, 251 imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); 252 clk_dm(IMX8MM_CLK_A53_DIV, 253 imx_clk_divider2("arm_a53_div", "arm_a53_cg", 254 base + 0x8000, 0, 3)); 255 256 clk_dm(IMX8MM_CLK_AHB, 257 imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels, 258 base + 0x9000)); 259 clk_dm(IMX8MM_CLK_IPG_ROOT, 260 imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1)); 261 262 clk_dm(IMX8MM_CLK_NAND_USDHC_BUS, 263 imx8m_clk_composite_critical("nand_usdhc_bus", 264 imx8mm_nand_usdhc_sels, 265 base + 0x8900)); 266 clk_dm(IMX8MM_CLK_USB_BUS, 267 imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80)); 268 269 /* IP */ 270#if CONFIG_IS_ENABLED(PCIE_DW_IMX) 271 clk_dm(IMX8MM_CLK_PCIE1_CTRL, 272 imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels, 273 base + 0xa300)); 274 clk_dm(IMX8MM_CLK_PCIE1_PHY, 275 imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels, 276 base + 0xa380)); 277 clk_dm(IMX8MM_CLK_PCIE1_AUX, 278 imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels, 279 base + 0xa400)); 280#endif 281 clk_dm(IMX8MM_CLK_USDHC1, 282 imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels, 283 base + 0xac00)); 284 clk_dm(IMX8MM_CLK_USDHC2, 285 imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels, 286 base + 0xac80)); 287 clk_dm(IMX8MM_CLK_I2C1, 288 imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00)); 289 clk_dm(IMX8MM_CLK_I2C2, 290 imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80)); 291 clk_dm(IMX8MM_CLK_I2C3, 292 imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00)); 293 clk_dm(IMX8MM_CLK_I2C4, 294 imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80)); 295 clk_dm(IMX8MM_CLK_WDOG, 296 imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900)); 297 clk_dm(IMX8MM_CLK_USDHC3, 298 imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels, 299 base + 0xbc80)); 300 clk_dm(IMX8MM_CLK_USB_CORE_REF, 301 imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100)); 302 clk_dm(IMX8MM_CLK_USB_PHY_REF, 303 imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180)); 304 clk_dm(IMX8MM_CLK_I2C1_ROOT, 305 imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0)); 306 clk_dm(IMX8MM_CLK_I2C2_ROOT, 307 imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0)); 308 clk_dm(IMX8MM_CLK_I2C3_ROOT, 309 imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); 310 clk_dm(IMX8MM_CLK_I2C4_ROOT, 311 imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); 312 clk_dm(IMX8MM_CLK_OCOTP_ROOT, 313 imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0)); 314 clk_dm(IMX8MM_CLK_USDHC1_ROOT, 315 imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); 316 clk_dm(IMX8MM_CLK_USDHC2_ROOT, 317 imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); 318 clk_dm(IMX8MM_CLK_WDOG1_ROOT, 319 imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0)); 320 clk_dm(IMX8MM_CLK_WDOG2_ROOT, 321 imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0)); 322 clk_dm(IMX8MM_CLK_WDOG3_ROOT, 323 imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0)); 324 clk_dm(IMX8MM_CLK_USDHC3_ROOT, 325 imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); 326 clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT, 327 imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); 328 329 /* clks not needed in SPL stage */ 330#ifndef CONFIG_SPL_BUILD 331 clk_dm(IMX8MM_CLK_ENET_AXI, 332 imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels, 333 base + 0x8880)); 334 clk_dm(IMX8MM_CLK_ENET_REF, 335 imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels, 336 base + 0xa980)); 337 clk_dm(IMX8MM_CLK_ENET_TIMER, 338 imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels, 339 base + 0xaa00)); 340 clk_dm(IMX8MM_CLK_ENET_PHY_REF, 341 imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels, 342 base + 0xaa80)); 343 clk_dm(IMX8MM_CLK_ENET1_ROOT, 344 imx_clk_gate4("enet1_root_clk", "enet_axi", 345 base + 0x40a0, 0)); 346 clk_dm(IMX8MM_CLK_PWM1, 347 imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380)); 348 clk_dm(IMX8MM_CLK_PWM2, 349 imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400)); 350 clk_dm(IMX8MM_CLK_PWM3, 351 imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480)); 352 clk_dm(IMX8MM_CLK_PWM4, 353 imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500)); 354 clk_dm(IMX8MM_CLK_PWM1_ROOT, 355 imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0)); 356 clk_dm(IMX8MM_CLK_PWM2_ROOT, 357 imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0)); 358 clk_dm(IMX8MM_CLK_PWM3_ROOT, 359 imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0)); 360 clk_dm(IMX8MM_CLK_PWM4_ROOT, 361 imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0)); 362#endif 363 364#if CONFIG_IS_ENABLED(PCIE_DW_IMX) 365 clk_dm(IMX8MM_CLK_PCIE1_ROOT, 366 imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0)); 367#endif 368 369#if CONFIG_IS_ENABLED(DM_SPI) 370 clk_dm(IMX8MM_CLK_ECSPI1, 371 imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280)); 372 clk_dm(IMX8MM_CLK_ECSPI2, 373 imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300)); 374 clk_dm(IMX8MM_CLK_ECSPI3, 375 imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180)); 376 377 clk_dm(IMX8MM_CLK_ECSPI1_ROOT, 378 imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); 379 clk_dm(IMX8MM_CLK_ECSPI2_ROOT, 380 imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); 381 clk_dm(IMX8MM_CLK_ECSPI3_ROOT, 382 imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); 383#endif 384 385#if CONFIG_IS_ENABLED(NXP_FSPI) 386 clk_dm(IMX8MM_CLK_QSPI, 387 imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80)); 388 clk_dm(IMX8MM_CLK_QSPI_ROOT, 389 imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0)); 390#endif 391 392 return 0; 393} 394 395static const struct udevice_id imx8mm_clk_ids[] = { 396 { .compatible = "fsl,imx8mm-ccm" }, 397 { }, 398}; 399 400U_BOOT_DRIVER(imx8mm_clk) = { 401 .name = "clk_imx8mm", 402 .id = UCLASS_CLK, 403 .of_match = imx8mm_clk_ids, 404 .ops = &ccf_clk_ops, 405 .probe = imx8mm_clk_probe, 406 .flags = DM_FLAG_PRE_RELOC, 407}; 408