1/* SPDX-License-Identifier: BSD-3-Clause */ 2/* 3 * This file is part of the libpayload project. 4 * 5 * Copyright (C) 2008 Advanced Micro Devices, Inc. 6 */ 7 8#ifndef _COREBOOT_TABLES_H 9#define _COREBOOT_TABLES_H 10 11struct timestamp_entry { 12 u32 entry_id; 13 u64 entry_stamp; 14} __packed; 15 16struct timestamp_table { 17 u64 base_time; 18 u16 max_entries; 19 u16 tick_freq_mhz; 20 u32 num_entries; 21 struct timestamp_entry entries[0]; /* Variable number of entries */ 22} __packed; 23 24enum timestamp_id { 25 /* coreboot-specific timestamp IDs */ 26 TS_START_ROMSTAGE = 1, 27 TS_BEFORE_INITRAM = 2, 28 TS_AFTER_INITRAM = 3, 29 TS_END_ROMSTAGE = 4, 30 TS_START_VBOOT = 5, 31 TS_END_VBOOT = 6, 32 TS_START_COPYRAM = 8, 33 TS_END_COPYRAM = 9, 34 TS_START_RAMSTAGE = 10, 35 TS_START_BOOTBLOCK = 11, 36 TS_END_BOOTBLOCK = 12, 37 TS_START_COPYROM = 13, 38 TS_END_COPYROM = 14, 39 TS_START_ULZMA = 15, 40 TS_END_ULZMA = 16, 41 TS_START_ULZ4F = 17, 42 TS_END_ULZ4F = 18, 43 TS_DEVICE_ENUMERATE = 30, 44 TS_DEVICE_CONFIGURE = 40, 45 TS_DEVICE_ENABLE = 50, 46 TS_DEVICE_INITIALIZE = 60, 47 TS_DEVICE_DONE = 70, 48 TS_CBMEM_POST = 75, 49 TS_WRITE_TABLES = 80, 50 TS_FINALIZE_CHIPS = 85, 51 TS_LOAD_PAYLOAD = 90, 52 TS_ACPI_WAKE_JUMP = 98, 53 TS_SELFBOOT_JUMP = 99, 54 55 /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */ 56 TS_START_COPYVER = 501, 57 TS_END_COPYVER = 502, 58 TS_START_TPMINIT = 503, 59 TS_END_TPMINIT = 504, 60 TS_START_VERIFY_SLOT = 505, 61 TS_END_VERIFY_SLOT = 506, 62 TS_START_HASH_BODY = 507, 63 TS_DONE_LOADING = 508, 64 TS_DONE_HASHING = 509, 65 TS_END_HASH_BODY = 510, 66 TS_START_COPYVPD = 550, 67 TS_END_COPYVPD_RO = 551, 68 TS_END_COPYVPD_RW = 552, 69 70 /* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */ 71 TS_ME_INFORM_DRAM_WAIT = 940, 72 TS_ME_INFORM_DRAM_DONE = 941, 73 74 /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */ 75 TS_FSP_MEMORY_INIT_START = 950, 76 TS_FSP_MEMORY_INIT_END = 951, 77 TS_FSP_TEMP_RAM_EXIT_START = 952, 78 TS_FSP_TEMP_RAM_EXIT_END = 953, 79 TS_FSP_SILICON_INIT_START = 954, 80 TS_FSP_SILICON_INIT_END = 955, 81 TS_FSP_BEFORE_ENUMERATE = 956, 82 TS_FSP_AFTER_ENUMERATE = 957, 83 TS_FSP_BEFORE_FINALIZE = 958, 84 TS_FSP_AFTER_FINALIZE = 959, 85 TS_FSP_BEFORE_END_OF_FIRMWARE = 960, 86 TS_FSP_AFTER_END_OF_FIRMWARE = 961, 87 88 /* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */ 89 90 /* U-Boot entry IDs start at 1000 */ 91 TS_U_BOOT_INITTED = 1000, /* This is where U-Boot starts */ 92 93 TS_RO_PARAMS_INIT = 1001, 94 TS_RO_VB_INIT = 1002, 95 TS_RO_VB_SELECT_FIRMWARE = 1003, 96 TS_RO_VB_SELECT_AND_LOAD_KERNEL = 1004, 97 98 TS_RW_VB_SELECT_AND_LOAD_KERNEL = 1010, 99 100 TS_VB_SELECT_AND_LOAD_KERNEL = 1020, 101 TS_VB_EC_VBOOT_DONE = 1030, 102 TS_VB_STORAGE_INIT_DONE = 1040, 103 TS_VB_READ_KERNEL_DONE = 1050, 104 TS_VB_VBOOT_DONE = 1100, 105 106 TS_START_KERNEL = 1101, 107 TS_KERNEL_DECOMPRESSION = 1102, 108 TS_U_BOOT_START_KERNEL = 1100, /* Right before jumping to kernel */ 109}; 110 111struct memory_area; 112 113struct cbuint64 { 114 u32 lo; 115 u32 hi; 116}; 117 118struct cb_header { 119 u8 signature[4]; 120 u32 header_bytes; 121 u32 header_checksum; 122 u32 table_bytes; 123 u32 table_checksum; 124 u32 table_entries; 125}; 126 127struct cb_record { 128 u32 tag; 129 u32 size; 130}; 131 132#define CB_TAG_UNUSED 0x0000 133#define CB_TAG_MEMORY 0x0001 134 135struct cb_memory_range { 136 struct cbuint64 start; 137 struct cbuint64 size; 138 u32 type; 139}; 140 141#define CB_MEM_RAM 1 142#define CB_MEM_RESERVED 2 143#define CB_MEM_ACPI 3 144#define CB_MEM_NVS 4 145#define CB_MEM_UNUSABLE 5 146#define CB_MEM_VENDOR_RSVD 6 147#define CB_MEM_TABLE 16 148 149struct cb_memory { 150 u32 tag; 151 u32 size; 152 struct cb_memory_range map[0]; 153}; 154 155#define CB_TAG_HWRPB 0x0002 156 157struct cb_hwrpb { 158 u32 tag; 159 u32 size; 160 u64 hwrpb; 161}; 162 163#define CB_TAG_MAINBOARD 0x0003 164 165struct cb_mainboard { 166 u32 tag; 167 u32 size; 168 u8 vendor_idx; 169 u8 part_number_idx; 170 u8 strings[0]; 171}; 172 173#define CB_TAG_VERSION 0x0004 174#define CB_TAG_EXTRA_VERSION 0x0005 175#define CB_TAG_BUILD 0x0006 176#define CB_TAG_COMPILE_TIME 0x0007 177#define CB_TAG_COMPILE_BY 0x0008 178#define CB_TAG_COMPILE_HOST 0x0009 179#define CB_TAG_COMPILE_DOMAIN 0x000a 180#define CB_TAG_COMPILER 0x000b 181#define CB_TAG_LINKER 0x000c 182#define CB_TAG_ASSEMBLER 0x000d 183 184struct cb_string { 185 u32 tag; 186 u32 size; 187 u8 string[0]; 188}; 189 190#define CB_TAG_SERIAL 0x000f 191 192struct cb_serial { 193 u32 tag; 194 u32 size; 195#define CB_SERIAL_TYPE_IO_MAPPED 1 196#define CB_SERIAL_TYPE_MEMORY_MAPPED 2 197 u32 type; 198 u32 baseaddr; 199 u32 baud; 200 u32 regwidth; 201 202 /* 203 * Crystal or input frequency to the chip containing the UART. 204 * Provide the board specific details to allow the payload to 205 * initialize the chip containing the UART and make independent 206 * decisions as to which dividers to select and their values 207 * to eventually arrive at the desired console baud-rate. 208 */ 209 u32 input_hertz; 210 211 /* 212 * UART PCI address: bus, device, function 213 * 1 << 31 - Valid bit, PCI UART in use 214 * Bus << 20 215 * Device << 15 216 * Function << 12 217 */ 218 u32 uart_pci_addr; 219}; 220 221#define CB_TAG_CONSOLE 0x0010 222 223struct cb_console { 224 u32 tag; 225 u32 size; 226 u16 type; 227}; 228 229#define CB_TAG_CONSOLE_SERIAL8250 0 230#define CB_TAG_CONSOLE_VGA 1 /* OBSOLETE */ 231#define CB_TAG_CONSOLE_BTEXT 2 /* OBSOLETE */ 232#define CB_TAG_CONSOLE_LOGBUF 3 233#define CB_TAG_CONSOLE_SROM 4 /* OBSOLETE */ 234#define CB_TAG_CONSOLE_EHCI 5 235 236#define CB_TAG_FORWARD 0x0011 237 238struct cb_forward { 239 u32 tag; 240 u32 size; 241 u64 forward; 242}; 243 244#define CB_TAG_FRAMEBUFFER 0x0012 245 246struct cb_framebuffer { 247 u32 tag; 248 u32 size; 249 u64 physical_address; 250 u32 x_resolution; 251 u32 y_resolution; 252 u32 bytes_per_line; 253 u8 bits_per_pixel; 254 u8 red_mask_pos; 255 u8 red_mask_size; 256 u8 green_mask_pos; 257 u8 green_mask_size; 258 u8 blue_mask_pos; 259 u8 blue_mask_size; 260 u8 reserved_mask_pos; 261 u8 reserved_mask_size; 262}; 263 264#define CB_TAG_GPIO 0x0013 265#define CB_GPIO_ACTIVE_LOW 0 266#define CB_GPIO_ACTIVE_HIGH 1 267#define CB_GPIO_MAX_NAME_LENGTH 16 268struct cb_gpio { 269 u32 port; 270 u32 polarity; 271 u32 value; 272 u8 name[CB_GPIO_MAX_NAME_LENGTH]; 273}; 274 275struct cb_gpios { 276 u32 tag; 277 u32 size; 278 u32 count; 279 struct cb_gpio gpios[0]; 280}; 281 282#define CB_TAG_FDT 0x0014 283 284struct cb_fdt { 285 u32 tag; 286 u32 size; /* size of the entire entry */ 287 /* the actual FDT gets placed here */ 288}; 289 290#define CB_TAG_VDAT 0x0015 291 292struct cb_vdat { 293 u32 tag; 294 u32 size; /* size of the entire entry */ 295 void *vdat_addr; 296 u32 vdat_size; 297}; 298 299#define CB_TAG_TIMESTAMPS 0x0016 300#define CB_TAG_CBMEM_CONSOLE 0x0017 301 302#define CBMC_CURSOR_MASK ((1 << 28) - 1) 303#define CBMC_OVERFLOW BIT(31) 304 305/* 306 * struct cbmem_console - In-memory console buffer for coreboot 307 * 308 * Structure describing console buffer. It is overlaid on a flat memory area, 309 * with body covering the extent of the memory. Once the buffer is full, 310 * output will wrap back around to the start of the buffer. The high bit of the 311 * cursor field gets set to indicate that this happened. If the underlying 312 * storage allows this, the buffer will persist across multiple boots and append 313 * to the previous log. 314 */ 315struct cbmem_console { 316 u32 size; 317 u32 cursor; 318 u8 body[0]; 319}; 320 321#define CB_TAG_MRC_CACHE 0x0018 322 323struct cb_cbmem_tab { 324 u32 tag; 325 u32 size; 326 u64 cbmem_tab; 327}; 328 329#define CB_TAG_VBNV 0x0019 330 331struct cb_vbnv { 332 u32 tag; 333 u32 size; 334 u32 vbnv_start; 335 u32 vbnv_size; 336}; 337 338#define CB_TAG_VBOOT_HANDOFF 0x0020 339 340#define CB_TAG_X86_ROM_MTRR 0x0021 341struct cb_x86_rom_mtrr { 342 u32 tag; 343 u32 size; 344 /* 345 * The variable range MTRR index covering the ROM. If one wants to 346 * enable caching the ROM, the variable MTRR needs to be set to 347 * write-protect. To disable the caching after enabling set the 348 * type to uncacheable 349 */ 350 u32 index; 351}; 352 353#define CB_TAG_DMA 0x0022 354#define CB_TAG_RAM_OOPS 0x0023 355#define CB_TAG_ACPI_GNVS 0x0024 356 357#define CB_TAG_BOARD_ID 0x0025 358struct cb_board_id { 359 u32 tag; 360 u32 size; 361 /* Board ID as retrieved from the board revision GPIOs. */ 362 u32 board_id; 363}; 364 365#define CB_TAG_MAC_ADDRS 0x0026 366struct mac_address { 367 u8 mac_addr[6]; 368 u8 pad[2]; /* Pad it to 8 bytes to keep it simple. */ 369}; 370 371struct cb_macs { 372 u32 tag; 373 u32 size; 374 u32 count; 375 struct mac_address mac_addrs[0]; 376}; 377 378#define CB_TAG_WIFI_CALIBRATION 0x0027 379 380#define CB_TAG_RAM_CODE 0x0028 381struct cb_ram_code { 382 u32 tag; 383 u32 size; 384 u32 ram_code; 385}; 386 387#define CB_TAG_SPI_FLASH 0x0029 388struct cb_spi_flash { 389 u32 tag; 390 u32 size; 391 u32 flash_size; 392 u32 sector_size; 393 u32 erase_cmd; 394}; 395 396#define CB_TAG_MTC 0x002b 397#define CB_TAG_VPD 0x002c 398struct lb_range { 399 u32 tag; 400 u32 size; 401 u64 range_start; 402 u32 range_size; 403}; 404 405#define CB_TAG_BOOT_MEDIA_PARAMS 0x0030 406struct cb_boot_media_params { 407 u32 tag; 408 u32 size; 409 /* offsets are relative to start of boot media */ 410 u64 fmap_offset; 411 u64 cbfs_offset; 412 u64 cbfs_size; 413 u64 boot_media_size; 414}; 415 416#define CB_TAG_CBMEM_ENTRY 0x0031 417#define CBMEM_ID_SMBIOS 0x534d4254 418 419struct cb_cbmem_entry { 420 u32 tag; 421 u32 size; 422 u64 address; 423 u32 entry_size; 424 u32 id; 425}; 426 427#define CB_TAG_TSC_INFO 0x0032 428struct cb_tsc_info { 429 u32 tag; 430 u32 size; 431 432 u32 freq_khz; 433}; 434 435#define CB_TAG_SERIALNO 0x002a 436#define CB_MAX_SERIALNO_LENGTH 32 437 438#define CB_TAG_ACPI_RSDP 0x0043 439 440#define CB_TAG_CMOS_OPTION_TABLE 0x00c8 441 442struct cb_cmos_option_table { 443 u32 tag; 444 u32 size; 445 u32 header_length; 446 /* entries follow after this header */ 447}; 448 449#define CB_TAG_OPTION 0x00c9 450 451#define CB_CMOS_MAX_NAME_LENGTH 32 452 453struct cb_cmos_entries { 454 u32 tag; 455 u32 size; 456 u32 bit; 457 u32 length; 458 u32 config; 459 u32 config_id; 460 u8 name[CB_CMOS_MAX_NAME_LENGTH]; 461}; 462 463#define CB_TAG_OPTION_ENUM 0x00ca 464#define CB_CMOS_MAX_TEXT_LENGTH 32 465struct cb_cmos_enums { 466 u32 tag; 467 u32 size; 468 u32 config_id; 469 u32 value; 470 u8 text[CB_CMOS_MAX_TEXT_LENGTH]; 471}; 472 473#define CB_TAG_OPTION_DEFAULTS 0x00cb 474#define CB_CMOS_IMAGE_BUFFER_SIZE 128 475 476struct cb_cmos_defaults { 477 u32 tag; 478 u32 size; 479 u32 name_length; 480 u8 name[CB_CMOS_MAX_NAME_LENGTH]; 481 u8 default_set[CB_CMOS_IMAGE_BUFFER_SIZE]; 482}; 483 484#define CB_TAG_OPTION_CHECKSUM 0x00cc 485#define CB_CHECKSUM_NONE 0 486#define CB_CHECKSUM_PCBIOS 1 487 488struct cb_cmos_checksum { 489 u32 tag; 490 u32 size; 491 u32 range_start; 492 u32 range_end; 493 u32 location; 494 u32 type; 495}; 496 497/* Helpful macros */ 498 499#define MEM_RANGE_COUNT(_rec) \ 500 (((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0])) 501 502#define MEM_RANGE_PTR(_rec, _idx) \ 503 (((u8 *) (_rec)) + sizeof(*(_rec)) \ 504 + (sizeof((_rec)->map[0]) * (_idx))) 505 506#define MB_VENDOR_STRING(_mb) \ 507 (((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx) 508 509#define MB_PART_STRING(_mb) \ 510 (((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx) 511 512#define UNPACK_CB64(_in) \ 513 ((((u64) _in.hi) << 32) | _in.lo) 514 515#define CBMEM_TOC_RESERVED 512 516#define MAX_CBMEM_ENTRIES 16 517#define CBMEM_MAGIC 0x434f5245 518 519struct cbmem_entry { 520 u32 magic; 521 u32 id; 522 u64 base; 523 u64 size; 524} __packed; 525 526#define CBMEM_ID_FREESPACE 0x46524545 527#define CBMEM_ID_GDT 0x4c474454 528#define CBMEM_ID_ACPI 0x41435049 529#define CBMEM_ID_CBTABLE 0x43425442 530#define CBMEM_ID_PIRQ 0x49525154 531#define CBMEM_ID_MPTABLE 0x534d5054 532#define CBMEM_ID_RESUME 0x5245534d 533#define CBMEM_ID_RESUME_SCRATCH 0x52455343 534#define CBMEM_ID_SMBIOS 0x534d4254 535#define CBMEM_ID_TIMESTAMP 0x54494d45 536#define CBMEM_ID_MRCDATA 0x4d524344 537#define CBMEM_ID_CONSOLE 0x434f4e53 538#define CBMEM_ID_NONE 0x00000000 539 540/** 541 * high_table_reserve() - reserve configuration table in high memory 542 * 543 * This reserves configuration table in high memory. 544 * 545 * @return: always 0 546 */ 547int high_table_reserve(void); 548 549/** 550 * high_table_malloc() - allocate configuration table in high memory 551 * 552 * This allocates configuration table in high memory. 553 * 554 * @bytes: size of configuration table to be allocated 555 * @return: pointer to configuration table in high memory 556 */ 557void *high_table_malloc(size_t bytes); 558 559/** 560 * write_coreboot_table() - write coreboot table 561 * 562 * This writes coreboot table at a given address. 563 * 564 * @addr: start address to write coreboot table 565 * @cfg_tables: pointer to configuration table memory area 566 */ 567void write_coreboot_table(u32 addr, struct memory_area *cfg_tables); 568 569/** 570 * locate_coreboot_table() - Try to find coreboot tables at standard locations 571 * 572 * Return: address of table that was found, or -ve error number 573 */ 574long locate_coreboot_table(void); 575 576#endif 577