1/*
2 * (C) Copyright 2022 Arm Limited
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 */
6
7#ifndef _SUNXI_CPU_SUNXI_NCAT2_H
8#define _SUNXI_CPU_SUNXI_NCAT2_H
9
10#define SUNXI_CCM_BASE			0x02001000
11#define SUNXI_TIMER_BASE		0x02050000
12
13#define SUNXI_TWI0_BASE			0x02502000
14#define SUNXI_TWI1_BASE			0x02502400
15#define SUNXI_TWI2_BASE			0x02502800
16#define SUNXI_TWI3_BASE			0x02502C00
17
18#define SUNXI_SRAMC_BASE		0x03000000
19/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
20#define SUNXI_SIDC_BASE			0x03006000
21#define SUNXI_SID_BASE			0x03006200
22#define SUNXI_GIC400_BASE		0x03020000
23
24#define SUNXI_MMC0_BASE			0x04020000
25#define SUNXI_MMC1_BASE			0x04021000
26#define SUNXI_MMC2_BASE			0x04022000
27
28#define SUNXI_R_CPUCFG_BASE		0x07000400
29#define SUNXI_PRCM_BASE			0x07010000
30
31#define SUNXI_CPUCFG_BASE		0x09010000
32
33#ifndef __ASSEMBLY__
34void sunxi_board_init(void);
35void sunxi_reset(void);
36int sunxi_get_sid(unsigned int *sid);
37#endif
38
39#endif /* _SUNXI_CPU_SUNXI_NCAT2_H */
40