1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
4 * (C) Copyright 2007-2013
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Jerry Wang <wangflord@allwinnertech.com>
7 */
8
9#ifndef _SUNXI_CPU_SUN9I_H
10#define _SUNXI_CPU_SUN9I_H
11
12#define REGS_AHB0_BASE			0x01C00000
13#define REGS_AHB1_BASE			0x00800000
14#define REGS_AHB2_BASE			0x03000000
15#define REGS_APB0_BASE			0x06000000
16#define REGS_APB1_BASE			0x07000000
17#define REGS_RCPUS_BASE			0x08000000
18
19#define SUNXI_SRAM_D_BASE		0x08100000
20
21/* AHB0 Module */
22#define SUNXI_NFC_BASE			(REGS_AHB0_BASE + 0x3000)
23
24#define SUNXI_GTBUS_BASE		(REGS_AHB0_BASE + 0x9000)
25/* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */
26#define SUNXI_SID_BASE			(REGS_AHB0_BASE + 0xe200)
27
28#define SUNXI_MMC0_BASE			(REGS_AHB0_BASE + 0x0f000)
29#define SUNXI_MMC1_BASE			(REGS_AHB0_BASE + 0x10000)
30#define SUNXI_MMC2_BASE			(REGS_AHB0_BASE + 0x11000)
31#define SUNXI_MMC3_BASE			(REGS_AHB0_BASE + 0x12000)
32#define SUNXI_MMC_COMMON_BASE		(REGS_AHB0_BASE + 0x13000)
33
34#define SUNXI_GIC400_BASE		(REGS_AHB0_BASE + 0x40000)
35
36#define SUNXI_DRAM_COM_BASE		(REGS_AHB0_BASE + 0x62000)
37#define SUNXI_DRAM_CTL0_BASE		(REGS_AHB0_BASE + 0x63000)
38#define SUNXI_DRAM_CTL1_BASE		(REGS_AHB0_BASE + 0x64000)
39#define SUNXI_DRAM_PHY0_BASE		(REGS_AHB0_BASE + 0x65000)
40#define SUNXI_DRAM_PHY1_BASE		(REGS_AHB0_BASE + 0x66000)
41
42#define SUNXI_DE_FE0_BASE		(REGS_AHB2_BASE + 0x100000)
43#define SUNXI_DE_BE0_BASE		(REGS_AHB2_BASE + 0x200000)
44#define SUNXI_LCD0_BASE			(REGS_AHB2_BASE + 0xC00000)
45#define SUNXI_LCD1_BASE			(REGS_AHB2_BASE + 0xC10000)
46#define SUNXI_LCD2_BASE			(REGS_AHB2_BASE + 0xC20000)
47#define SUNXI_HDMI_BASE			(REGS_AHB2_BASE + 0xD00000)
48
49/* APB0 Module */
50#define SUNXI_CCM_BASE			(REGS_APB0_BASE + 0x0000)
51#define SUNXI_TIMER_BASE		(REGS_APB0_BASE + 0x0C00)
52#define SUNXI_PWM_BASE			(REGS_APB0_BASE + 0x1400)
53
54/* APB1 Module */
55#define SUNXI_TWI0_BASE			(REGS_APB1_BASE + 0x2800)
56#define SUNXI_TWI1_BASE			(REGS_APB1_BASE + 0x2C00)
57
58/* RCPUS Module */
59#define SUNXI_PRCM_BASE			(REGS_RCPUS_BASE + 0x1400)
60#define SUNXI_RSB_BASE			(REGS_RCPUS_BASE + 0x3400)
61
62#ifndef __ASSEMBLY__
63void sunxi_board_init(void);
64void sunxi_reset(void);
65int sunxi_get_sid(unsigned int *sid);
66#endif
67
68#endif /* _SUNXI_CPU_SUN9I_H */
69