1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 */
5
6#ifndef _ASM_ARCH_PCC_H
7#define _ASM_ARCH_PCC_H
8
9#include <asm/arch/scg.h>
10
11/* PCC2 */
12
13enum pcc2_entry {
14	/* On-Platform (32 entries) */
15	RSVD0_PCC2_SLOT			= 0,
16	RSVD1_PCC2_SLOT			= 1,
17	CA7_GIC_PCC2_SLOT		= 2,
18	RSVD3_PCC2_SLOT			= 3,
19	RSVD4_PCC2_SLOT			= 4,
20	RSVD5_PCC2_SLOT			= 5,
21	RSVD6_PCC2_SLOT			= 6,
22	RSVD7_PCC2_SLOT			= 7,
23	DMA1_PCC2_SLOT			= 8,
24	RSVD9_PCC2_SLOT			= 9,
25	RSVD10_PCC2_SLOT		= 10,
26	RSVD11_PCC2_SLOT		= 11,
27	RSVD12_PCC2_SLOT		= 12,
28	RSVD13_PCC2_SLOT		= 13,
29	RSVD14_PCC2_SLOT		= 14,
30	RGPIO1_PCC2_SLOT		= 15,
31	FLEXBUS0_PCC2_SLOT		= 16,
32	RSVD17_PCC2_SLOT		= 17,
33	RSVD18_PCC2_SLOT		= 18,
34	RSVD19_PCC2_SLOT		= 19,
35	RSVD20_PCC2_SLOT		= 20,
36	RSVD21_PCC2_SLOT		= 21,
37	RSVD22_PCC2_SLOT		= 22,
38	RSVD23_PCC2_SLOT		= 23,
39	RSVD24_PCC2_SLOT		= 24,
40	RSVD25_PCC2_SLOT		= 25,
41	RSVD26_PCC2_SLOT		= 26,
42	SEMA42_1_PCC2_SLOT		= 27,
43	RSVD28_PCC2_SLOT		= 28,
44	RSVD29_PCC2_SLOT		= 29,
45	RSVD30_PCC2_SLOT		= 30,
46	RSVD31_PCC2_SLOT		= 31,
47
48	/* Off-Platform (96 entries) */
49	RSVD32_PCC2_SLOT		= 32,
50	DMA1_CH_MUX0_PCC2_SLOT		= 33,
51	MU_B_PCC2_SLOT			= 34,
52	SNVS_PCC2_SLOT			= 35,
53	CAAM_PCC2_SLOT			= 36,
54	LPTPM4_PCC2_SLOT		= 37,
55	LPTPM5_PCC2_SLOT		= 38,
56	LPIT1_PCC2_SLOT			= 39,
57	RSVD40_PCC2_SLOT		= 40,
58	LPSPI2_PCC2_SLOT		= 41,
59	LPSPI3_PCC2_SLOT		= 42,
60	LPI2C4_PCC2_SLOT		= 43,
61	LPI2C5_PCC2_SLOT		= 44,
62	LPUART4_PCC2_SLOT		= 45,
63	LPUART5_PCC2_SLOT		= 46,
64	RSVD47_PCC2_SLOT		= 47,
65	RSVD48_PCC2_SLOT		= 48,
66	FLEXIO1_PCC2_SLOT		= 49,
67	RSVD50_PCC2_SLOT		= 50,
68	USBOTG0_PCC2_SLOT		= 51,
69	USBOTG1_PCC2_SLOT		= 52,
70	USBPHY_PCC2_SLOT		= 53,
71	USB_PL301_PCC2_SLOT		= 54,
72	USDHC0_PCC2_SLOT		= 55,
73	USDHC1_PCC2_SLOT		= 56,
74	RSVD57_PCC2_SLOT		= 57,
75	TRGMUX1_PCC2_SLOT		= 58,
76	RSVD59_PCC2_SLOT		= 59,
77	RSVD60_PCC2_SLOT		= 60,
78	WDG1_PCC2_SLOT			= 61,
79	SCG1_PCC2_SLOT			= 62,
80	PCC2_PCC2_SLOT			= 63,
81	PMC1_PCC2_SLOT			= 64,
82	SMC1_PCC2_SLOT			= 65,
83	RCM1_PCC2_SLOT			= 66,
84	WDG2_PCC2_SLOT			= 67,
85	RSVD68_PCC2_SLOT		= 68,
86	TEST_SPACE1_PCC2_SLOT		= 69,
87	TEST_SPACE2_PCC2_SLOT		= 70,
88	TEST_SPACE3_PCC2_SLOT		= 71,
89	RSVD72_PCC2_SLOT		= 72,
90	RSVD73_PCC2_SLOT		= 73,
91	RSVD74_PCC2_SLOT		= 74,
92	RSVD75_PCC2_SLOT		= 75,
93	RSVD76_PCC2_SLOT		= 76,
94	RSVD77_PCC2_SLOT		= 77,
95	RSVD78_PCC2_SLOT		= 78,
96	RSVD79_PCC2_SLOT		= 79,
97	RSVD80_PCC2_SLOT		= 80,
98	RSVD81_PCC2_SLOT		= 81,
99	RSVD82_PCC2_SLOT		= 82,
100	RSVD83_PCC2_SLOT		= 83,
101	RSVD84_PCC2_SLOT		= 84,
102	RSVD85_PCC2_SLOT		= 85,
103	RSVD86_PCC2_SLOT		= 86,
104	RSVD87_PCC2_SLOT		= 87,
105	RSVD88_PCC2_SLOT		= 88,
106	RSVD89_PCC2_SLOT		= 89,
107	RSVD90_PCC2_SLOT		= 90,
108	RSVD91_PCC2_SLOT		= 91,
109	RSVD92_PCC2_SLOT		= 92,
110	RSVD93_PCC2_SLOT		= 93,
111	RSVD94_PCC2_SLOT		= 94,
112	RSVD95_PCC2_SLOT		= 95,
113	RSVD96_PCC2_SLOT		= 96,
114	RSVD97_PCC2_SLOT		= 97,
115	RSVD98_PCC2_SLOT		= 98,
116	RSVD99_PCC2_SLOT		= 99,
117	RSVD100_PCC2_SLOT		= 100,
118	RSVD101_PCC2_SLOT		= 101,
119	RSVD102_PCC2_SLOT		= 102,
120	RSVD103_PCC2_SLOT		= 103,
121	RSVD104_PCC2_SLOT		= 104,
122	RSVD105_PCC2_SLOT		= 105,
123	RSVD106_PCC2_SLOT		= 106,
124	RSVD107_PCC2_SLOT		= 107,
125	RSVD108_PCC2_SLOT		= 108,
126	RSVD109_PCC2_SLOT		= 109,
127	RSVD110_PCC2_SLOT		= 110,
128	RSVD111_PCC2_SLOT		= 111,
129	RSVD112_PCC2_SLOT		= 112,
130	RSVD113_PCC2_SLOT		= 113,
131	RSVD114_PCC2_SLOT		= 114,
132	RSVD115_PCC2_SLOT		= 115,
133	RSVD116_PCC2_SLOT		= 116,
134	RSVD117_PCC2_SLOT		= 117,
135	RSVD118_PCC2_SLOT		= 118,
136	RSVD119_PCC2_SLOT		= 119,
137	RSVD120_PCC2_SLOT		= 120,
138	RSVD121_PCC2_SLOT		= 121,
139	RSVD122_PCC2_SLOT		= 122,
140	RSVD123_PCC2_SLOT		= 123,
141	RSVD124_PCC2_SLOT		= 124,
142	RSVD125_PCC2_SLOT		= 125,
143	RSVD126_PCC2_SLOT		= 126,
144	RSVD127_PCC2_SLOT		= 127,
145};
146
147enum pcc3_entry {
148	/* On-Platform (32 entries) */
149	RSVD0_PCC3_SLOT			= 0,
150	RSVD1_PCC3_SLOT			= 1,
151	RSVD2_PCC3_SLOT			= 2,
152	RSVD3_PCC3_SLOT			= 3,
153	RSVD4_PCC3_SLOT			= 4,
154	RSVD5_PCC3_SLOT			= 5,
155	RSVD6_PCC3_SLOT			= 6,
156	RSVD7_PCC3_SLOT			= 7,
157	RSVD8_PCC3_SLOT			= 8,
158	RSVD9_PCC3_SLOT			= 9,
159	RSVD10_PCC3_SLOT		= 10,
160	RSVD11_PCC3_SLOT		= 11,
161	RSVD12_PCC3_SLOT		= 12,
162	RSVD13_PCC3_SLOT		= 13,
163	RSVD14_PCC3_SLOT		= 14,
164	RSVD15_PCC3_SLOT		= 15,
165	ROMCP1_PCC3_SLOT		= 16,
166	RSVD17_PCC3_SLOT		= 17,
167	RSVD18_PCC3_SLOT		= 18,
168	RSVD19_PCC3_SLOT		= 19,
169	RSVD20_PCC3_SLOT		= 20,
170	RSVD21_PCC3_SLOT		= 21,
171	RSVD22_PCC3_SLOT		= 22,
172	RSVD23_PCC3_SLOT		= 23,
173	RSVD24_PCC3_SLOT		= 24,
174	RSVD25_PCC3_SLOT		= 25,
175	RSVD26_PCC3_SLOT		= 26,
176	RSVD27_PCC3_SLOT		= 27,
177	RSVD28_PCC3_SLOT		= 28,
178	RSVD29_PCC3_SLOT		= 29,
179	RSVD30_PCC3_SLOT		= 30,
180	RSVD31_PCC3_SLOT		= 31,
181
182	/* Off-Platform (96 entries) */
183	RSVD32_PCC3_SLOT		= 32,
184	LPTPM6_PCC3_SLOT		= 33,
185	LPTPM7_PCC3_SLOT		= 34,
186	RSVD35_PCC3_SLOT		= 35,
187	LPI2C6_PCC3_SLOT		= 36,
188	LPI2C7_PCC3_SLOT		= 37,
189	LPUART6_PCC3_SLOT		= 38,
190	LPUART7_PCC3_SLOT		= 39,
191	VIU0_PCC3_SLOT			= 40,
192	DSI0_PCC3_SLOT			= 41,
193	LCDIF0_PCC3_SLOT		= 42,
194	MMDC0_PCC3_SLOT			= 43,
195	IOMUXC1_PCC3_SLOT		= 44,
196	IOMUXC_DDR_PCC3_SLOT		= 45,
197	PORTC_PCC3_SLOT			= 46,
198	PORTD_PCC3_SLOT			= 47,
199	PORTE_PCC3_SLOT			= 48,
200	PORTF_PCC3_SLOT			= 49,
201	RSVD50_PCC3_SLOT		= 50,
202	PCC3_PCC3_SLOT			= 51,
203	RSVD52_PCC3_SLOT		= 52,
204	WKPU_PCC3_SLOT			= 53,
205	RSVD54_PCC3_SLOT		= 54,
206	RSVD55_PCC3_SLOT		= 55,
207	RSVD56_PCC3_SLOT		= 56,
208	RSVD57_PCC3_SLOT		= 57,
209	RSVD58_PCC3_SLOT		= 58,
210	RSVD59_PCC3_SLOT		= 59,
211	RSVD60_PCC3_SLOT		= 60,
212	RSVD61_PCC3_SLOT		= 61,
213	RSVD62_PCC3_SLOT		= 62,
214	RSVD63_PCC3_SLOT		= 63,
215	RSVD64_PCC3_SLOT		= 64,
216	RSVD65_PCC3_SLOT		= 65,
217	RSVD66_PCC3_SLOT		= 66,
218	RSVD67_PCC3_SLOT		= 67,
219	RSVD68_PCC3_SLOT		= 68,
220	RSVD69_PCC3_SLOT		= 69,
221	RSVD70_PCC3_SLOT		= 70,
222	RSVD71_PCC3_SLOT		= 71,
223	RSVD72_PCC3_SLOT		= 72,
224	RSVD73_PCC3_SLOT		= 73,
225	RSVD74_PCC3_SLOT		= 74,
226	RSVD75_PCC3_SLOT		= 75,
227	RSVD76_PCC3_SLOT		= 76,
228	RSVD77_PCC3_SLOT		= 77,
229	RSVD78_PCC3_SLOT		= 78,
230	RSVD79_PCC3_SLOT		= 79,
231	RSVD80_PCC3_SLOT		= 80,
232	GPU3D_PCC3_SLOT			= 81,
233	GPU2D_PCC3_SLOT			= 82,
234	RSVD83_PCC3_SLOT		= 83,
235	RSVD84_PCC3_SLOT		= 84,
236	RSVD85_PCC3_SLOT		= 85,
237	RSVD86_PCC3_SLOT		= 86,
238	RSVD87_PCC3_SLOT		= 87,
239	RSVD88_PCC3_SLOT		= 88,
240	RSVD89_PCC3_SLOT		= 89,
241	RSVD90_PCC3_SLOT		= 90,
242	RSVD91_PCC3_SLOT		= 91,
243	RSVD92_PCC3_SLOT		= 92,
244	RSVD93_PCC3_SLOT		= 93,
245	RSVD94_PCC3_SLOT		= 94,
246	RSVD95_PCC3_SLOT		= 95,
247	RSVD96_PCC3_SLOT		= 96,
248	RSVD97_PCC3_SLOT		= 97,
249	RSVD98_PCC3_SLOT		= 98,
250	RSVD99_PCC3_SLOT		= 99,
251	RSVD100_PCC3_SLOT		= 100,
252	RSVD101_PCC3_SLOT		= 101,
253	RSVD102_PCC3_SLOT		= 102,
254	RSVD103_PCC3_SLOT		= 103,
255	RSVD104_PCC3_SLOT		= 104,
256	RSVD105_PCC3_SLOT		= 105,
257	RSVD106_PCC3_SLOT		= 106,
258	RSVD107_PCC3_SLOT		= 107,
259	RSVD108_PCC3_SLOT		= 108,
260	RSVD109_PCC3_SLOT		= 109,
261	RSVD110_PCC3_SLOT		= 110,
262	RSVD111_PCC3_SLOT		= 111,
263	RSVD112_PCC3_SLOT		= 112,
264	RSVD113_PCC3_SLOT		= 113,
265	RSVD114_PCC3_SLOT		= 114,
266	RSVD115_PCC3_SLOT		= 115,
267	RSVD116_PCC3_SLOT		= 116,
268	RSVD117_PCC3_SLOT		= 117,
269	RSVD118_PCC3_SLOT		= 118,
270	RSVD119_PCC3_SLOT		= 119,
271	RSVD120_PCC3_SLOT		= 120,
272	RSVD121_PCC3_SLOT		= 121,
273	RSVD122_PCC3_SLOT		= 122,
274	RSVD123_PCC3_SLOT		= 123,
275	RSVD124_PCC3_SLOT		= 124,
276	RSVD125_PCC3_SLOT		= 125,
277	RSVD126_PCC3_SLOT		= 126,
278	RSVD127_PCC3_SLOT		= 127,
279};
280
281
282/* PCC registers */
283#define PCC_PR_OFFSET	31
284#define PCC_PR_MASK		(0x1 << PCC_PR_OFFSET)
285#define PCC_CGC_OFFSET	30
286#define PCC_CGC_MASK	(0x1 << PCC_CGC_OFFSET)
287#define PCC_INUSE_OFFSET	29
288#define PCC_INUSE_MASK		(0x1 << PCC_INUSE_OFFSET)
289#define PCC_PCS_OFFSET	24
290#define PCC_PCS_MASK	(0x7 << PCC_PCS_OFFSET)
291#define PCC_FRAC_OFFSET	3
292#define PCC_FRAC_MASK	(0x1 << PCC_FRAC_OFFSET)
293#define PCC_PCD_OFFSET	0
294#define PCC_PCD_MASK	(0x7 << PCC_PCD_OFFSET)
295
296
297enum pcc_clksrc_type {
298	CLKSRC_PER_PLAT = 0,
299	CLKSRC_PER_BUS = 1,
300	CLKSRC_NO_PCS = 2,
301};
302
303enum pcc_div_type {
304	PCC_HAS_DIV,
305	PCC_NO_DIV,
306};
307
308/* All peripheral clocks on A7 PCCs */
309enum pcc_clk {
310	/*PCC2 clocks*/
311	PER_CLK_DMA1 = 0,
312	PER_CLK_RGPIO2P1,
313	PER_CLK_FLEXBUS,
314	PER_CLK_SEMA42_1,
315	PER_CLK_DMA_MUX1,
316	PER_CLK_SNVS,
317	PER_CLK_CAAM,
318	PER_CLK_LPTPM4,
319	PER_CLK_LPTPM5,
320	PER_CLK_LPIT1,
321	PER_CLK_LPSPI2,
322	PER_CLK_LPSPI3,
323	PER_CLK_LPI2C4,
324	PER_CLK_LPI2C5,
325	PER_CLK_LPUART4,
326	PER_CLK_LPUART5,
327	PER_CLK_FLEXIO1,
328	PER_CLK_USB0,
329	PER_CLK_USB1,
330	PER_CLK_USB_PHY,
331	PER_CLK_USB_PL301,
332	PER_CLK_USDHC0,
333	PER_CLK_USDHC1,
334	PER_CLK_WDG1,
335	PER_CLK_WDG2,
336
337	/*PCC3 clocks*/
338	PER_CLK_LPTPM6,
339	PER_CLK_LPTPM7,
340	PER_CLK_LPI2C6,
341	PER_CLK_LPI2C7,
342	PER_CLK_LPUART6,
343	PER_CLK_LPUART7,
344	PER_CLK_VIU,
345	PER_CLK_DSI,
346	PER_CLK_LCDIF,
347	PER_CLK_MMDC,
348	PER_CLK_PCTLC,
349	PER_CLK_PCTLD,
350	PER_CLK_PCTLE,
351	PER_CLK_PCTLF,
352	PER_CLK_GPU3D,
353	PER_CLK_GPU2D,
354};
355
356
357/* This structure keeps info for each pcc slot */
358struct pcc_entry {
359	u32 pcc_base;
360	u32 pcc_slot;
361	enum pcc_clksrc_type clksrc;
362	enum pcc_div_type div;
363};
364
365int pcc_clock_enable(enum pcc_clk clk, bool enable);
366int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src);
367int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div);
368bool pcc_clock_is_enable(enum pcc_clk clk);
369int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src);
370u32 pcc_clock_get_rate(enum pcc_clk clk);
371#endif
372