1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
4 */
5
6#ifndef __ASM_ARCH_MX31_IMX_REGS_H
7#define __ASM_ARCH_MX31_IMX_REGS_H
8
9#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
10#include <asm/types.h>
11
12/* Clock control module registers */
13struct clock_control_regs {
14	u32 ccmr;
15	u32 pdr0;
16	u32 pdr1;
17	u32 rcsr;
18	u32 mpctl;
19	u32 upctl;
20	u32 spctl;
21	u32 cosr;
22	u32 cgr0;
23	u32 cgr1;
24	u32 cgr2;
25	u32 wimr0;
26	u32 ldc;
27	u32 dcvr0;
28	u32 dcvr1;
29	u32 dcvr2;
30	u32 dcvr3;
31	u32 ltr0;
32	u32 ltr1;
33	u32 ltr2;
34	u32 ltr3;
35	u32 ltbr0;
36	u32 ltbr1;
37	u32 pmcr0;
38	u32 pmcr1;
39	u32 pdr2;
40};
41
42/* IIM control registers */
43struct iim_regs {
44	u32 iim_stat;
45	u32 iim_statm;
46	u32 iim_err;
47	u32 iim_emask;
48	u32 iim_fctl;
49	u32 iim_ua;
50	u32 iim_la;
51	u32 iim_sdat;
52	u32 iim_prev;
53	u32 iim_srev;
54	u32 iim_prg_p;
55	u32 iim_scs0;
56	u32 iim_scs1;
57	u32 iim_scs2;
58	u32 iim_scs3;
59	u32 res[0x1f1];
60	struct fuse_bank {
61		u32 fuse_regs[0x20];
62		u32 fuse_rsvd[0xe0];
63	} bank[3];
64};
65
66struct fuse_bank0_regs {
67	u32 fuse0_5[6];
68	u32 usr;
69	u32 fuse7_15[9];
70};
71
72struct fuse_bank2_regs {
73	u32 fuse0;
74	u32 uid[8];
75	u32 fuse9_15[7];
76};
77
78struct iomuxc_regs {
79	u32 unused1;
80	u32 unused2;
81	u32 gpr;
82};
83
84struct mx3_cpu_type {
85	u8 srev;
86	u32 v;
87};
88
89#define IOMUX_PADNUM_MASK	0x1ff
90#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
91
92/*
93 * various IOMUX pad functions
94 */
95enum iomux_pad_config {
96	PAD_CTL_NOLOOPBACK	= 0x0 << 9,
97	PAD_CTL_LOOPBACK	= 0x1 << 9,
98	PAD_CTL_PKE_NONE	= 0x0 << 8,
99	PAD_CTL_PKE_ENABLE	= 0x1 << 8,
100	PAD_CTL_PUE_KEEPER	= 0x0 << 7,
101	PAD_CTL_PUE_PUD		= 0x1 << 7,
102	PAD_CTL_100K_PD		= 0x0 << 5,
103	PAD_CTL_100K_PU		= 0x1 << 5,
104	PAD_CTL_47K_PU		= 0x2 << 5,
105	PAD_CTL_22K_PU		= 0x3 << 5,
106	PAD_CTL_HYS_CMOS	= 0x0 << 4,
107	PAD_CTL_HYS_SCHMITZ	= 0x1 << 4,
108	PAD_CTL_ODE_CMOS	= 0x0 << 3,
109	PAD_CTL_ODE_OpenDrain	= 0x1 << 3,
110	PAD_CTL_DRV_NORMAL	= 0x0 << 1,
111	PAD_CTL_DRV_HIGH	= 0x1 << 1,
112	PAD_CTL_DRV_MAX		= 0x2 << 1,
113	PAD_CTL_SRE_SLOW	= 0x0 << 0,
114	PAD_CTL_SRE_FAST	= 0x1 << 0
115};
116
117/*
118 * This enumeration is constructed based on the Section
119 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
120 * value is constructed based on the rules described above.
121 */
122
123enum iomux_pins {
124	MX31_PIN_TTM_PAD	= IOMUX_PIN(0xff,   0),
125	MX31_PIN_CSPI3_SPI_RDY	= IOMUX_PIN(0xff,   1),
126	MX31_PIN_CSPI3_SCLK	= IOMUX_PIN(0xff,   2),
127	MX31_PIN_CSPI3_MISO	= IOMUX_PIN(0xff,   3),
128	MX31_PIN_CSPI3_MOSI	= IOMUX_PIN(0xff,   4),
129	MX31_PIN_CLKSS		= IOMUX_PIN(0xff,   5),
130	MX31_PIN_CE_CONTROL	= IOMUX_PIN(0xff,   6),
131	MX31_PIN_ATA_RESET_B	= IOMUX_PIN(95,     7),
132	MX31_PIN_ATA_DMACK	= IOMUX_PIN(94,     8),
133	MX31_PIN_ATA_DIOW	= IOMUX_PIN(93,     9),
134	MX31_PIN_ATA_DIOR	= IOMUX_PIN(92,    10),
135	MX31_PIN_ATA_CS1	= IOMUX_PIN(91,    11),
136	MX31_PIN_ATA_CS0	= IOMUX_PIN(90,    12),
137	MX31_PIN_SD1_DATA3	= IOMUX_PIN(63,    13),
138	MX31_PIN_SD1_DATA2	= IOMUX_PIN(62,    14),
139	MX31_PIN_SD1_DATA1	= IOMUX_PIN(61,    15),
140	MX31_PIN_SD1_DATA0	= IOMUX_PIN(60,    16),
141	MX31_PIN_SD1_CLK	= IOMUX_PIN(59,    17),
142	MX31_PIN_SD1_CMD	= IOMUX_PIN(58,    18),
143	MX31_PIN_D3_SPL		= IOMUX_PIN(0xff,  19),
144	MX31_PIN_D3_CLS		= IOMUX_PIN(0xff,  20),
145	MX31_PIN_D3_REV		= IOMUX_PIN(0xff,  21),
146	MX31_PIN_CONTRAST	= IOMUX_PIN(0xff,  22),
147	MX31_PIN_VSYNC3		= IOMUX_PIN(0xff,  23),
148	MX31_PIN_READ		= IOMUX_PIN(0xff,  24),
149	MX31_PIN_WRITE		= IOMUX_PIN(0xff,  25),
150	MX31_PIN_PAR_RS		= IOMUX_PIN(0xff,  26),
151	MX31_PIN_SER_RS		= IOMUX_PIN(89,    27),
152	MX31_PIN_LCS1		= IOMUX_PIN(88,    28),
153	MX31_PIN_LCS0		= IOMUX_PIN(87,    29),
154	MX31_PIN_SD_D_CLK	= IOMUX_PIN(86,    30),
155	MX31_PIN_SD_D_IO	= IOMUX_PIN(85,    31),
156	MX31_PIN_SD_D_I		= IOMUX_PIN(84,    32),
157	MX31_PIN_DRDY0		= IOMUX_PIN(0xff,  33),
158	MX31_PIN_FPSHIFT	= IOMUX_PIN(0xff,  34),
159	MX31_PIN_HSYNC		= IOMUX_PIN(0xff,  35),
160	MX31_PIN_VSYNC0		= IOMUX_PIN(0xff,  36),
161	MX31_PIN_LD17		= IOMUX_PIN(0xff,  37),
162	MX31_PIN_LD16		= IOMUX_PIN(0xff,  38),
163	MX31_PIN_LD15		= IOMUX_PIN(0xff,  39),
164	MX31_PIN_LD14		= IOMUX_PIN(0xff,  40),
165	MX31_PIN_LD13		= IOMUX_PIN(0xff,  41),
166	MX31_PIN_LD12		= IOMUX_PIN(0xff,  42),
167	MX31_PIN_LD11		= IOMUX_PIN(0xff,  43),
168	MX31_PIN_LD10		= IOMUX_PIN(0xff,  44),
169	MX31_PIN_LD9		= IOMUX_PIN(0xff,  45),
170	MX31_PIN_LD8		= IOMUX_PIN(0xff,  46),
171	MX31_PIN_LD7		= IOMUX_PIN(0xff,  47),
172	MX31_PIN_LD6		= IOMUX_PIN(0xff,  48),
173	MX31_PIN_LD5		= IOMUX_PIN(0xff,  49),
174	MX31_PIN_LD4		= IOMUX_PIN(0xff,  50),
175	MX31_PIN_LD3		= IOMUX_PIN(0xff,  51),
176	MX31_PIN_LD2		= IOMUX_PIN(0xff,  52),
177	MX31_PIN_LD1		= IOMUX_PIN(0xff,  53),
178	MX31_PIN_LD0		= IOMUX_PIN(0xff,  54),
179	MX31_PIN_USBH2_DATA1	= IOMUX_PIN(0xff,  55),
180	MX31_PIN_USBH2_DATA0	= IOMUX_PIN(0xff,  56),
181	MX31_PIN_USBH2_NXT	= IOMUX_PIN(0xff,  57),
182	MX31_PIN_USBH2_STP	= IOMUX_PIN(0xff,  58),
183	MX31_PIN_USBH2_DIR	= IOMUX_PIN(0xff,  59),
184	MX31_PIN_USBH2_CLK	= IOMUX_PIN(0xff,  60),
185	MX31_PIN_USBOTG_DATA7	= IOMUX_PIN(0xff,  61),
186	MX31_PIN_USBOTG_DATA6	= IOMUX_PIN(0xff,  62),
187	MX31_PIN_USBOTG_DATA5	= IOMUX_PIN(0xff,  63),
188	MX31_PIN_USBOTG_DATA4	= IOMUX_PIN(0xff,  64),
189	MX31_PIN_USBOTG_DATA3	= IOMUX_PIN(0xff,  65),
190	MX31_PIN_USBOTG_DATA2	= IOMUX_PIN(0xff,  66),
191	MX31_PIN_USBOTG_DATA1	= IOMUX_PIN(0xff,  67),
192	MX31_PIN_USBOTG_DATA0	= IOMUX_PIN(0xff,  68),
193	MX31_PIN_USBOTG_NXT	= IOMUX_PIN(0xff,  69),
194	MX31_PIN_USBOTG_STP	= IOMUX_PIN(0xff,  70),
195	MX31_PIN_USBOTG_DIR	= IOMUX_PIN(0xff,  71),
196	MX31_PIN_USBOTG_CLK	= IOMUX_PIN(0xff,  72),
197	MX31_PIN_USB_BYP	= IOMUX_PIN(31,    73),
198	MX31_PIN_USB_OC		= IOMUX_PIN(30,    74),
199	MX31_PIN_USB_PWR	= IOMUX_PIN(29,    75),
200	MX31_PIN_SJC_MOD	= IOMUX_PIN(0xff,  76),
201	MX31_PIN_DE_B		= IOMUX_PIN(0xff,  77),
202	MX31_PIN_TRSTB		= IOMUX_PIN(0xff,  78),
203	MX31_PIN_TDO		= IOMUX_PIN(0xff,  79),
204	MX31_PIN_TDI		= IOMUX_PIN(0xff,  80),
205	MX31_PIN_TMS		= IOMUX_PIN(0xff,  81),
206	MX31_PIN_TCK		= IOMUX_PIN(0xff,  82),
207	MX31_PIN_RTCK		= IOMUX_PIN(0xff,  83),
208	MX31_PIN_KEY_COL7	= IOMUX_PIN(57,    84),
209	MX31_PIN_KEY_COL6	= IOMUX_PIN(56,    85),
210	MX31_PIN_KEY_COL5	= IOMUX_PIN(55,    86),
211	MX31_PIN_KEY_COL4	= IOMUX_PIN(54,    87),
212	MX31_PIN_KEY_COL3	= IOMUX_PIN(0xff,  88),
213	MX31_PIN_KEY_COL2	= IOMUX_PIN(0xff,  89),
214	MX31_PIN_KEY_COL1	= IOMUX_PIN(0xff,  90),
215	MX31_PIN_KEY_COL0	= IOMUX_PIN(0xff,  91),
216	MX31_PIN_KEY_ROW7	= IOMUX_PIN(53,    92),
217	MX31_PIN_KEY_ROW6	= IOMUX_PIN(52,    93),
218	MX31_PIN_KEY_ROW5	= IOMUX_PIN(51,    94),
219	MX31_PIN_KEY_ROW4	= IOMUX_PIN(50,    95),
220	MX31_PIN_KEY_ROW3	= IOMUX_PIN(0xff,  96),
221	MX31_PIN_KEY_ROW2	= IOMUX_PIN(0xff,  97),
222	MX31_PIN_KEY_ROW1	= IOMUX_PIN(0xff,  98),
223	MX31_PIN_KEY_ROW0	= IOMUX_PIN(0xff,  99),
224	MX31_PIN_BATT_LINE	= IOMUX_PIN(49,   100),
225	MX31_PIN_CTS2		= IOMUX_PIN(0xff, 101),
226	MX31_PIN_RTS2		= IOMUX_PIN(0xff, 102),
227	MX31_PIN_TXD2		= IOMUX_PIN(28,   103),
228	MX31_PIN_RXD2		= IOMUX_PIN(27,   104),
229	MX31_PIN_DTR_DCE2	= IOMUX_PIN(48,   105),
230	MX31_PIN_DCD_DTE1	= IOMUX_PIN(47,   106),
231	MX31_PIN_RI_DTE1	= IOMUX_PIN(46,   107),
232	MX31_PIN_DSR_DTE1	= IOMUX_PIN(45,   108),
233	MX31_PIN_DTR_DTE1	= IOMUX_PIN(44,   109),
234	MX31_PIN_DCD_DCE1	= IOMUX_PIN(43,   110),
235	MX31_PIN_RI_DCE1	= IOMUX_PIN(42,   111),
236	MX31_PIN_DSR_DCE1	= IOMUX_PIN(41,   112),
237	MX31_PIN_DTR_DCE1	= IOMUX_PIN(40,   113),
238	MX31_PIN_CTS1		= IOMUX_PIN(39,   114),
239	MX31_PIN_RTS1		= IOMUX_PIN(38,   115),
240	MX31_PIN_TXD1		= IOMUX_PIN(37,   116),
241	MX31_PIN_RXD1		= IOMUX_PIN(36,   117),
242	MX31_PIN_CSPI2_SPI_RDY	= IOMUX_PIN(0xff, 118),
243	MX31_PIN_CSPI2_SCLK	= IOMUX_PIN(0xff, 119),
244	MX31_PIN_CSPI2_SS2	= IOMUX_PIN(0xff, 120),
245	MX31_PIN_CSPI2_SS1	= IOMUX_PIN(0xff, 121),
246	MX31_PIN_CSPI2_SS0	= IOMUX_PIN(0xff, 122),
247	MX31_PIN_CSPI2_MISO	= IOMUX_PIN(0xff, 123),
248	MX31_PIN_CSPI2_MOSI	= IOMUX_PIN(0xff, 124),
249	MX31_PIN_CSPI1_SPI_RDY	= IOMUX_PIN(0xff, 125),
250	MX31_PIN_CSPI1_SCLK	= IOMUX_PIN(0xff, 126),
251	MX31_PIN_CSPI1_SS2	= IOMUX_PIN(0xff, 127),
252	MX31_PIN_CSPI1_SS1	= IOMUX_PIN(0xff, 128),
253	MX31_PIN_CSPI1_SS0	= IOMUX_PIN(0xff, 129),
254	MX31_PIN_CSPI1_MISO	= IOMUX_PIN(0xff, 130),
255	MX31_PIN_CSPI1_MOSI	= IOMUX_PIN(0xff, 131),
256	MX31_PIN_SFS6		= IOMUX_PIN(26,   132),
257	MX31_PIN_SCK6		= IOMUX_PIN(25,   133),
258	MX31_PIN_SRXD6		= IOMUX_PIN(24,   134),
259	MX31_PIN_STXD6		= IOMUX_PIN(23,   135),
260	MX31_PIN_SFS5		= IOMUX_PIN(0xff, 136),
261	MX31_PIN_SCK5		= IOMUX_PIN(0xff, 137),
262	MX31_PIN_SRXD5		= IOMUX_PIN(22,   138),
263	MX31_PIN_STXD5		= IOMUX_PIN(21,   139),
264	MX31_PIN_SFS4		= IOMUX_PIN(0xff, 140),
265	MX31_PIN_SCK4		= IOMUX_PIN(0xff, 141),
266	MX31_PIN_SRXD4		= IOMUX_PIN(20,   142),
267	MX31_PIN_STXD4		= IOMUX_PIN(19,   143),
268	MX31_PIN_SFS3		= IOMUX_PIN(0xff, 144),
269	MX31_PIN_SCK3		= IOMUX_PIN(0xff, 145),
270	MX31_PIN_SRXD3		= IOMUX_PIN(18,   146),
271	MX31_PIN_STXD3		= IOMUX_PIN(17,   147),
272	MX31_PIN_I2C_DAT	= IOMUX_PIN(0xff, 148),
273	MX31_PIN_I2C_CLK	= IOMUX_PIN(0xff, 149),
274	MX31_PIN_CSI_PIXCLK	= IOMUX_PIN(83,   150),
275	MX31_PIN_CSI_HSYNC	= IOMUX_PIN(82,   151),
276	MX31_PIN_CSI_VSYNC	= IOMUX_PIN(81,   152),
277	MX31_PIN_CSI_MCLK	= IOMUX_PIN(80,   153),
278	MX31_PIN_CSI_D15	= IOMUX_PIN(79,   154),
279	MX31_PIN_CSI_D14	= IOMUX_PIN(78,   155),
280	MX31_PIN_CSI_D13	= IOMUX_PIN(77,   156),
281	MX31_PIN_CSI_D12	= IOMUX_PIN(76,   157),
282	MX31_PIN_CSI_D11	= IOMUX_PIN(75,   158),
283	MX31_PIN_CSI_D10	= IOMUX_PIN(74,   159),
284	MX31_PIN_CSI_D9		= IOMUX_PIN(73,   160),
285	MX31_PIN_CSI_D8		= IOMUX_PIN(72,   161),
286	MX31_PIN_CSI_D7		= IOMUX_PIN(71,   162),
287	MX31_PIN_CSI_D6		= IOMUX_PIN(70,   163),
288	MX31_PIN_CSI_D5		= IOMUX_PIN(69,   164),
289	MX31_PIN_CSI_D4		= IOMUX_PIN(68,   165),
290	MX31_PIN_M_GRANT	= IOMUX_PIN(0xff, 166),
291	MX31_PIN_M_REQUEST	= IOMUX_PIN(0xff, 167),
292	MX31_PIN_PC_POE		= IOMUX_PIN(0xff, 168),
293	MX31_PIN_PC_RW_B	= IOMUX_PIN(0xff, 169),
294	MX31_PIN_IOIS16		= IOMUX_PIN(0xff, 170),
295	MX31_PIN_PC_RST		= IOMUX_PIN(0xff, 171),
296	MX31_PIN_PC_BVD2	= IOMUX_PIN(0xff, 172),
297	MX31_PIN_PC_BVD1	= IOMUX_PIN(0xff, 173),
298	MX31_PIN_PC_VS2		= IOMUX_PIN(0xff, 174),
299	MX31_PIN_PC_VS1		= IOMUX_PIN(0xff, 175),
300	MX31_PIN_PC_PWRON	= IOMUX_PIN(0xff, 176),
301	MX31_PIN_PC_READY	= IOMUX_PIN(0xff, 177),
302	MX31_PIN_PC_WAIT_B	= IOMUX_PIN(0xff, 178),
303	MX31_PIN_PC_CD2_B	= IOMUX_PIN(0xff, 179),
304	MX31_PIN_PC_CD1_B	= IOMUX_PIN(0xff, 180),
305	MX31_PIN_D0		= IOMUX_PIN(0xff, 181),
306	MX31_PIN_D1		= IOMUX_PIN(0xff, 182),
307	MX31_PIN_D2		= IOMUX_PIN(0xff, 183),
308	MX31_PIN_D3		= IOMUX_PIN(0xff, 184),
309	MX31_PIN_D4		= IOMUX_PIN(0xff, 185),
310	MX31_PIN_D5		= IOMUX_PIN(0xff, 186),
311	MX31_PIN_D6		= IOMUX_PIN(0xff, 187),
312	MX31_PIN_D7		= IOMUX_PIN(0xff, 188),
313	MX31_PIN_D8		= IOMUX_PIN(0xff, 189),
314	MX31_PIN_D9		= IOMUX_PIN(0xff, 190),
315	MX31_PIN_D10		= IOMUX_PIN(0xff, 191),
316	MX31_PIN_D11		= IOMUX_PIN(0xff, 192),
317	MX31_PIN_D12		= IOMUX_PIN(0xff, 193),
318	MX31_PIN_D13		= IOMUX_PIN(0xff, 194),
319	MX31_PIN_D14		= IOMUX_PIN(0xff, 195),
320	MX31_PIN_D15		= IOMUX_PIN(0xff, 196),
321	MX31_PIN_NFRB		= IOMUX_PIN(16,   197),
322	MX31_PIN_NFCE_B		= IOMUX_PIN(15,   198),
323	MX31_PIN_NFWP_B		= IOMUX_PIN(14,   199),
324	MX31_PIN_NFCLE		= IOMUX_PIN(13,   200),
325	MX31_PIN_NFALE		= IOMUX_PIN(12,   201),
326	MX31_PIN_NFRE_B		= IOMUX_PIN(11,   202),
327	MX31_PIN_NFWE_B		= IOMUX_PIN(10,   203),
328	MX31_PIN_SDQS3		= IOMUX_PIN(0xff, 204),
329	MX31_PIN_SDQS2		= IOMUX_PIN(0xff, 205),
330	MX31_PIN_SDQS1		= IOMUX_PIN(0xff, 206),
331	MX31_PIN_SDQS0		= IOMUX_PIN(0xff, 207),
332	MX31_PIN_SDCLK_B	= IOMUX_PIN(0xff, 208),
333	MX31_PIN_SDCLK		= IOMUX_PIN(0xff, 209),
334	MX31_PIN_SDCKE1		= IOMUX_PIN(0xff, 210),
335	MX31_PIN_SDCKE0		= IOMUX_PIN(0xff, 211),
336	MX31_PIN_SDWE		= IOMUX_PIN(0xff, 212),
337	MX31_PIN_CAS		= IOMUX_PIN(0xff, 213),
338	MX31_PIN_RAS		= IOMUX_PIN(0xff, 214),
339	MX31_PIN_RW		= IOMUX_PIN(0xff, 215),
340	MX31_PIN_BCLK		= IOMUX_PIN(0xff, 216),
341	MX31_PIN_LBA		= IOMUX_PIN(0xff, 217),
342	MX31_PIN_ECB		= IOMUX_PIN(0xff, 218),
343	MX31_PIN_CS5		= IOMUX_PIN(0xff, 219),
344	MX31_PIN_CS4		= IOMUX_PIN(0xff, 220),
345	MX31_PIN_CS3		= IOMUX_PIN(0xff, 221),
346	MX31_PIN_CS2		= IOMUX_PIN(0xff, 222),
347	MX31_PIN_CS1		= IOMUX_PIN(0xff, 223),
348	MX31_PIN_CS0		= IOMUX_PIN(0xff, 224),
349	MX31_PIN_OE		= IOMUX_PIN(0xff, 225),
350	MX31_PIN_EB1		= IOMUX_PIN(0xff, 226),
351	MX31_PIN_EB0		= IOMUX_PIN(0xff, 227),
352	MX31_PIN_DQM3		= IOMUX_PIN(0xff, 228),
353	MX31_PIN_DQM2		= IOMUX_PIN(0xff, 229),
354	MX31_PIN_DQM1		= IOMUX_PIN(0xff, 230),
355	MX31_PIN_DQM0		= IOMUX_PIN(0xff, 231),
356	MX31_PIN_SD31		= IOMUX_PIN(0xff, 232),
357	MX31_PIN_SD30		= IOMUX_PIN(0xff, 233),
358	MX31_PIN_SD29		= IOMUX_PIN(0xff, 234),
359	MX31_PIN_SD28		= IOMUX_PIN(0xff, 235),
360	MX31_PIN_SD27		= IOMUX_PIN(0xff, 236),
361	MX31_PIN_SD26		= IOMUX_PIN(0xff, 237),
362	MX31_PIN_SD25		= IOMUX_PIN(0xff, 238),
363	MX31_PIN_SD24		= IOMUX_PIN(0xff, 239),
364	MX31_PIN_SD23		= IOMUX_PIN(0xff, 240),
365	MX31_PIN_SD22		= IOMUX_PIN(0xff, 241),
366	MX31_PIN_SD21		= IOMUX_PIN(0xff, 242),
367	MX31_PIN_SD20		= IOMUX_PIN(0xff, 243),
368	MX31_PIN_SD19		= IOMUX_PIN(0xff, 244),
369	MX31_PIN_SD18		= IOMUX_PIN(0xff, 245),
370	MX31_PIN_SD17		= IOMUX_PIN(0xff, 246),
371	MX31_PIN_SD16		= IOMUX_PIN(0xff, 247),
372	MX31_PIN_SD15		= IOMUX_PIN(0xff, 248),
373	MX31_PIN_SD14		= IOMUX_PIN(0xff, 249),
374	MX31_PIN_SD13		= IOMUX_PIN(0xff, 250),
375	MX31_PIN_SD12		= IOMUX_PIN(0xff, 251),
376	MX31_PIN_SD11		= IOMUX_PIN(0xff, 252),
377	MX31_PIN_SD10		= IOMUX_PIN(0xff, 253),
378	MX31_PIN_SD9		= IOMUX_PIN(0xff, 254),
379	MX31_PIN_SD8		= IOMUX_PIN(0xff, 255),
380	MX31_PIN_SD7		= IOMUX_PIN(0xff, 256),
381	MX31_PIN_SD6		= IOMUX_PIN(0xff, 257),
382	MX31_PIN_SD5		= IOMUX_PIN(0xff, 258),
383	MX31_PIN_SD4		= IOMUX_PIN(0xff, 259),
384	MX31_PIN_SD3		= IOMUX_PIN(0xff, 260),
385	MX31_PIN_SD2		= IOMUX_PIN(0xff, 261),
386	MX31_PIN_SD1		= IOMUX_PIN(0xff, 262),
387	MX31_PIN_SD0		= IOMUX_PIN(0xff, 263),
388	MX31_PIN_SDBA0		= IOMUX_PIN(0xff, 264),
389	MX31_PIN_SDBA1		= IOMUX_PIN(0xff, 265),
390	MX31_PIN_A25		= IOMUX_PIN(0xff, 266),
391	MX31_PIN_A24		= IOMUX_PIN(0xff, 267),
392	MX31_PIN_A23		= IOMUX_PIN(0xff, 268),
393	MX31_PIN_A22		= IOMUX_PIN(0xff, 269),
394	MX31_PIN_A21		= IOMUX_PIN(0xff, 270),
395	MX31_PIN_A20		= IOMUX_PIN(0xff, 271),
396	MX31_PIN_A19		= IOMUX_PIN(0xff, 272),
397	MX31_PIN_A18		= IOMUX_PIN(0xff, 273),
398	MX31_PIN_A17		= IOMUX_PIN(0xff, 274),
399	MX31_PIN_A16		= IOMUX_PIN(0xff, 275),
400	MX31_PIN_A14		= IOMUX_PIN(0xff, 276),
401	MX31_PIN_A15		= IOMUX_PIN(0xff, 277),
402	MX31_PIN_A13		= IOMUX_PIN(0xff, 278),
403	MX31_PIN_A12		= IOMUX_PIN(0xff, 279),
404	MX31_PIN_A11		= IOMUX_PIN(0xff, 280),
405	MX31_PIN_MA10		= IOMUX_PIN(0xff, 281),
406	MX31_PIN_A10		= IOMUX_PIN(0xff, 282),
407	MX31_PIN_A9		= IOMUX_PIN(0xff, 283),
408	MX31_PIN_A8		= IOMUX_PIN(0xff, 284),
409	MX31_PIN_A7		= IOMUX_PIN(0xff, 285),
410	MX31_PIN_A6		= IOMUX_PIN(0xff, 286),
411	MX31_PIN_A5		= IOMUX_PIN(0xff, 287),
412	MX31_PIN_A4		= IOMUX_PIN(0xff, 288),
413	MX31_PIN_A3		= IOMUX_PIN(0xff, 289),
414	MX31_PIN_A2		= IOMUX_PIN(0xff, 290),
415	MX31_PIN_A1		= IOMUX_PIN(0xff, 291),
416	MX31_PIN_A0		= IOMUX_PIN(0xff, 292),
417	MX31_PIN_VPG1		= IOMUX_PIN(0xff, 293),
418	MX31_PIN_VPG0		= IOMUX_PIN(0xff, 294),
419	MX31_PIN_DVFS1		= IOMUX_PIN(0xff, 295),
420	MX31_PIN_DVFS0		= IOMUX_PIN(0xff, 296),
421	MX31_PIN_VSTBY		= IOMUX_PIN(0xff, 297),
422	MX31_PIN_POWER_FAIL	= IOMUX_PIN(0xff, 298),
423	MX31_PIN_CKIL		= IOMUX_PIN(0xff, 299),
424	MX31_PIN_BOOT_MODE4	= IOMUX_PIN(0xff, 300),
425	MX31_PIN_BOOT_MODE3	= IOMUX_PIN(0xff, 301),
426	MX31_PIN_BOOT_MODE2	= IOMUX_PIN(0xff, 302),
427	MX31_PIN_BOOT_MODE1	= IOMUX_PIN(0xff, 303),
428	MX31_PIN_BOOT_MODE0	= IOMUX_PIN(0xff, 304),
429	MX31_PIN_CLKO		= IOMUX_PIN(0xff, 305),
430	MX31_PIN_POR_B		= IOMUX_PIN(0xff, 306),
431	MX31_PIN_RESET_IN_B	= IOMUX_PIN(0xff, 307),
432	MX31_PIN_CKIH		= IOMUX_PIN(0xff, 308),
433	MX31_PIN_SIMPD0		= IOMUX_PIN(35,   309),
434	MX31_PIN_SRX0		= IOMUX_PIN(34,   310),
435	MX31_PIN_STX0		= IOMUX_PIN(33,   311),
436	MX31_PIN_SVEN0		= IOMUX_PIN(32,   312),
437	MX31_PIN_SRST0		= IOMUX_PIN(67,   313),
438	MX31_PIN_SCLK0		= IOMUX_PIN(66,   314),
439	MX31_PIN_GPIO3_1	= IOMUX_PIN(65,   315),
440	MX31_PIN_GPIO3_0	= IOMUX_PIN(64,   316),
441	MX31_PIN_GPIO1_6	= IOMUX_PIN(6,    317),
442	MX31_PIN_GPIO1_5	= IOMUX_PIN(5,    318),
443	MX31_PIN_GPIO1_4	= IOMUX_PIN(4,    319),
444	MX31_PIN_GPIO1_3	= IOMUX_PIN(3,    320),
445	MX31_PIN_GPIO1_2	= IOMUX_PIN(2,    321),
446	MX31_PIN_GPIO1_1	= IOMUX_PIN(1,    322),
447	MX31_PIN_GPIO1_0	= IOMUX_PIN(0,    323),
448	MX31_PIN_PWMO		= IOMUX_PIN(9,    324),
449	MX31_PIN_WATCHDOG_RST	= IOMUX_PIN(0xff, 325),
450	MX31_PIN_COMPARE	= IOMUX_PIN(8,    326),
451	MX31_PIN_CAPTURE	= IOMUX_PIN(7,    327),
452};
453
454/*
455 * various IOMUX general purpose functions
456 */
457enum iomux_gp_func {
458	MUX_PGP_FIRI			= 1 << 0,
459	MUX_DDR_MODE			= 1 << 1,
460	MUX_PGP_CSPI_BB			= 1 << 2,
461	MUX_PGP_ATA_1			= 1 << 3,
462	MUX_PGP_ATA_2			= 1 << 4,
463	MUX_PGP_ATA_3			= 1 << 5,
464	MUX_PGP_ATA_4			= 1 << 6,
465	MUX_PGP_ATA_5			= 1 << 7,
466	MUX_PGP_ATA_6			= 1 << 8,
467	MUX_PGP_ATA_7			= 1 << 9,
468	MUX_PGP_ATA_8			= 1 << 10,
469	MUX_PGP_UH2			= 1 << 11,
470	MUX_SDCTL_CSD0_SEL		= 1 << 12,
471	MUX_SDCTL_CSD1_SEL		= 1 << 13,
472	MUX_CSPI1_UART3			= 1 << 14,
473	MUX_EXTDMAREQ2_MBX_SEL		= 1 << 15,
474	MUX_TAMPER_DETECT_EN		= 1 << 16,
475	MUX_PGP_USB_4WIRE		= 1 << 17,
476	MUX_PGP_USB_COMMON		= 1 << 18,
477	MUX_SDHC_MEMSTICK1		= 1 << 19,
478	MUX_SDHC_MEMSTICK2		= 1 << 20,
479	MUX_PGP_SPLL_BYP		= 1 << 21,
480	MUX_PGP_UPLL_BYP		= 1 << 22,
481	MUX_PGP_MSHC1_CLK_SEL		= 1 << 23,
482	MUX_PGP_MSHC2_CLK_SEL		= 1 << 24,
483	MUX_CSPI3_UART5_SEL		= 1 << 25,
484	MUX_PGP_ATA_9			= 1 << 26,
485	MUX_PGP_USB_SUSPEND		= 1 << 27,
486	MUX_PGP_USB_OTG_LOOPBACK	= 1 << 28,
487	MUX_PGP_USB_HS1_LOOPBACK	= 1 << 29,
488	MUX_PGP_USB_HS2_LOOPBACK	= 1 << 30,
489	MUX_CLKO_DDR_MODE		= 1 << 31,
490};
491
492/* Bit definitions for RCSR register in CCM */
493#define CCM_RCSR_NF16B	(1 << 31)
494#define CCM_RCSR_NFMS	(1 << 30)
495
496/* WEIM CS control registers */
497struct mx31_weim_cscr {
498	u32 upper;
499	u32 lower;
500	u32 additional;
501	u32 reserved;
502};
503
504struct mx31_weim {
505	struct mx31_weim_cscr cscr[6];
506};
507
508/* ESD control registers */
509struct esdc_regs {
510	u32 ctl0;
511	u32 cfg0;
512	u32 ctl1;
513	u32 cfg1;
514	u32 misc;
515	u32 dly[5];
516	u32 dlyl;
517};
518
519#endif
520
521#define ARCH_MXC
522
523#define __REG(x)     (*((volatile u32 *)(x)))
524#define __REG16(x)   (*((volatile u16 *)(x)))
525#define __REG8(x)    (*((volatile u8 *)(x)))
526
527#define CCM_BASE	0x53f80000
528#define CCM_CCMR	(CCM_BASE + 0x00)
529#define CCM_PDR0	(CCM_BASE + 0x04)
530#define CCM_PDR1	(CCM_BASE + 0x08)
531#define CCM_RCSR	(CCM_BASE + 0x0c)
532#define CCM_MPCTL	(CCM_BASE + 0x10)
533#define CCM_UPCTL	(CCM_BASE + 0x14)
534#define CCM_SPCTL	(CCM_BASE + 0x18)
535#define CCM_COSR	(CCM_BASE + 0x1C)
536#define CCM_CGR0	(CCM_BASE + 0x20)
537#define CCM_CGR1	(CCM_BASE + 0x24)
538#define CCM_CGR2	(CCM_BASE + 0x28)
539
540#define CCMR_MDS	(1 << 7)
541#define CCMR_SBYCS	(1 << 4)
542#define CCMR_MPE	(1 << 3)
543#define CCMR_PRCS_MASK	(3 << 1)
544#define CCMR_FPM	(1 << 1)
545#define CCMR_CKIH	(2 << 1)
546
547#define MX31_IIM_BASE_ADDR	0x5001C000
548#define IIM_BASE_ADDR		MX31_IIM_BASE_ADDR
549
550#define PDR0_CSI_PODF(x)	(((x) & 0x3f) << 26)
551#define PDR0_CSI_PRDF(x)	(((x) & 0x7) << 23)
552#define PDR0_PER_PODF(x)	(((x) & 0x1f) << 16)
553#define PDR0_HSP_PODF(x)	(((x) & 0x7) << 11)
554#define PDR0_NFC_PODF(x)	(((x) & 0x7) << 8)
555#define PDR0_IPG_PODF(x)	(((x) & 0x3) << 6)
556#define PDR0_MAX_PODF(x)	(((x) & 0x7) << 3)
557#define PDR0_MCU_PODF(x)	((x) & 0x7)
558
559#define PDR1_USB_PRDF(x)	(((x) & 0x3) << 30)
560#define PDR1_USB_PODF(x)	(((x) & 0x7) << 27)
561#define PDR1_FIRI_PRDF(x)	(((x) & 0x7) << 24)
562#define PDR1_FIRI_PODF(x)	(((x) & 0x3f) << 18)
563#define PDR1_SSI2_PRDF(x)	(((x) & 0x7) << 15)
564#define PDR1_SSI2_PODF(x)	(((x) & 0x3f) << 9)
565#define PDR1_SSI1_PRDF(x)	(((x) & 0x7) << 6)
566#define PDR1_SSI1_PODF(x)	((x) & 0x3f)
567
568#define PLL_BRMO(x)		(((x) & 0x1) << 31)
569#define PLL_PD(x)		(((x) & 0xf) << 26)
570#define PLL_MFD(x)		(((x) & 0x3ff) << 16)
571#define PLL_MFI(x)		(((x) & 0xf) << 10)
572#define PLL_MFN(x)		(((x) & 0x3ff) << 0)
573
574#define GET_PDR0_CSI_PODF(x)	(((x) >> 26) & 0x3f)
575#define GET_PDR0_CSI_PRDF(x)	(((x) >> 23) & 0x7)
576#define GET_PDR0_PER_PODF(x)	(((x) >> 16) & 0x1f)
577#define GET_PDR0_HSP_PODF(x)	(((x) >> 11) & 0x7)
578#define GET_PDR0_NFC_PODF(x)	(((x) >> 8) & 0x7)
579#define GET_PDR0_IPG_PODF(x)	(((x) >> 6) & 0x3)
580#define GET_PDR0_MAX_PODF(x)	(((x) >> 3) & 0x7)
581#define GET_PDR0_MCU_PODF(x)	((x) & 0x7)
582
583#define GET_PLL_PD(x)		(((x) >> 26) & 0xf)
584#define GET_PLL_MFD(x)		(((x) >> 16) & 0x3ff)
585#define GET_PLL_MFI(x)		(((x) >> 10) & 0xf)
586#define GET_PLL_MFN(x)		(((x) >> 0) & 0x3ff)
587
588
589#define WEIM_ESDCTL0	0xB8001000
590#define WEIM_ESDCFG0	0xB8001004
591#define WEIM_ESDCTL1	0xB8001008
592#define WEIM_ESDCFG1	0xB800100C
593#define WEIM_ESDMISC	0xB8001010
594
595#define UART1_BASE	0x43F90000
596#define UART2_BASE	0x43F94000
597#define UART3_BASE	0x5000C000
598#define UART4_BASE	0x43FB0000
599#define UART5_BASE	0x43FB4000
600
601#define UART_BASE_ADDR(n)	(			\
602	!!sizeof(struct {				\
603		static_assert((n) >= 1 && (n) <= 5);	\
604		int pad;				\
605		}) * (					\
606	(n) == 1 ? UART1_BASE :				\
607	(n) == 2 ? UART2_BASE :				\
608	(n) == 3 ? UART3_BASE :				\
609	(n) == 4 ? UART4_BASE :				\
610	UART5_BASE_ADDR)				\
611	)
612
613#define I2C1_BASE_ADDR          0x43f80000
614#define I2C1_CLK_OFFSET		26
615#define I2C2_BASE_ADDR          0x43F98000
616#define I2C2_CLK_OFFSET		28
617#define I2C3_BASE_ADDR          0x43f84000
618#define I2C3_CLK_OFFSET		30
619
620#define ESDCTL_SDE			(1 << 31)
621#define ESDCTL_CMD_RW			(0 << 28)
622#define ESDCTL_CMD_PRECHARGE		(1 << 28)
623#define ESDCTL_CMD_AUTOREFRESH		(2 << 28)
624#define ESDCTL_CMD_LOADMODEREG		(3 << 28)
625#define ESDCTL_CMD_MANUALREFRESH	(4 << 28)
626#define ESDCTL_ROW_13			(2 << 24)
627#define ESDCTL_ROW(x)			((x) << 24)
628#define ESDCTL_COL_9			(1 << 20)
629#define ESDCTL_COL(x)			((x) << 20)
630#define ESDCTL_DSIZ(x)			((x) << 16)
631#define ESDCTL_SREFR(x)			((x) << 13)
632#define ESDCTL_PWDT(x)			((x) << 10)
633#define ESDCTL_FP(x)			((x) << 8)
634#define ESDCTL_BL(x)			((x) << 7)
635#define ESDCTL_PRCT(x)			((x) << 0)
636
637#define ESDCTL_BASE_ADDR	0xB8001000
638
639/* 13 fields of the upper CS control register */
640#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
641		cnc, wsc, ew, wws, edc) \
642	((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\
643	 (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\
644	 (wws) << 4 | (edc) << 0)
645/* 12 fields of the lower CS control register */
646#define CSCR_L(oea, oen, ebwa, ebwn, \
647		csa, ebc, dsz, csn, psr, cre, wrap, csen) \
648	((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
649	 (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
650	 (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
651/* 14 fields of the additional CS control register */
652#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
653		wwu, age, cnc2, fce) \
654	((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
655	 (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
656	 (dww) << 6 | (dct) << 4 | (wwu) << 3 |\
657	 (age) << 2 | (cnc2) << 1 | (fce) << 0)
658
659#define WEIM_BASE	0xb8002000
660
661#define IOMUXC_BASE	0x43FAC000
662#define IOMUXC_SW_MUX_CTL(x)	(IOMUXC_BASE + 0xc + (x) * 4)
663#define IOMUXC_SW_PAD_CTL(x)	(IOMUXC_BASE + 0x154 + (x) * 4)
664
665#define IPU_BASE		0x53fc0000
666#define IPU_CONF		IPU_BASE
667
668#define IPU_CONF_PXL_ENDIAN	(1<<8)
669#define IPU_CONF_DU_EN		(1<<7)
670#define IPU_CONF_DI_EN		(1<<6)
671#define IPU_CONF_ADC_EN		(1<<5)
672#define IPU_CONF_SDC_EN		(1<<4)
673#define IPU_CONF_PF_EN		(1<<3)
674#define IPU_CONF_ROT_EN		(1<<2)
675#define IPU_CONF_IC_EN		(1<<1)
676#define IPU_CONF_CSI_EN		(1<<0)
677
678#define ARM_PPMRR		0x40000015
679
680#define WDOG1_BASE_ADDR		0x53FDC000
681
682/*
683 * GPIO
684 */
685#define GPIO1_BASE_ADDR	0x53FCC000
686#define GPIO2_BASE_ADDR	0x53FD0000
687#define GPIO3_BASE_ADDR	0x53FA4000
688#define GPIO_DR		0x00000000	/* data register */
689#define GPIO_GDIR	0x00000004	/* direction register */
690#define GPIO_PSR	0x00000008	/* pad status register */
691
692/*
693 * Signal Multiplexing (IOMUX)
694 */
695
696/* bits in the SW_MUX_CTL registers */
697#define MUX_CTL_OUT_GPIO_DR	(0 << 4)
698#define MUX_CTL_OUT_FUNC	(1 << 4)
699#define MUX_CTL_OUT_ALT1	(2 << 4)
700#define MUX_CTL_OUT_ALT2	(3 << 4)
701#define MUX_CTL_OUT_ALT3	(4 << 4)
702#define MUX_CTL_OUT_ALT4	(5 << 4)
703#define MUX_CTL_OUT_ALT5	(6 << 4)
704#define MUX_CTL_OUT_ALT6	(7 << 4)
705#define MUX_CTL_IN_NONE		(0 << 0)
706#define MUX_CTL_IN_GPIO		(1 << 0)
707#define MUX_CTL_IN_FUNC		(2 << 0)
708#define MUX_CTL_IN_ALT1		(4 << 0)
709#define MUX_CTL_IN_ALT2		(8 << 0)
710
711#define MUX_CTL_FUNC		(MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
712#define MUX_CTL_ALT1		(MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
713#define MUX_CTL_ALT2		(MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
714#define MUX_CTL_GPIO		(MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
715
716/* Register offsets based on IOMUXC_BASE */
717/* 0x00 .. 0x7b */
718#define MUX_CTL_CSPI3_MISO		0x0c
719#define MUX_CTL_CSPI3_SCLK		0x0d
720#define MUX_CTL_CSPI3_SPI_RDY	0x0e
721#define MUX_CTL_CSPI3_MOSI		0x13
722
723#define MUX_CTL_SD1_DATA1	0x18
724#define MUX_CTL_SD1_DATA2	0x19
725#define MUX_CTL_SD1_DATA3	0x1a
726#define MUX_CTL_SD1_CMD		0x1d
727#define MUX_CTL_SD1_CLK		0x1e
728#define MUX_CTL_SD1_DATA0	0x1f
729
730#define MUX_CTL_USBH2_DATA1	0x40
731#define MUX_CTL_USBH2_DIR	0x44
732#define MUX_CTL_USBH2_STP	0x45
733#define MUX_CTL_USBH2_NXT	0x46
734#define MUX_CTL_USBH2_DATA0	0x47
735#define MUX_CTL_USBH2_CLK	0x4B
736
737#define MUX_CTL_TXD2		0x70
738#define MUX_CTL_RTS2		0x71
739#define MUX_CTL_CTS2		0x72
740#define MUX_CTL_RXD2		0x77
741
742#define MUX_CTL_RTS1		0x7c
743#define MUX_CTL_CTS1		0x7d
744#define MUX_CTL_DTR_DCE1	0x7e
745#define MUX_CTL_DSR_DCE1	0x7f
746#define MUX_CTL_CSPI2_SCLK	0x80
747#define MUX_CTL_CSPI2_SPI_RDY	0x81
748#define MUX_CTL_RXD1		0x82
749#define MUX_CTL_TXD1		0x83
750#define MUX_CTL_CSPI2_MISO	0x84
751#define MUX_CTL_CSPI2_SS0	0x85
752#define MUX_CTL_CSPI2_SS1	0x86
753#define MUX_CTL_CSPI2_SS2	0x87
754#define MUX_CTL_CSPI1_SS2	0x88
755#define MUX_CTL_CSPI1_SCLK	0x89
756#define MUX_CTL_CSPI1_SPI_RDY	0x8a
757#define MUX_CTL_CSPI2_MOSI	0x8b
758#define MUX_CTL_CSPI1_MOSI	0x8c
759#define MUX_CTL_CSPI1_MISO	0x8d
760#define MUX_CTL_CSPI1_SS0	0x8e
761#define MUX_CTL_CSPI1_SS1	0x8f
762#define MUX_CTL_STXD6		0x90
763#define MUX_CTL_SRXD6		0x91
764#define MUX_CTL_SCK6		0x92
765#define MUX_CTL_SFS6		0x93
766
767#define MUX_CTL_STXD3		0x9C
768#define MUX_CTL_SRXD3		0x9D
769#define MUX_CTL_SCK3		0x9E
770#define MUX_CTL_SFS3		0x9F
771
772#define MUX_CTL_NFC_WP		0xD0
773#define MUX_CTL_NFC_CE		0xD1
774#define MUX_CTL_NFC_RB		0xD2
775#define MUX_CTL_NFC_WE		0xD4
776#define MUX_CTL_NFC_RE		0xD5
777#define MUX_CTL_NFC_ALE		0xD6
778#define MUX_CTL_NFC_CLE		0xD7
779
780
781#define MUX_CTL_CAPTURE		0x150
782#define MUX_CTL_COMPARE		0x151
783
784/*
785 * Helper macros for the MUX_[contact name]__[pin function] macros
786 */
787#define IOMUX_MODE_POS 9
788#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
789
790/*
791 * These macros can be used in mx31_gpio_mux() and have the form
792 * MUX_[contact name]__[pin function]
793 */
794#define MUX_RXD1__UART1_RXD_MUX	IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
795#define MUX_TXD1__UART1_TXD_MUX	IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
796#define MUX_RTS1__UART1_RTS_B	IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
797#define MUX_CTS1__UART1_CTS_B	IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
798
799#define MUX_RXD2__UART2_RXD_MUX	IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC)
800#define MUX_TXD2__UART2_TXD_MUX	IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC)
801#define MUX_RTS2__UART2_RTS_B	IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC)
802#define MUX_CTS2__UART2_CTS_B	IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC)
803
804#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
805#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
806#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
807#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
808#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
809#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
810	IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
811#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
812
813#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
814#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
815#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
816#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
817#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
818#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
819	IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
820#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
821
822#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
823#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
824
825/* PAD control registers for SDR/DDR */
826#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B	(IOMUXC_BASE + 0x26C)
827#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0	(IOMUXC_BASE + 0x270)
828#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS		(IOMUXC_BASE + 0x274)
829#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA		(IOMUXC_BASE + 0x278)
830#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4		(IOMUXC_BASE + 0x27C)
831#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1		(IOMUXC_BASE + 0x280)
832#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1		(IOMUXC_BASE + 0x284)
833#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2	(IOMUXC_BASE + 0x288)
834#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31	(IOMUXC_BASE + 0x28C)
835#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28	(IOMUXC_BASE + 0x290)
836#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25	(IOMUXC_BASE + 0x294)
837#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22	(IOMUXC_BASE + 0x298)
838#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19	(IOMUXC_BASE + 0x29C)
839#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16	(IOMUXC_BASE + 0x2A0)
840#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13	(IOMUXC_BASE + 0x2A4)
841#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10		(IOMUXC_BASE + 0x2A8)
842#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7		(IOMUXC_BASE + 0x2AC)
843#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4		(IOMUXC_BASE + 0x2B0)
844#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1		(IOMUXC_BASE + 0x2B4)
845#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1		(IOMUXC_BASE + 0x2B8)
846#define IOMUXC_SW_PAD_CTL_A21_A22_A23		(IOMUXC_BASE + 0x2BC)
847#define IOMUXC_SW_PAD_CTL_A18_A19_A20		(IOMUXC_BASE + 0x2C0)
848#define IOMUXC_SW_PAD_CTL_A15_A16_A17		(IOMUXC_BASE + 0x2C4)
849#define IOMUXC_SW_PAD_CTL_A12_A13_A14		(IOMUXC_BASE + 0x2C8)
850#define IOMUXC_SW_PAD_CTL_A10_MA10_A11		(IOMUXC_BASE + 0x2CC)
851#define IOMUXC_SW_PAD_CTL_A7_A8_A9		(IOMUXC_BASE + 0x2D0)
852#define IOMUXC_SW_PAD_CTL_A4_A5_A6		(IOMUXC_BASE + 0x2D4)
853#define IOMUXC_SW_PAD_CTL_A1_A2_A3		(IOMUXC_BASE + 0x2D8)
854#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0		(IOMUXC_BASE + 0x2DC)
855
856/*
857 * Memory regions and CS
858 */
859#define IPU_MEM_BASE	0x70000000
860#define CSD0_BASE	0x80000000
861#define CSD1_BASE	0x90000000
862#define CS0_BASE	0xA0000000
863#define CS1_BASE	0xA8000000
864#define CS2_BASE	0xB0000000
865#define CS3_BASE	0xB2000000
866#define CS4_BASE	0xB4000000
867#define CS4_PSRAM_BASE	0xB5000000
868#define CS5_BASE	0xB6000000
869#define PCMCIA_MEM_BASE	0xC0000000
870
871/*
872 * NAND controller
873 */
874#define NFC_BASE_ADDR	0xB8000000
875
876/* SD card controller */
877#define SDHC1_BASE_ADDR	0x50004000
878#define SDHC2_BASE_ADDR	0x50008000
879
880/*
881 * Internal RAM (16KB)
882 */
883#define	IRAM_BASE_ADDR	0x1FFFC000
884#define IRAM_SIZE	(16 * 1024)
885
886#define MX31_AIPS1_BASE_ADDR	0x43f00000
887#define IMX_USB_BASE		(MX31_AIPS1_BASE_ADDR + 0x88000)
888#define IMX_USB_PORT_OFFSET	0x200
889
890/*
891 * CSPI register definitions
892 */
893#define MXC_SPI_BASE_ADDRESSES \
894	0x43fa4000, \
895	0x50010000, \
896	0x53f84000,
897
898/*
899 * Generic timer support
900 */
901#ifdef CONFIG_MX31_CLK32
902#define	CFG_SYS_TIMER_RATE	CONFIG_MX31_CLK32
903#else
904#define	CFG_SYS_TIMER_RATE	32768
905#endif
906
907#endif /* __ASM_ARCH_MX31_IMX_REGS_H */
908