1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2013
4 * David Feng <fenghua@phytium.com.cn>
5 */
6
7#include <asm-offsets.h>
8#include <config.h>
9#include <linux/linkage.h>
10#include <asm/macro.h>
11#include <asm/armv8/mmu.h>
12
13/*************************************************************************
14 *
15 * Startup Code (reset vector)
16 *
17 *************************************************************************/
18
19.globl	_start
20_start:
21#if defined(CONFIG_LINUX_KERNEL_IMAGE_HEADER)
22#include <asm/boot0-linux-kernel-header.h>
23#elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
24/*
25 * Various SoCs need something special and SoC-specific up front in
26 * order to boot, allow them to set that in their boot0.h file and then
27 * use it here.
28 */
29#include <asm/arch/boot0.h>
30#else
31	b	reset
32#endif
33
34	.align 3
35
36.globl	_TEXT_BASE
37_TEXT_BASE:
38	.quad	CONFIG_TEXT_BASE
39
40/*
41 * These are defined in the linker script.
42 */
43.globl	_end_ofs
44_end_ofs:
45	.quad	_end - _start
46
47.globl	_bss_start_ofs
48_bss_start_ofs:
49	.quad	__bss_start - _start
50
51.globl	_bss_end_ofs
52_bss_end_ofs:
53	.quad	__bss_end - _start
54
55reset:
56	/* Allow the board to save important registers */
57	b	save_boot_params
58.globl	save_boot_params_ret
59save_boot_params_ret:
60
61#if CONFIG_POSITION_INDEPENDENT && !defined(CONFIG_SPL_BUILD)
62	/* Verify that we're 4K aligned.  */
63	adr	x0, _start
64	ands	x0, x0, #0xfff
65	b.eq	1f
660:
67	/*
68	 * FATAL, can't continue.
69	 * U-Boot needs to be loaded at a 4K aligned address.
70	 *
71	 * We use ADRP and ADD to load some symbol addresses during startup.
72	 * The ADD uses an absolute (non pc-relative) lo12 relocation
73	 * thus requiring 4K alignment.
74	 */
75	wfi
76	b	0b
771:
78
79	/*
80	 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
81	 * executed at a different address than it was linked at.
82	 */
83pie_fixup:
84	adr	x0, _start		/* x0 <- Runtime value of _start */
85	ldr	x1, _TEXT_BASE		/* x1 <- Linked value of _start */
86	subs	x9, x0, x1		/* x9 <- Run-vs-link offset */
87	beq	pie_fixup_done
88	adrp    x2, __rel_dyn_start     /* x2 <- Runtime &__rel_dyn_start */
89	add     x2, x2, #:lo12:__rel_dyn_start
90	adrp    x3, __rel_dyn_end       /* x3 <- Runtime &__rel_dyn_end */
91	add     x3, x3, #:lo12:__rel_dyn_end
92pie_fix_loop:
93	ldp	x0, x1, [x2], #16	/* (x0, x1) <- (Link location, fixup) */
94	ldr	x4, [x2], #8		/* x4 <- addend */
95	cmp	w1, #1027		/* relative fixup? */
96	bne	pie_skip_reloc
97	/* relative fix: store addend plus offset at dest location */
98	add	x0, x0, x9
99	add	x4, x4, x9
100	str	x4, [x0]
101pie_skip_reloc:
102	cmp	x2, x3
103	b.lo	pie_fix_loop
104pie_fixup_done:
105#endif
106
107#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
108.macro	set_vbar, regname, reg
109	msr	\regname, \reg
110.endm
111	adr	x0, vectors
112#else
113.macro	set_vbar, regname, reg
114.endm
115#endif
116	/*
117	 * Could be EL3/EL2/EL1, Initial State:
118	 * Little Endian, MMU Disabled, i/dCache Disabled
119	 */
120	switch_el x1, 3f, 2f, 1f
1213:	set_vbar vbar_el3, x0
122	mrs	x0, scr_el3
123	orr	x0, x0, #0xf			/* SCR_EL3.NS|IRQ|FIQ|EA */
124	msr	scr_el3, x0
125	msr	cptr_el3, xzr			/* Enable FP/SIMD */
126	b	0f
1272:	mrs	x1, hcr_el2
128	tbnz	x1, #HCR_EL2_E2H_BIT, 1f	/* HCR_EL2.E2H */
129	orr	x1, x1, #HCR_EL2_AMO_EL2	/* Route SErrors to EL2 */
130	msr	hcr_el2, x1
131	set_vbar vbar_el2, x0
132	mov	x0, #0x33ff
133	msr	cptr_el2, x0			/* Enable FP/SIMD */
134	b	0f
1351:	set_vbar vbar_el1, x0
136	mov	x0, #3 << 20
137	msr	cpacr_el1, x0			/* Enable FP/SIMD */
1380:
139	msr	daifclr, #0x4			/* Unmask SError interrupts */
140
141#if CONFIG_COUNTER_FREQUENCY
142	branch_if_not_highest_el x0, 4f
143	ldr	x0, =CONFIG_COUNTER_FREQUENCY
144	msr	cntfrq_el0, x0			/* Initialize CNTFRQ */
145#endif
146
1474:	isb
148
149	/*
150	 * Enable SMPEN bit for coherency.
151	 * This register is not architectural but at the moment
152	 * this bit should be set for A53/A57/A72.
153	 */
154#ifdef CONFIG_ARMV8_SET_SMPEN
155	switch_el x1, 3f, 1f, 1f
1563:
157	mrs     x0, S3_1_c15_c2_1               /* cpuectlr_el1 */
158	orr     x0, x0, #0x40
159	msr     S3_1_c15_c2_1, x0
160	isb
1611:
162#endif
163
164	/* Apply ARM core specific erratas */
165	bl	apply_core_errata
166
167	/*
168	 * Cache/BPB/TLB Invalidate
169	 * i-cache is invalidated before enabled in icache_enable()
170	 * tlb is invalidated before mmu is enabled in dcache_enable()
171	 * d-cache is invalidated before enabled in dcache_enable()
172	 */
173
174	/* Processor specific initialization */
175	bl	lowlevel_init
176
177#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
178	branch_if_master x0, master_cpu
179	b	spin_table_secondary_jump
180	/* never return */
181#elif defined(CONFIG_ARMV8_MULTIENTRY)
182	branch_if_master x0, master_cpu
183
184	/*
185	 * Slave CPUs
186	 */
187slave_cpu:
188	wfe
189	ldr	x1, =CPU_RELEASE_ADDR
190	ldr	x0, [x1]
191	cbz	x0, slave_cpu
192	br	x0			/* branch to the given address */
193#endif /* CONFIG_ARMV8_MULTIENTRY */
194master_cpu:
195	msr	SPSel, #1		/* make sure we use SP_ELx */
196	bl	_main
197
198/*-----------------------------------------------------------------------*/
199
200WEAK(apply_core_errata)
201
202	mov	x29, lr			/* Save LR */
203	/* For now, we support Cortex-A53, Cortex-A57 specific errata */
204
205	/* Check if we are running on a Cortex-A53 core */
206	branch_if_a53_core x0, apply_a53_core_errata
207
208	/* Check if we are running on a Cortex-A57 core */
209	branch_if_a57_core x0, apply_a57_core_errata
2100:
211	mov	lr, x29			/* Restore LR */
212	ret
213
214apply_a53_core_errata:
215
216#ifdef CONFIG_ARM_ERRATA_855873
217	mrs	x0, midr_el1
218	tst	x0, #(0xf << 20)
219	b.ne	0b
220
221	mrs	x0, midr_el1
222	and	x0, x0, #0xf
223	cmp	x0, #3
224	b.lt	0b
225
226	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
227	/* Enable data cache clean as data cache clean/invalidate */
228	orr	x0, x0, #1 << 44
229	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
230	isb
231#endif
232	b 0b
233
234apply_a57_core_errata:
235
236#ifdef CONFIG_ARM_ERRATA_828024
237	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
238	/* Disable non-allocate hint of w-b-n-a memory type */
239	orr	x0, x0, #1 << 49
240	/* Disable write streaming no L1-allocate threshold */
241	orr	x0, x0, #3 << 25
242	/* Disable write streaming no-allocate threshold */
243	orr	x0, x0, #3 << 27
244	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
245	isb
246#endif
247
248#ifdef CONFIG_ARM_ERRATA_826974
249	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
250	/* Disable speculative load execution ahead of a DMB */
251	orr	x0, x0, #1 << 59
252	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
253	isb
254#endif
255
256#ifdef CONFIG_ARM_ERRATA_833471
257	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
258	/* FPSCR write flush.
259	 * Note that in some cases where a flush is unnecessary this
260	    could impact performance. */
261	orr	x0, x0, #1 << 38
262	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
263	isb
264#endif
265
266#ifdef CONFIG_ARM_ERRATA_829520
267	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
268	/* Disable Indirect Predictor bit will prevent this erratum
269	    from occurring
270	 * Note that in some cases where a flush is unnecessary this
271	    could impact performance. */
272	orr	x0, x0, #1 << 4
273	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
274	isb
275#endif
276
277#ifdef CONFIG_ARM_ERRATA_833069
278	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
279	/* Disable Enable Invalidates of BTB bit */
280	and	x0, x0, #0xE
281	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
282	isb
283#endif
284	b 0b
285ENDPROC(apply_core_errata)
286
287/*-----------------------------------------------------------------------*/
288
289WEAK(lowlevel_init)
290	mov	x29, lr			/* Save LR */
291
292#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
293	branch_if_slave x0, 1f
294	ldr	x0, =GICD_BASE
295	bl	gic_init_secure
2961:
297#if defined(CONFIG_GICV3)
298	ldr	x0, =GICR_BASE
299	bl	gic_init_secure_percpu
300#elif defined(CONFIG_GICV2)
301	ldr	x0, =GICD_BASE
302	ldr	x1, =GICC_BASE
303	bl	gic_init_secure_percpu
304#endif
305#endif
306
307#ifdef CONFIG_ARMV8_MULTIENTRY
308	branch_if_master x0, 2f
309
310	/*
311	 * Slave should wait for master clearing spin table.
312	 * This sync prevent salves observing incorrect
313	 * value of spin table and jumping to wrong place.
314	 */
315#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
316#ifdef CONFIG_GICV2
317	ldr	x0, =GICC_BASE
318#endif
319	bl	gic_wait_for_interrupt
320#endif
321
322	/*
323	 * All slaves will enter EL2 and optionally EL1.
324	 */
325	adr	x4, lowlevel_in_el2
326	ldr	x5, =ES_TO_AARCH64
327	bl	armv8_switch_to_el2
328
329lowlevel_in_el2:
330#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
331	adr	x4, lowlevel_in_el1
332	ldr	x5, =ES_TO_AARCH64
333	bl	armv8_switch_to_el1
334
335lowlevel_in_el1:
336#endif
337
338#endif /* CONFIG_ARMV8_MULTIENTRY */
339
3402:
341	mov	lr, x29			/* Restore LR */
342	ret
343ENDPROC(lowlevel_init)
344
345WEAK(smp_kick_all_cpus)
346	/* Kick secondary cpus up by SGI 0 interrupt */
347#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
348	ldr	x0, =GICD_BASE
349	b	gic_kick_secondary_cpus
350#endif
351	ret
352ENDPROC(smp_kick_all_cpus)
353
354/*-----------------------------------------------------------------------*/
355
356ENTRY(c_runtime_cpu_setup)
357#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
358	/* Relocate vBAR */
359	adr	x0, vectors
360	switch_el x1, 3f, 2f, 1f
3613:	msr	vbar_el3, x0
362	b	0f
3632:	msr	vbar_el2, x0
364	b	0f
3651:	msr	vbar_el1, x0
3660:
367#endif
368
369	ret
370ENDPROC(c_runtime_cpu_setup)
371
372WEAK(save_boot_params)
373#if (IS_ENABLED(CONFIG_BLOBLIST))
374	/* Calculate the PC-relative address of saved_args */
375	adr	x9, saved_args_offset
376	ldr	w10, saved_args_offset
377	add	x9, x9, w10, sxtw
378
379	stp	x0, x1, [x9]
380	stp	x2, x3, [x9, #16]
381#endif
382	b	save_boot_params_ret	/* back to my caller */
383ENDPROC(save_boot_params)
384
385#if (IS_ENABLED(CONFIG_BLOBLIST))
386saved_args_offset:
387	.long	saved_args - .	/* offset from current code to save_args */
388
389	.section .data
390	.align 2
391	.global saved_args
392saved_args:
393	.rept 4
394	.dword 0
395	.endr
396END(saved_args)
397#endif
398