1/* $OpenBSD: psycho.c,v 1.84 2024/03/29 21:29:33 miod Exp $ */ 2/* $NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp $ */ 3 4/* 5 * Copyright (c) 1999, 2000 Matthew R. Green 6 * Copyright (c) 2003 Henric Jungheim 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 25 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 27 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33/* 34 * Support for `psycho' and `psycho+' UPA to PCI bridge and 35 * UltraSPARC IIi and IIe `sabre' PCI controllers. 36 */ 37 38#include <sys/param.h> 39#include <sys/device.h> 40#include <sys/errno.h> 41#include <sys/extent.h> 42#include <sys/malloc.h> 43#include <sys/systm.h> 44#include <sys/time.h> 45#include <sys/timetc.h> 46 47#include <uvm/uvm_extern.h> 48 49#define _SPARC_BUS_DMA_PRIVATE 50#include <machine/bus.h> 51#include <machine/autoconf.h> 52#include <machine/openfirm.h> 53#include <machine/psl.h> 54 55#include <dev/pci/pcivar.h> 56#include <dev/pci/pcireg.h> 57 58#include <sparc64/dev/iommureg.h> 59#include <sparc64/dev/iommuvar.h> 60#include <sparc64/dev/psychoreg.h> 61#include <sparc64/dev/psychovar.h> 62#include <sparc64/dev/starfire.h> 63#include <sparc64/sparc64/cache.h> 64 65#ifdef DEBUG 66#define PDB_PROM 0x01 67#define PDB_BUSMAP 0x02 68#define PDB_INTR 0x04 69#define PDB_CONF 0x08 70int psycho_debug = ~0; 71#define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 72#else 73#define DPRINTF(l, s) 74#endif 75 76pci_chipset_tag_t psycho_alloc_chipset(struct psycho_pbm *, int, 77 pci_chipset_tag_t); 78void psycho_get_bus_range(int, int *); 79void psycho_get_ranges(int, struct psycho_ranges **, int *); 80void psycho_set_intr(struct psycho_softc *, int, void *, 81 u_int64_t *, u_int64_t *, const char *); 82bus_space_tag_t psycho_alloc_bus_tag(struct psycho_pbm *, 83 const char *, int, int, int); 84 85/* Interrupt handlers */ 86int psycho_ue(void *); 87int psycho_ce(void *); 88int psycho_bus_a(void *); 89int psycho_bus_b(void *); 90int psycho_bus_error(struct psycho_softc *, int); 91int psycho_powerfail(void *); 92int psycho_wakeup(void *); 93 94/* IOMMU support */ 95void psycho_iommu_init(struct psycho_softc *, int); 96 97/* 98 * bus space and bus dma support for UltraSPARC `psycho'. note that most 99 * of the bus dma support is provided by the iommu dvma controller. 100 */ 101int psycho_bus_map(bus_space_tag_t, bus_space_tag_t, bus_addr_t, 102 bus_size_t, int, bus_space_handle_t *); 103paddr_t psycho_bus_mmap(bus_space_tag_t, bus_space_tag_t, bus_addr_t, off_t, 104 int, int); 105bus_addr_t psycho_bus_addr(bus_space_tag_t, bus_space_tag_t, 106 bus_space_handle_t); 107void *psycho_intr_establish(bus_space_tag_t, bus_space_tag_t, int, int, int, 108 int (*)(void *), void *, const char *); 109 110int psycho_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, bus_size_t, int, 111 bus_size_t, bus_size_t, int, bus_dmamap_t *); 112void psycho_sabre_dvmamap_sync(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 113 bus_size_t, bus_size_t, int); 114void psycho_map_psycho(struct psycho_softc *, int, bus_addr_t, bus_size_t, 115 bus_addr_t, bus_size_t); 116int psycho_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 117void psycho_identify_pbm(struct psycho_softc *sc, struct psycho_pbm *pp, 118 struct pcibus_attach_args *pa); 119 120int psycho_conf_size(pci_chipset_tag_t, pcitag_t); 121pcireg_t psycho_conf_read(pci_chipset_tag_t, pcitag_t, int); 122void psycho_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 123 124/* base pci_chipset */ 125extern struct sparc_pci_chipset _sparc_pci_chipset; 126 127u_int stick_get_timecount(struct timecounter *); 128 129struct timecounter stick_timecounter = { 130 .tc_get_timecount = stick_get_timecount, 131 .tc_counter_mask = ~0u, 132 .tc_frequency = 0, 133 .tc_name = "stick", 134 .tc_quality = 1000, 135 .tc_priv = NULL, 136 .tc_user = 0, 137}; 138 139/* 140 * autoconfiguration 141 */ 142int psycho_match(struct device *, void *, void *); 143void psycho_attach(struct device *, struct device *, void *); 144int psycho_print(void *aux, const char *p); 145 146 147const struct cfattach psycho_ca = { 148 sizeof(struct psycho_softc), psycho_match, psycho_attach 149}; 150 151struct cfdriver psycho_cd = { 152 NULL, "psycho", DV_DULL 153}; 154 155/* 156 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 157 * single PCI bus and does not have a streaming buffer. It often has an APB 158 * (advanced PCI bridge) connected to it, which was designed specifically for 159 * the IIi. The APB lets the IIi handle two independent PCI buses, and 160 * appears as two "simba"'s underneath the sabre. 161 * 162 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 163 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 164 * "psycho+" controls both a 64-bit 33MHz and a 64-bit 66MHz PCI bus. You 165 * will usually find a "psycho+" since I don't think the original "psycho" 166 * ever shipped, and if it did it would be in the U30. 167 * 168 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 169 * both part of the same IC, they only have a single register space. As such, 170 * they need to be configured together, even though the autoconfiguration will 171 * attach them separately. 172 * 173 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 174 * as pci1 and pci2, although they have been implemented with other PCI bus 175 * numbers on some machines. 176 * 177 * On UltraII machines, there can be any number of "psycho+" ICs, each 178 * providing two PCI buses. 179 * 180 * 181 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 182 * the values of the following interrupts in this order: 183 * 184 * PCI Bus Error (30) 185 * DMA UE (2e) 186 * DMA CE (2f) 187 * Power Fail (25) 188 * 189 * We really should attach handlers for each. 190 * 191 */ 192#define ROM_PCI_NAME "pci" 193 194struct psycho_type { 195 char *p_name; 196 int p_type; 197} psycho_types[] = { 198 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 199 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 200 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 201 { "pci108e,a000", PSYCHO_MODE_SABRE }, 202 { "pci108e,a001", PSYCHO_MODE_SABRE }, 203 { "pci10cf,138f", PSYCHO_MODE_CMU_CH }, 204 { "pci10cf,1390", PSYCHO_MODE_CMU_CH }, 205 { NULL, 0 } 206}; 207 208int 209psycho_match(struct device *parent, void *match, void *aux) 210{ 211 struct mainbus_attach_args *ma = aux; 212 struct psycho_type *ptype; 213 char *str; 214 215 /* match on a name of "pci" and a sabre or a psycho */ 216 if (strcmp(ma->ma_name, ROM_PCI_NAME) != 0) 217 return (0); 218 219 for (ptype = psycho_types; ptype->p_name != NULL; ptype++) { 220 str = getpropstring(ma->ma_node, "model"); 221 if (strcmp(str, ptype->p_name) == 0) 222 return (1); 223 str = getpropstring(ma->ma_node, "compatible"); 224 if (strcmp(str, ptype->p_name) == 0) 225 return (1); 226 } 227 return (0); 228} 229 230/* 231 * SUNW,psycho initialization ... 232 * - find the per-psycho registers 233 * - figure out the IGN. 234 * - find our partner psycho 235 * - configure ourselves 236 * - bus range, bus, 237 * - get interrupt-map and interrupt-map-mask 238 * - setup the chipsets. 239 * - if we're the first of the pair, initialise the IOMMU, otherwise 240 * just copy its tags and addresses. 241 */ 242void 243psycho_attach(struct device *parent, struct device *self, void *aux) 244{ 245 struct psycho_softc *sc = (struct psycho_softc *)self; 246 struct psycho_softc *osc = NULL; 247 struct psycho_pbm *pp; 248 struct pcibus_attach_args pba; 249 struct mainbus_attach_args *ma = aux; 250 u_int64_t csr; 251 int psycho_br[2], n; 252 struct psycho_type *ptype; 253 char buf[32]; 254 u_int stick_rate; 255 256 sc->sc_node = ma->ma_node; 257 sc->sc_bustag = ma->ma_bustag; 258 sc->sc_dmatag = ma->ma_dmatag; 259 260 /* 261 * call the model-specific initialization routine. 262 */ 263 264 for (ptype = psycho_types; ptype->p_name != NULL; ptype++) { 265 char *str; 266 267 str = getpropstring(ma->ma_node, "model"); 268 if (strcmp(str, ptype->p_name) == 0) 269 break; 270 str = getpropstring(ma->ma_node, "compatible"); 271 if (strcmp(str, ptype->p_name) == 0) 272 break; 273 } 274 if (ptype->p_name == NULL) 275 panic("psycho_attach: unknown model?"); 276 sc->sc_mode = ptype->p_type; 277 278 /* 279 * The psycho gets three register banks: 280 * (0) per-PBM configuration and status registers 281 * (1) per-PBM PCI configuration space, containing only the 282 * PBM 256-byte PCI header 283 * (2) the shared psycho configuration registers (struct psychoreg) 284 * 285 * XXX use the prom address for the psycho registers? we do so far. 286 */ 287 288 /* Register layouts are different. stuupid. */ 289 if (sc->sc_mode == PSYCHO_MODE_PSYCHO || 290 sc->sc_mode == PSYCHO_MODE_CMU_CH) { 291 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 292 293 if (ma->ma_naddress > 2) { 294 psycho_map_psycho(sc, 0, 295 ma->ma_address[2], sizeof(struct psychoreg), 296 ma->ma_address[0], sizeof(struct pci_ctl)); 297 } else if (ma->ma_nreg > 2) { 298 psycho_map_psycho(sc, 1, 299 ma->ma_reg[2].ur_paddr, ma->ma_reg[2].ur_len, 300 ma->ma_reg[0].ur_paddr, ma->ma_reg[0].ur_len); 301 } else 302 panic("psycho_attach: %d not enough registers", 303 ma->ma_nreg); 304 } else { 305 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 306 307 if (ma->ma_naddress) { 308 psycho_map_psycho(sc, 0, 309 ma->ma_address[0], sizeof(struct psychoreg), 310 ma->ma_address[0] + 311 offsetof(struct psychoreg, psy_pcictl[0]), 312 sizeof(struct pci_ctl)); 313 } else if (ma->ma_nreg) { 314 psycho_map_psycho(sc, 1, 315 ma->ma_reg[0].ur_paddr, ma->ma_reg[0].ur_len, 316 ma->ma_reg[0].ur_paddr + 317 offsetof(struct psychoreg, psy_pcictl[0]), 318 sizeof(struct pci_ctl)); 319 } else 320 panic("psycho_attach: %d not enough registers", 321 ma->ma_nreg); 322 } 323 324 csr = psycho_psychoreg_read(sc, psy_csr); 325 sc->sc_ign = INTMAP_IGN; /* APB IGN is always 0x1f << 6 = 0x7c */ 326 if (sc->sc_mode == PSYCHO_MODE_PSYCHO || 327 sc->sc_mode == PSYCHO_MODE_CMU_CH) 328 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 329 330 printf(": %s, impl %d, version %d, ign %x\n", ptype->p_name, 331 PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), sc->sc_ign); 332 333 /* 334 * Match other psycho's that are already configured against 335 * the base physical address. This will be the same for a 336 * pair of devices that share register space. 337 */ 338 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 339 struct psycho_softc *asc = 340 (struct psycho_softc *)psycho_cd.cd_devs[n]; 341 342 if (asc == NULL || asc == sc) 343 /* This entry is not there or it is me */ 344 continue; 345 346 if (asc->sc_basepaddr != sc->sc_basepaddr) 347 /* This is an unrelated psycho */ 348 continue; 349 350 /* Found partner */ 351 osc = asc; 352 break; 353 } 354 355 /* Oh, dear. OK, lets get started */ 356 357 /* 358 * Setup the PCI control register 359 */ 360 csr = psycho_pcictl_read(sc, pci_csr); 361 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | 362 PCICTL_4ENABLE; 363 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 364 PCICTL_RTRYWAIT); 365 psycho_pcictl_write(sc, pci_csr, csr); 366 367 /* 368 * Allocate our psycho_pbm 369 */ 370 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, 371 M_NOWAIT | M_ZERO); 372 if (pp == NULL) 373 panic("could not allocate psycho pbm"); 374 375 pp->pp_sc = sc; 376 377 /* grab the psycho ranges */ 378 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 379 380 /* get the bus-range for the psycho */ 381 psycho_get_bus_range(sc->sc_node, psycho_br); 382 383 bzero(&pba, sizeof(pba)); 384 pba.pba_domain = pci_ndomains++; 385 pba.pba_bus = psycho_br[0]; 386 387 printf("%s: bus range %u-%u, PCI bus %d\n", sc->sc_dev.dv_xname, 388 psycho_br[0], psycho_br[1], psycho_br[0]); 389 390 pp->pp_pcictl = sc->sc_pcictl; 391 392 /* allocate our tags */ 393 pp->pp_memt = psycho_alloc_mem_tag(pp); 394 pp->pp_iot = psycho_alloc_io_tag(pp); 395 if (sc->sc_mode == PSYCHO_MODE_CMU_CH) 396 pp->pp_dmat = ma->ma_dmatag; 397 else 398 pp->pp_dmat = psycho_alloc_dma_tag(pp); 399 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 400 (pp->pp_iot ? PCI_FLAGS_IO_ENABLED : 0); 401 402 /* allocate a chipset for this */ 403 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 404 405 /* setup the rest of the psycho pbm */ 406 pba.pba_pc = pp->pp_pc; 407 408 /* 409 * And finally, if we're a sabre or the first of a pair of psycho's to 410 * arrive here, start up the IOMMU and get a config space tag. 411 */ 412 413 if (osc == NULL) { 414 uint64_t timeo; 415 416 /* Initialize Starfire PC interrupt translation. */ 417 if (OF_getprop(findroot(), "name", buf, sizeof(buf)) > 0 && 418 strcmp(buf, "SUNW,Ultra-Enterprise-10000") == 0) 419 starfire_pc_ittrans_init(ma->ma_upaid); 420 421 /* 422 * Establish handlers for interesting interrupts.... 423 * 424 * XXX We need to remember these and remove this to support 425 * hotplug on the UPA/FHC bus. 426 * 427 * XXX Not all controllers have these, but installing them 428 * is better than trying to sort through this mess. 429 */ 430 psycho_set_intr(sc, 15, psycho_ue, 431 psycho_psychoreg_vaddr(sc, ue_int_map), 432 psycho_psychoreg_vaddr(sc, ue_clr_int), "ue"); 433 if (sc->sc_mode == PSYCHO_MODE_PSYCHO || 434 sc->sc_mode == PSYCHO_MODE_SABRE) { 435 psycho_set_intr(sc, 1, psycho_ce, 436 psycho_psychoreg_vaddr(sc, ce_int_map), 437 psycho_psychoreg_vaddr(sc, ce_clr_int), "ce"); 438 psycho_set_intr(sc, 15, psycho_bus_a, 439 psycho_psychoreg_vaddr(sc, pciaerr_int_map), 440 psycho_psychoreg_vaddr(sc, pciaerr_clr_int), 441 "bus_a"); 442 } 443#if 0 444 psycho_set_intr(sc, 15, psycho_powerfail, 445 psycho_psychoreg_vaddr(sc, power_int_map), 446 psycho_psychoreg_vaddr(sc, power_clr_int), "powerfail"); 447#endif 448 if (sc->sc_mode == PSYCHO_MODE_PSYCHO || 449 sc->sc_mode == PSYCHO_MODE_CMU_CH) { 450 psycho_set_intr(sc, 15, psycho_bus_b, 451 psycho_psychoreg_vaddr(sc, pciberr_int_map), 452 psycho_psychoreg_vaddr(sc, pciberr_clr_int), 453 "bus_b"); 454 } 455 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 456 psycho_set_intr(sc, 1, psycho_wakeup, 457 psycho_psychoreg_vaddr(sc, pwrmgt_int_map), 458 psycho_psychoreg_vaddr(sc, pwrmgt_clr_int), 459 "wakeup"); 460 } 461 462 /* 463 * Apparently a number of machines with psycho and psycho+ 464 * controllers have interrupt latency issues. We'll try 465 * setting the interrupt retry timeout to 0xff which gives us 466 * a retry of 3-6 usec (which is what sysio is set to) for the 467 * moment, which seems to help alleviate this problem. 468 */ 469 timeo = psycho_psychoreg_read(sc, intr_retry_timer); 470 if (timeo > 0xfff) { 471#ifdef DEBUG 472 printf("decreasing interrupt retry timeout " 473 "from %lx to 0xff\n", (long)timeo); 474#endif 475 psycho_psychoreg_write(sc, intr_retry_timer, 0xff); 476 } 477 478 /* 479 * Setup IOMMU and PCI configuration if we're the first 480 * of a pair of psycho's to arrive here. 481 * 482 * We should calculate a TSB size based on the amount of RAM, 483 * number of bus controllers, and number and type of child 484 * devices. 485 * 486 * For the moment, 32KB should be more than enough. 487 */ 488 sc->sc_is = malloc(sizeof(struct iommu_state), 489 M_DEVBUF, M_NOWAIT | M_ZERO); 490 if (sc->sc_is == NULL) 491 panic("psycho_attach: malloc iommu_state"); 492 493 if (getproplen(sc->sc_node, "no-streaming-cache") < 0) { 494 struct strbuf_ctl *sb = &pp->pp_sb; 495 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 496 497 /* 498 * Initialize the strbuf_ctl. 499 * 500 * The flush sync buffer must be 64-byte aligned. 501 */ 502 503 sb->sb_flush = (void *)(va & ~0x3f); 504 505 sb->sb_bustag = sc->sc_bustag; 506 if (bus_space_subregion(sc->sc_bustag, sc->sc_pcictl, 507 offsetof(struct pci_ctl, pci_strbuf), 508 sizeof(struct iommu_strbuf), 509 &sb->sb_sb)) { 510 printf("STC0 subregion failed\n"); 511 sb->sb_flush = 0; 512 } 513 } 514 515 /* Point out iommu at the strbuf_ctl. */ 516 sc->sc_is->is_sb[0] = &pp->pp_sb; 517 518 /* CMU-CH doesn't have an IOMMU. */ 519 if (sc->sc_mode != PSYCHO_MODE_CMU_CH) { 520 printf("%s: ", sc->sc_dev.dv_xname); 521 psycho_iommu_init(sc, 2); 522 } 523 524 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 525 if (bus_space_map(sc->sc_configtag, 526 sc->sc_basepaddr, 0x01000000, 0, &sc->sc_configaddr)) 527 panic("can't map psycho PCI configuration space"); 528 } else { 529 /* Just copy IOMMU state, config tag and address */ 530 sc->sc_is = osc->sc_is; 531 sc->sc_configtag = osc->sc_configtag; 532 sc->sc_configaddr = osc->sc_configaddr; 533 534 if (getproplen(sc->sc_node, "no-streaming-cache") < 0) { 535 struct strbuf_ctl *sb = &pp->pp_sb; 536 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 537 538 /* 539 * Initialize the strbuf_ctl. 540 * 541 * The flush sync buffer must be 64-byte aligned. 542 */ 543 544 sb->sb_flush = (void *)(va & ~0x3f); 545 546 sb->sb_bustag = sc->sc_bustag; 547 if (bus_space_subregion(sc->sc_bustag, sc->sc_pcictl, 548 offsetof(struct pci_ctl, pci_strbuf), 549 sizeof(struct iommu_strbuf), 550 &sb->sb_sb)) { 551 printf("STC1 subregion failed\n"); 552 sb->sb_flush = 0; 553 } 554 555 /* Point out iommu at the strbuf_ctl. */ 556 sc->sc_is->is_sb[1] = sb; 557 } 558 559 /* Point out iommu at the strbuf_ctl. */ 560 sc->sc_is->is_sb[1] = &pp->pp_sb; 561 562 printf("%s: ", sc->sc_dev.dv_xname); 563 printf("dvma map %x-%x", sc->sc_is->is_dvmabase, 564 sc->sc_is->is_dvmaend); 565#ifdef DEBUG 566 printf(", iotdb %llx-%llx", 567 (unsigned long long)sc->sc_is->is_ptsb, 568 (unsigned long long)(sc->sc_is->is_ptsb + 569 (PAGE_SIZE << sc->sc_is->is_tsbsize))); 570#endif 571 iommu_reset(sc->sc_is); 572 printf("\n"); 573 } 574 575 /* 576 * The UltraSPARC IIe has new STICK logic that provides a 577 * timebase counter that doesn't scale with processor 578 * frequency. Use it to provide a timecounter. 579 */ 580 stick_rate = getpropint(findroot(), "stick-frequency", 0); 581 if (stick_rate > 0 && sc->sc_mode == PSYCHO_MODE_SABRE) { 582 stick_timecounter.tc_frequency = stick_rate; 583 stick_timecounter.tc_priv = sc; 584 tc_init(&stick_timecounter); 585 } 586 587 /* 588 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 589 */ 590 pba.pba_busname = "pci"; 591#if 0 592 pba.pba_flags = sc->sc_psycho_this->pp_flags; 593#endif 594 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 595 pba.pba_iot = sc->sc_psycho_this->pp_iot; 596 pba.pba_memt = sc->sc_psycho_this->pp_memt; 597 pba.pba_pc->bustag = sc->sc_configtag; 598 pba.pba_pc->bushandle = sc->sc_configaddr; 599 pba.pba_pc->conf_size = psycho_conf_size; 600 pba.pba_pc->conf_read = psycho_conf_read; 601 pba.pba_pc->conf_write = psycho_conf_write; 602 pba.pba_pc->intr_map = psycho_intr_map; 603 604 if (sc->sc_mode == PSYCHO_MODE_PSYCHO || 605 sc->sc_mode == PSYCHO_MODE_CMU_CH) 606 psycho_identify_pbm(sc, pp, &pba); 607 else 608 pp->pp_id = PSYCHO_PBM_UNKNOWN; 609 610 config_found(self, &pba, psycho_print); 611} 612 613void 614psycho_identify_pbm(struct psycho_softc *sc, struct psycho_pbm *pp, 615 struct pcibus_attach_args *pa) 616{ 617 vaddr_t pci_va = (vaddr_t)bus_space_vaddr(sc->sc_bustag, sc->sc_pcictl); 618 paddr_t pci_pa; 619 620 if (pmap_extract(pmap_kernel(), pci_va, &pci_pa) == 0) 621 pp->pp_id = PSYCHO_PBM_UNKNOWN; 622 else switch(pci_pa & 0xffff) { 623 case 0x2000: 624 pp->pp_id = PSYCHO_PBM_A; 625 break; 626 case 0x4000: 627 pp->pp_id = PSYCHO_PBM_B; 628 break; 629 default: 630 pp->pp_id = PSYCHO_PBM_UNKNOWN; 631 break; 632 } 633} 634 635void 636psycho_map_psycho(struct psycho_softc* sc, int do_map, bus_addr_t reg_addr, 637 bus_size_t reg_size, bus_addr_t pci_addr, bus_size_t pci_size) 638{ 639 if (do_map) { 640 if (bus_space_map(sc->sc_bustag, 641 reg_addr, reg_size, 0, &sc->sc_regsh)) 642 panic("psycho_attach: cannot map regs"); 643 644 if (pci_addr >= reg_addr && 645 pci_addr + pci_size <= reg_addr + reg_size) { 646 if (bus_space_subregion(sc->sc_bustag, sc->sc_regsh, 647 pci_addr - reg_addr, pci_size, &sc->sc_pcictl)) 648 panic("psycho_map_psycho: map ctl"); 649 } 650 else if (bus_space_map(sc->sc_bustag, pci_addr, pci_size, 651 0, &sc->sc_pcictl)) 652 panic("psycho_map_psycho: cannot map pci"); 653 } else { 654 if (bus_space_map(sc->sc_bustag, reg_addr, reg_size, 655 BUS_SPACE_MAP_PROMADDRESS, &sc->sc_regsh)) 656 panic("psycho_map_psycho: cannot map ctl"); 657 if (bus_space_map(sc->sc_bustag, pci_addr, pci_size, 658 BUS_SPACE_MAP_PROMADDRESS, &sc->sc_pcictl)) 659 panic("psycho_map_psycho: cannot map pci"); 660 } 661} 662 663int 664psycho_print(void *aux, const char *p) 665{ 666 if (p == NULL) 667 return (UNCONF); 668 return (QUIET); 669} 670 671void 672psycho_set_intr(struct psycho_softc *sc, int ipl, void *handler, 673 u_int64_t *mapper, u_int64_t *clearer, const char *suffix) 674{ 675 struct intrhand *ih; 676 677 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT | M_ZERO); 678 if (ih == NULL) 679 panic("couldn't malloc intrhand"); 680 ih->ih_arg = sc; 681 ih->ih_map = mapper; 682 ih->ih_clr = clearer; 683 ih->ih_fun = handler; 684 ih->ih_pil = ipl; 685 ih->ih_number = INTVEC(*(ih->ih_map)); 686 snprintf(ih->ih_name, sizeof(ih->ih_name), 687 "%s:%s", sc->sc_dev.dv_xname, suffix); 688 689 DPRINTF(PDB_INTR, ( 690 "\ninstalling handler %p arg %p for %s with number %x pil %u", 691 ih->ih_fun, ih->ih_arg, sc->sc_dev.dv_xname, ih->ih_number, 692 ih->ih_pil)); 693 694 intr_establish(ih); 695} 696 697/* 698 * PCI bus support 699 */ 700 701/* 702 * allocate a PCI chipset tag and set its cookie. 703 */ 704pci_chipset_tag_t 705psycho_alloc_chipset(struct psycho_pbm *pp, int node, pci_chipset_tag_t pc) 706{ 707 pci_chipset_tag_t npc; 708 709 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 710 if (npc == NULL) 711 panic("could not allocate pci_chipset_tag_t"); 712 memcpy(npc, pc, sizeof *pc); 713 npc->cookie = pp; 714 npc->rootnode = node; 715 716 return (npc); 717} 718 719/* 720 * grovel the OBP for various psycho properties 721 */ 722void 723psycho_get_bus_range(int node, int *brp) 724{ 725 int n, error; 726 727 error = getprop(node, "bus-range", sizeof(*brp), &n, (void **)&brp); 728 if (error) 729 panic("could not get psycho bus-range, error %d", error); 730 if (n != 2) 731 panic("broken psycho bus-range"); 732 DPRINTF(PDB_PROM, 733 ("psycho debug: got `bus-range' for node %08x: %u - %u\n", 734 node, brp[0], brp[1])); 735} 736 737void 738psycho_get_ranges(int node, struct psycho_ranges **rp, int *np) 739{ 740 741 if (getprop(node, "ranges", sizeof(**rp), np, (void **)rp)) 742 panic("could not get psycho ranges"); 743 DPRINTF(PDB_PROM, 744 ("psycho debug: got `ranges' for node %08x: %d entries\n", 745 node, *np)); 746} 747 748/* 749 * Interrupt handlers. 750 */ 751 752int 753psycho_ue(void *arg) 754{ 755 struct psycho_softc *sc = arg; 756 unsigned long long afsr = psycho_psychoreg_read(sc, psy_ue_afsr); 757 unsigned long long afar = psycho_psychoreg_read(sc, psy_ue_afar); 758 759 /* 760 * It's uncorrectable. Dump the regs and panic. 761 */ 762 panic("%s: uncorrectable DMA error AFAR %llx (pa=%lx tte=%llx/%llx) " 763 "AFSR %llx", sc->sc_dev.dv_xname, afar, 764 iommu_extract(sc->sc_is, (vaddr_t)afar), 765 iommu_lookup_tte(sc->sc_is, (vaddr_t)afar), 766 iommu_fetch_tte(sc->sc_is, (paddr_t)afar), 767 afsr); 768 return (1); 769} 770 771int 772psycho_ce(void *arg) 773{ 774 struct psycho_softc *sc = arg; 775 u_int64_t afar, afsr; 776 777 /* 778 * It's correctable. Dump the regs and continue. 779 */ 780 781 afar = psycho_psychoreg_read(sc, psy_ce_afar); 782 afsr = psycho_psychoreg_read(sc, psy_ce_afsr); 783 784 printf("%s: correctable DMA error AFAR %llx AFSR %llx\n", 785 sc->sc_dev.dv_xname, afar, afsr); 786 787 /* Clear error. */ 788 psycho_psychoreg_write(sc, psy_ce_afsr, 789 afsr & (PSY_CEAFSR_PDRD | PSY_CEAFSR_PDWR | 790 PSY_CEAFSR_SDRD | PSY_CEAFSR_SDWR)); 791 792 return (1); 793} 794 795int 796psycho_bus_error(struct psycho_softc *sc, int bus) 797{ 798 u_int64_t afsr, afar, bits; 799 800 afar = psycho_psychoreg_read(sc, psy_pcictl[bus].pci_afar); 801 afsr = psycho_psychoreg_read(sc, psy_pcictl[bus].pci_afsr); 802 803 bits = afsr & (PSY_PCIAFSR_PMA | PSY_PCIAFSR_PTA | PSY_PCIAFSR_PTRY | 804 PSY_PCIAFSR_PPERR | PSY_PCIAFSR_SMA | PSY_PCIAFSR_STA | 805 PSY_PCIAFSR_STRY | PSY_PCIAFSR_SPERR); 806 807 if (bits == 0) 808 return (0); 809 810 /* 811 * It's uncorrectable. Dump the regs and panic. 812 */ 813 printf("%s: PCI bus %c error AFAR %llx (pa=%llx) AFSR %llx\n", 814 sc->sc_dev.dv_xname, 'A' + bus, (long long)afar, 815 (long long)iommu_extract(sc->sc_is, (vaddr_t)afar), 816 (long long)afsr); 817 818 psycho_psychoreg_write(sc, psy_pcictl[bus].pci_afsr, bits); 819 return (1); 820} 821 822int 823psycho_bus_a(void *arg) 824{ 825 struct psycho_softc *sc = arg; 826 827 return (psycho_bus_error(sc, 0)); 828} 829 830int 831psycho_bus_b(void *arg) 832{ 833 struct psycho_softc *sc = arg; 834 835 return (psycho_bus_error(sc, 1)); 836} 837 838int 839psycho_powerfail(void *arg) 840{ 841 /* 842 * We lost power. Try to shut down NOW. 843 */ 844 panic("Power Failure Detected"); 845 /* NOTREACHED */ 846 return (1); 847} 848 849int 850psycho_wakeup(void *arg) 851{ 852 struct psycho_softc *sc = arg; 853 854 /* 855 * Gee, we don't really have a framework to deal with this 856 * properly. 857 */ 858 printf("%s: power management wakeup\n", sc->sc_dev.dv_xname); 859 return (1); 860} 861 862/* 863 * initialise the IOMMU.. 864 */ 865void 866psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 867{ 868 struct iommu_state *is = sc->sc_is; 869 int *vdma = NULL, nitem; 870 u_int32_t iobase = -1; 871 char *name; 872 873 /* punch in our copies */ 874 is->is_bustag = sc->sc_bustag; 875 bus_space_subregion(sc->sc_bustag, sc->sc_regsh, 876 offsetof(struct psychoreg, psy_iommu), sizeof(struct iommureg), 877 &is->is_iommu); 878 879 /* 880 * Separate the men from the boys. If it has a `virtual-dma' 881 * property, use it. 882 */ 883 if (!getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 884 (void **)&vdma)) { 885 /* Damn. Gotta use these values. */ 886 iobase = vdma[0]; 887#define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break 888 switch (vdma[1]) { 889 TSBCASE(1); TSBCASE(2); TSBCASE(3); 890 TSBCASE(4); TSBCASE(5); TSBCASE(6); 891 default: 892 printf("bogus tsb size %x, using 7\n", vdma[1]); 893 TSBCASE(7); 894 } 895#undef TSBCASE 896 DPRINTF(PDB_CONF, ("psycho_iommu_init: iobase=0x%x\n", iobase)); 897 free(vdma, M_DEVBUF, 0); 898 } else { 899 DPRINTF(PDB_CONF, ("psycho_iommu_init: getprop failed, " 900 "iobase=0x%x, tsbsize=%d\n", iobase, tsbsize)); 901 } 902 903 /* give us a nice name.. */ 904 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 905 if (name == NULL) 906 panic("couldn't malloc iommu name"); 907 snprintf(name, 32, "%s dvma", sc->sc_dev.dv_xname); 908 909 iommu_init(name, &iommu_hw_default, is, tsbsize, iobase); 910} 911 912/* 913 * below here is bus space and bus dma support 914 */ 915 916bus_space_tag_t 917psycho_alloc_mem_tag(struct psycho_pbm *pp) 918{ 919 return (psycho_alloc_bus_tag(pp, "mem", 920 0x02, /* 32-bit mem space (where's the #define???) */ 921 ASI_PRIMARY, ASI_PRIMARY_LITTLE)); 922} 923 924bus_space_tag_t 925psycho_alloc_io_tag(struct psycho_pbm *pp) 926{ 927 return (psycho_alloc_bus_tag(pp, "io", 928 0x01, /* IO space (where's the #define???) */ 929 ASI_PHYS_NON_CACHED_LITTLE, ASI_PHYS_NON_CACHED)); 930} 931 932bus_space_tag_t 933psycho_alloc_config_tag(struct psycho_pbm *pp) 934{ 935 return (psycho_alloc_bus_tag(pp, "cfg", 936 0x00, /* Config space (where's the #define???) */ 937 ASI_PHYS_NON_CACHED_LITTLE, ASI_PHYS_NON_CACHED)); 938} 939 940bus_space_tag_t 941psycho_alloc_bus_tag(struct psycho_pbm *pp, 942 const char *name, int ss, int asi, int sasi) 943{ 944 struct psycho_softc *sc = pp->pp_sc; 945 struct sparc_bus_space_tag *bt; 946 947 bt = malloc(sizeof(*bt), M_DEVBUF, M_NOWAIT | M_ZERO); 948 if (bt == NULL) 949 panic("could not allocate psycho bus tag"); 950 951 snprintf(bt->name, sizeof(bt->name), "%s-pbm_%s(%d-%2.2x)", 952 sc->sc_dev.dv_xname, name, ss, asi); 953 954 bt->cookie = pp; 955 bt->parent = sc->sc_bustag; 956 bt->default_type = ss; 957 bt->asi = asi; 958 bt->sasi = sasi; 959 bt->sparc_bus_map = psycho_bus_map; 960 bt->sparc_bus_mmap = psycho_bus_mmap; 961 bt->sparc_bus_addr = psycho_bus_addr; 962 bt->sparc_intr_establish = psycho_intr_establish; 963 964 return (bt); 965} 966 967bus_dma_tag_t 968psycho_alloc_dma_tag(struct psycho_pbm *pp) 969{ 970 struct psycho_softc *sc = pp->pp_sc; 971 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 972 973 dt = (bus_dma_tag_t)malloc(sizeof(struct sparc_bus_dma_tag), 974 M_DEVBUF, M_NOWAIT | M_ZERO); 975 if (dt == NULL) 976 panic("could not allocate psycho dma tag"); 977 978 dt->_cookie = pp; 979 dt->_parent = pdt; 980 dt->_dmamap_create = psycho_dmamap_create; 981 dt->_dmamap_destroy = iommu_dvmamap_destroy; 982 dt->_dmamap_load = iommu_dvmamap_load; 983 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 984 dt->_dmamap_unload = iommu_dvmamap_unload; 985 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 986 dt->_dmamap_sync = iommu_dvmamap_sync; 987 else 988 dt->_dmamap_sync = psycho_sabre_dvmamap_sync; 989 dt->_dmamem_alloc = iommu_dvmamem_alloc; 990 dt->_dmamem_free = iommu_dvmamem_free; 991 992 return (dt); 993} 994 995/* 996 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 997 * PCI physical addresses. 998 */ 999 1000int 1001psycho_bus_map(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t offset, 1002 bus_size_t size, int flags, bus_space_handle_t *hp) 1003{ 1004 struct psycho_pbm *pp = t->cookie; 1005 int i, ss; 1006 1007 DPRINTF(PDB_BUSMAP, ("\npsycho_bus_map: type %d off %llx sz %llx " 1008 "flags %d", t->default_type, (unsigned long long)offset, 1009 (unsigned long long)size, flags)); 1010 1011 ss = t->default_type; 1012 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 1013 1014 if (t->parent == 0 || t->parent->sparc_bus_map == 0) { 1015 printf("\npsycho_bus_map: invalid parent"); 1016 return (EINVAL); 1017 } 1018 1019 t = t->parent; 1020 1021 if (flags & BUS_SPACE_MAP_PROMADDRESS) { 1022 return ((*t->sparc_bus_map) 1023 (t, t0, offset, size, flags, hp)); 1024 } 1025 1026 for (i = 0; i < pp->pp_nrange; i++) { 1027 bus_addr_t paddr; 1028 1029 if (((pp->pp_range[i].cspace >> 24) & 0x03) != ss) 1030 continue; 1031 1032 paddr = pp->pp_range[i].phys_lo + offset; 1033 paddr |= ((bus_addr_t)pp->pp_range[i].phys_hi) << 32; 1034 DPRINTF(PDB_BUSMAP, 1035 ("\n_psycho_bus_map: mapping paddr space %lx offset %lx " 1036 "paddr %llx", 1037 (long)ss, (long)offset, 1038 (unsigned long long)paddr)); 1039 return ((*t->sparc_bus_map)(t, t0, paddr, size, flags, hp)); 1040 } 1041 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 1042 return (EINVAL); 1043} 1044 1045paddr_t 1046psycho_bus_mmap(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t paddr, 1047 off_t off, int prot, int flags) 1048{ 1049 bus_addr_t offset = paddr; 1050 struct psycho_pbm *pp = t->cookie; 1051 int i, ss; 1052 1053 ss = t->default_type; 1054 1055 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_mmap: prot %d flags %d pa %llx", 1056 prot, flags, (unsigned long long)paddr)); 1057 1058 if (t->parent == 0 || t->parent->sparc_bus_mmap == 0) { 1059 printf("\npsycho_bus_mmap: invalid parent"); 1060 return (-1); 1061 } 1062 1063 t = t->parent; 1064 1065 for (i = 0; i < pp->pp_nrange; i++) { 1066 bus_addr_t paddr; 1067 1068 if (((pp->pp_range[i].cspace >> 24) & 0x03) != ss) 1069 continue; 1070 1071 paddr = pp->pp_range[i].phys_lo + offset; 1072 paddr |= ((bus_addr_t)pp->pp_range[i].phys_hi) << 32; 1073 DPRINTF(PDB_BUSMAP, ("\npsycho_bus_mmap: mapping paddr " 1074 "space %lx offset %lx paddr %llx", 1075 (long)ss, (long)offset, 1076 (unsigned long long)paddr)); 1077 return ((*t->sparc_bus_mmap)(t, t0, paddr, off, prot, flags)); 1078 } 1079 1080 return (-1); 1081} 1082 1083bus_addr_t 1084psycho_bus_addr(bus_space_tag_t t, bus_space_tag_t t0, bus_space_handle_t h) 1085{ 1086 struct psycho_pbm *pp = t->cookie; 1087 bus_addr_t addr; 1088 int i, ss; 1089 1090 ss = t->default_type; 1091 1092 if (t->parent == 0 || t->parent->sparc_bus_addr == 0) { 1093 printf("\npsycho_bus_addr: invalid parent"); 1094 return (-1); 1095 } 1096 1097 t = t->parent; 1098 1099 addr = ((*t->sparc_bus_addr)(t, t0, h)); 1100 if (addr == -1) 1101 return (-1); 1102 1103 for (i = 0; i < pp->pp_nrange; i++) { 1104 if (((pp->pp_range[i].cspace >> 24) & 0x03) != ss) 1105 continue; 1106 1107 return (BUS_ADDR_PADDR(addr) - pp->pp_range[i].phys_lo); 1108 } 1109 1110 return (-1); 1111} 1112 1113int 1114psycho_conf_size(pci_chipset_tag_t pc, pcitag_t tag) 1115{ 1116 return PCI_CONFIG_SPACE_SIZE; 1117} 1118 1119pcireg_t 1120psycho_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 1121{ 1122 struct cpu_info *ci = curcpu(); 1123 pcireg_t val; 1124 int s; 1125 1126 s = splhigh(); 1127 __membar("#Sync"); 1128 ci->ci_pci_probe = 1; 1129 val = bus_space_read_4(pc->bustag, pc->bushandle, 1130 PCITAG_OFFSET(tag) + reg); 1131 __membar("#Sync"); 1132 if (ci->ci_pci_fault) 1133 val = 0xffffffff; 1134 ci->ci_pci_probe = ci->ci_pci_fault = 0; 1135 splx(s); 1136 1137 return (val); 1138} 1139 1140void 1141psycho_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 1142{ 1143 bus_space_write_4(pc->bustag, pc->bushandle, 1144 PCITAG_OFFSET(tag) + reg, data); 1145} 1146 1147/* 1148 * Bus-specific interrupt mapping 1149 */ 1150int 1151psycho_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 1152{ 1153 struct psycho_pbm *pp = pa->pa_pc->cookie; 1154 struct psycho_softc *sc = pp->pp_sc; 1155 u_int dev; 1156 1157 if (*ihp != (pci_intr_handle_t)-1) { 1158 *ihp |= sc->sc_ign; 1159 return (0); 1160 } 1161 1162 /* 1163 * We didn't find a PROM mapping for this interrupt. Try to 1164 * construct one ourselves based on the swizzled interrupt pin 1165 * and the interrupt mapping for PCI slots documented in the 1166 * UltraSPARC-IIi User's Manual. 1167 */ 1168 1169 if (pa->pa_intrpin == 0) 1170 return (-1); 1171 1172 /* 1173 * This deserves some documentation. Should anyone 1174 * have anything official looking, please speak up. 1175 */ 1176 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1177 pp->pp_id == PSYCHO_PBM_B) 1178 dev = PCITAG_DEV(pa->pa_intrtag) - 2; 1179 else 1180 dev = PCITAG_DEV(pa->pa_intrtag) - 1; 1181 1182 *ihp = (pa->pa_intrpin - 1) & INTMAP_PCIINT; 1183 *ihp |= ((pp->pp_id == PSYCHO_PBM_B) ? INTMAP_PCIBUS : 0); 1184 *ihp |= (dev << 2) & INTMAP_PCISLOT; 1185 *ihp |= sc->sc_ign; 1186 1187 return (0); 1188} 1189 1190/* 1191 * install an interrupt handler for a PCI device 1192 */ 1193void * 1194psycho_intr_establish(bus_space_tag_t t, bus_space_tag_t t0, int ihandle, 1195 int level, int flags, int (*handler)(void *), void *arg, const char *what) 1196{ 1197 struct psycho_pbm *pp = t->cookie; 1198 struct psycho_softc *sc = pp->pp_sc; 1199 struct intrhand *ih; 1200 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 1201 int64_t intrmap = 0; 1202 int ino; 1203 long vec = INTVEC(ihandle); 1204 1205 /* 1206 * Hunt through all the interrupt mapping regs to look for our 1207 * interrupt vector. 1208 * 1209 * XXX We only compare INOs rather than IGNs since the firmware may 1210 * not provide the IGN and the IGN is constant for all device on that 1211 * PCI controller. This could cause problems for the FFB/external 1212 * interrupt which has a full vector that can be set arbitrarily. 1213 */ 1214 1215 DPRINTF(PDB_INTR, 1216 ("\npsycho_intr_establish: ihandle %x vec %lx", ihandle, vec)); 1217 ino = INTINO(vec); 1218 DPRINTF(PDB_INTR, (" ino %x", ino)); 1219 1220 /* If the device didn't ask for an IPL, use the one encoded. */ 1221 if (level == IPL_NONE) 1222 level = INTLEV(vec); 1223 /* If it still has no level, print a warning and assign IPL 2 */ 1224 if (level == IPL_NONE) { 1225 printf("ERROR: no IPL, setting IPL 2.\n"); 1226 level = 2; 1227 } 1228 1229 if (flags & BUS_INTR_ESTABLISH_SOFTINTR) 1230 goto found; 1231 1232 DPRINTF(PDB_INTR, 1233 ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", 1234 (long)ino, intrlev[ino])); 1235 1236 /* 1237 * First look for PCI interrupts, otherwise the PCI A slot 0 1238 * INTA# interrupt might match an unused non-PCI (obio) 1239 * interrupt. 1240 */ 1241 1242 for (intrmapptr = psycho_psychoreg_vaddr(sc, pcia_slot0_int), 1243 intrclrptr = psycho_psychoreg_vaddr(sc, pcia0_clr_int[0]); 1244 intrmapptr <= (volatile u_int64_t *) 1245 psycho_psychoreg_vaddr(sc, pcib_slot3_int); 1246 intrmapptr++, intrclrptr += 4) { 1247 /* Skip PCI-A Slot 2 and PCI-A Slot 3 on psycho's */ 1248 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1249 (intrmapptr == 1250 psycho_psychoreg_vaddr(sc, pcia_slot2_int) || 1251 intrmapptr == 1252 psycho_psychoreg_vaddr(sc, pcia_slot3_int))) 1253 continue; 1254 1255 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1256 intrclrptr += vec & 0x3; 1257 goto found; 1258 } 1259 } 1260 1261 /* Now hunt through obio. */ 1262 for (intrmapptr = psycho_psychoreg_vaddr(sc, scsi_int_map), 1263 intrclrptr = psycho_psychoreg_vaddr(sc, scsi_clr_int); 1264 intrmapptr < (volatile u_int64_t *) 1265 psycho_psychoreg_vaddr(sc, ffb0_int_map); 1266 intrmapptr++, intrclrptr++) { 1267 if (INTINO(*intrmapptr) == ino) 1268 goto found; 1269 } 1270 1271 printf("Cannot find interrupt vector %lx\n", vec); 1272 return (NULL); 1273 1274found: 1275 ih = bus_intr_allocate(t0, handler, arg, ino | sc->sc_ign, level, 1276 intrmapptr, intrclrptr, what); 1277 if (ih == NULL) { 1278 printf("Cannot allocate interrupt vector %lx\n", vec); 1279 return (NULL); 1280 } 1281 1282 DPRINTF(PDB_INTR, ( 1283 "\ninstalling handler %p arg %p with number %x pil %u", 1284 ih->ih_fun, ih->ih_arg, ih->ih_number, ih->ih_pil)); 1285 1286 if (flags & BUS_INTR_ESTABLISH_MPSAFE) 1287 ih->ih_mpsafe = 1; 1288 1289 intr_establish(ih); 1290 1291 /* 1292 * Enable the interrupt now we have the handler installed. 1293 * Read the current value as we can't change it besides the 1294 * valid bit so make sure only this bit is changed. 1295 * 1296 * XXXX --- we really should use bus_space for this. 1297 */ 1298 if (intrmapptr) { 1299 intrmap = *intrmapptr; 1300 DPRINTF(PDB_INTR, ("; read intrmap = %016llx", 1301 (unsigned long long)intrmap)); 1302 1303 /* Enable the interrupt */ 1304 intrmap |= INTMAP_V; 1305 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1306 DPRINTF(PDB_INTR, ("; writing intrmap = %016llx", 1307 (unsigned long long)intrmap)); 1308 *intrmapptr = intrmap; 1309 DPRINTF(PDB_INTR, ("; reread intrmap = %016llx", 1310 (unsigned long long)(intrmap = *intrmapptr))); 1311 } 1312 return (ih); 1313} 1314 1315/* 1316 * hooks into the iommu dvma calls. 1317 */ 1318int 1319psycho_dmamap_create(bus_dma_tag_t t, bus_dma_tag_t t0, bus_size_t size, 1320 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 1321 bus_dmamap_t *dmamp) 1322{ 1323 struct psycho_pbm *pp = t->_cookie; 1324 1325 return (iommu_dvmamap_create(t, t0, &pp->pp_sb, size, nsegments, 1326 maxsegsz, boundary, flags, dmamp)); 1327} 1328 1329void 1330psycho_sabre_dvmamap_sync(bus_dma_tag_t t, bus_dma_tag_t t0, bus_dmamap_t map, 1331 bus_size_t offset, bus_size_t len, int ops) 1332{ 1333 struct psycho_pbm *pp = t->_cookie; 1334 struct psycho_softc *sc = pp->pp_sc; 1335 1336 if (ops & BUS_DMASYNC_POSTREAD) 1337 psycho_psychoreg_read(sc, pci_dma_write_sync); 1338 1339 if (ops & (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_PREWRITE)) 1340 __membar("#MemIssue"); 1341} 1342 1343u_int 1344stick_get_timecount(struct timecounter *tc) 1345{ 1346 struct psycho_softc *sc = tc->tc_priv; 1347 1348 return psycho_psychoreg_read(sc, stick_reg_low); 1349} 1350