1#if defined(__SUNPRO_C) && defined(__sparcv9)
2# define ABI64  /* They've said -xarch=v9 at command line */
3#elif defined(__GNUC__) && defined(__arch64__)
4# define ABI64  /* They've said -m64 at command line */
5#endif
6
7#ifdef ABI64
8  .register	%g2,#scratch
9  .register	%g3,#scratch
10# define	FRAME	-192
11# define	BIAS	2047
12#else
13# define	FRAME	-96
14# define	BIAS	0
15#endif
16
17.global	_sparcv9_vis1_probe
18.align	8
19_sparcv9_vis1_probe:
20	add	%sp,BIAS+2,%o1
21	.word	0xc19a5a40	!ldda	[%o1]ASI_FP16_P,%f0
22	retl
23	.word	0x81b00d80	!fxor	%f0,%f0,%f0
24.type	_sparcv9_vis1_probe,#function
25.size	_sparcv9_vis1_probe,.-_sparcv9_vis1_probe
26
27! Probe and instrument VIS1 instruction. Output is number of cycles it
28! takes to execute rdtick and pair of VIS1 instructions. US-Tx VIS unit
29! is slow (documented to be 6 cycles on T2) and the core is in-order
30! single-issue, it should be possible to distinguish Tx reliably...
31! Observed return values are:
32!
33!	UltraSPARC IIe		7
34!	UltraSPARC III		7
35!	UltraSPARC T1		24
36!
37! Numbers for T2 and SPARC64 V-VII are more than welcomed.
38!
39! It would be possible to detect specifically US-T1 by instrumenting
40! fmul8ulx16, which is emulated on T1 and as such accounts for quite
41! a lot of %tick-s, couple of thousand on Linux...
42.global	_sparcv9_vis1_instrument
43.align	8
44_sparcv9_vis1_instrument:
45	.word	0x91410000	!rd	%tick,%o0
46	.word	0x81b00d80	!fxor	%f0,%f0,%f0
47	.word	0x85b08d82	!fxor	%f2,%f2,%f2
48	.word	0x93410000	!rd	%tick,%o1
49	.word	0x81b00d80	!fxor	%f0,%f0,%f0
50	.word	0x85b08d82	!fxor	%f2,%f2,%f2
51	.word	0x95410000	!rd	%tick,%o2
52	.word	0x81b00d80	!fxor	%f0,%f0,%f0
53	.word	0x85b08d82	!fxor	%f2,%f2,%f2
54	.word	0x97410000	!rd	%tick,%o3
55	.word	0x81b00d80	!fxor	%f0,%f0,%f0
56	.word	0x85b08d82	!fxor	%f2,%f2,%f2
57	.word	0x99410000	!rd	%tick,%o4
58
59	! calculate intervals
60	sub	%o1,%o0,%o0
61	sub	%o2,%o1,%o1
62	sub	%o3,%o2,%o2
63	sub	%o4,%o3,%o3
64
65	! find minimum value
66	cmp	%o0,%o1
67	.word	0x38680002	!bgu,a	%xcc,.+8
68	mov	%o1,%o0
69	cmp	%o0,%o2
70	.word	0x38680002	!bgu,a	%xcc,.+8
71	mov	%o2,%o0
72	cmp	%o0,%o3
73	.word	0x38680002	!bgu,a	%xcc,.+8
74	mov	%o3,%o0
75
76	retl
77	nop
78.type	_sparcv9_vis1_instrument,#function
79.size	_sparcv9_vis1_instrument,.-_sparcv9_vis1_instrument
80
81.global	_sparcv9_vis2_probe
82.align	8
83_sparcv9_vis2_probe:
84	retl
85	.word	0x81b00980	!bshuffle	%f0,%f0,%f0
86.type	_sparcv9_vis2_probe,#function
87.size	_sparcv9_vis2_probe,.-_sparcv9_vis2_probe
88
89.global	_sparcv9_fmadd_probe
90.align	8
91_sparcv9_fmadd_probe:
92	.word	0x81b00d80	!fxor	%f0,%f0,%f0
93	.word	0x85b08d82	!fxor	%f2,%f2,%f2
94	retl
95	.word	0x81b80440	!fmaddd	%f0,%f0,%f2,%f0
96.type	_sparcv9_fmadd_probe,#function
97.size	_sparcv9_fmadd_probe,.-_sparcv9_fmadd_probe
98
99.section	".init",#alloc,#execinstr
100	call	OPENSSL_cpuid_setup
101	nop
102