1/* tc-h8300.c -- Assemble code for the Renesas H8/300 2 Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 3 2001, 2002, 2003, 2004 Free Software Foundation, Inc. 4 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to the Free 19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 20 02111-1307, USA. */ 21 22/* Written By Steve Chamberlain <sac@cygnus.com>. */ 23 24#include <stdio.h> 25#include "as.h" 26#include "subsegs.h" 27#include "bfd.h" 28 29#ifdef BFD_ASSEMBLER 30#include "dwarf2dbg.h" 31#endif 32 33#define DEFINE_TABLE 34#define h8_opcodes ops 35#include "opcode/h8300.h" 36#include "safe-ctype.h" 37 38#ifdef OBJ_ELF 39#include "elf/h8.h" 40#endif 41 42const char comment_chars[] = ";"; 43const char line_comment_chars[] = "#"; 44const char line_separator_chars[] = ""; 45 46static void sbranch (int); 47static void h8300hmode (int); 48static void h8300smode (int); 49static void h8300hnmode (int); 50static void h8300snmode (int); 51static void h8300sxmode (int); 52static void h8300sxnmode (int); 53static void pint (int); 54 55int Hmode; 56int Smode; 57int Nmode; 58int SXmode; 59 60#define PSIZE (Hmode && !Nmode ? L_32 : L_16) 61 62static int bsize = L_8; /* Default branch displacement. */ 63 64struct h8_instruction 65{ 66 int length; 67 int noperands; 68 int idx; 69 int size; 70 const struct h8_opcode *opcode; 71}; 72 73static struct h8_instruction *h8_instructions; 74 75static void 76h8300hmode (int arg ATTRIBUTE_UNUSED) 77{ 78 Hmode = 1; 79 Smode = 0; 80#ifdef BFD_ASSEMBLER 81 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h)) 82 as_warn (_("could not set architecture and machine")); 83#endif 84} 85 86static void 87h8300smode (int arg ATTRIBUTE_UNUSED) 88{ 89 Smode = 1; 90 Hmode = 1; 91#ifdef BFD_ASSEMBLER 92 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s)) 93 as_warn (_("could not set architecture and machine")); 94#endif 95} 96 97static void 98h8300hnmode (int arg ATTRIBUTE_UNUSED) 99{ 100 Hmode = 1; 101 Smode = 0; 102 Nmode = 1; 103#ifdef BFD_ASSEMBLER 104 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn)) 105 as_warn (_("could not set architecture and machine")); 106#endif 107} 108 109static void 110h8300snmode (int arg ATTRIBUTE_UNUSED) 111{ 112 Smode = 1; 113 Hmode = 1; 114 Nmode = 1; 115#ifdef BFD_ASSEMBLER 116 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn)) 117 as_warn (_("could not set architecture and machine")); 118#endif 119} 120 121static void 122h8300sxmode (int arg ATTRIBUTE_UNUSED) 123{ 124 Smode = 1; 125 Hmode = 1; 126 SXmode = 1; 127#ifdef BFD_ASSEMBLER 128 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx)) 129 as_warn (_("could not set architecture and machine")); 130#endif 131} 132 133static void 134h8300sxnmode (int arg ATTRIBUTE_UNUSED) 135{ 136 Smode = 1; 137 Hmode = 1; 138 SXmode = 1; 139 Nmode = 1; 140#ifdef BFD_ASSEMBLER 141 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn)) 142 as_warn (_("could not set architecture and machine")); 143#endif 144} 145 146static void 147sbranch (int size) 148{ 149 bsize = size; 150} 151 152static void 153pint (int arg ATTRIBUTE_UNUSED) 154{ 155 cons (Hmode ? 4 : 2); 156} 157 158/* This table describes all the machine specific pseudo-ops the assembler 159 has to support. The fields are: 160 pseudo-op name without dot 161 function to call to execute this pseudo-op 162 Integer arg to pass to the function. */ 163 164const pseudo_typeS md_pseudo_table[] = 165{ 166 {"h8300h", h8300hmode, 0}, 167 {"h8300hn", h8300hnmode, 0}, 168 {"h8300s", h8300smode, 0}, 169 {"h8300sn", h8300snmode, 0}, 170 {"h8300sx", h8300sxmode, 0}, 171 {"h8300sxn", h8300sxnmode, 0}, 172 {"sbranch", sbranch, L_8}, 173 {"lbranch", sbranch, L_16}, 174 175 {"int", pint, 0}, 176 {"data.b", cons, 1}, 177 {"data.w", cons, 2}, 178 {"data.l", cons, 4}, 179 {"form", listing_psize, 0}, 180 {"heading", listing_title, 0}, 181 {"import", s_ignore, 0}, 182 {"page", listing_eject, 0}, 183 {"program", s_ignore, 0}, 184 {0, 0, 0} 185}; 186 187const int md_reloc_size; 188 189const char EXP_CHARS[] = "eE"; 190 191/* Chars that mean this number is a floating point constant 192 As in 0f12.456 193 or 0d1.2345e12. */ 194const char FLT_CHARS[] = "rRsSfFdDxXpP"; 195 196static struct hash_control *opcode_hash_control; /* Opcode mnemonics. */ 197 198/* This function is called once, at assembler startup time. This 199 should set up all the tables, etc. that the MD part of the assembler 200 needs. */ 201 202void 203md_begin (void) 204{ 205 unsigned int nopcodes; 206 struct h8_opcode *p, *p1; 207 struct h8_instruction *pi; 208 char prev_buffer[100]; 209 int idx = 0; 210 211#ifdef BFD_ASSEMBLER 212 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300)) 213 as_warn (_("could not set architecture and machine")); 214#endif 215 216 opcode_hash_control = hash_new (); 217 prev_buffer[0] = 0; 218 219 nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); 220 221 h8_instructions = (struct h8_instruction *) 222 xmalloc (nopcodes * sizeof (struct h8_instruction)); 223 224 pi = h8_instructions; 225 p1 = h8_opcodes; 226 /* We do a minimum amount of sorting on the opcode table; this is to 227 make it easy to describe the mova instructions without unnecessary 228 code duplication. 229 Sorting only takes place inside blocks of instructions of the form 230 X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */ 231 while (p1) 232 { 233 struct h8_opcode *first_skipped = 0; 234 int len, cmplen = 0; 235 char *src = p1->name; 236 char *dst, *buffer; 237 238 if (p1->name == 0) 239 break; 240 /* Strip off any . part when inserting the opcode and only enter 241 unique codes into the hash table. */ 242 dst = buffer = malloc (strlen (src) + 1); 243 while (*src) 244 { 245 if (*src == '.') 246 { 247 src++; 248 break; 249 } 250 if (*src == '/') 251 cmplen = src - p1->name + 1; 252 *dst++ = *src++; 253 } 254 *dst = 0; 255 len = dst - buffer; 256 if (cmplen == 0) 257 cmplen = len; 258 hash_insert (opcode_hash_control, buffer, (char *) pi); 259 strcpy (prev_buffer, buffer); 260 idx++; 261 262 for (p = p1; p->name; p++) 263 { 264 /* A negative TIME is used to indicate that we've added this opcode 265 already. */ 266 if (p->time == -1) 267 continue; 268 if (strncmp (p->name, buffer, cmplen) != 0 269 || (p->name[cmplen] != '\0' && p->name[cmplen] != '.' 270 && p->name[cmplen - 1] != '/')) 271 { 272 if (first_skipped == 0) 273 first_skipped = p; 274 break; 275 } 276 if (strncmp (p->name, buffer, len) != 0) 277 { 278 if (first_skipped == 0) 279 first_skipped = p; 280 continue; 281 } 282 283 p->time = -1; 284 pi->size = p->name[len] == '.' ? p->name[len + 1] : 0; 285 pi->idx = idx; 286 287 /* Find the number of operands. */ 288 pi->noperands = 0; 289 while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E) 290 pi->noperands++; 291 292 /* Find the length of the opcode in bytes. */ 293 pi->length = 0; 294 while (p->data.nib[pi->length * 2] != (op_type) E) 295 pi->length++; 296 297 pi->opcode = p; 298 pi++; 299 } 300 p1 = first_skipped; 301 } 302 303 /* Add entry for the NULL vector terminator. */ 304 pi->length = 0; 305 pi->noperands = 0; 306 pi->idx = 0; 307 pi->size = 0; 308 pi->opcode = 0; 309 310 linkrelax = 1; 311} 312 313struct h8_op 314{ 315 op_type mode; 316 unsigned reg; 317 expressionS exp; 318}; 319 320static void clever_message (const struct h8_instruction *, struct h8_op *); 321static void fix_operand_size (struct h8_op *, int); 322static void build_bytes (const struct h8_instruction *, struct h8_op *); 323static void do_a_fix_imm (int, int, struct h8_op *, int); 324static void check_operand (struct h8_op *, unsigned int, char *); 325static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ; 326static char *get_operands (unsigned, char *, struct h8_op *); 327static void get_operand (char **, struct h8_op *, int); 328static int parse_reg (char *, op_type *, unsigned *, int); 329static char *skip_colonthing (char *, int *); 330static char *parse_exp (char *, struct h8_op *); 331 332static int constant_fits_width_p (struct h8_op *, unsigned int); 333static int constant_fits_size_p (struct h8_op *, int, int); 334 335/* 336 parse operands 337 WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp 338 r0l,r0h,..r7l,r7h 339 @WREG 340 @WREG+ 341 @-WREG 342 #const 343 ccr 344*/ 345 346/* Try to parse a reg name. Return the number of chars consumed. */ 347 348static int 349parse_reg (char *src, op_type *mode, unsigned int *reg, int direction) 350{ 351 char *end; 352 int len; 353 354 /* Cribbed from get_symbol_end. */ 355 if (!is_name_beginner (*src) || *src == '\001') 356 return 0; 357 end = src + 1; 358 while ((is_part_of_name (*end) && *end != '.') || *end == '\001') 359 end++; 360 len = end - src; 361 362 if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p') 363 { 364 *mode = PSIZE | REG | direction; 365 *reg = 7; 366 return len; 367 } 368 if (len == 3 && 369 TOLOWER (src[0]) == 'c' && 370 TOLOWER (src[1]) == 'c' && 371 TOLOWER (src[2]) == 'r') 372 { 373 *mode = CCR; 374 *reg = 0; 375 return len; 376 } 377 if (len == 3 && 378 TOLOWER (src[0]) == 'e' && 379 TOLOWER (src[1]) == 'x' && 380 TOLOWER (src[2]) == 'r') 381 { 382 *mode = EXR; 383 *reg = 1; 384 return len; 385 } 386 if (len == 3 && 387 TOLOWER (src[0]) == 'v' && 388 TOLOWER (src[1]) == 'b' && 389 TOLOWER (src[2]) == 'r') 390 { 391 *mode = VBR; 392 *reg = 6; 393 return len; 394 } 395 if (len == 3 && 396 TOLOWER (src[0]) == 's' && 397 TOLOWER (src[1]) == 'b' && 398 TOLOWER (src[2]) == 'r') 399 { 400 *mode = SBR; 401 *reg = 7; 402 return len; 403 } 404 if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p') 405 { 406 *mode = PSIZE | REG | direction; 407 *reg = 6; 408 return len; 409 } 410 if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && 411 src[2] >= '0' && src[2] <= '7') 412 { 413 *mode = L_32 | REG | direction; 414 *reg = src[2] - '0'; 415 if (!Hmode) 416 as_warn (_("Reg not valid for H8/300")); 417 return len; 418 } 419 if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7') 420 { 421 *mode = L_16 | REG | direction; 422 *reg = src[1] - '0' + 8; 423 if (!Hmode) 424 as_warn (_("Reg not valid for H8/300")); 425 return len; 426 } 427 428 if (TOLOWER (src[0]) == 'r') 429 { 430 if (src[1] >= '0' && src[1] <= '7') 431 { 432 if (len == 3 && TOLOWER (src[2]) == 'l') 433 { 434 *mode = L_8 | REG | direction; 435 *reg = (src[1] - '0') + 8; 436 return len; 437 } 438 if (len == 3 && TOLOWER (src[2]) == 'h') 439 { 440 *mode = L_8 | REG | direction; 441 *reg = (src[1] - '0'); 442 return len; 443 } 444 if (len == 2) 445 { 446 *mode = L_16 | REG | direction; 447 *reg = (src[1] - '0'); 448 return len; 449 } 450 } 451 } 452 453 return 0; 454} 455 456 457/* Parse an immediate or address-related constant and store it in OP. 458 If the user also specifies the operand's size, store that size 459 in OP->MODE, otherwise leave it for later code to decide. */ 460 461static char * 462parse_exp (char *src, struct h8_op *op) 463{ 464 char *save; 465 466 save = input_line_pointer; 467 input_line_pointer = src; 468 expression (&op->exp); 469 if (op->exp.X_op == O_absent) 470 as_bad (_("missing operand")); 471 src = input_line_pointer; 472 input_line_pointer = save; 473 474 return skip_colonthing (src, &op->mode); 475} 476 477 478/* If SRC starts with an explicit operand size, skip it and store the size 479 in *MODE. Leave *MODE unchanged otherwise. */ 480 481static char * 482skip_colonthing (char *src, int *mode) 483{ 484 if (*src == ':') 485 { 486 src++; 487 *mode &= ~SIZE; 488 if (src[0] == '8' && !ISDIGIT (src[1])) 489 *mode |= L_8; 490 else if (src[0] == '2' && !ISDIGIT (src[1])) 491 *mode |= L_2; 492 else if (src[0] == '3' && !ISDIGIT (src[1])) 493 *mode |= L_3; 494 else if (src[0] == '4' && !ISDIGIT (src[1])) 495 *mode |= L_4; 496 else if (src[0] == '5' && !ISDIGIT (src[1])) 497 *mode |= L_5; 498 else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2])) 499 *mode |= L_24; 500 else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2])) 501 *mode |= L_32; 502 else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2])) 503 *mode |= L_16; 504 else 505 as_bad (_("invalid operand size requested")); 506 507 while (ISDIGIT (*src)) 508 src++; 509 } 510 return src; 511} 512 513/* The many forms of operand: 514 515 Rn Register direct 516 @Rn Register indirect 517 @(exp[:16], Rn) Register indirect with displacement 518 @Rn+ 519 @-Rn 520 @aa:8 absolute 8 bit 521 @aa:16 absolute 16 bit 522 @aa absolute 16 bit 523 524 #xx[:size] immediate data 525 @(exp:[8], pc) pc rel 526 @@aa[:8] memory indirect. */ 527 528static int 529constant_fits_width_p (struct h8_op *operand, unsigned int width) 530{ 531 return ((operand->exp.X_add_number & ~width) == 0 532 || (operand->exp.X_add_number | width) == (unsigned)(~0)); 533} 534 535static int 536constant_fits_size_p (struct h8_op *operand, int size, int no_symbols) 537{ 538 offsetT num = operand->exp.X_add_number; 539 if (no_symbols 540 && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0)) 541 return 0; 542 switch (size) 543 { 544 case L_2: 545 return (num & ~3) == 0; 546 case L_3: 547 return (num & ~7) == 0; 548 case L_3NZ: 549 return num >= 1 && num < 8; 550 case L_4: 551 return (num & ~15) == 0; 552 case L_5: 553 return num >= 1 && num < 32; 554 case L_8: 555 return (num & ~0xFF) == 0 || ((unsigned)num | 0x7F) == ~0u; 556 case L_8U: 557 return (num & ~0xFF) == 0; 558 case L_16: 559 return (num & ~0xFFFF) == 0 || ((unsigned)num | 0x7FFF) == ~0u; 560 case L_16U: 561 return (num & ~0xFFFF) == 0; 562 case L_32: 563 return 1; 564 default: 565 abort (); 566 } 567} 568 569static void 570get_operand (char **ptr, struct h8_op *op, int direction) 571{ 572 char *src = *ptr; 573 op_type mode; 574 unsigned int num; 575 unsigned int len; 576 577 op->mode = 0; 578 579 /* Check for '(' and ')' for instructions ldm and stm. */ 580 if (src[0] == '(' && src[8] == ')') 581 ++ src; 582 583 /* Gross. Gross. ldm and stm have a format not easily handled 584 by get_operand. We deal with it explicitly here. */ 585 if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && 586 ISDIGIT (src[2]) && src[3] == '-' && 587 TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6])) 588 { 589 int low, high; 590 591 low = src[2] - '0'; 592 high = src[6] - '0'; 593 594 /* Check register pair's validity as per tech note TN-H8*-193A/E 595 from Renesas for H8S and H8SX hardware manual. */ 596 if ( !(low == 0 && (high == 1 || high == 2 || high == 3)) 597 && !(low == 1 && (high == 2 || high == 3 || high == 4) && SXmode) 598 && !(low == 2 && (high == 3 || ((high == 4 || high == 5) && SXmode))) 599 && !(low == 3 && (high == 4 || high == 5 || high == 6) && SXmode) 600 && !(low == 4 && (high == 5 || high == 6)) 601 && !(low == 4 && high == 7 && SXmode) 602 && !(low == 5 && (high == 6 || high == 7) && SXmode) 603 && !(low == 6 && high == 7 && SXmode)) 604 as_bad (_("Invalid register list for ldm/stm\n")); 605 606 /* Even sicker. We encode two registers into op->reg. One 607 for the low register to save, the other for the high 608 register to save; we also set the high bit in op->reg 609 so we know this is "very special". */ 610 op->reg = 0x80000000 | (high << 8) | low; 611 op->mode = REG; 612 if (src[7] == ')') 613 *ptr = src + 8; 614 else 615 *ptr = src + 7; 616 return; 617 } 618 619 len = parse_reg (src, &op->mode, &op->reg, direction); 620 if (len) 621 { 622 src += len; 623 if (*src == '.') 624 { 625 int size = op->mode & SIZE; 626 switch (src[1]) 627 { 628 case 'l': case 'L': 629 if (size != L_32) 630 as_warn (_("mismatch between register and suffix")); 631 op->mode = (op->mode & ~MODE) | LOWREG; 632 break; 633 case 'w': case 'W': 634 if (size != L_32 && size != L_16) 635 as_warn (_("mismatch between register and suffix")); 636 op->mode = (op->mode & ~MODE) | LOWREG; 637 op->mode = (op->mode & ~SIZE) | L_16; 638 break; 639 case 'b': case 'B': 640 op->mode = (op->mode & ~MODE) | LOWREG; 641 if (size != L_32 && size != L_8) 642 as_warn (_("mismatch between register and suffix")); 643 op->mode = (op->mode & ~MODE) | LOWREG; 644 op->mode = (op->mode & ~SIZE) | L_8; 645 break; 646 default: 647 as_warn ("invalid suffix after register."); 648 break; 649 } 650 src += 2; 651 } 652 *ptr = src; 653 return; 654 } 655 656 if (*src == '@') 657 { 658 src++; 659 if (*src == '@') 660 { 661 *ptr = parse_exp (src + 1, op); 662 if (op->exp.X_add_number >= 0x100) 663 { 664 int divisor = 1; 665 666 op->mode = VECIND; 667 /* FIXME : 2? or 4? */ 668 if (op->exp.X_add_number >= 0x400) 669 as_bad (_("address too high for vector table jmp/jsr")); 670 else if (op->exp.X_add_number >= 0x200) 671 divisor = 4; 672 else 673 divisor = 2; 674 675 op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80; 676 } 677 else 678 op->mode = MEMIND; 679 return; 680 } 681 682 if (*src == '-' || *src == '+') 683 { 684 len = parse_reg (src + 1, &mode, &num, direction); 685 if (len == 0) 686 { 687 /* Oops, not a reg after all, must be ordinary exp. */ 688 op->mode = ABS | direction; 689 *ptr = parse_exp (src, op); 690 return; 691 } 692 693 if (((mode & SIZE) != PSIZE) 694 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 695 && (!Nmode || ((mode & SIZE) != L_32))) 696 as_bad (_("Wrong size pointer register for architecture.")); 697 698 op->mode = src[0] == '-' ? RDPREDEC : RDPREINC; 699 op->reg = num; 700 *ptr = src + 1 + len; 701 return; 702 } 703 if (*src == '(') 704 { 705 src++; 706 707 /* See if this is @(ERn.x, PC). */ 708 len = parse_reg (src, &mode, &op->reg, direction); 709 if (len != 0 && (mode & MODE) == REG && src[len] == '.') 710 { 711 switch (TOLOWER (src[len + 1])) 712 { 713 case 'b': 714 mode = PCIDXB | direction; 715 break; 716 case 'w': 717 mode = PCIDXW | direction; 718 break; 719 case 'l': 720 mode = PCIDXL | direction; 721 break; 722 default: 723 mode = 0; 724 break; 725 } 726 if (mode 727 && src[len + 2] == ',' 728 && TOLOWER (src[len + 3]) != 'p' 729 && TOLOWER (src[len + 4]) != 'c' 730 && src[len + 5] != ')') 731 { 732 *ptr = src + len + 6; 733 op->mode |= mode; 734 return; 735 } 736 /* Fall through into disp case - the grammar is somewhat 737 ambiguous, so we should try whether it's a DISP operand 738 after all ("ER3.L" might be a poorly named label...). */ 739 } 740 741 /* Disp. */ 742 743 /* Start off assuming a 16 bit offset. */ 744 745 src = parse_exp (src, op); 746 if (*src == ')') 747 { 748 op->mode |= ABS | direction; 749 *ptr = src + 1; 750 return; 751 } 752 753 if (*src != ',') 754 { 755 as_bad (_("expected @(exp, reg16)")); 756 return; 757 } 758 src++; 759 760 len = parse_reg (src, &mode, &op->reg, direction); 761 if (len == 0 || (mode & MODE) != REG) 762 { 763 as_bad (_("expected @(exp, reg16)")); 764 return; 765 } 766 src += len; 767 if (src[0] == '.') 768 { 769 switch (TOLOWER (src[1])) 770 { 771 case 'b': 772 op->mode |= INDEXB | direction; 773 break; 774 case 'w': 775 op->mode |= INDEXW | direction; 776 break; 777 case 'l': 778 op->mode |= INDEXL | direction; 779 break; 780 default: 781 as_bad (_("expected .L, .W or .B for register in indexed addressing mode")); 782 } 783 src += 2; 784 op->reg &= 7; 785 } 786 else 787 op->mode |= DISP | direction; 788 src = skip_colonthing (src, &op->mode); 789 790 if (*src != ')' && '(') 791 { 792 as_bad (_("expected @(exp, reg16)")); 793 return; 794 } 795 *ptr = src + 1; 796 return; 797 } 798 len = parse_reg (src, &mode, &num, direction); 799 800 if (len) 801 { 802 src += len; 803 if (*src == '+' || *src == '-') 804 { 805 if (((mode & SIZE) != PSIZE) 806 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 807 && (!Nmode || ((mode & SIZE) != L_32))) 808 as_bad (_("Wrong size pointer register for architecture.")); 809 op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC; 810 op->reg = num; 811 src++; 812 *ptr = src; 813 return; 814 } 815 if (((mode & SIZE) != PSIZE) 816 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 817 && (!Nmode || ((mode & SIZE) != L_32))) 818 as_bad (_("Wrong size pointer register for architecture.")); 819 820 op->mode = direction | IND | PSIZE; 821 op->reg = num; 822 *ptr = src; 823 824 return; 825 } 826 else 827 { 828 /* must be a symbol */ 829 830 op->mode = ABS | direction; 831 *ptr = parse_exp (src, op); 832 return; 833 } 834 } 835 836 if (*src == '#') 837 { 838 op->mode = IMM; 839 *ptr = parse_exp (src + 1, op); 840 return; 841 } 842 else if (strncmp (src, "mach", 4) == 0 || 843 strncmp (src, "macl", 4) == 0 || 844 strncmp (src, "MACH", 4) == 0 || 845 strncmp (src, "MACL", 4) == 0) 846 { 847 op->reg = TOLOWER (src[3]) == 'l'; 848 op->mode = MACREG; 849 *ptr = src + 4; 850 return; 851 } 852 else 853 { 854 op->mode = PCREL; 855 *ptr = parse_exp (src, op); 856 } 857} 858 859static char * 860get_operands (unsigned int noperands, char *op_end, struct h8_op *operand) 861{ 862 char *ptr = op_end; 863 864 switch (noperands) 865 { 866 case 0: 867 break; 868 869 case 1: 870 ptr++; 871 get_operand (&ptr, operand + 0, SRC); 872 if (*ptr == ',') 873 { 874 ptr++; 875 get_operand (&ptr, operand + 1, DST); 876 } 877 break; 878 879 case 2: 880 ptr++; 881 get_operand (&ptr, operand + 0, SRC); 882 if (*ptr == ',') 883 ptr++; 884 get_operand (&ptr, operand + 1, DST); 885 break; 886 887 case 3: 888 ptr++; 889 get_operand (&ptr, operand + 0, SRC); 890 if (*ptr == ',') 891 ptr++; 892 get_operand (&ptr, operand + 1, DST); 893 if (*ptr == ',') 894 ptr++; 895 get_operand (&ptr, operand + 2, OP3); 896 break; 897 898 default: 899 abort (); 900 } 901 902 return ptr; 903} 904 905/* MOVA has special requirements. Rather than adding twice the amount of 906 addressing modes, we simply special case it a bit. */ 907static void 908get_mova_operands (char *op_end, struct h8_op *operand) 909{ 910 char *ptr = op_end; 911 912 if (ptr[1] != '@' || ptr[2] != '(') 913 goto error; 914 ptr += 3; 915 operand[0].mode = 0; 916 ptr = parse_exp (ptr, &operand[0]); 917 918 if (*ptr !=',') 919 goto error; 920 ptr++; 921 get_operand (&ptr, operand + 1, DST); 922 923 if (*ptr =='.') 924 { 925 ptr++; 926 switch (*ptr++) 927 { 928 case 'b': case 'B': 929 operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; 930 break; 931 case 'w': case 'W': 932 operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; 933 break; 934 case 'l': case 'L': 935 operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; 936 break; 937 default: 938 goto error; 939 } 940 } 941 else if ((operand[1].mode & MODE) == LOWREG) 942 { 943 switch (operand[1].mode & SIZE) 944 { 945 case L_8: 946 operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; 947 break; 948 case L_16: 949 operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; 950 break; 951 case L_32: 952 operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; 953 break; 954 default: 955 goto error; 956 } 957 } 958 else 959 goto error; 960 961 if (*ptr++ != ')' || *ptr++ != ',') 962 goto error; 963 get_operand (&ptr, operand + 2, OP3); 964 /* See if we can use the short form of MOVA. */ 965 if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG) 966 && (operand[2].mode & MODE) == REG 967 && (operand[1].reg & 7) == (operand[2].reg & 7)) 968 { 969 operand[1].mode = operand[2].mode = 0; 970 operand[0].reg = operand[2].reg & 7; 971 } 972 return; 973 974 error: 975 as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"")); 976} 977 978static void 979get_rtsl_operands (char *ptr, struct h8_op *operand) 980{ 981 int mode, num, num2, len, type = 0; 982 983 ptr++; 984 if (*ptr == '(') 985 { 986 ptr++; 987 type = 1; 988 } 989 len = parse_reg (ptr, &mode, &num, SRC); 990 if (len == 0 || (mode & MODE) != REG) 991 { 992 as_bad (_("expected register")); 993 return; 994 } 995 ptr += len; 996 if (*ptr == '-') 997 { 998 len = parse_reg (++ptr, &mode, &num2, SRC); 999 if (len == 0 || (mode & MODE) != REG) 1000 { 1001 as_bad (_("expected register")); 1002 return; 1003 } 1004 ptr += len; 1005 /* CONST_xxx are used as placeholders in the opcode table. */ 1006 num = num2 - num; 1007 if (num < 0 || num > 3) 1008 { 1009 as_bad (_("invalid register list")); 1010 return; 1011 } 1012 } 1013 else 1014 num2 = num, num = 0; 1015 if (type == 1 && *ptr++ != ')') 1016 { 1017 as_bad (_("expected closing paren")); 1018 return; 1019 } 1020 operand[0].mode = RS32; 1021 operand[1].mode = RD32; 1022 operand[0].reg = num; 1023 operand[1].reg = num2; 1024} 1025 1026/* Passed a pointer to a list of opcodes which use different 1027 addressing modes, return the opcode which matches the opcodes 1028 provided. */ 1029 1030static const struct h8_instruction * 1031get_specific (const struct h8_instruction *instruction, 1032 struct h8_op *operands, int size) 1033{ 1034 const struct h8_instruction *this_try = instruction; 1035 const struct h8_instruction *found_other = 0, *found_mismatched = 0; 1036 int found = 0; 1037 int this_index = instruction->idx; 1038 int noperands = 0; 1039 1040 /* There's only one ldm/stm and it's easier to just 1041 get out quick for them. */ 1042 if (OP_KIND (instruction->opcode->how) == O_LDM 1043 || OP_KIND (instruction->opcode->how) == O_STM) 1044 return this_try; 1045 1046 while (noperands < 3 && operands[noperands].mode != 0) 1047 noperands++; 1048 1049 while (this_index == instruction->idx && !found) 1050 { 1051 int this_size; 1052 1053 found = 1; 1054 this_try = instruction++; 1055 this_size = this_try->opcode->how & SN; 1056 1057 if (this_try->noperands != noperands) 1058 found = 0; 1059 else if (this_try->noperands > 0) 1060 { 1061 int i; 1062 1063 for (i = 0; i < this_try->noperands && found; i++) 1064 { 1065 op_type op = this_try->opcode->args.nib[i]; 1066 int op_mode = op & MODE; 1067 int op_size = op & SIZE; 1068 int x = operands[i].mode; 1069 int x_mode = x & MODE; 1070 int x_size = x & SIZE; 1071 1072 if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG)) 1073 { 1074 if ((x_size == L_8 && (operands[i].reg & 8) == 0) 1075 || (x_size == L_16 && (operands[i].reg & 8) == 8)) 1076 as_warn (_("can't use high part of register in operand %d"), i); 1077 1078 if (x_size != op_size) 1079 found = 0; 1080 } 1081 else if (op_mode == REG) 1082 { 1083 if (x_mode == LOWREG) 1084 x_mode = REG; 1085 if (x_mode != REG) 1086 found = 0; 1087 1088 if (x_size == L_P) 1089 x_size = (Hmode ? L_32 : L_16); 1090 if (op_size == L_P) 1091 op_size = (Hmode ? L_32 : L_16); 1092 1093 /* The size of the reg is v important. */ 1094 if (op_size != x_size) 1095 found = 0; 1096 } 1097 else if (op_mode & CTRL) /* control register */ 1098 { 1099 if (!(x_mode & CTRL)) 1100 found = 0; 1101 1102 switch (x_mode) 1103 { 1104 case CCR: 1105 if (op_mode != CCR && 1106 op_mode != CCR_EXR && 1107 op_mode != CC_EX_VB_SB) 1108 found = 0; 1109 break; 1110 case EXR: 1111 if (op_mode != EXR && 1112 op_mode != CCR_EXR && 1113 op_mode != CC_EX_VB_SB) 1114 found = 0; 1115 break; 1116 case MACH: 1117 if (op_mode != MACH && 1118 op_mode != MACREG) 1119 found = 0; 1120 break; 1121 case MACL: 1122 if (op_mode != MACL && 1123 op_mode != MACREG) 1124 found = 0; 1125 break; 1126 case VBR: 1127 if (op_mode != VBR && 1128 op_mode != VBR_SBR && 1129 op_mode != CC_EX_VB_SB) 1130 found = 0; 1131 break; 1132 case SBR: 1133 if (op_mode != SBR && 1134 op_mode != VBR_SBR && 1135 op_mode != CC_EX_VB_SB) 1136 found = 0; 1137 break; 1138 } 1139 } 1140 else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL)) 1141 { 1142 operands[i].mode &= ~MODE; 1143 operands[i].mode |= ABSJMP; 1144 /* But it may not be 24 bits long. */ 1145 if (x_mode == ABS && !Hmode) 1146 { 1147 operands[i].mode &= ~SIZE; 1148 operands[i].mode |= L_16; 1149 } 1150 if ((operands[i].mode & SIZE) == L_32 1151 && (op_mode & SIZE) != L_32) 1152 found = 0; 1153 } 1154 else if (x_mode == IMM && op_mode != IMM) 1155 { 1156 offsetT num = operands[i].exp.X_add_number; 1157 if (op_mode == KBIT || op_mode == DBIT) 1158 /* This is ok if the immediate value is sensible. */; 1159 else if (op_mode == CONST_2) 1160 found = num == 2; 1161 else if (op_mode == CONST_4) 1162 found = num == 4; 1163 else if (op_mode == CONST_8) 1164 found = num == 8; 1165 else if (op_mode == CONST_16) 1166 found = num == 16; 1167 else 1168 found = 0; 1169 } 1170 else if (op_mode == PCREL && op_mode == x_mode) 1171 { 1172 /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour: 1173 If x_size is L_8, promote it. */ 1174 if (OP_KIND (this_try->opcode->how) == O_MOVSD 1175 || OP_KIND (this_try->opcode->how) == O_BSRBC 1176 || OP_KIND (this_try->opcode->how) == O_BSRBS) 1177 if (x_size == L_8) 1178 x_size = L_16; 1179 1180 /* The size of the displacement is important. */ 1181 if (op_size != x_size) 1182 found = 0; 1183 } 1184 else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS 1185 || op_mode == INDEXB || op_mode == INDEXW 1186 || op_mode == INDEXL) 1187 && op_mode == x_mode) 1188 { 1189 /* Promote a L_24 to L_32 if it makes us match. */ 1190 if (x_size == L_24 && op_size == L_32) 1191 { 1192 x &= ~SIZE; 1193 x |= x_size = L_32; 1194 } 1195 1196#if 0 /* ??? */ 1197 /* Promote an L8 to L_16 if it makes us match. */ 1198 if ((op_mode == ABS || op_mode == DISP) && x_size == L_8) 1199 { 1200 if (op_size == L_16) 1201 x_size = L_16; 1202 } 1203#endif 1204 1205 if (((x_size == L_16 && op_size == L_16U) 1206 || (x_size == L_8 && op_size == L_8U) 1207 || (x_size == L_3 && op_size == L_3NZ)) 1208 /* We're deliberately more permissive for ABS modes. */ 1209 && (op_mode == ABS 1210 || constant_fits_size_p (operands + i, op_size, 1211 op & NO_SYMBOLS))) 1212 x_size = op_size; 1213 1214 if (x_size != 0 && op_size != x_size) 1215 found = 0; 1216 else if (x_size == 0 1217 && ! constant_fits_size_p (operands + i, op_size, 1218 op & NO_SYMBOLS)) 1219 found = 0; 1220 } 1221 else if (op_mode != x_mode) 1222 { 1223 found = 0; 1224 } 1225 } 1226 } 1227 if (found) 1228 { 1229 if ((this_try->opcode->available == AV_H8SX && ! SXmode) 1230 || (this_try->opcode->available == AV_H8S && ! Smode) 1231 || (this_try->opcode->available == AV_H8H && ! Hmode)) 1232 found = 0, found_other = this_try; 1233 else if (this_size != size && (this_size != SN && size != SN)) 1234 found_mismatched = this_try, found = 0; 1235 1236 } 1237 } 1238 if (found) 1239 return this_try; 1240 if (found_other) 1241 { 1242 as_warn (_("Opcode `%s' with these operand types not available in %s mode"), 1243 found_other->opcode->name, 1244 (! Hmode && ! Smode ? "H8/300" 1245 : SXmode ? "H8sx" 1246 : Smode ? "H8/300S" 1247 : "H8/300H")); 1248 } 1249 else if (found_mismatched) 1250 { 1251 as_warn (_("mismatch between opcode size and operand size")); 1252 return found_mismatched; 1253 } 1254 return 0; 1255} 1256 1257static void 1258check_operand (struct h8_op *operand, unsigned int width, char *string) 1259{ 1260 if (operand->exp.X_add_symbol == 0 1261 && operand->exp.X_op_symbol == 0) 1262 { 1263 /* No symbol involved, let's look at offset, it's dangerous if 1264 any of the high bits are not 0 or ff's, find out by oring or 1265 anding with the width and seeing if the answer is 0 or all 1266 fs. */ 1267 1268 if (! constant_fits_width_p (operand, width)) 1269 { 1270 if (width == 255 1271 && (operand->exp.X_add_number & 0xff00) == 0xff00) 1272 { 1273 /* Just ignore this one - which happens when trying to 1274 fit a 16 bit address truncated into an 8 bit address 1275 of something like bset. */ 1276 } 1277 else if (strcmp (string, "@") == 0 1278 && width == 0xffff 1279 && (operand->exp.X_add_number & 0xff8000) == 0xff8000) 1280 { 1281 /* Just ignore this one - which happens when trying to 1282 fit a 24 bit address truncated into a 16 bit address 1283 of something like mov.w. */ 1284 } 1285 else 1286 { 1287 as_warn (_("operand %s0x%lx out of range."), string, 1288 (unsigned long) operand->exp.X_add_number); 1289 } 1290 } 1291 } 1292} 1293 1294/* RELAXMODE has one of 3 values: 1295 1296 0 Output a "normal" reloc, no relaxing possible for this insn/reloc 1297 1298 1 Output a relaxable 24bit absolute mov.w address relocation 1299 (may relax into a 16bit absolute address). 1300 1301 2 Output a relaxable 16/24 absolute mov.b address relocation 1302 (may relax into an 8bit absolute address). */ 1303 1304static void 1305do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode) 1306{ 1307 int idx; 1308 int size; 1309 int where; 1310 char *bytes = frag_now->fr_literal + offset; 1311 1312 char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; 1313 1314 if (operand->exp.X_add_symbol == 0) 1315 { 1316 switch (operand->mode & SIZE) 1317 { 1318 case L_2: 1319 check_operand (operand, 0x3, t); 1320 bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4); 1321 break; 1322 case L_3: 1323 case L_3NZ: 1324 check_operand (operand, 0x7, t); 1325 bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4); 1326 break; 1327 case L_4: 1328 check_operand (operand, 0xF, t); 1329 bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4); 1330 break; 1331 case L_5: 1332 check_operand (operand, 0x1F, t); 1333 bytes[0] |= operand->exp.X_add_number & 31; 1334 break; 1335 case L_8: 1336 case L_8U: 1337 check_operand (operand, 0xff, t); 1338 bytes[0] |= operand->exp.X_add_number; 1339 break; 1340 case L_16: 1341 case L_16U: 1342 check_operand (operand, 0xffff, t); 1343 bytes[0] |= operand->exp.X_add_number >> 8; 1344 bytes[1] |= operand->exp.X_add_number >> 0; 1345 break; 1346 case L_24: 1347 check_operand (operand, 0xffffff, t); 1348 bytes[0] |= operand->exp.X_add_number >> 16; 1349 bytes[1] |= operand->exp.X_add_number >> 8; 1350 bytes[2] |= operand->exp.X_add_number >> 0; 1351 break; 1352 1353 case L_32: 1354 /* This should be done with bfd. */ 1355 bytes[0] |= operand->exp.X_add_number >> 24; 1356 bytes[1] |= operand->exp.X_add_number >> 16; 1357 bytes[2] |= operand->exp.X_add_number >> 8; 1358 bytes[3] |= operand->exp.X_add_number >> 0; 1359 if (relaxmode != 0) 1360 { 1361 idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1; 1362 fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx); 1363 } 1364 break; 1365 } 1366 } 1367 else 1368 { 1369 switch (operand->mode & SIZE) 1370 { 1371 case L_24: 1372 case L_32: 1373 size = 4; 1374 where = (operand->mode & SIZE) == L_24 ? -1 : 0; 1375 if (relaxmode == 2) 1376 idx = R_MOV24B1; 1377 else if (relaxmode == 1) 1378 idx = R_MOVL1; 1379 else 1380 idx = R_RELLONG; 1381 break; 1382 default: 1383 as_bad (_("Can't work out size of operand.\n")); 1384 case L_16: 1385 case L_16U: 1386 size = 2; 1387 where = 0; 1388 if (relaxmode == 2) 1389 idx = R_MOV16B1; 1390 else 1391 idx = R_RELWORD; 1392 operand->exp.X_add_number = 1393 ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1394 operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1]; 1395 break; 1396 case L_8: 1397 size = 1; 1398 where = 0; 1399 idx = R_RELBYTE; 1400 operand->exp.X_add_number = 1401 ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80; 1402 operand->exp.X_add_number |= bytes[0]; 1403 } 1404 1405 fix_new_exp (frag_now, 1406 offset + where, 1407 size, 1408 &operand->exp, 1409 0, 1410 idx); 1411 } 1412} 1413 1414/* Now we know what sort of opcodes it is, let's build the bytes. */ 1415 1416static void 1417build_bytes (const struct h8_instruction *this_try, struct h8_op *operand) 1418{ 1419 int i; 1420 char *output = frag_more (this_try->length); 1421 op_type *nibble_ptr = this_try->opcode->data.nib; 1422 op_type c; 1423 unsigned int nibble_count = 0; 1424 int op_at[3]; 1425 int nib = 0; 1426 int movb = 0; 1427 char asnibbles[100]; 1428 char *p = asnibbles; 1429 int high, low; 1430 1431 if (!Hmode && this_try->opcode->available != AV_H8) 1432 as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"), 1433 this_try->opcode->name); 1434 else if (!Smode 1435 && this_try->opcode->available != AV_H8 1436 && this_try->opcode->available != AV_H8H) 1437 as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"), 1438 this_try->opcode->name); 1439 else if (!SXmode 1440 && this_try->opcode->available != AV_H8 1441 && this_try->opcode->available != AV_H8H 1442 && this_try->opcode->available != AV_H8S) 1443 as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"), 1444 this_try->opcode->name); 1445 1446 while (*nibble_ptr != (op_type) E) 1447 { 1448 int d; 1449 1450 nib = 0; 1451 c = *nibble_ptr++; 1452 1453 d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0; 1454 1455 if (c < 16) 1456 nib = c; 1457 else 1458 { 1459 int c2 = c & MODE; 1460 1461 if (c2 == REG || c2 == LOWREG 1462 || c2 == IND || c2 == PREINC || c2 == PREDEC 1463 || c2 == POSTINC || c2 == POSTDEC) 1464 { 1465 nib = operand[d].reg; 1466 if (c2 == LOWREG) 1467 nib &= 7; 1468 } 1469 1470 else if (c & CTRL) /* Control reg operand. */ 1471 nib = operand[d].reg; 1472 1473 else if ((c & DISPREG) == (DISPREG)) 1474 { 1475 nib = operand[d].reg; 1476 } 1477 else if (c2 == ABS) 1478 { 1479 operand[d].mode = c; 1480 op_at[d] = nibble_count; 1481 nib = 0; 1482 } 1483 else if (c2 == IMM || c2 == PCREL || c2 == ABS 1484 || (c & ABSJMP) || c2 == DISP) 1485 { 1486 operand[d].mode = c; 1487 op_at[d] = nibble_count; 1488 nib = 0; 1489 } 1490 else if ((c & IGNORE) || (c & DATA)) 1491 nib = 0; 1492 1493 else if (c2 == DBIT) 1494 { 1495 switch (operand[0].exp.X_add_number) 1496 { 1497 case 1: 1498 nib = c; 1499 break; 1500 case 2: 1501 nib = 0x8 | c; 1502 break; 1503 default: 1504 as_bad (_("Need #1 or #2 here")); 1505 } 1506 } 1507 else if (c2 == KBIT) 1508 { 1509 switch (operand[0].exp.X_add_number) 1510 { 1511 case 1: 1512 nib = 0; 1513 break; 1514 case 2: 1515 nib = 8; 1516 break; 1517 case 4: 1518 if (!Hmode) 1519 as_warn (_("#4 not valid on H8/300.")); 1520 nib = 9; 1521 break; 1522 1523 default: 1524 as_bad (_("Need #1 or #2 here")); 1525 break; 1526 } 1527 /* Stop it making a fix. */ 1528 operand[0].mode = 0; 1529 } 1530 1531 if (c & MEMRELAX) 1532 operand[d].mode |= MEMRELAX; 1533 1534 if (c & B31) 1535 nib |= 0x8; 1536 1537 if (c & B21) 1538 nib |= 0x4; 1539 1540 if (c & B11) 1541 nib |= 0x2; 1542 1543 if (c & B01) 1544 nib |= 0x1; 1545 1546 if (c2 == MACREG) 1547 { 1548 if (operand[0].mode == MACREG) 1549 /* stmac has mac[hl] as the first operand. */ 1550 nib = 2 + operand[0].reg; 1551 else 1552 /* ldmac has mac[hl] as the second operand. */ 1553 nib = 2 + operand[1].reg; 1554 } 1555 } 1556 nibble_count++; 1557 1558 *p++ = nib; 1559 } 1560 1561 /* Disgusting. Why, oh why didn't someone ask us for advice 1562 on the assembler format. */ 1563 if (OP_KIND (this_try->opcode->how) == O_LDM) 1564 { 1565 high = (operand[1].reg >> 8) & 0xf; 1566 low = (operand[1].reg) & 0xf; 1567 asnibbles[2] = high - low; 1568 asnibbles[7] = high; 1569 } 1570 else if (OP_KIND (this_try->opcode->how) == O_STM) 1571 { 1572 high = (operand[0].reg >> 8) & 0xf; 1573 low = (operand[0].reg) & 0xf; 1574 asnibbles[2] = high - low; 1575 asnibbles[7] = low; 1576 } 1577 1578 for (i = 0; i < this_try->length; i++) 1579 output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1]; 1580 1581 /* Note if this is a movb or a bit manipulation instruction 1582 there is a special relaxation which only applies. */ 1583 if ( this_try->opcode->how == O (O_MOV, SB) 1584 || this_try->opcode->how == O (O_BCLR, SB) 1585 || this_try->opcode->how == O (O_BAND, SB) 1586 || this_try->opcode->how == O (O_BIAND, SB) 1587 || this_try->opcode->how == O (O_BILD, SB) 1588 || this_try->opcode->how == O (O_BIOR, SB) 1589 || this_try->opcode->how == O (O_BIST, SB) 1590 || this_try->opcode->how == O (O_BIXOR, SB) 1591 || this_try->opcode->how == O (O_BLD, SB) 1592 || this_try->opcode->how == O (O_BNOT, SB) 1593 || this_try->opcode->how == O (O_BOR, SB) 1594 || this_try->opcode->how == O (O_BSET, SB) 1595 || this_try->opcode->how == O (O_BST, SB) 1596 || this_try->opcode->how == O (O_BTST, SB) 1597 || this_try->opcode->how == O (O_BXOR, SB)) 1598 movb = 1; 1599 1600 /* Output any fixes. */ 1601 for (i = 0; i < this_try->noperands; i++) 1602 { 1603 int x = operand[i].mode; 1604 int x_mode = x & MODE; 1605 1606 if (x_mode == IMM || x_mode == DISP) 1607 do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, 1608 op_at[i] & 1, operand + i, (x & MEMRELAX) != 0); 1609 1610 else if (x_mode == ABS) 1611 do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, 1612 op_at[i] & 1, operand + i, 1613 (x & MEMRELAX) ? movb + 1 : 0); 1614 1615 else if (x_mode == PCREL) 1616 { 1617 int size16 = (x & SIZE) == L_16; 1618 int size = size16 ? 2 : 1; 1619 int type = size16 ? R_PCRWORD : R_PCRBYTE; 1620 fixS *fixP; 1621 1622 check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@"); 1623 1624 if (operand[i].exp.X_add_number & 1) 1625 as_warn (_("branch operand has odd offset (%lx)\n"), 1626 (unsigned long) operand->exp.X_add_number); 1627#ifndef OBJ_ELF 1628 /* The COFF port has always been off by one, changing it 1629 now would be an incompatible change, so we leave it as-is. 1630 1631 We don't want to do this for ELF as we want to be 1632 compatible with the proposed ELF format from Hitachi. */ 1633 operand[i].exp.X_add_number -= 1; 1634#endif 1635 if (size16) 1636 { 1637 operand[i].exp.X_add_number = 1638 ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1639 } 1640 else 1641 { 1642 operand[i].exp.X_add_number = 1643 ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80; 1644 } 1645 1646 /* For BRA/S. */ 1647 if (! size16) 1648 operand[i].exp.X_add_number |= output[op_at[i] / 2]; 1649 1650 fixP = fix_new_exp (frag_now, 1651 output - frag_now->fr_literal + op_at[i] / 2, 1652 size, 1653 &operand[i].exp, 1654 1, 1655 type); 1656 fixP->fx_signed = 1; 1657 } 1658 else if (x_mode == MEMIND) 1659 { 1660 check_operand (operand + i, 0xff, "@@"); 1661 fix_new_exp (frag_now, 1662 output - frag_now->fr_literal + 1, 1663 1, 1664 &operand[i].exp, 1665 0, 1666 R_MEM_INDIRECT); 1667 } 1668 else if (x_mode == VECIND) 1669 { 1670 check_operand (operand + i, 0x7f, "@@"); 1671 /* FIXME: approximating the effect of "B31" here... 1672 This is very hackish, and ought to be done a better way. */ 1673 operand[i].exp.X_add_number |= 0x80; 1674 fix_new_exp (frag_now, 1675 output - frag_now->fr_literal + 1, 1676 1, 1677 &operand[i].exp, 1678 0, 1679 R_MEM_INDIRECT); 1680 } 1681 else if (x & ABSJMP) 1682 { 1683 int where = 0; 1684 bfd_reloc_code_real_type reloc_type = R_JMPL1; 1685 1686#ifdef OBJ_ELF 1687 /* To be compatible with the proposed H8 ELF format, we 1688 want the relocation's offset to point to the first byte 1689 that will be modified, not to the start of the instruction. */ 1690 1691 if ((operand->mode & SIZE) == L_32) 1692 { 1693 where = 2; 1694 reloc_type = R_RELLONG; 1695 } 1696 else 1697 where = 1; 1698#endif 1699 1700 /* This jmp may be a jump or a branch. */ 1701 1702 check_operand (operand + i, 1703 SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff, 1704 "@"); 1705 1706 if (operand[i].exp.X_add_number & 1) 1707 as_warn (_("branch operand has odd offset (%lx)\n"), 1708 (unsigned long) operand->exp.X_add_number); 1709 1710 if (!Hmode) 1711 operand[i].exp.X_add_number = 1712 ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1713 fix_new_exp (frag_now, 1714 output - frag_now->fr_literal + where, 1715 4, 1716 &operand[i].exp, 1717 0, 1718 reloc_type); 1719 } 1720 } 1721} 1722 1723/* Try to give an intelligent error message for common and simple to 1724 detect errors. */ 1725 1726static void 1727clever_message (const struct h8_instruction *instruction, 1728 struct h8_op *operand) 1729{ 1730 /* Find out if there was more than one possible opcode. */ 1731 1732 if ((instruction + 1)->idx != instruction->idx) 1733 { 1734 int argn; 1735 1736 /* Only one opcode of this flavour, try to guess which operand 1737 didn't match. */ 1738 for (argn = 0; argn < instruction->noperands; argn++) 1739 { 1740 switch (instruction->opcode->args.nib[argn]) 1741 { 1742 case RD16: 1743 if (operand[argn].mode != RD16) 1744 { 1745 as_bad (_("destination operand must be 16 bit register")); 1746 return; 1747 1748 } 1749 break; 1750 1751 case RS8: 1752 if (operand[argn].mode != RS8) 1753 { 1754 as_bad (_("source operand must be 8 bit register")); 1755 return; 1756 } 1757 break; 1758 1759 case ABS16DST: 1760 if (operand[argn].mode != ABS16DST) 1761 { 1762 as_bad (_("destination operand must be 16bit absolute address")); 1763 return; 1764 } 1765 break; 1766 case RD8: 1767 if (operand[argn].mode != RD8) 1768 { 1769 as_bad (_("destination operand must be 8 bit register")); 1770 return; 1771 } 1772 break; 1773 1774 case ABS16SRC: 1775 if (operand[argn].mode != ABS16SRC) 1776 { 1777 as_bad (_("source operand must be 16bit absolute address")); 1778 return; 1779 } 1780 break; 1781 1782 } 1783 } 1784 } 1785 as_bad (_("invalid operands")); 1786} 1787 1788 1789/* If OPERAND is part of an address, adjust its size and value given 1790 that it addresses SIZE bytes. 1791 1792 This function decides how big non-immediate constants are when no 1793 size was explicitly given. It also scales down the assembly-level 1794 displacement in an @(d:2,ERn) operand. */ 1795 1796static void 1797fix_operand_size (struct h8_op *operand, int size) 1798{ 1799 if (SXmode && (operand->mode & MODE) == DISP) 1800 { 1801 /* If the user didn't specify an operand width, see if we 1802 can use @(d:2,ERn). */ 1803 if ((operand->mode & SIZE) == 0 1804 && operand->exp.X_add_symbol == 0 1805 && operand->exp.X_op_symbol == 0 1806 && (operand->exp.X_add_number == size 1807 || operand->exp.X_add_number == size * 2 1808 || operand->exp.X_add_number == size * 3)) 1809 operand->mode |= L_2; 1810 1811 /* Scale down the displacement in an @(d:2,ERn) operand. 1812 X_add_number then contains the desired field value. */ 1813 if ((operand->mode & SIZE) == L_2) 1814 { 1815 if (operand->exp.X_add_number % size != 0) 1816 as_warn (_("operand/size mis-match")); 1817 operand->exp.X_add_number /= size; 1818 } 1819 } 1820 1821 if ((operand->mode & SIZE) == 0) 1822 switch (operand->mode & MODE) 1823 { 1824 case DISP: 1825 case INDEXB: 1826 case INDEXW: 1827 case INDEXL: 1828 case ABS: 1829 /* Pick a 24-bit address unless we know that a 16-bit address 1830 is safe. get_specific() will relax L_24 into L_32 where 1831 necessary. */ 1832 if (Hmode 1833 && !Nmode 1834 && (operand->exp.X_add_number < -32768 1835 || operand->exp.X_add_number > 32767 1836 || operand->exp.X_add_symbol != 0 1837 || operand->exp.X_op_symbol != 0)) 1838 operand->mode |= L_24; 1839 else 1840 operand->mode |= L_16; 1841 break; 1842 1843 case PCREL: 1844 /* This condition is long standing, though somewhat suspect. */ 1845 if (operand->exp.X_add_number > -128 1846 && operand->exp.X_add_number < 127) 1847 operand->mode |= L_8; 1848 else 1849 operand->mode |= L_16; 1850 break; 1851 } 1852} 1853 1854 1855/* This is the guts of the machine-dependent assembler. STR points to 1856 a machine dependent instruction. This function is supposed to emit 1857 the frags/bytes it assembles. */ 1858 1859void 1860md_assemble (char *str) 1861{ 1862 char *op_start; 1863 char *op_end; 1864 struct h8_op operand[3]; 1865 const struct h8_instruction *instruction; 1866 const struct h8_instruction *prev_instruction; 1867 1868 char *dot = 0; 1869 char *slash = 0; 1870 char c; 1871 int size, i; 1872 1873 /* Drop leading whitespace. */ 1874 while (*str == ' ') 1875 str++; 1876 1877 /* Find the op code end. */ 1878 for (op_start = op_end = str; 1879 *op_end != 0 && *op_end != ' '; 1880 op_end++) 1881 { 1882 if (*op_end == '.') 1883 { 1884 dot = op_end + 1; 1885 *op_end = 0; 1886 op_end += 2; 1887 break; 1888 } 1889 else if (*op_end == '/' && ! slash) 1890 slash = op_end; 1891 } 1892 1893 if (op_end == op_start) 1894 { 1895 as_bad (_("can't find opcode ")); 1896 } 1897 c = *op_end; 1898 1899 *op_end = 0; 1900 1901 /* The assembler stops scanning the opcode at slashes, so it fails 1902 to make characters following them lower case. Fix them. */ 1903 if (slash) 1904 while (*++slash) 1905 *slash = TOLOWER (*slash); 1906 1907 instruction = (const struct h8_instruction *) 1908 hash_find (opcode_hash_control, op_start); 1909 1910 if (instruction == NULL) 1911 { 1912 as_bad (_("unknown opcode")); 1913 return; 1914 } 1915 1916 /* We used to set input_line_pointer to the result of get_operands, 1917 but that is wrong. Our caller assumes we don't change it. */ 1918 1919 operand[0].mode = 0; 1920 operand[1].mode = 0; 1921 operand[2].mode = 0; 1922 1923 if (OP_KIND (instruction->opcode->how) == O_MOVAB 1924 || OP_KIND (instruction->opcode->how) == O_MOVAW 1925 || OP_KIND (instruction->opcode->how) == O_MOVAL) 1926 get_mova_operands (op_end, operand); 1927 else if (OP_KIND (instruction->opcode->how) == O_RTEL 1928 || OP_KIND (instruction->opcode->how) == O_RTSL) 1929 get_rtsl_operands (op_end, operand); 1930 else 1931 get_operands (instruction->noperands, op_end, operand); 1932 1933 *op_end = c; 1934 prev_instruction = instruction; 1935 1936 /* Now we have operands from instruction. 1937 Let's check them out for ldm and stm. */ 1938 if (OP_KIND (instruction->opcode->how) == O_LDM) 1939 { 1940 /* The first operand must be @er7+, and the 1941 second operand must be a register pair. */ 1942 if ((operand[0].mode != RSINC) 1943 || (operand[0].reg != 7) 1944 || ((operand[1].reg & 0x80000000) == 0)) 1945 as_bad (_("invalid operand in ldm")); 1946 } 1947 else if (OP_KIND (instruction->opcode->how) == O_STM) 1948 { 1949 /* The first operand must be a register pair, 1950 and the second operand must be @-er7. */ 1951 if (((operand[0].reg & 0x80000000) == 0) 1952 || (operand[1].mode != RDDEC) 1953 || (operand[1].reg != 7)) 1954 as_bad (_("invalid operand in stm")); 1955 } 1956 1957 size = SN; 1958 if (dot) 1959 { 1960 switch (TOLOWER (*dot)) 1961 { 1962 case 'b': 1963 size = SB; 1964 break; 1965 1966 case 'w': 1967 size = SW; 1968 break; 1969 1970 case 'l': 1971 size = SL; 1972 break; 1973 } 1974 } 1975 if (OP_KIND (instruction->opcode->how) == O_MOVAB || 1976 OP_KIND (instruction->opcode->how) == O_MOVAW || 1977 OP_KIND (instruction->opcode->how) == O_MOVAL) 1978 { 1979 switch (operand[0].mode & MODE) 1980 { 1981 case INDEXB: 1982 default: 1983 fix_operand_size (&operand[1], 1); 1984 break; 1985 case INDEXW: 1986 fix_operand_size (&operand[1], 2); 1987 break; 1988 case INDEXL: 1989 fix_operand_size (&operand[1], 4); 1990 break; 1991 } 1992 } 1993 else 1994 { 1995 for (i = 0; i < 3 && operand[i].mode != 0; i++) 1996 switch (size) 1997 { 1998 case SN: 1999 case SB: 2000 default: 2001 fix_operand_size (&operand[i], 1); 2002 break; 2003 case SW: 2004 fix_operand_size (&operand[i], 2); 2005 break; 2006 case SL: 2007 fix_operand_size (&operand[i], 4); 2008 break; 2009 } 2010 } 2011 2012 instruction = get_specific (instruction, operand, size); 2013 2014 if (instruction == 0) 2015 { 2016 /* Couldn't find an opcode which matched the operands. */ 2017 char *where = frag_more (2); 2018 2019 where[0] = 0x0; 2020 where[1] = 0x0; 2021 clever_message (prev_instruction, operand); 2022 2023 return; 2024 } 2025 2026 build_bytes (instruction, operand); 2027 2028#ifdef BFD_ASSEMBLER 2029 dwarf2_emit_insn (instruction->length); 2030#endif 2031} 2032 2033#ifndef BFD_ASSEMBLER 2034void 2035tc_crawl_symbol_chain (object_headers *headers ATTRIBUTE_UNUSED) 2036{ 2037 printf (_("call to tc_crawl_symbol_chain \n")); 2038} 2039#endif 2040 2041symbolS * 2042md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 2043{ 2044 return 0; 2045} 2046 2047#ifndef BFD_ASSEMBLER 2048void 2049tc_headers_hook (object_headers *headers ATTRIBUTE_UNUSED) 2050{ 2051 printf (_("call to tc_headers_hook \n")); 2052} 2053#endif 2054 2055/* Various routines to kill one day */ 2056/* Equal to MAX_PRECISION in atof-ieee.c */ 2057#define MAX_LITTLENUMS 6 2058 2059/* Turn a string in input_line_pointer into a floating point constant 2060 of type TYPE, and store the appropriate bytes in *LITP. The number 2061 of LITTLENUMS emitted is stored in *SIZEP. An error message is 2062 returned, or NULL on OK. */ 2063 2064char * 2065md_atof (int type, char *litP, int *sizeP) 2066{ 2067 int prec; 2068 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 2069 LITTLENUM_TYPE *wordP; 2070 char *t; 2071 2072 switch (type) 2073 { 2074 case 'f': 2075 case 'F': 2076 case 's': 2077 case 'S': 2078 prec = 2; 2079 break; 2080 2081 case 'd': 2082 case 'D': 2083 case 'r': 2084 case 'R': 2085 prec = 4; 2086 break; 2087 2088 case 'x': 2089 case 'X': 2090 prec = 6; 2091 break; 2092 2093 case 'p': 2094 case 'P': 2095 prec = 6; 2096 break; 2097 2098 default: 2099 *sizeP = 0; 2100 return _("Bad call to MD_ATOF()"); 2101 } 2102 t = atof_ieee (input_line_pointer, type, words); 2103 if (t) 2104 input_line_pointer = t; 2105 2106 *sizeP = prec * sizeof (LITTLENUM_TYPE); 2107 for (wordP = words; prec--;) 2108 { 2109 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE)); 2110 litP += sizeof (LITTLENUM_TYPE); 2111 } 2112 return 0; 2113} 2114 2115const char *md_shortopts = ""; 2116struct option md_longopts[] = { 2117 {NULL, no_argument, NULL, 0} 2118}; 2119 2120size_t md_longopts_size = sizeof (md_longopts); 2121 2122int 2123md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED) 2124{ 2125 return 0; 2126} 2127 2128void 2129md_show_usage (FILE *stream ATTRIBUTE_UNUSED) 2130{ 2131} 2132 2133void tc_aout_fix_to_chars (void); 2134 2135void 2136tc_aout_fix_to_chars (void) 2137{ 2138 printf (_("call to tc_aout_fix_to_chars \n")); 2139 abort (); 2140} 2141 2142void 2143md_convert_frag ( 2144#ifdef BFD_ASSEMBLER 2145 bfd *headers ATTRIBUTE_UNUSED, 2146#else 2147 object_headers *headers ATTRIBUTE_UNUSED, 2148#endif 2149 segT seg ATTRIBUTE_UNUSED, 2150 fragS *fragP ATTRIBUTE_UNUSED) 2151{ 2152 printf (_("call to md_convert_frag \n")); 2153 abort (); 2154} 2155 2156#ifdef BFD_ASSEMBLER 2157valueT 2158md_section_align (segT segment, valueT size) 2159{ 2160 int align = bfd_get_section_alignment (stdoutput, segment); 2161 return ((size + (1 << align) - 1) & (-1 << align)); 2162} 2163#else 2164valueT 2165md_section_align (segT seg, valueT size) 2166{ 2167 return ((size + (1 << section_alignment[(int) seg]) - 1) 2168 & (-1 << section_alignment[(int) seg])); 2169} 2170#endif 2171 2172 2173void 2174md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 2175{ 2176 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 2177 long val = *valP; 2178 2179 switch (fixP->fx_size) 2180 { 2181 case 1: 2182 *buf++ = val; 2183 break; 2184 case 2: 2185 *buf++ = (val >> 8); 2186 *buf++ = val; 2187 break; 2188 case 4: 2189 *buf++ = (val >> 24); 2190 *buf++ = (val >> 16); 2191 *buf++ = (val >> 8); 2192 *buf++ = val; 2193 break; 2194 default: 2195 abort (); 2196 } 2197 2198 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) 2199 fixP->fx_done = 1; 2200} 2201 2202int 2203md_estimate_size_before_relax (register fragS *fragP ATTRIBUTE_UNUSED, 2204 register segT segment_type ATTRIBUTE_UNUSED) 2205{ 2206 printf (_("call tomd_estimate_size_before_relax \n")); 2207 abort (); 2208} 2209 2210/* Put number into target byte order. */ 2211void 2212md_number_to_chars (char *ptr, valueT use, int nbytes) 2213{ 2214 number_to_chars_bigendian (ptr, use, nbytes); 2215} 2216 2217long 2218md_pcrel_from (fixS *fixP ATTRIBUTE_UNUSED) 2219{ 2220 abort (); 2221} 2222 2223#ifndef BFD_ASSEMBLER 2224void 2225tc_reloc_mangle (fixS *fix_ptr, struct internal_reloc *intr, bfd_vma base) 2226{ 2227 symbolS *symbol_ptr; 2228 2229 symbol_ptr = fix_ptr->fx_addsy; 2230 2231 /* If this relocation is attached to a symbol then it's ok 2232 to output it. */ 2233 if (fix_ptr->fx_r_type == TC_CONS_RELOC) 2234 { 2235 /* cons likes to create reloc32's whatever the size of the reloc.. 2236 */ 2237 switch (fix_ptr->fx_size) 2238 { 2239 case 4: 2240 intr->r_type = R_RELLONG; 2241 break; 2242 case 2: 2243 intr->r_type = R_RELWORD; 2244 break; 2245 case 1: 2246 intr->r_type = R_RELBYTE; 2247 break; 2248 default: 2249 abort (); 2250 } 2251 } 2252 else 2253 { 2254 intr->r_type = fix_ptr->fx_r_type; 2255 } 2256 2257 intr->r_vaddr = fix_ptr->fx_frag->fr_address + fix_ptr->fx_where + base; 2258 intr->r_offset = fix_ptr->fx_offset; 2259 2260 if (symbol_ptr) 2261 { 2262 if (symbol_ptr->sy_number != -1) 2263 intr->r_symndx = symbol_ptr->sy_number; 2264 else 2265 { 2266 symbolS *segsym; 2267 2268 /* This case arises when a reference is made to `.'. */ 2269 segsym = seg_info (S_GET_SEGMENT (symbol_ptr))->dot; 2270 if (segsym == NULL) 2271 intr->r_symndx = -1; 2272 else 2273 { 2274 intr->r_symndx = segsym->sy_number; 2275 intr->r_offset += S_GET_VALUE (symbol_ptr); 2276 } 2277 } 2278 } 2279 else 2280 intr->r_symndx = -1; 2281} 2282#else /* BFD_ASSEMBLER */ 2283arelent * 2284tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 2285{ 2286 arelent *rel; 2287 bfd_reloc_code_real_type r_type; 2288 2289 if (fixp->fx_addsy && fixp->fx_subsy) 2290 { 2291 if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy)) 2292 || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section) 2293 { 2294 as_bad_where (fixp->fx_file, fixp->fx_line, 2295 "Difference of symbols in different sections is not supported"); 2296 return NULL; 2297 } 2298 } 2299 2300 rel = (arelent *) xmalloc (sizeof (arelent)); 2301 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 2302 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 2303 rel->address = fixp->fx_frag->fr_address + fixp->fx_where; 2304 rel->addend = fixp->fx_offset; 2305 2306 r_type = fixp->fx_r_type; 2307 2308#define DEBUG 0 2309#if DEBUG 2310 fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type)); 2311 fflush(stderr); 2312#endif 2313 rel->howto = bfd_reloc_type_lookup (stdoutput, r_type); 2314 if (rel->howto == NULL) 2315 { 2316 as_bad_where (fixp->fx_file, fixp->fx_line, 2317 _("Cannot represent relocation type %s"), 2318 bfd_get_reloc_code_name (r_type)); 2319 return NULL; 2320 } 2321 2322 return rel; 2323} 2324#endif 2325