1/* 2 * File: include/asm-blackfin/mach-bf527/cdefBF52x_base.h 3 * Based on: 4 * Author: 5 * 6 * Created: 7 * Description: 8 * 9 * Rev: 10 * 11 * Modified: 12 * 13 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2, or (at your option) 18 * any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; see the file COPYING. 27 * If not, write to the Free Software Foundation, 28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 29 */ 30 31#ifndef _CDEF_BF52X_H 32 33#include "defBF52x_base.h" 34 35/* ==== begin from cdefBF534.h ==== */ 36 37/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 38#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 39#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) 40#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 41#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 42#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 43#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) 44#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 45#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 46#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 47#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) 48#define bfin_read_CHIPID() bfin_read16(CHIPID) 49#define bfin_write_CHIPID(val) bfin_write16(CHIPID, val) 50 51 52/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ 53#define bfin_read_SWRST() bfin_read16(SWRST) 54#define bfin_write_SWRST(val) bfin_write16(SWRST, val) 55#define bfin_read_SYSCR() bfin_read16(SYSCR) 56#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) 57 58#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) 59#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) 60#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) 61#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) 62/* legacy register name (below) provided for backwards code compatibility */ 63#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) 64#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val) 65 66#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) 67#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) 68#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) 69#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) 70#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) 71#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) 72#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) 73#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) 74 75#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) 76#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) 77/* legacy register name (below) provided for backwards code compatibility */ 78#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) 79#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val) 80 81#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) 82#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) 83/* legacy register name (below) provided for backwards code compatibility */ 84#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) 85#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val) 86 87/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ 88 89#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) 90#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) 91#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) 92#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) 93#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) 94#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) 95#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) 96#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) 97#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) 98#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) 99#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) 100#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) 101#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) 102#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) 103 104/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ 105#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) 106#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) 107#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) 108#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) 109#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) 110#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) 111 112 113/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ 114#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) 115#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) 116#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) 117#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) 118#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) 119#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) 120#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) 121#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) 122#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) 123#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) 124#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) 125#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val) 126#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) 127#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) 128 129 130/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ 131#define bfin_read_UART0_THR() bfin_read16(UART0_THR) 132#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) 133#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) 134#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) 135#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) 136#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) 137#define bfin_read_UART0_IER() bfin_read16(UART0_IER) 138#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) 139#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) 140#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) 141#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) 142#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) 143#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) 144#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) 145#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) 146#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) 147#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) 148#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) 149#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) 150#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) 151#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) 152#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) 153#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) 154#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) 155 156 157/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ 158#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) 159#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) 160#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) 161#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) 162#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) 163#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) 164#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) 165#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) 166#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) 167#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) 168#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) 169#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) 170#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) 171#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) 172 173 174/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ 175#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) 176#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) 177#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) 178#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) 179#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) 180#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) 181#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) 182#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) 183 184#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) 185#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) 186#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) 187#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) 188#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) 189#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) 190#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) 191#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) 192 193#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) 194#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) 195#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) 196#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) 197#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) 198#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) 199#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) 200#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) 201 202#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) 203#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) 204#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) 205#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) 206#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) 207#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) 208#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) 209#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) 210 211#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) 212#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) 213#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) 214#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) 215#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) 216#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) 217#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) 218#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) 219 220#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) 221#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) 222#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) 223#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) 224#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) 225#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) 226#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) 227#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) 228 229#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) 230#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) 231#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) 232#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) 233#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) 234#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) 235#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) 236#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) 237 238#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) 239#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) 240#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) 241#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) 242#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) 243#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) 244#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) 245#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) 246 247#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) 248#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) 249#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) 250#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) 251#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) 252#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) 253 254 255/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ 256#define bfin_read_PORTFIO() bfin_read16(PORTFIO) 257#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) 258#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) 259#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) 260#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) 261#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) 262#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) 263#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) 264#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) 265#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) 266#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) 267#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) 268#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) 269#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) 270#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) 271#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) 272#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) 273#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) 274#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) 275#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) 276#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) 277#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) 278#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) 279#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) 280#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) 281#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) 282#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) 283#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) 284#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) 285#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) 286#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) 287#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) 288#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) 289#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) 290 291 292/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ 293#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) 294#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) 295#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) 296#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) 297#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) 298#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) 299#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) 300#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) 301#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) 302#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) 303#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) 304#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) 305#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32) 306#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val) 307#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32) 308#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val) 309#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16) 310#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val) 311#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16) 312#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val) 313#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) 314#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) 315#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) 316#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) 317#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) 318#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) 319#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) 320#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) 321#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) 322#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) 323#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) 324#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) 325#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) 326#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) 327#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) 328#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) 329#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) 330#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) 331#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) 332#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) 333#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) 334#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) 335#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) 336#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) 337#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) 338#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) 339#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) 340#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) 341#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) 342#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) 343#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) 344#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) 345 346 347/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ 348#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) 349#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) 350#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) 351#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) 352#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) 353#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) 354#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) 355#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) 356#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) 357#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) 358#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) 359#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) 360#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32) 361#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val) 362#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32) 363#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val) 364#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16) 365#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val) 366#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16) 367#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val) 368#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) 369#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) 370#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) 371#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) 372#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) 373#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) 374#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) 375#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) 376#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) 377#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) 378#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) 379#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) 380#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) 381#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) 382#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) 383#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) 384#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) 385#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) 386#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) 387#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) 388#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) 389#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) 390#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) 391#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) 392#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) 393#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) 394#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) 395#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) 396#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) 397#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) 398#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) 399#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) 400 401 402/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ 403#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) 404#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) 405#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) 406#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) 407#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) 408#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) 409#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) 410#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) 411#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) 412#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) 413#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) 414#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) 415#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) 416#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) 417 418 419/* DMA Traffic Control Registers */ 420#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) 421#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) 422#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) 423#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) 424 425/* Alternate deprecated register names (below) provided for backwards code compatibility */ 426#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) 427#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val) 428#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) 429#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val) 430 431/* DMA Controller */ 432#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) 433#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) 434#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) 435#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) 436#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) 437#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) 438#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) 439#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) 440#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) 441#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) 442#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) 443#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) 444#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) 445#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) 446#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) 447#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) 448#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) 449#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) 450#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) 451#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) 452#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) 453#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) 454#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) 455#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) 456#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) 457#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) 458 459#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) 460#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) 461#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) 462#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) 463#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) 464#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) 465#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) 466#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) 467#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) 468#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) 469#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) 470#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) 471#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) 472#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) 473#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) 474#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) 475#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) 476#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) 477#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) 478#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) 479#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) 480#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) 481#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) 482#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) 483#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) 484#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) 485 486#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) 487#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) 488#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) 489#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) 490#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) 491#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) 492#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) 493#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) 494#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) 495#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) 496#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) 497#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) 498#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) 499#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) 500#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) 501#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) 502#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) 503#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) 504#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) 505#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) 506#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) 507#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) 508#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) 509#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) 510#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) 511#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) 512 513#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) 514#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) 515#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) 516#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) 517#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) 518#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) 519#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) 520#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) 521#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) 522#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) 523#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) 524#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) 525#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) 526#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) 527#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) 528#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) 529#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) 530#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) 531#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) 532#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) 533#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) 534#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) 535#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) 536#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) 537#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) 538#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) 539 540#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) 541#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) 542#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) 543#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) 544#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) 545#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) 546#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) 547#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) 548#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) 549#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) 550#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) 551#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) 552#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) 553#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) 554#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) 555#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) 556#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) 557#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) 558#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) 559#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) 560#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) 561#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) 562#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) 563#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) 564#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) 565#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) 566 567#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) 568#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) 569#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) 570#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) 571#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) 572#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) 573#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) 574#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) 575#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 576#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) 577#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) 578#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) 579#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) 580#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) 581#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) 582#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) 583#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) 584#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) 585#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) 586#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) 587#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) 588#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) 589#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) 590#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) 591#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) 592#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) 593 594#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) 595#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) 596#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) 597#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) 598#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) 599#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) 600#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) 601#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) 602#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) 603#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) 604#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) 605#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) 606#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) 607#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) 608#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) 609#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) 610#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) 611#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) 612#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) 613#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) 614#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) 615#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) 616#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) 617#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) 618#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) 619#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) 620 621#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) 622#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) 623#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) 624#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) 625#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) 626#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) 627#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) 628#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) 629#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) 630#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) 631#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) 632#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) 633#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) 634#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) 635#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) 636#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) 637#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) 638#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) 639#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) 640#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) 641#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) 642#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) 643#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) 644#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) 645#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) 646#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) 647 648#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) 649#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) 650#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) 651#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) 652#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) 653#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) 654#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) 655#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) 656#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) 657#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) 658#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) 659#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) 660#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) 661#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) 662#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) 663#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) 664#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) 665#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) 666#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) 667#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) 668#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) 669#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) 670#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) 671#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) 672#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) 673#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) 674 675#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) 676#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) 677#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) 678#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) 679#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) 680#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) 681#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) 682#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) 683#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) 684#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) 685#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) 686#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) 687#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) 688#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) 689#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) 690#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) 691#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) 692#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) 693#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) 694#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) 695#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) 696#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) 697#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) 698#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) 699#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) 700#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) 701 702#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) 703#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) 704#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) 705#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) 706#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) 707#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) 708#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) 709#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) 710#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) 711#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) 712#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) 713#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) 714#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) 715#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) 716#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) 717#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) 718#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) 719#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) 720#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) 721#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) 722#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) 723#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) 724#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) 725#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) 726#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) 727#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) 728 729#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) 730#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) 731#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) 732#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) 733#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) 734#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) 735#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) 736#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) 737#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) 738#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) 739#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) 740#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) 741#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) 742#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) 743#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) 744#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) 745#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) 746#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) 747#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) 748#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) 749#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) 750#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) 751#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) 752#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) 753#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) 754#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) 755 756#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) 757#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) 758#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) 759#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) 760#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) 761#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) 762#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) 763#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) 764#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) 765#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) 766#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) 767#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) 768#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) 769#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) 770#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) 771#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) 772#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) 773#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) 774#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) 775#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) 776#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) 777#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) 778#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) 779#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) 780#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) 781#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) 782 783#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) 784#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) 785#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) 786#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) 787#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) 788#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) 789#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) 790#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) 791#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) 792#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) 793#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) 794#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) 795#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) 796#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) 797#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) 798#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) 799#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) 800#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) 801#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) 802#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) 803#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) 804#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) 805#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) 806#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) 807#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) 808#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) 809 810#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) 811#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) 812#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) 813#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) 814#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) 815#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) 816#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) 817#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) 818#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) 819#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) 820#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) 821#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) 822#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) 823#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) 824#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) 825#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) 826#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) 827#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) 828#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) 829#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) 830#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) 831#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) 832#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) 833#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) 834#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) 835#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) 836 837#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) 838#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) 839#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) 840#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) 841#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) 842#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) 843#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) 844#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) 845#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) 846#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) 847#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) 848#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) 849#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) 850#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) 851#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) 852#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) 853#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) 854#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) 855#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) 856#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) 857#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) 858#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) 859#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) 860#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) 861#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) 862#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) 863 864 865/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ 866#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) 867#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) 868#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) 869#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) 870#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) 871#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) 872#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) 873#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) 874#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) 875#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) 876 877 878/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ 879#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) 880#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val) 881#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) 882#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val) 883#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) 884#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val) 885#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) 886#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val) 887#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) 888#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val) 889#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) 890#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val) 891#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) 892#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val) 893#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) 894#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val) 895#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) 896#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val) 897#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) 898#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val) 899#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) 900#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val) 901#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) 902#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val) 903#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) 904#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val) 905#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) 906#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val) 907#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) 908#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val) 909#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) 910#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val) 911 912 913/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ 914#define bfin_read_PORTGIO() bfin_read16(PORTGIO) 915#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) 916#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) 917#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) 918#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) 919#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) 920#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) 921#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) 922#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) 923#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) 924#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) 925#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) 926#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) 927#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) 928#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) 929#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) 930#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) 931#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) 932#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) 933#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) 934#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) 935#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) 936#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) 937#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) 938#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) 939#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) 940#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) 941#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) 942#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) 943#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) 944#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) 945#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) 946#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) 947#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) 948 949 950/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ 951#define bfin_read_PORTHIO() bfin_read16(PORTHIO) 952#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) 953#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) 954#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) 955#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) 956#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) 957#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) 958#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) 959#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) 960#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) 961#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) 962#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) 963#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) 964#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) 965#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) 966#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) 967#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) 968#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) 969#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) 970#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) 971#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) 972#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) 973#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) 974#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) 975#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) 976#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) 977#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) 978#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) 979#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) 980#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) 981#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) 982#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) 983#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) 984#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) 985 986 987/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ 988#define bfin_read_UART1_THR() bfin_read16(UART1_THR) 989#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) 990#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) 991#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) 992#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) 993#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) 994#define bfin_read_UART1_IER() bfin_read16(UART1_IER) 995#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) 996#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) 997#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) 998#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) 999#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) 1000#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) 1001#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) 1002#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) 1003#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) 1004#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) 1005#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) 1006#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) 1007#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) 1008#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) 1009#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) 1010#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) 1011#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) 1012 1013/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */ 1014 1015/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ 1016#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) 1017#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) 1018#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) 1019#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) 1020#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) 1021#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) 1022#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) 1023#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) 1024 1025 1026/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ 1027#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) 1028#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) 1029#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) 1030#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) 1031#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) 1032#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) 1033#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) 1034#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) 1035#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) 1036#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) 1037#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) 1038#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) 1039#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) 1040#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) 1041 1042#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) 1043#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) 1044#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) 1045#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) 1046#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) 1047#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) 1048#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) 1049#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) 1050#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) 1051#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) 1052#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) 1053#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) 1054#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) 1055#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) 1056 1057/* ==== end from cdefBF534.h ==== */ 1058 1059/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ 1060 1061#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) 1062#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) 1063#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) 1064#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) 1065#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) 1066#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) 1067 1068#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) 1069#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) 1070#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) 1071#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) 1072#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) 1073#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) 1074#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) 1075#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) 1076#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) 1077#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) 1078#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) 1079#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) 1080#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS) 1081#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val) 1082#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS) 1083#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val) 1084#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS) 1085#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val) 1086#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE) 1087#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val) 1088#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW) 1089#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val) 1090#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS) 1091#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val) 1092 1093/* HOST Port Registers */ 1094 1095#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) 1096#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) 1097#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) 1098#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) 1099#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) 1100#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) 1101 1102/* Counter Registers */ 1103 1104#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) 1105#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) 1106#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) 1107#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) 1108#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) 1109#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) 1110#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) 1111#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) 1112#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) 1113#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) 1114#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) 1115#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) 1116#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) 1117#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) 1118#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) 1119#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) 1120 1121/* OTP/FUSE Registers */ 1122 1123#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) 1124#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) 1125#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) 1126#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) 1127#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) 1128#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) 1129#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) 1130#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) 1131 1132/* Security Registers */ 1133 1134#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) 1135#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) 1136#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) 1137#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) 1138#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) 1139#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) 1140 1141/* OTP Read/Write Data Buffer Registers */ 1142 1143#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) 1144#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) 1145#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) 1146#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) 1147#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) 1148#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) 1149#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) 1150#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) 1151 1152/* NFC Registers */ 1153 1154#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) 1155#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) 1156#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) 1157#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) 1158#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) 1159#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) 1160#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) 1161#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) 1162#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) 1163#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) 1164#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) 1165#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) 1166#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) 1167#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) 1168#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) 1169#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) 1170#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) 1171#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) 1172#define bfin_read_NFC_RST() bfin_read16(NFC_RST) 1173#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) 1174#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) 1175#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) 1176#define bfin_read_NFC_READ() bfin_read16(NFC_READ) 1177#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) 1178#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) 1179#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) 1180#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) 1181#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) 1182#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) 1183#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) 1184#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) 1185#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) 1186 1187#endif /* _CDEF_BF52X_H */ 1188