1/*
2 * icom.h
3 *
4 * Copyright (C) 2001 Michael Anderson, IBM Corporation
5 *
6 * Serial device driver include file.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
21 */
22
23#include<linux/serial_core.h>
24
25#define BAUD_TABLE_LIMIT	((sizeof(icom_acfg_baud)/sizeof(int)) - 1)
26static int icom_acfg_baud[] = {
27	300,
28	600,
29	900,
30	1200,
31	1800,
32	2400,
33	3600,
34	4800,
35	7200,
36	9600,
37	14400,
38	19200,
39	28800,
40	38400,
41	57600,
42	76800,
43	115200,
44	153600,
45	230400,
46	307200,
47	460800,
48};
49
50struct icom_regs {
51	u32 control;		/* Adapter Control Register     */
52	u32 interrupt;		/* Adapter Interrupt Register   */
53	u32 int_mask;		/* Adapter Interrupt Mask Reg   */
54	u32 int_pri;		/* Adapter Interrupt Priority r */
55	u32 int_reg_b;		/* Adapter non-masked Interrupt */
56	u32 resvd01;
57	u32 resvd02;
58	u32 resvd03;
59	u32 control_2;		/* Adapter Control Register 2   */
60	u32 interrupt_2;	/* Adapter Interrupt Register 2 */
61	u32 int_mask_2;		/* Adapter Interrupt Mask 2     */
62	u32 int_pri_2;		/* Adapter Interrupt Prior 2    */
63	u32 int_reg_2b;		/* Adapter non-masked 2         */
64};
65
66struct func_dram {
67	u32 reserved[108];	/* 0-1B0   reserved by personality code */
68	u32 RcvStatusAddr;	/* 1B0-1B3 Status Address for Next rcv */
69	u8 RcvStnAddr;		/* 1B4     Receive Station Addr */
70	u8 IdleState;		/* 1B5     Idle State */
71	u8 IdleMonitor;		/* 1B6     Idle Monitor */
72	u8 FlagFillIdleTimer;	/* 1B7     Flag Fill Idle Timer */
73	u32 XmitStatusAddr;	/* 1B8-1BB Transmit Status Address */
74	u8 StartXmitCmd;	/* 1BC     Start Xmit Command */
75	u8 HDLCConfigReg;	/* 1BD     Reserved */
76	u8 CauseCode;		/* 1BE     Cause code for fatal error */
77	u8 xchar;		/* 1BF     High priority send */
78	u32 reserved3;		/* 1C0-1C3 Reserved */
79	u8 PrevCmdReg;		/* 1C4     Reserved */
80	u8 CmdReg;		/* 1C5     Command Register */
81	u8 async_config2;	/* 1C6     Async Config Byte 2 */
82	u8 async_config3;	/* 1C7     Async Config Byte 3 */
83	u8 dce_resvd[20];	/* 1C8-1DB DCE Rsvd           */
84	u8 dce_resvd21;		/* 1DC     DCE Rsvd (21st byte */
85	u8 misc_flags;		/* 1DD     misc flags         */
86#define V2_HARDWARE     0x40
87#define ICOM_HDW_ACTIVE 0x01
88	u8 call_length;		/* 1DE     Phone #/CFI buff ln */
89	u8 call_length2;	/* 1DF     Upper byte (unused) */
90	u32 call_addr;		/* 1E0-1E3 Phn #/CFI buff addr */
91	u16 timer_value;	/* 1E4-1E5 general timer value */
92	u8 timer_command;	/* 1E6     general timer cmd  */
93	u8 dce_command;		/* 1E7     dce command reg    */
94	u8 dce_cmd_status;	/* 1E8     dce command stat   */
95	u8 x21_r1_ioff;		/* 1E9     dce ready counter  */
96	u8 x21_r0_ioff;		/* 1EA     dce not ready ctr  */
97	u8 x21_ralt_ioff;	/* 1EB     dce CNR counter    */
98	u8 x21_r1_ion;		/* 1EC     dce ready I on ctr */
99	u8 rsvd_ier;		/* 1ED     Rsvd for IER (if ne */
100	u8 ier;			/* 1EE     Interrupt Enable   */
101	u8 isr;			/* 1EF     Input Signal Reg   */
102	u8 osr;			/* 1F0     Output Signal Reg  */
103	u8 reset;		/* 1F1     Reset/Reload Reg   */
104	u8 disable;		/* 1F2     Disable Reg        */
105	u8 sync;		/* 1F3     Sync Reg           */
106	u8 error_stat;		/* 1F4     Error Status       */
107	u8 cable_id;		/* 1F5     Cable ID           */
108	u8 cs_length;		/* 1F6     CS Load Length     */
109	u8 mac_length;		/* 1F7     Mac Load Length    */
110	u32 cs_load_addr;	/* 1F8-1FB Call Load PCI Addr */
111	u32 mac_load_addr;	/* 1FC-1FF Mac Load PCI Addr  */
112};
113
114/*
115 * adapter defines and structures
116 */
117#define ICOM_CONTROL_START_A         0x00000008
118#define ICOM_CONTROL_STOP_A          0x00000004
119#define ICOM_CONTROL_START_B         0x00000002
120#define ICOM_CONTROL_STOP_B          0x00000001
121#define ICOM_CONTROL_START_C         0x00000008
122#define ICOM_CONTROL_STOP_C          0x00000004
123#define ICOM_CONTROL_START_D         0x00000002
124#define ICOM_CONTROL_STOP_D          0x00000001
125#define ICOM_IRAM_OFFSET             0x1000
126#define ICOM_IRAM_SIZE               0x0C00
127#define ICOM_DCE_IRAM_OFFSET         0x0A00
128#define ICOM_CABLE_ID_VALID          0x01
129#define ICOM_CABLE_ID_MASK           0xF0
130#define ICOM_DISABLE                 0x80
131#define CMD_XMIT_RCV_ENABLE          0xC0
132#define CMD_XMIT_ENABLE              0x40
133#define CMD_RCV_DISABLE              0x00
134#define CMD_RCV_ENABLE               0x80
135#define CMD_RESTART                  0x01
136#define CMD_HOLD_XMIT                0x02
137#define CMD_SND_BREAK                0x04
138#define RS232_CABLE                  0x06
139#define V24_CABLE                    0x0E
140#define V35_CABLE                    0x0C
141#define V36_CABLE                    0x02
142#define NO_CABLE                     0x00
143#define START_DOWNLOAD               0x80
144#define ICOM_INT_MASK_PRC_A          0x00003FFF
145#define ICOM_INT_MASK_PRC_B          0x3FFF0000
146#define ICOM_INT_MASK_PRC_C          0x00003FFF
147#define ICOM_INT_MASK_PRC_D          0x3FFF0000
148#define INT_RCV_COMPLETED            0x1000
149#define INT_XMIT_COMPLETED           0x2000
150#define INT_IDLE_DETECT              0x0800
151#define INT_RCV_DISABLED             0x0400
152#define INT_XMIT_DISABLED            0x0200
153#define INT_RCV_XMIT_SHUTDOWN        0x0100
154#define INT_FATAL_ERROR              0x0080
155#define INT_CABLE_PULL               0x0020
156#define INT_SIGNAL_CHANGE            0x0010
157#define HDLC_PPP_PURE_ASYNC          0x02
158#define HDLC_FF_FILL                 0x00
159#define HDLC_HDW_FLOW                0x01
160#define START_XMIT                   0x80
161#define ICOM_ACFG_DRIVE1             0x20
162#define ICOM_ACFG_NO_PARITY          0x00
163#define ICOM_ACFG_PARITY_ENAB        0x02
164#define ICOM_ACFG_PARITY_ODD         0x01
165#define ICOM_ACFG_8BPC               0x00
166#define ICOM_ACFG_7BPC               0x04
167#define ICOM_ACFG_6BPC               0x08
168#define ICOM_ACFG_5BPC               0x0C
169#define ICOM_ACFG_1STOP_BIT          0x00
170#define ICOM_ACFG_2STOP_BIT          0x10
171#define ICOM_DTR                     0x80
172#define ICOM_RTS                     0x40
173#define ICOM_RI                      0x08
174#define ICOM_DSR                     0x80
175#define ICOM_DCD                     0x20
176#define ICOM_CTS                     0x40
177
178#define NUM_XBUFFS 1
179#define NUM_RBUFFS 2
180#define RCV_BUFF_SZ 0x0200
181#define XMIT_BUFF_SZ 0x1000
182struct statusArea {
183    /**********************************************/
184	/* Transmit Status Area                       */
185    /**********************************************/
186	struct xmit_status_area{
187		u32 leNext;	/* Next entry in Little Endian on Adapter */
188		u32 leNextASD;
189		u32 leBuffer;	/* Buffer for entry in LE for Adapter */
190		u16 leLengthASD;
191		u16 leOffsetASD;
192		u16 leLength;	/* Length of data in segment */
193		u16 flags;
194#define SA_FLAGS_DONE           0x0080	/* Done with Segment */
195#define SA_FLAGS_CONTINUED      0x8000	/* More Segments */
196#define SA_FLAGS_IDLE           0x4000	/* Mark IDLE after frm */
197#define SA_FLAGS_READY_TO_XMIT  0x0800
198#define SA_FLAGS_STAT_MASK      0x007F
199	} xmit[NUM_XBUFFS];
200
201    /**********************************************/
202	/* Receive Status Area                        */
203    /**********************************************/
204	struct {
205		u32 leNext;	/* Next entry in Little Endian on Adapter */
206		u32 leNextASD;
207		u32 leBuffer;	/* Buffer for entry in LE for Adapter */
208		u16 WorkingLength;	/* size of segment */
209		u16 reserv01;
210		u16 leLength;	/* Length of data in segment */
211		u16 flags;
212#define SA_FL_RCV_DONE           0x0010	/* Data ready */
213#define SA_FLAGS_OVERRUN         0x0040
214#define SA_FLAGS_PARITY_ERROR    0x0080
215#define SA_FLAGS_FRAME_ERROR     0x0001
216#define SA_FLAGS_FRAME_TRUNC     0x0002
217#define SA_FLAGS_BREAK_DET       0x0004	/* set conditionally by device driver, not hardware */
218#define SA_FLAGS_RCV_MASK        0xFFE6
219	} rcv[NUM_RBUFFS];
220};
221
222struct icom_adapter;
223
224
225#define ICOM_MAJOR       243
226#define ICOM_MINOR_START 0
227
228struct icom_port {
229	struct uart_port uart_port;
230	u8 imbed_modem;
231#define ICOM_UNKNOWN		1
232#define ICOM_RVX		2
233#define ICOM_IMBED_MODEM	3
234	unsigned char cable_id;
235	unsigned char read_status_mask;
236	unsigned char ignore_status_mask;
237	void __iomem * int_reg;
238	struct icom_regs __iomem *global_reg;
239	struct func_dram __iomem *dram;
240	int port;
241	struct statusArea *statStg;
242	dma_addr_t statStg_pci;
243	u32 *xmitRestart;
244	dma_addr_t xmitRestart_pci;
245	unsigned char *xmit_buf;
246	dma_addr_t xmit_buf_pci;
247	unsigned char *recv_buf;
248	dma_addr_t recv_buf_pci;
249	int next_rcv;
250	int put_length;
251	int status;
252#define ICOM_PORT_ACTIVE	1	/* Port exists. */
253#define ICOM_PORT_OFF		0	/* Port does not exist. */
254	int load_in_progress;
255	struct icom_adapter *adapter;
256};
257
258struct icom_adapter {
259	void __iomem * base_addr;
260	unsigned long base_addr_pci;
261	struct pci_dev *pci_dev;
262	struct icom_port port_info[4];
263	int index;
264	int version;
265#define ADAPTER_V1	0x0001
266#define ADAPTER_V2	0x0002
267	u32 subsystem_id;
268#define FOUR_PORT_MODEL				0x0252
269#define V2_TWO_PORTS_RVX			0x021A
270#define V2_ONE_PORT_RVX_ONE_PORT_IMBED_MDM	0x0251
271	int numb_ports;
272	struct list_head icom_adapter_entry;
273	struct kobject kobj;
274};
275
276/* prototype */
277extern void iCom_sercons_init(void);
278
279struct lookup_proc_table {
280	u32	__iomem *global_control_reg;
281	unsigned long	processor_id;
282};
283
284struct lookup_int_table {
285	u32	__iomem *global_int_mask;
286	unsigned long	processor_id;
287};
288