1/* 2 * PCI Express PCI Hot Plug Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM Corp. 7 * Copyright (C) 2003-2004 Intel Corporation 8 * 9 * All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 19 * NON INFRINGEMENT. See the GNU General Public License for more 20 * details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 27 * 28 */ 29 30#include <linux/kernel.h> 31#include <linux/module.h> 32#include <linux/types.h> 33#include <linux/signal.h> 34#include <linux/jiffies.h> 35#include <linux/timer.h> 36#include <linux/pci.h> 37#include <linux/interrupt.h> 38#include <linux/time.h> 39 40#include "../pci.h" 41#include "pciehp.h" 42#ifdef DEBUG 43#define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */ 44#define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */ 45#define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */ 46#define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */ 47#define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT) 48#define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE) 49/* Redefine this flagword to set debug level */ 50#define DEBUG_LEVEL DBG_K_STANDARD 51 52#define DEFINE_DBG_BUFFER char __dbg_str_buf[256]; 53 54#define DBG_PRINT( dbg_flags, args... ) \ 55 do { \ 56 if ( DEBUG_LEVEL & ( dbg_flags ) ) \ 57 { \ 58 int len; \ 59 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \ 60 __FILE__, __LINE__, __FUNCTION__ ); \ 61 sprintf( __dbg_str_buf + len, args ); \ 62 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \ 63 } \ 64 } while (0) 65 66#define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]"); 67#define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]"); 68#else 69#define DEFINE_DBG_BUFFER 70#define DBG_ENTER_ROUTINE 71#define DBG_LEAVE_ROUTINE 72#endif /* DEBUG */ 73 74static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); 75 76struct ctrl_reg { 77 u8 cap_id; 78 u8 nxt_ptr; 79 u16 cap_reg; 80 u32 dev_cap; 81 u16 dev_ctrl; 82 u16 dev_status; 83 u32 lnk_cap; 84 u16 lnk_ctrl; 85 u16 lnk_status; 86 u32 slot_cap; 87 u16 slot_ctrl; 88 u16 slot_status; 89 u16 root_ctrl; 90 u16 rsvp; 91 u32 root_status; 92} __attribute__ ((packed)); 93 94/* offsets to the controller registers based on the above structure layout */ 95enum ctrl_offsets { 96 PCIECAPID = offsetof(struct ctrl_reg, cap_id), 97 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr), 98 CAPREG = offsetof(struct ctrl_reg, cap_reg), 99 DEVCAP = offsetof(struct ctrl_reg, dev_cap), 100 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl), 101 DEVSTATUS = offsetof(struct ctrl_reg, dev_status), 102 LNKCAP = offsetof(struct ctrl_reg, lnk_cap), 103 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl), 104 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status), 105 SLOTCAP = offsetof(struct ctrl_reg, slot_cap), 106 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl), 107 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status), 108 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl), 109 ROOTSTATUS = offsetof(struct ctrl_reg, root_status), 110}; 111 112static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) 113{ 114 struct pci_dev *dev = ctrl->pci_dev; 115 return pci_read_config_word(dev, ctrl->cap_base + reg, value); 116} 117 118static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) 119{ 120 struct pci_dev *dev = ctrl->pci_dev; 121 return pci_read_config_dword(dev, ctrl->cap_base + reg, value); 122} 123 124static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) 125{ 126 struct pci_dev *dev = ctrl->pci_dev; 127 return pci_write_config_word(dev, ctrl->cap_base + reg, value); 128} 129 130static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) 131{ 132 struct pci_dev *dev = ctrl->pci_dev; 133 return pci_write_config_dword(dev, ctrl->cap_base + reg, value); 134} 135 136/* Field definitions in PCI Express Capabilities Register */ 137#define CAP_VER 0x000F 138#define DEV_PORT_TYPE 0x00F0 139#define SLOT_IMPL 0x0100 140#define MSG_NUM 0x3E00 141 142/* Device or Port Type */ 143#define NAT_ENDPT 0x00 144#define LEG_ENDPT 0x01 145#define ROOT_PORT 0x04 146#define UP_STREAM 0x05 147#define DN_STREAM 0x06 148#define PCIE_PCI_BRDG 0x07 149#define PCI_PCIE_BRDG 0x10 150 151/* Field definitions in Device Capabilities Register */ 152#define DATTN_BUTTN_PRSN 0x1000 153#define DATTN_LED_PRSN 0x2000 154#define DPWR_LED_PRSN 0x4000 155 156/* Field definitions in Link Capabilities Register */ 157#define MAX_LNK_SPEED 0x000F 158#define MAX_LNK_WIDTH 0x03F0 159 160/* Link Width Encoding */ 161#define LNK_X1 0x01 162#define LNK_X2 0x02 163#define LNK_X4 0x04 164#define LNK_X8 0x08 165#define LNK_X12 0x0C 166#define LNK_X16 0x10 167#define LNK_X32 0x20 168 169/*Field definitions of Link Status Register */ 170#define LNK_SPEED 0x000F 171#define NEG_LINK_WD 0x03F0 172#define LNK_TRN_ERR 0x0400 173#define LNK_TRN 0x0800 174#define SLOT_CLK_CONF 0x1000 175 176/* Field definitions in Slot Capabilities Register */ 177#define ATTN_BUTTN_PRSN 0x00000001 178#define PWR_CTRL_PRSN 0x00000002 179#define MRL_SENS_PRSN 0x00000004 180#define ATTN_LED_PRSN 0x00000008 181#define PWR_LED_PRSN 0x00000010 182#define HP_SUPR_RM_SUP 0x00000020 183#define HP_CAP 0x00000040 184#define SLOT_PWR_VALUE 0x000003F8 185#define SLOT_PWR_LIMIT 0x00000C00 186#define PSN 0xFFF80000 /* PSN: Physical Slot Number */ 187 188/* Field definitions in Slot Control Register */ 189#define ATTN_BUTTN_ENABLE 0x0001 190#define PWR_FAULT_DETECT_ENABLE 0x0002 191#define MRL_DETECT_ENABLE 0x0004 192#define PRSN_DETECT_ENABLE 0x0008 193#define CMD_CMPL_INTR_ENABLE 0x0010 194#define HP_INTR_ENABLE 0x0020 195#define ATTN_LED_CTRL 0x00C0 196#define PWR_LED_CTRL 0x0300 197#define PWR_CTRL 0x0400 198#define EMI_CTRL 0x0800 199 200/* Attention indicator and Power indicator states */ 201#define LED_ON 0x01 202#define LED_BLINK 0x10 203#define LED_OFF 0x11 204 205/* Power Control Command */ 206#define POWER_ON 0 207#define POWER_OFF 0x0400 208 209/* EMI Status defines */ 210#define EMI_DISENGAGED 0 211#define EMI_ENGAGED 1 212 213/* Field definitions in Slot Status Register */ 214#define ATTN_BUTTN_PRESSED 0x0001 215#define PWR_FAULT_DETECTED 0x0002 216#define MRL_SENS_CHANGED 0x0004 217#define PRSN_DETECT_CHANGED 0x0008 218#define CMD_COMPLETED 0x0010 219#define MRL_STATE 0x0020 220#define PRSN_STATE 0x0040 221#define EMI_STATE 0x0080 222#define EMI_STATUS_BIT 7 223 224DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ 225 226static irqreturn_t pcie_isr(int irq, void *dev_id); 227static void start_int_poll_timer(struct controller *ctrl, int sec); 228 229/* This is the interrupt polling timeout function. */ 230static void int_poll_timeout(unsigned long data) 231{ 232 struct controller *ctrl = (struct controller *)data; 233 234 DBG_ENTER_ROUTINE 235 236 /* Poll for interrupt events. regs == NULL => polling */ 237 pcie_isr(0, ctrl); 238 239 init_timer(&ctrl->poll_timer); 240 if (!pciehp_poll_time) 241 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/ 242 243 start_int_poll_timer(ctrl, pciehp_poll_time); 244} 245 246/* This function starts the interrupt polling timer. */ 247static void start_int_poll_timer(struct controller *ctrl, int sec) 248{ 249 /* Clamp to sane value */ 250 if ((sec <= 0) || (sec > 60)) 251 sec = 2; 252 253 ctrl->poll_timer.function = &int_poll_timeout; 254 ctrl->poll_timer.data = (unsigned long)ctrl; 255 ctrl->poll_timer.expires = jiffies + sec * HZ; 256 add_timer(&ctrl->poll_timer); 257} 258 259static inline int pcie_wait_cmd(struct controller *ctrl) 260{ 261 int retval = 0; 262 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; 263 unsigned long timeout = msecs_to_jiffies(msecs); 264 int rc; 265 266 rc = wait_event_interruptible_timeout(ctrl->queue, 267 !ctrl->cmd_busy, timeout); 268 if (!rc) 269 dbg("Command not completed in 1000 msec\n"); 270 else if (rc < 0) { 271 retval = -EINTR; 272 info("Command was interrupted by a signal\n"); 273 } 274 275 return retval; 276} 277 278static int pcie_write_cmd(struct slot *slot, u16 cmd) 279{ 280 struct controller *ctrl = slot->ctrl; 281 int retval = 0; 282 u16 slot_status; 283 284 DBG_ENTER_ROUTINE 285 286 mutex_lock(&ctrl->ctrl_lock); 287 288 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 289 if (retval) { 290 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); 291 goto out; 292 } 293 294 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) { 295 /* After 1 sec and CMD_COMPLETED still not set, just 296 proceed forward to issue the next command according 297 to spec. Just print out the error message */ 298 dbg("%s: CMD_COMPLETED not clear after 1 sec.\n", 299 __FUNCTION__); 300 } 301 302 ctrl->cmd_busy = 1; 303 retval = pciehp_writew(ctrl, SLOTCTRL, (cmd | CMD_CMPL_INTR_ENABLE)); 304 if (retval) { 305 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__); 306 goto out; 307 } 308 309 /* 310 * Wait for command completion. 311 */ 312 retval = pcie_wait_cmd(ctrl); 313 out: 314 mutex_unlock(&ctrl->ctrl_lock); 315 DBG_LEAVE_ROUTINE 316 return retval; 317} 318 319static int hpc_check_lnk_status(struct controller *ctrl) 320{ 321 u16 lnk_status; 322 int retval = 0; 323 324 DBG_ENTER_ROUTINE 325 326 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); 327 if (retval) { 328 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); 329 return retval; 330 } 331 332 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status); 333 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || 334 !(lnk_status & NEG_LINK_WD)) { 335 err("%s : Link Training Error occurs \n", __FUNCTION__); 336 retval = -1; 337 return retval; 338 } 339 340 DBG_LEAVE_ROUTINE 341 return retval; 342} 343 344 345static int hpc_get_attention_status(struct slot *slot, u8 *status) 346{ 347 struct controller *ctrl = slot->ctrl; 348 u16 slot_ctrl; 349 u8 atten_led_state; 350 int retval = 0; 351 352 DBG_ENTER_ROUTINE 353 354 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 355 if (retval) { 356 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); 357 return retval; 358 } 359 360 dbg("%s: SLOTCTRL %x, value read %x\n", 361 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl); 362 363 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; 364 365 switch (atten_led_state) { 366 case 0: 367 *status = 0xFF; /* Reserved */ 368 break; 369 case 1: 370 *status = 1; /* On */ 371 break; 372 case 2: 373 *status = 2; /* Blink */ 374 break; 375 case 3: 376 *status = 0; /* Off */ 377 break; 378 default: 379 *status = 0xFF; 380 break; 381 } 382 383 DBG_LEAVE_ROUTINE 384 return 0; 385} 386 387static int hpc_get_power_status(struct slot *slot, u8 *status) 388{ 389 struct controller *ctrl = slot->ctrl; 390 u16 slot_ctrl; 391 u8 pwr_state; 392 int retval = 0; 393 394 DBG_ENTER_ROUTINE 395 396 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 397 if (retval) { 398 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); 399 return retval; 400 } 401 dbg("%s: SLOTCTRL %x value read %x\n", 402 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl); 403 404 pwr_state = (slot_ctrl & PWR_CTRL) >> 10; 405 406 switch (pwr_state) { 407 case 0: 408 *status = 1; 409 break; 410 case 1: 411 *status = 0; 412 break; 413 default: 414 *status = 0xFF; 415 break; 416 } 417 418 DBG_LEAVE_ROUTINE 419 return retval; 420} 421 422 423static int hpc_get_latch_status(struct slot *slot, u8 *status) 424{ 425 struct controller *ctrl = slot->ctrl; 426 u16 slot_status; 427 int retval = 0; 428 429 DBG_ENTER_ROUTINE 430 431 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 432 if (retval) { 433 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); 434 return retval; 435 } 436 437 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; 438 439 DBG_LEAVE_ROUTINE 440 return 0; 441} 442 443static int hpc_get_adapter_status(struct slot *slot, u8 *status) 444{ 445 struct controller *ctrl = slot->ctrl; 446 u16 slot_status; 447 u8 card_state; 448 int retval = 0; 449 450 DBG_ENTER_ROUTINE 451 452 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 453 if (retval) { 454 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); 455 return retval; 456 } 457 card_state = (u8)((slot_status & PRSN_STATE) >> 6); 458 *status = (card_state == 1) ? 1 : 0; 459 460 DBG_LEAVE_ROUTINE 461 return 0; 462} 463 464static int hpc_query_power_fault(struct slot *slot) 465{ 466 struct controller *ctrl = slot->ctrl; 467 u16 slot_status; 468 u8 pwr_fault; 469 int retval = 0; 470 471 DBG_ENTER_ROUTINE 472 473 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 474 if (retval) { 475 err("%s: Cannot check for power fault\n", __FUNCTION__); 476 return retval; 477 } 478 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); 479 480 DBG_LEAVE_ROUTINE 481 return pwr_fault; 482} 483 484static int hpc_get_emi_status(struct slot *slot, u8 *status) 485{ 486 struct controller *ctrl = slot->ctrl; 487 u16 slot_status; 488 int retval = 0; 489 490 DBG_ENTER_ROUTINE 491 492 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 493 if (retval) { 494 err("%s : Cannot check EMI status\n", __FUNCTION__); 495 return retval; 496 } 497 *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT; 498 499 DBG_LEAVE_ROUTINE 500 return retval; 501} 502 503static int hpc_toggle_emi(struct slot *slot) 504{ 505 struct controller *ctrl = slot->ctrl; 506 u16 slot_cmd = 0; 507 u16 slot_ctrl; 508 int rc = 0; 509 510 DBG_ENTER_ROUTINE 511 512 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 513 if (rc) { 514 err("%s : hp_register_read_word SLOT_CTRL failed\n", 515 __FUNCTION__); 516 return rc; 517 } 518 519 slot_cmd = (slot_ctrl | EMI_CTRL); 520 if (!pciehp_poll_mode) 521 slot_cmd = slot_cmd | HP_INTR_ENABLE; 522 523 pcie_write_cmd(slot, slot_cmd); 524 slot->last_emi_toggle = get_seconds(); 525 DBG_LEAVE_ROUTINE 526 return rc; 527} 528 529static int hpc_set_attention_status(struct slot *slot, u8 value) 530{ 531 struct controller *ctrl = slot->ctrl; 532 u16 slot_cmd = 0; 533 u16 slot_ctrl; 534 int rc = 0; 535 536 DBG_ENTER_ROUTINE 537 538 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 539 if (rc) { 540 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); 541 return rc; 542 } 543 544 switch (value) { 545 case 0 : /* turn off */ 546 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0; 547 break; 548 case 1: /* turn on */ 549 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040; 550 break; 551 case 2: /* turn blink */ 552 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080; 553 break; 554 default: 555 return -1; 556 } 557 if (!pciehp_poll_mode) 558 slot_cmd = slot_cmd | HP_INTR_ENABLE; 559 560 pcie_write_cmd(slot, slot_cmd); 561 dbg("%s: SLOTCTRL %x write cmd %x\n", 562 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); 563 564 DBG_LEAVE_ROUTINE 565 return rc; 566} 567 568 569static void hpc_set_green_led_on(struct slot *slot) 570{ 571 struct controller *ctrl = slot->ctrl; 572 u16 slot_cmd; 573 u16 slot_ctrl; 574 int rc = 0; 575 576 DBG_ENTER_ROUTINE 577 578 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 579 if (rc) { 580 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); 581 return; 582 } 583 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100; 584 if (!pciehp_poll_mode) 585 slot_cmd = slot_cmd | HP_INTR_ENABLE; 586 587 pcie_write_cmd(slot, slot_cmd); 588 589 dbg("%s: SLOTCTRL %x write cmd %x\n", 590 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); 591 DBG_LEAVE_ROUTINE 592 return; 593} 594 595static void hpc_set_green_led_off(struct slot *slot) 596{ 597 struct controller *ctrl = slot->ctrl; 598 u16 slot_cmd; 599 u16 slot_ctrl; 600 int rc = 0; 601 602 DBG_ENTER_ROUTINE 603 604 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 605 if (rc) { 606 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); 607 return; 608 } 609 610 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300; 611 612 if (!pciehp_poll_mode) 613 slot_cmd = slot_cmd | HP_INTR_ENABLE; 614 pcie_write_cmd(slot, slot_cmd); 615 dbg("%s: SLOTCTRL %x write cmd %x\n", 616 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); 617 618 DBG_LEAVE_ROUTINE 619 return; 620} 621 622static void hpc_set_green_led_blink(struct slot *slot) 623{ 624 struct controller *ctrl = slot->ctrl; 625 u16 slot_cmd; 626 u16 slot_ctrl; 627 int rc = 0; 628 629 DBG_ENTER_ROUTINE 630 631 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 632 if (rc) { 633 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); 634 return; 635 } 636 637 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200; 638 639 if (!pciehp_poll_mode) 640 slot_cmd = slot_cmd | HP_INTR_ENABLE; 641 pcie_write_cmd(slot, slot_cmd); 642 643 dbg("%s: SLOTCTRL %x write cmd %x\n", 644 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); 645 DBG_LEAVE_ROUTINE 646 return; 647} 648 649static void hpc_release_ctlr(struct controller *ctrl) 650{ 651 DBG_ENTER_ROUTINE 652 653 if (pciehp_poll_mode) 654 del_timer(&ctrl->poll_timer); 655 else 656 free_irq(ctrl->pci_dev->irq, ctrl); 657 658 /* 659 * If this is the last controller to be released, destroy the 660 * pciehp work queue 661 */ 662 if (atomic_dec_and_test(&pciehp_num_controllers)) 663 destroy_workqueue(pciehp_wq); 664 665 DBG_LEAVE_ROUTINE 666} 667 668static int hpc_power_on_slot(struct slot * slot) 669{ 670 struct controller *ctrl = slot->ctrl; 671 u16 slot_cmd; 672 u16 slot_ctrl, slot_status; 673 int retval = 0; 674 675 DBG_ENTER_ROUTINE 676 677 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); 678 679 /* Clear sticky power-fault bit from previous power failures */ 680 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 681 if (retval) { 682 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); 683 return retval; 684 } 685 slot_status &= PWR_FAULT_DETECTED; 686 if (slot_status) { 687 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status); 688 if (retval) { 689 err("%s: Cannot write to SLOTSTATUS register\n", 690 __FUNCTION__); 691 return retval; 692 } 693 } 694 695 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 696 if (retval) { 697 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); 698 return retval; 699 } 700 701 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON; 702 703 /* Enable detection that we turned off at slot power-off time */ 704 if (!pciehp_poll_mode) 705 slot_cmd = slot_cmd | 706 PWR_FAULT_DETECT_ENABLE | 707 MRL_DETECT_ENABLE | 708 PRSN_DETECT_ENABLE | 709 HP_INTR_ENABLE; 710 711 retval = pcie_write_cmd(slot, slot_cmd); 712 713 if (retval) { 714 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd); 715 return -1; 716 } 717 dbg("%s: SLOTCTRL %x write cmd %x\n", 718 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); 719 720 DBG_LEAVE_ROUTINE 721 722 return retval; 723} 724 725static int hpc_power_off_slot(struct slot * slot) 726{ 727 struct controller *ctrl = slot->ctrl; 728 u16 slot_cmd; 729 u16 slot_ctrl; 730 int retval = 0; 731 732 DBG_ENTER_ROUTINE 733 734 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); 735 736 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 737 if (retval) { 738 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); 739 return retval; 740 } 741 742 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF; 743 744 /* 745 * If we get MRL or presence detect interrupts now, the isr 746 * will notice the sticky power-fault bit too and issue power 747 * indicator change commands. This will lead to an endless loop 748 * of command completions, since the power-fault bit remains on 749 * till the slot is powered on again. 750 */ 751 if (!pciehp_poll_mode) 752 slot_cmd = (slot_cmd & 753 ~PWR_FAULT_DETECT_ENABLE & 754 ~MRL_DETECT_ENABLE & 755 ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE; 756 757 retval = pcie_write_cmd(slot, slot_cmd); 758 759 if (retval) { 760 err("%s: Write command failed!\n", __FUNCTION__); 761 return -1; 762 } 763 dbg("%s: SLOTCTRL %x write cmd %x\n", 764 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); 765 766 DBG_LEAVE_ROUTINE 767 768 return retval; 769} 770 771static irqreturn_t pcie_isr(int irq, void *dev_id) 772{ 773 struct controller *ctrl = (struct controller *)dev_id; 774 u16 slot_status, intr_detect, intr_loc; 775 u16 temp_word; 776 int hp_slot = 0; /* only 1 slot per PCI Express port */ 777 int rc = 0; 778 779 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 780 if (rc) { 781 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); 782 return IRQ_NONE; 783 } 784 785 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED | 786 PRSN_DETECT_CHANGED | CMD_COMPLETED ); 787 788 intr_loc = slot_status & intr_detect; 789 790 /* Check to see if it was our interrupt */ 791 if ( !intr_loc ) 792 return IRQ_NONE; 793 794 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc); 795 /* Mask Hot-plug Interrupt Enable */ 796 if (!pciehp_poll_mode) { 797 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); 798 if (rc) { 799 err("%s: Cannot read SLOT_CTRL register\n", 800 __FUNCTION__); 801 return IRQ_NONE; 802 } 803 804 dbg("%s: pciehp_readw(SLOTCTRL) with value %x\n", 805 __FUNCTION__, temp_word); 806 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; 807 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); 808 if (rc) { 809 err("%s: Cannot write to SLOTCTRL register\n", 810 __FUNCTION__); 811 return IRQ_NONE; 812 } 813 814 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 815 if (rc) { 816 err("%s: Cannot read SLOT_STATUS register\n", 817 __FUNCTION__); 818 return IRQ_NONE; 819 } 820 dbg("%s: pciehp_readw(SLOTSTATUS) with value %x\n", 821 __FUNCTION__, slot_status); 822 823 /* Clear command complete interrupt caused by this write */ 824 temp_word = 0x1f; 825 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); 826 if (rc) { 827 err("%s: Cannot write to SLOTSTATUS register\n", 828 __FUNCTION__); 829 return IRQ_NONE; 830 } 831 } 832 833 if (intr_loc & CMD_COMPLETED) { 834 /* 835 * Command Complete Interrupt Pending 836 */ 837 ctrl->cmd_busy = 0; 838 wake_up_interruptible(&ctrl->queue); 839 } 840 841 if (intr_loc & MRL_SENS_CHANGED) 842 pciehp_handle_switch_change(hp_slot, ctrl); 843 844 if (intr_loc & ATTN_BUTTN_PRESSED) 845 pciehp_handle_attention_button(hp_slot, ctrl); 846 847 if (intr_loc & PRSN_DETECT_CHANGED) 848 pciehp_handle_presence_change(hp_slot, ctrl); 849 850 if (intr_loc & PWR_FAULT_DETECTED) 851 pciehp_handle_power_fault(hp_slot, ctrl); 852 853 /* Clear all events after serving them */ 854 temp_word = 0x1F; 855 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); 856 if (rc) { 857 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__); 858 return IRQ_NONE; 859 } 860 /* Unmask Hot-plug Interrupt Enable */ 861 if (!pciehp_poll_mode) { 862 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); 863 if (rc) { 864 err("%s: Cannot read SLOTCTRL register\n", 865 __FUNCTION__); 866 return IRQ_NONE; 867 } 868 869 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__); 870 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; 871 872 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); 873 if (rc) { 874 err("%s: Cannot write to SLOTCTRL register\n", 875 __FUNCTION__); 876 return IRQ_NONE; 877 } 878 879 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 880 if (rc) { 881 err("%s: Cannot read SLOT_STATUS register\n", 882 __FUNCTION__); 883 return IRQ_NONE; 884 } 885 886 /* Clear command complete interrupt caused by this write */ 887 temp_word = 0x1F; 888 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); 889 if (rc) { 890 err("%s: Cannot write to SLOTSTATUS failed\n", 891 __FUNCTION__); 892 return IRQ_NONE; 893 } 894 dbg("%s: pciehp_writew(SLOTSTATUS) with value %x\n", 895 __FUNCTION__, temp_word); 896 } 897 898 return IRQ_HANDLED; 899} 900 901static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value) 902{ 903 struct controller *ctrl = slot->ctrl; 904 enum pcie_link_speed lnk_speed; 905 u32 lnk_cap; 906 int retval = 0; 907 908 DBG_ENTER_ROUTINE 909 910 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); 911 if (retval) { 912 err("%s: Cannot read LNKCAP register\n", __FUNCTION__); 913 return retval; 914 } 915 916 switch (lnk_cap & 0x000F) { 917 case 1: 918 lnk_speed = PCIE_2PT5GB; 919 break; 920 default: 921 lnk_speed = PCIE_LNK_SPEED_UNKNOWN; 922 break; 923 } 924 925 *value = lnk_speed; 926 dbg("Max link speed = %d\n", lnk_speed); 927 DBG_LEAVE_ROUTINE 928 return retval; 929} 930 931static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value) 932{ 933 struct controller *ctrl = slot->ctrl; 934 enum pcie_link_width lnk_wdth; 935 u32 lnk_cap; 936 int retval = 0; 937 938 DBG_ENTER_ROUTINE 939 940 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); 941 if (retval) { 942 err("%s: Cannot read LNKCAP register\n", __FUNCTION__); 943 return retval; 944 } 945 946 switch ((lnk_cap & 0x03F0) >> 4){ 947 case 0: 948 lnk_wdth = PCIE_LNK_WIDTH_RESRV; 949 break; 950 case 1: 951 lnk_wdth = PCIE_LNK_X1; 952 break; 953 case 2: 954 lnk_wdth = PCIE_LNK_X2; 955 break; 956 case 4: 957 lnk_wdth = PCIE_LNK_X4; 958 break; 959 case 8: 960 lnk_wdth = PCIE_LNK_X8; 961 break; 962 case 12: 963 lnk_wdth = PCIE_LNK_X12; 964 break; 965 case 16: 966 lnk_wdth = PCIE_LNK_X16; 967 break; 968 case 32: 969 lnk_wdth = PCIE_LNK_X32; 970 break; 971 default: 972 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 973 break; 974 } 975 976 *value = lnk_wdth; 977 dbg("Max link width = %d\n", lnk_wdth); 978 DBG_LEAVE_ROUTINE 979 return retval; 980} 981 982static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value) 983{ 984 struct controller *ctrl = slot->ctrl; 985 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; 986 int retval = 0; 987 u16 lnk_status; 988 989 DBG_ENTER_ROUTINE 990 991 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); 992 if (retval) { 993 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); 994 return retval; 995 } 996 997 switch (lnk_status & 0x0F) { 998 case 1: 999 lnk_speed = PCIE_2PT5GB; 1000 break; 1001 default: 1002 lnk_speed = PCIE_LNK_SPEED_UNKNOWN; 1003 break; 1004 } 1005 1006 *value = lnk_speed; 1007 dbg("Current link speed = %d\n", lnk_speed); 1008 DBG_LEAVE_ROUTINE 1009 return retval; 1010} 1011 1012static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value) 1013{ 1014 struct controller *ctrl = slot->ctrl; 1015 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 1016 int retval = 0; 1017 u16 lnk_status; 1018 1019 DBG_ENTER_ROUTINE 1020 1021 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); 1022 if (retval) { 1023 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); 1024 return retval; 1025 } 1026 1027 switch ((lnk_status & 0x03F0) >> 4){ 1028 case 0: 1029 lnk_wdth = PCIE_LNK_WIDTH_RESRV; 1030 break; 1031 case 1: 1032 lnk_wdth = PCIE_LNK_X1; 1033 break; 1034 case 2: 1035 lnk_wdth = PCIE_LNK_X2; 1036 break; 1037 case 4: 1038 lnk_wdth = PCIE_LNK_X4; 1039 break; 1040 case 8: 1041 lnk_wdth = PCIE_LNK_X8; 1042 break; 1043 case 12: 1044 lnk_wdth = PCIE_LNK_X12; 1045 break; 1046 case 16: 1047 lnk_wdth = PCIE_LNK_X16; 1048 break; 1049 case 32: 1050 lnk_wdth = PCIE_LNK_X32; 1051 break; 1052 default: 1053 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 1054 break; 1055 } 1056 1057 *value = lnk_wdth; 1058 dbg("Current link width = %d\n", lnk_wdth); 1059 DBG_LEAVE_ROUTINE 1060 return retval; 1061} 1062 1063static struct hpc_ops pciehp_hpc_ops = { 1064 .power_on_slot = hpc_power_on_slot, 1065 .power_off_slot = hpc_power_off_slot, 1066 .set_attention_status = hpc_set_attention_status, 1067 .get_power_status = hpc_get_power_status, 1068 .get_attention_status = hpc_get_attention_status, 1069 .get_latch_status = hpc_get_latch_status, 1070 .get_adapter_status = hpc_get_adapter_status, 1071 .get_emi_status = hpc_get_emi_status, 1072 .toggle_emi = hpc_toggle_emi, 1073 1074 .get_max_bus_speed = hpc_get_max_lnk_speed, 1075 .get_cur_bus_speed = hpc_get_cur_lnk_speed, 1076 .get_max_lnk_width = hpc_get_max_lnk_width, 1077 .get_cur_lnk_width = hpc_get_cur_lnk_width, 1078 1079 .query_power_fault = hpc_query_power_fault, 1080 .green_led_on = hpc_set_green_led_on, 1081 .green_led_off = hpc_set_green_led_off, 1082 .green_led_blink = hpc_set_green_led_blink, 1083 1084 .release_ctlr = hpc_release_ctlr, 1085 .check_lnk_status = hpc_check_lnk_status, 1086}; 1087 1088#ifdef CONFIG_ACPI 1089int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev) 1090{ 1091 acpi_status status; 1092 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev)); 1093 struct pci_dev *pdev = dev; 1094 struct pci_bus *parent; 1095 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL }; 1096 1097 /* 1098 * Per PCI firmware specification, we should run the ACPI _OSC 1099 * method to get control of hotplug hardware before using it. 1100 * If an _OSC is missing, we look for an OSHP to do the same thing. 1101 * To handle different BIOS behavior, we look for _OSC and OSHP 1102 * within the scope of the hotplug controller and its parents, upto 1103 * the host bridge under which this controller exists. 1104 */ 1105 while (!handle) { 1106 /* 1107 * This hotplug controller was not listed in the ACPI name 1108 * space at all. Try to get acpi handle of parent pci bus. 1109 */ 1110 if (!pdev || !pdev->bus->parent) 1111 break; 1112 parent = pdev->bus->parent; 1113 dbg("Could not find %s in acpi namespace, trying parent\n", 1114 pci_name(pdev)); 1115 if (!parent->self) 1116 /* Parent must be a host bridge */ 1117 handle = acpi_get_pci_rootbridge_handle( 1118 pci_domain_nr(parent), 1119 parent->number); 1120 else 1121 handle = DEVICE_ACPI_HANDLE( 1122 &(parent->self->dev)); 1123 pdev = parent->self; 1124 } 1125 1126 while (handle) { 1127 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string); 1128 dbg("Trying to get hotplug control for %s \n", 1129 (char *)string.pointer); 1130 status = pci_osc_control_set(handle, 1131 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL); 1132 if (status == AE_NOT_FOUND) 1133 status = acpi_run_oshp(handle); 1134 if (ACPI_SUCCESS(status)) { 1135 dbg("Gained control for hotplug HW for pci %s (%s)\n", 1136 pci_name(dev), (char *)string.pointer); 1137 kfree(string.pointer); 1138 return 0; 1139 } 1140 if (acpi_root_bridge(handle)) 1141 break; 1142 chandle = handle; 1143 status = acpi_get_parent(chandle, &handle); 1144 if (ACPI_FAILURE(status)) 1145 break; 1146 } 1147 1148 err("Cannot get control of hotplug hardware for pci %s\n", 1149 pci_name(dev)); 1150 1151 kfree(string.pointer); 1152 return -1; 1153} 1154#endif 1155 1156 1157 1158int pcie_init(struct controller * ctrl, struct pcie_device *dev) 1159{ 1160 int rc; 1161 u16 temp_word; 1162 u16 cap_reg; 1163 u16 intr_enable = 0; 1164 u32 slot_cap; 1165 int cap_base; 1166 u16 slot_status, slot_ctrl; 1167 struct pci_dev *pdev; 1168 1169 DBG_ENTER_ROUTINE 1170 1171 pdev = dev->port; 1172 ctrl->pci_dev = pdev; /* save pci_dev in context */ 1173 1174 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n", 1175 __FUNCTION__, pdev->vendor, pdev->device); 1176 1177 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) { 1178 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__); 1179 goto abort_free_ctlr; 1180 } 1181 1182 ctrl->cap_base = cap_base; 1183 1184 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, cap_base); 1185 1186 rc = pciehp_readw(ctrl, CAPREG, &cap_reg); 1187 if (rc) { 1188 err("%s: Cannot read CAPREG register\n", __FUNCTION__); 1189 goto abort_free_ctlr; 1190 } 1191 dbg("%s: CAPREG offset %x cap_reg %x\n", 1192 __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg); 1193 1194 if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040) 1195 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) { 1196 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__); 1197 goto abort_free_ctlr; 1198 } 1199 1200 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap); 1201 if (rc) { 1202 err("%s: Cannot read SLOTCAP register\n", __FUNCTION__); 1203 goto abort_free_ctlr; 1204 } 1205 dbg("%s: SLOTCAP offset %x slot_cap %x\n", 1206 __FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap); 1207 1208 if (!(slot_cap & HP_CAP)) { 1209 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__); 1210 goto abort_free_ctlr; 1211 } 1212 /* For debugging purpose */ 1213 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 1214 if (rc) { 1215 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); 1216 goto abort_free_ctlr; 1217 } 1218 dbg("%s: SLOTSTATUS offset %x slot_status %x\n", 1219 __FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status); 1220 1221 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 1222 if (rc) { 1223 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); 1224 goto abort_free_ctlr; 1225 } 1226 dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n", 1227 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl); 1228 1229 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++) 1230 if (pci_resource_len(pdev, rc) > 0) 1231 dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc, 1232 (unsigned long long)pci_resource_start(pdev, rc), 1233 (unsigned long long)pci_resource_len(pdev, rc)); 1234 1235 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, 1236 pdev->subsystem_vendor, pdev->subsystem_device); 1237 1238 mutex_init(&ctrl->crit_sect); 1239 mutex_init(&ctrl->ctrl_lock); 1240 1241 /* setup wait queue */ 1242 init_waitqueue_head(&ctrl->queue); 1243 1244 /* return PCI Controller Info */ 1245 ctrl->slot_device_offset = 0; 1246 ctrl->num_slots = 1; 1247 ctrl->first_slot = slot_cap >> 19; 1248 ctrl->ctrlcap = slot_cap & 0x0000007f; 1249 1250 /* Mask Hot-plug Interrupt Enable */ 1251 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); 1252 if (rc) { 1253 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); 1254 goto abort_free_ctlr; 1255 } 1256 1257 dbg("%s: SLOTCTRL %x value read %x\n", 1258 __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word); 1259 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; 1260 1261 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); 1262 if (rc) { 1263 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__); 1264 goto abort_free_ctlr; 1265 } 1266 1267 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 1268 if (rc) { 1269 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); 1270 goto abort_free_ctlr; 1271 } 1272 1273 temp_word = 0x1F; /* Clear all events */ 1274 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); 1275 if (rc) { 1276 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__); 1277 goto abort_free_ctlr; 1278 } 1279 1280 if (pciehp_poll_mode) { 1281 /* Install interrupt polling timer. Start with 10 sec delay */ 1282 init_timer(&ctrl->poll_timer); 1283 start_int_poll_timer(ctrl, 10); 1284 } else { 1285 /* Installs the interrupt handler */ 1286 rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED, 1287 MY_NAME, (void *)ctrl); 1288 dbg("%s: request_irq %d for hpc%d (returns %d)\n", 1289 __FUNCTION__, ctrl->pci_dev->irq, 1290 atomic_read(&pciehp_num_controllers), rc); 1291 if (rc) { 1292 err("Can't get irq %d for the hotplug controller\n", 1293 ctrl->pci_dev->irq); 1294 goto abort_free_ctlr; 1295 } 1296 } 1297 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number, 1298 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq); 1299 1300 /* 1301 * If this is the first controller to be initialized, 1302 * initialize the pciehp work queue 1303 */ 1304 if (atomic_add_return(1, &pciehp_num_controllers) == 1) { 1305 pciehp_wq = create_singlethread_workqueue("pciehpd"); 1306 if (!pciehp_wq) { 1307 rc = -ENOMEM; 1308 goto abort_free_irq; 1309 } 1310 } 1311 1312 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); 1313 if (rc) { 1314 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); 1315 goto abort_free_irq; 1316 } 1317 1318 intr_enable = intr_enable | PRSN_DETECT_ENABLE; 1319 1320 if (ATTN_BUTTN(slot_cap)) 1321 intr_enable = intr_enable | ATTN_BUTTN_ENABLE; 1322 1323 if (POWER_CTRL(slot_cap)) 1324 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE; 1325 1326 if (MRL_SENS(slot_cap)) 1327 intr_enable = intr_enable | MRL_DETECT_ENABLE; 1328 1329 temp_word = (temp_word & ~intr_enable) | intr_enable; 1330 1331 if (pciehp_poll_mode) { 1332 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0; 1333 } else { 1334 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; 1335 } 1336 1337 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */ 1338 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); 1339 if (rc) { 1340 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__); 1341 goto abort_free_irq; 1342 } 1343 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 1344 if (rc) { 1345 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); 1346 goto abort_disable_intr; 1347 } 1348 1349 temp_word = 0x1F; /* Clear all events */ 1350 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); 1351 if (rc) { 1352 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__); 1353 goto abort_disable_intr; 1354 } 1355 1356 if (pciehp_force) { 1357 dbg("Bypassing BIOS check for pciehp use on %s\n", 1358 pci_name(ctrl->pci_dev)); 1359 } else { 1360 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev); 1361 if (rc) 1362 goto abort_disable_intr; 1363 } 1364 1365 ctrl->hpc_ops = &pciehp_hpc_ops; 1366 1367 DBG_LEAVE_ROUTINE 1368 return 0; 1369 1370 /* We end up here for the many possible ways to fail this API. */ 1371abort_disable_intr: 1372 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); 1373 if (!rc) { 1374 temp_word &= ~(intr_enable | HP_INTR_ENABLE); 1375 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); 1376 } 1377 if (rc) 1378 err("%s : disabling interrupts failed\n", __FUNCTION__); 1379 1380abort_free_irq: 1381 if (pciehp_poll_mode) 1382 del_timer_sync(&ctrl->poll_timer); 1383 else 1384 free_irq(ctrl->pci_dev->irq, ctrl); 1385 1386abort_free_ctlr: 1387 DBG_LEAVE_ROUTINE 1388 return -1; 1389} 1390