1#ifndef BCM43xx_H_ 2#define BCM43xx_H_ 3 4#include <linux/hw_random.h> 5#include <linux/version.h> 6#include <linux/kernel.h> 7#include <linux/spinlock.h> 8#include <linux/interrupt.h> 9#include <linux/stringify.h> 10#include <linux/pci.h> 11#include <net/ieee80211.h> 12#include <net/ieee80211softmac.h> 13#include <asm/atomic.h> 14#include <asm/io.h> 15 16 17#include "bcm43xx_debugfs.h" 18#include "bcm43xx_leds.h" 19 20 21#define PFX KBUILD_MODNAME ": " 22 23#define BCM43xx_SWITCH_CORE_MAX_RETRIES 50 24#define BCM43xx_IRQWAIT_MAX_RETRIES 100 25 26#define BCM43xx_IO_SIZE 8192 27 28/* Active Core PCI Configuration Register. */ 29#define BCM43xx_PCICFG_ACTIVE_CORE 0x80 30/* SPROM control register. */ 31#define BCM43xx_PCICFG_SPROMCTL 0x88 32/* Interrupt Control PCI Configuration Register. (Only on PCI cores with rev >= 6) */ 33#define BCM43xx_PCICFG_ICR 0x94 34 35/* MMIO offsets */ 36#define BCM43xx_MMIO_DMA0_REASON 0x20 37#define BCM43xx_MMIO_DMA0_IRQ_MASK 0x24 38#define BCM43xx_MMIO_DMA1_REASON 0x28 39#define BCM43xx_MMIO_DMA1_IRQ_MASK 0x2C 40#define BCM43xx_MMIO_DMA2_REASON 0x30 41#define BCM43xx_MMIO_DMA2_IRQ_MASK 0x34 42#define BCM43xx_MMIO_DMA3_REASON 0x38 43#define BCM43xx_MMIO_DMA3_IRQ_MASK 0x3C 44#define BCM43xx_MMIO_DMA4_REASON 0x40 45#define BCM43xx_MMIO_DMA4_IRQ_MASK 0x44 46#define BCM43xx_MMIO_DMA5_REASON 0x48 47#define BCM43xx_MMIO_DMA5_IRQ_MASK 0x4C 48#define BCM43xx_MMIO_STATUS_BITFIELD 0x120 49#define BCM43xx_MMIO_STATUS2_BITFIELD 0x124 50#define BCM43xx_MMIO_GEN_IRQ_REASON 0x128 51#define BCM43xx_MMIO_GEN_IRQ_MASK 0x12C 52#define BCM43xx_MMIO_RAM_CONTROL 0x130 53#define BCM43xx_MMIO_RAM_DATA 0x134 54#define BCM43xx_MMIO_PS_STATUS 0x140 55#define BCM43xx_MMIO_RADIO_HWENABLED_HI 0x158 56#define BCM43xx_MMIO_SHM_CONTROL 0x160 57#define BCM43xx_MMIO_SHM_DATA 0x164 58#define BCM43xx_MMIO_SHM_DATA_UNALIGNED 0x166 59#define BCM43xx_MMIO_XMITSTAT_0 0x170 60#define BCM43xx_MMIO_XMITSTAT_1 0x174 61#define BCM43xx_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */ 62#define BCM43xx_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */ 63 64/* 32-bit DMA */ 65#define BCM43xx_MMIO_DMA32_BASE0 0x200 66#define BCM43xx_MMIO_DMA32_BASE1 0x220 67#define BCM43xx_MMIO_DMA32_BASE2 0x240 68#define BCM43xx_MMIO_DMA32_BASE3 0x260 69#define BCM43xx_MMIO_DMA32_BASE4 0x280 70#define BCM43xx_MMIO_DMA32_BASE5 0x2A0 71/* 64-bit DMA */ 72#define BCM43xx_MMIO_DMA64_BASE0 0x200 73#define BCM43xx_MMIO_DMA64_BASE1 0x240 74#define BCM43xx_MMIO_DMA64_BASE2 0x280 75#define BCM43xx_MMIO_DMA64_BASE3 0x2C0 76#define BCM43xx_MMIO_DMA64_BASE4 0x300 77#define BCM43xx_MMIO_DMA64_BASE5 0x340 78/* PIO */ 79#define BCM43xx_MMIO_PIO1_BASE 0x300 80#define BCM43xx_MMIO_PIO2_BASE 0x310 81#define BCM43xx_MMIO_PIO3_BASE 0x320 82#define BCM43xx_MMIO_PIO4_BASE 0x330 83 84#define BCM43xx_MMIO_PHY_VER 0x3E0 85#define BCM43xx_MMIO_PHY_RADIO 0x3E2 86#define BCM43xx_MMIO_ANTENNA 0x3E8 87#define BCM43xx_MMIO_CHANNEL 0x3F0 88#define BCM43xx_MMIO_CHANNEL_EXT 0x3F4 89#define BCM43xx_MMIO_RADIO_CONTROL 0x3F6 90#define BCM43xx_MMIO_RADIO_DATA_HIGH 0x3F8 91#define BCM43xx_MMIO_RADIO_DATA_LOW 0x3FA 92#define BCM43xx_MMIO_PHY_CONTROL 0x3FC 93#define BCM43xx_MMIO_PHY_DATA 0x3FE 94#define BCM43xx_MMIO_MACFILTER_CONTROL 0x420 95#define BCM43xx_MMIO_MACFILTER_DATA 0x422 96#define BCM43xx_MMIO_RADIO_HWENABLED_LO 0x49A 97#define BCM43xx_MMIO_GPIO_CONTROL 0x49C 98#define BCM43xx_MMIO_GPIO_MASK 0x49E 99#define BCM43xx_MMIO_TSF_0 0x632 /* core rev < 3 only */ 100#define BCM43xx_MMIO_TSF_1 0x634 /* core rev < 3 only */ 101#define BCM43xx_MMIO_TSF_2 0x636 /* core rev < 3 only */ 102#define BCM43xx_MMIO_TSF_3 0x638 /* core rev < 3 only */ 103#define BCM43xx_MMIO_RNG 0x65A 104#define BCM43xx_MMIO_POWERUP_DELAY 0x6A8 105 106/* SPROM offsets. */ 107#define BCM43xx_SPROM_BASE 0x1000 108#define BCM43xx_SPROM_BOARDFLAGS2 0x1c 109#define BCM43xx_SPROM_IL0MACADDR 0x24 110#define BCM43xx_SPROM_ET0MACADDR 0x27 111#define BCM43xx_SPROM_ET1MACADDR 0x2a 112#define BCM43xx_SPROM_ETHPHY 0x2d 113#define BCM43xx_SPROM_BOARDREV 0x2e 114#define BCM43xx_SPROM_PA0B0 0x2f 115#define BCM43xx_SPROM_PA0B1 0x30 116#define BCM43xx_SPROM_PA0B2 0x31 117#define BCM43xx_SPROM_WL0GPIO0 0x32 118#define BCM43xx_SPROM_WL0GPIO2 0x33 119#define BCM43xx_SPROM_MAXPWR 0x34 120#define BCM43xx_SPROM_PA1B0 0x35 121#define BCM43xx_SPROM_PA1B1 0x36 122#define BCM43xx_SPROM_PA1B2 0x37 123#define BCM43xx_SPROM_IDL_TSSI_TGT 0x38 124#define BCM43xx_SPROM_BOARDFLAGS 0x39 125#define BCM43xx_SPROM_ANTENNA_GAIN 0x3a 126#define BCM43xx_SPROM_VERSION 0x3f 127 128/* BCM43xx_SPROM_BOARDFLAGS values */ 129#define BCM43xx_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */ 130#define BCM43xx_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */ 131#define BCM43xx_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */ 132#define BCM43xx_BFL_RSSI 0x0008 /* software calculates nrssi slope. */ 133#define BCM43xx_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */ 134#define BCM43xx_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */ 135#define BCM43xx_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */ 136#define BCM43xx_BFL_ENETADM 0x0080 /* has ADMtek switch */ 137#define BCM43xx_BFL_ENETVLAN 0x0100 /* can do vlan */ 138#define BCM43xx_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */ 139#define BCM43xx_BFL_NOPCI 0x0400 /* leaves PCI floating */ 140#define BCM43xx_BFL_FEM 0x0800 /* supports the Front End Module */ 141#define BCM43xx_BFL_EXTLNA 0x1000 /* has an external LNA */ 142#define BCM43xx_BFL_HGPA 0x2000 /* had high gain PA */ 143#define BCM43xx_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */ 144#define BCM43xx_BFL_ALTIQ 0x8000 /* alternate I/Q settings */ 145 146/* GPIO register offset, in both ChipCommon and PCI core. */ 147#define BCM43xx_GPIO_CONTROL 0x6c 148 149/* SHM Routing */ 150#define BCM43xx_SHM_SHARED 0x0001 151#define BCM43xx_SHM_WIRELESS 0x0002 152#define BCM43xx_SHM_PCM 0x0003 153#define BCM43xx_SHM_HWMAC 0x0004 154#define BCM43xx_SHM_UCODE 0x0300 155 156/* MacFilter offsets. */ 157#define BCM43xx_MACFILTER_SELF 0x0000 158#define BCM43xx_MACFILTER_ASSOC 0x0003 159 160/* Chipcommon registers. */ 161#define BCM43xx_CHIPCOMMON_CAPABILITIES 0x04 162#define BCM43xx_CHIPCOMMON_CTL 0x28 163#define BCM43xx_CHIPCOMMON_PLLONDELAY 0xB0 164#define BCM43xx_CHIPCOMMON_FREFSELDELAY 0xB4 165#define BCM43xx_CHIPCOMMON_SLOWCLKCTL 0xB8 166#define BCM43xx_CHIPCOMMON_SYSCLKCTL 0xC0 167 168/* PCI core specific registers. */ 169#define BCM43xx_PCICORE_BCAST_ADDR 0x50 170#define BCM43xx_PCICORE_BCAST_DATA 0x54 171#define BCM43xx_PCICORE_SBTOPCI2 0x108 172 173/* SBTOPCI2 values. */ 174#define BCM43xx_SBTOPCI2_PREFETCH 0x4 175#define BCM43xx_SBTOPCI2_BURST 0x8 176#define BCM43xx_SBTOPCI2_MEMREAD_MULTI 0x20 177 178/* PCI-E core registers. */ 179#define BCM43xx_PCIECORE_REG_ADDR 0x0130 180#define BCM43xx_PCIECORE_REG_DATA 0x0134 181#define BCM43xx_PCIECORE_MDIO_CTL 0x0128 182#define BCM43xx_PCIECORE_MDIO_DATA 0x012C 183 184/* PCI-E registers. */ 185#define BCM43xx_PCIE_TLP_WORKAROUND 0x0004 186#define BCM43xx_PCIE_DLLP_LINKCTL 0x0100 187 188/* PCI-E MDIO bits. */ 189#define BCM43xx_PCIE_MDIO_ST 0x40000000 190#define BCM43xx_PCIE_MDIO_WT 0x10000000 191#define BCM43xx_PCIE_MDIO_DEV 22 192#define BCM43xx_PCIE_MDIO_REG 18 193#define BCM43xx_PCIE_MDIO_TA 0x00020000 194#define BCM43xx_PCIE_MDIO_TC 0x0100 195 196/* MDIO devices. */ 197#define BCM43xx_MDIO_SERDES_RX 0x1F 198 199/* SERDES RX registers. */ 200#define BCM43xx_SERDES_RXTIMER 0x2 201#define BCM43xx_SERDES_CDR 0x6 202#define BCM43xx_SERDES_CDR_BW 0x7 203 204/* Chipcommon capabilities. */ 205#define BCM43xx_CAPABILITIES_PCTL 0x00040000 206#define BCM43xx_CAPABILITIES_PLLMASK 0x00030000 207#define BCM43xx_CAPABILITIES_PLLSHIFT 16 208#define BCM43xx_CAPABILITIES_FLASHMASK 0x00000700 209#define BCM43xx_CAPABILITIES_FLASHSHIFT 8 210#define BCM43xx_CAPABILITIES_EXTBUSPRESENT 0x00000040 211#define BCM43xx_CAPABILITIES_UARTGPIO 0x00000020 212#define BCM43xx_CAPABILITIES_UARTCLOCKMASK 0x00000018 213#define BCM43xx_CAPABILITIES_UARTCLOCKSHIFT 3 214#define BCM43xx_CAPABILITIES_MIPSBIGENDIAN 0x00000004 215#define BCM43xx_CAPABILITIES_NRUARTSMASK 0x00000003 216 217/* PowerControl */ 218#define BCM43xx_PCTL_IN 0xB0 219#define BCM43xx_PCTL_OUT 0xB4 220#define BCM43xx_PCTL_OUTENABLE 0xB8 221#define BCM43xx_PCTL_XTAL_POWERUP 0x40 222#define BCM43xx_PCTL_PLL_POWERDOWN 0x80 223 224/* PowerControl Clock Modes */ 225#define BCM43xx_PCTL_CLK_FAST 0x00 226#define BCM43xx_PCTL_CLK_SLOW 0x01 227#define BCM43xx_PCTL_CLK_DYNAMIC 0x02 228 229#define BCM43xx_PCTL_FORCE_SLOW 0x0800 230#define BCM43xx_PCTL_FORCE_PLL 0x1000 231#define BCM43xx_PCTL_DYN_XTAL 0x2000 232 233/* COREIDs */ 234#define BCM43xx_COREID_CHIPCOMMON 0x800 235#define BCM43xx_COREID_ILINE20 0x801 236#define BCM43xx_COREID_SDRAM 0x803 237#define BCM43xx_COREID_PCI 0x804 238#define BCM43xx_COREID_MIPS 0x805 239#define BCM43xx_COREID_ETHERNET 0x806 240#define BCM43xx_COREID_V90 0x807 241#define BCM43xx_COREID_USB11_HOSTDEV 0x80a 242#define BCM43xx_COREID_IPSEC 0x80b 243#define BCM43xx_COREID_PCMCIA 0x80d 244#define BCM43xx_COREID_EXT_IF 0x80f 245#define BCM43xx_COREID_80211 0x812 246#define BCM43xx_COREID_MIPS_3302 0x816 247#define BCM43xx_COREID_USB11_HOST 0x817 248#define BCM43xx_COREID_USB11_DEV 0x818 249#define BCM43xx_COREID_USB20_HOST 0x819 250#define BCM43xx_COREID_USB20_DEV 0x81a 251#define BCM43xx_COREID_SDIO_HOST 0x81b 252#define BCM43xx_COREID_PCIE 0x820 253 254/* Core Information Registers */ 255#define BCM43xx_CIR_BASE 0xf00 256#define BCM43xx_CIR_SBTPSFLAG (BCM43xx_CIR_BASE + 0x18) 257#define BCM43xx_CIR_SBIMSTATE (BCM43xx_CIR_BASE + 0x90) 258#define BCM43xx_CIR_SBINTVEC (BCM43xx_CIR_BASE + 0x94) 259#define BCM43xx_CIR_SBTMSTATELOW (BCM43xx_CIR_BASE + 0x98) 260#define BCM43xx_CIR_SBTMSTATEHIGH (BCM43xx_CIR_BASE + 0x9c) 261#define BCM43xx_CIR_SBIMCONFIGLOW (BCM43xx_CIR_BASE + 0xa8) 262#define BCM43xx_CIR_SB_ID_HI (BCM43xx_CIR_BASE + 0xfc) 263 264/* Mask to get the Backplane Flag Number from SBTPSFLAG. */ 265#define BCM43xx_BACKPLANE_FLAG_NR_MASK 0x3f 266 267/* SBIMCONFIGLOW values/masks. */ 268#define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK 0x00000007 269#define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT 0 270#define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK 0x00000070 271#define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT 4 272#define BCM43xx_SBIMCONFIGLOW_CONNID_MASK 0x00ff0000 273#define BCM43xx_SBIMCONFIGLOW_CONNID_SHIFT 16 274 275/* sbtmstatelow state flags */ 276#define BCM43xx_SBTMSTATELOW_RESET 0x01 277#define BCM43xx_SBTMSTATELOW_REJECT 0x02 278#define BCM43xx_SBTMSTATELOW_CLOCK 0x10000 279#define BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK 0x20000 280#define BCM43xx_SBTMSTATELOW_G_MODE_ENABLE 0x20000000 281 282/* sbtmstatehigh state flags */ 283#define BCM43xx_SBTMSTATEHIGH_SERROR 0x00000001 284#define BCM43xx_SBTMSTATEHIGH_BUSY 0x00000004 285#define BCM43xx_SBTMSTATEHIGH_TIMEOUT 0x00000020 286#define BCM43xx_SBTMSTATEHIGH_G_PHY_AVAIL 0x00010000 287#define BCM43xx_SBTMSTATEHIGH_A_PHY_AVAIL 0x00020000 288#define BCM43xx_SBTMSTATEHIGH_COREFLAGS 0x1FFF0000 289#define BCM43xx_SBTMSTATEHIGH_DMA64BIT 0x10000000 290#define BCM43xx_SBTMSTATEHIGH_GATEDCLK 0x20000000 291#define BCM43xx_SBTMSTATEHIGH_BISTFAILED 0x40000000 292#define BCM43xx_SBTMSTATEHIGH_BISTCOMPLETE 0x80000000 293 294/* sbimstate flags */ 295#define BCM43xx_SBIMSTATE_IB_ERROR 0x20000 296#define BCM43xx_SBIMSTATE_TIMEOUT 0x40000 297 298/* PHYVersioning */ 299#define BCM43xx_PHYTYPE_A 0x00 300#define BCM43xx_PHYTYPE_B 0x01 301#define BCM43xx_PHYTYPE_G 0x02 302 303/* PHYRegisters */ 304#define BCM43xx_PHY_ILT_A_CTRL 0x0072 305#define BCM43xx_PHY_ILT_A_DATA1 0x0073 306#define BCM43xx_PHY_ILT_A_DATA2 0x0074 307#define BCM43xx_PHY_G_LO_CONTROL 0x0810 308#define BCM43xx_PHY_ILT_G_CTRL 0x0472 309#define BCM43xx_PHY_ILT_G_DATA1 0x0473 310#define BCM43xx_PHY_ILT_G_DATA2 0x0474 311#define BCM43xx_PHY_A_PCTL 0x007B 312#define BCM43xx_PHY_G_PCTL 0x0029 313#define BCM43xx_PHY_A_CRS 0x0029 314#define BCM43xx_PHY_RADIO_BITFIELD 0x0401 315#define BCM43xx_PHY_G_CRS 0x0429 316#define BCM43xx_PHY_NRSSILT_CTRL 0x0803 317#define BCM43xx_PHY_NRSSILT_DATA 0x0804 318 319/* RadioRegisters */ 320#define BCM43xx_RADIOCTL_ID 0x01 321 322/* StatusBitField */ 323#define BCM43xx_SBF_MAC_ENABLED 0x00000001 324#define BCM43xx_SBF_2 0x00000002 325#define BCM43xx_SBF_CORE_READY 0x00000004 326#define BCM43xx_SBF_400 0x00000400 327#define BCM43xx_SBF_4000 0x00004000 328#define BCM43xx_SBF_8000 0x00008000 329#define BCM43xx_SBF_XFER_REG_BYTESWAP 0x00010000 330#define BCM43xx_SBF_MODE_NOTADHOC 0x00020000 331#define BCM43xx_SBF_MODE_AP 0x00040000 332#define BCM43xx_SBF_RADIOREG_LOCK 0x00080000 333#define BCM43xx_SBF_MODE_MONITOR 0x00400000 334#define BCM43xx_SBF_MODE_PROMISC 0x01000000 335#define BCM43xx_SBF_PS1 0x02000000 336#define BCM43xx_SBF_PS2 0x04000000 337#define BCM43xx_SBF_NO_SSID_BCAST 0x08000000 338#define BCM43xx_SBF_TIME_UPDATE 0x10000000 339#define BCM43xx_SBF_MODE_G 0x80000000 340 341/* Microcode */ 342#define BCM43xx_UCODE_REVISION 0x0000 343#define BCM43xx_UCODE_PATCHLEVEL 0x0002 344#define BCM43xx_UCODE_DATE 0x0004 345#define BCM43xx_UCODE_TIME 0x0006 346#define BCM43xx_UCODE_STATUS 0x0040 347 348/* MicrocodeFlagsBitfield (addr + lo-word values?)*/ 349#define BCM43xx_UCODEFLAGS_OFFSET 0x005E 350 351#define BCM43xx_UCODEFLAG_AUTODIV 0x0001 352#define BCM43xx_UCODEFLAG_UNKBGPHY 0x0002 353#define BCM43xx_UCODEFLAG_UNKBPHY 0x0004 354#define BCM43xx_UCODEFLAG_UNKGPHY 0x0020 355#define BCM43xx_UCODEFLAG_UNKPACTRL 0x0040 356#define BCM43xx_UCODEFLAG_JAPAN 0x0080 357 358/* Hardware Radio Enable masks */ 359#define BCM43xx_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16) 360#define BCM43xx_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4) 361 362/* Generic-Interrupt reasons. */ 363#define BCM43xx_IRQ_READY (1 << 0) 364#define BCM43xx_IRQ_BEACON (1 << 1) 365#define BCM43xx_IRQ_PS (1 << 2) 366#define BCM43xx_IRQ_REG124 (1 << 5) 367#define BCM43xx_IRQ_PMQ (1 << 6) 368#define BCM43xx_IRQ_PIO_WORKAROUND (1 << 8) 369#define BCM43xx_IRQ_XMIT_ERROR (1 << 11) 370#define BCM43xx_IRQ_RX (1 << 15) 371#define BCM43xx_IRQ_SCAN (1 << 16) 372#define BCM43xx_IRQ_NOISE (1 << 18) 373#define BCM43xx_IRQ_XMIT_STATUS (1 << 29) 374 375#define BCM43xx_IRQ_ALL 0xffffffff 376#define BCM43xx_IRQ_INITIAL (BCM43xx_IRQ_PS | \ 377 BCM43xx_IRQ_REG124 | \ 378 BCM43xx_IRQ_PMQ | \ 379 BCM43xx_IRQ_XMIT_ERROR | \ 380 BCM43xx_IRQ_RX | \ 381 BCM43xx_IRQ_SCAN | \ 382 BCM43xx_IRQ_NOISE | \ 383 BCM43xx_IRQ_XMIT_STATUS) 384 385 386/* Initial default iw_mode */ 387#define BCM43xx_INITIAL_IWMODE IW_MODE_INFRA 388 389/* Bus type PCI. */ 390#define BCM43xx_BUSTYPE_PCI 0 391/* Bus type Silicone Backplane Bus. */ 392#define BCM43xx_BUSTYPE_SB 1 393/* Bus type PCMCIA. */ 394#define BCM43xx_BUSTYPE_PCMCIA 2 395 396/* Threshold values. */ 397#define BCM43xx_MIN_RTS_THRESHOLD 1U 398#define BCM43xx_MAX_RTS_THRESHOLD 2304U 399#define BCM43xx_DEFAULT_RTS_THRESHOLD BCM43xx_MAX_RTS_THRESHOLD 400 401#define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7 402#define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4 403 404#define RX_RSSI_MAX 60 405 406/* Max size of a security key */ 407#define BCM43xx_SEC_KEYSIZE 16 408/* Security algorithms. */ 409enum { 410 BCM43xx_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */ 411 BCM43xx_SEC_ALGO_WEP, 412 BCM43xx_SEC_ALGO_UNKNOWN, 413 BCM43xx_SEC_ALGO_AES, 414 BCM43xx_SEC_ALGO_WEP104, 415 BCM43xx_SEC_ALGO_TKIP, 416}; 417 418#ifdef assert 419# undef assert 420#endif 421#ifdef CONFIG_BCM43XX_DEBUG 422#define assert(expr) \ 423 do { \ 424 if (unlikely(!(expr))) { \ 425 printk(KERN_ERR PFX "ASSERTION FAILED (%s) at: %s:%d:%s()\n", \ 426 #expr, __FILE__, __LINE__, __FUNCTION__); \ 427 } \ 428 } while (0) 429#else 430#define assert(expr) do { /* nothing */ } while (0) 431#endif 432 433/* rate limited printk(). */ 434#ifdef printkl 435# undef printkl 436#endif 437#define printkl(f, x...) do { if (printk_ratelimit()) printk(f ,##x); } while (0) 438/* rate limited printk() for debugging */ 439#ifdef dprintkl 440# undef dprintkl 441#endif 442#ifdef CONFIG_BCM43XX_DEBUG 443# define dprintkl printkl 444#else 445# define dprintkl(f, x...) do { /* nothing */ } while (0) 446#endif 447 448/* Helper macro for if branches. 449 * An if branch marked with this macro is only taken in DEBUG mode. 450 * Example: 451 * if (DEBUG_ONLY(foo == bar)) { 452 * do something 453 * } 454 * In DEBUG mode, the branch will be taken if (foo == bar). 455 * In non-DEBUG mode, the branch will never be taken. 456 */ 457#ifdef DEBUG_ONLY 458# undef DEBUG_ONLY 459#endif 460#ifdef CONFIG_BCM43XX_DEBUG 461# define DEBUG_ONLY(x) (x) 462#else 463# define DEBUG_ONLY(x) 0 464#endif 465 466/* debugging printk() */ 467#ifdef dprintk 468# undef dprintk 469#endif 470#ifdef CONFIG_BCM43XX_DEBUG 471# define dprintk(f, x...) do { printk(f ,##x); } while (0) 472#else 473# define dprintk(f, x...) do { /* nothing */ } while (0) 474#endif 475 476 477struct net_device; 478struct pci_dev; 479struct bcm43xx_dmaring; 480struct bcm43xx_pioqueue; 481 482struct bcm43xx_initval { 483 u16 offset; 484 u16 size; 485 u32 value; 486} __attribute__((__packed__)); 487 488/* Values for bcm430x_sprominfo.locale */ 489enum { 490 BCM43xx_LOCALE_WORLD = 0, 491 BCM43xx_LOCALE_THAILAND, 492 BCM43xx_LOCALE_ISRAEL, 493 BCM43xx_LOCALE_JORDAN, 494 BCM43xx_LOCALE_CHINA, 495 BCM43xx_LOCALE_JAPAN, 496 BCM43xx_LOCALE_USA_CANADA_ANZ, 497 BCM43xx_LOCALE_EUROPE, 498 BCM43xx_LOCALE_USA_LOW, 499 BCM43xx_LOCALE_JAPAN_HIGH, 500 BCM43xx_LOCALE_ALL, 501 BCM43xx_LOCALE_NONE, 502}; 503 504#define BCM43xx_SPROM_SIZE 64 /* in 16-bit words. */ 505struct bcm43xx_sprominfo { 506 u16 boardflags2; 507 u8 il0macaddr[6]; 508 u8 et0macaddr[6]; 509 u8 et1macaddr[6]; 510 u8 et0phyaddr:5; 511 u8 et1phyaddr:5; 512 u8 boardrev; 513 u8 locale:4; 514 u8 antennas_aphy:2; 515 u8 antennas_bgphy:2; 516 u16 pa0b0; 517 u16 pa0b1; 518 u16 pa0b2; 519 u8 wl0gpio0; 520 u8 wl0gpio1; 521 u8 wl0gpio2; 522 u8 wl0gpio3; 523 u8 maxpower_aphy; 524 u8 maxpower_bgphy; 525 u16 pa1b0; 526 u16 pa1b1; 527 u16 pa1b2; 528 u8 idle_tssi_tgt_aphy; 529 u8 idle_tssi_tgt_bgphy; 530 u16 boardflags; 531 u16 antennagain_aphy; 532 u16 antennagain_bgphy; 533}; 534 535/* Value pair to measure the LocalOscillator. */ 536struct bcm43xx_lopair { 537 s8 low; 538 s8 high; 539 u8 used:1; 540}; 541#define BCM43xx_LO_COUNT (14*4) 542 543struct bcm43xx_phyinfo { 544 /* Hardware Data */ 545 u8 analog; 546 u8 type; 547 u8 rev; 548 u16 antenna_diversity; 549 u16 savedpctlreg; 550 u16 minlowsig[2]; 551 u16 minlowsigpos[2]; 552 u8 connected:1, 553 calibrated:1, 554 is_locked:1, /* used in bcm43xx_phy_{un}lock() */ 555 dyn_tssi_tbl:1; /* used in bcm43xx_phy_init_tssi2dbm_table() */ 556 /* LO Measurement Data. 557 * Use bcm43xx_get_lopair() to get a value. 558 */ 559 struct bcm43xx_lopair *_lo_pairs; 560 561 /* TSSI to dBm table in use */ 562 const s8 *tssi2dbm; 563 /* idle TSSI value */ 564 s8 idle_tssi; 565 566 /* Values from bcm43xx_calc_loopback_gain() */ 567 u16 loopback_gain[2]; 568 569 /* PHY lock for core.rev < 3 570 * This lock is only used by bcm43xx_phy_{un}lock() 571 */ 572 spinlock_t lock; 573 574 /* Firmware. */ 575 const struct firmware *ucode; 576 const struct firmware *pcm; 577 const struct firmware *initvals0; 578 const struct firmware *initvals1; 579}; 580 581 582struct bcm43xx_radioinfo { 583 u16 manufact; 584 u16 version; 585 u8 revision; 586 587 /* Desired TX power in dBm Q5.2 */ 588 u16 txpower_desired; 589 /* TX Power control values. */ 590 union { 591 /* B/G PHY */ 592 struct { 593 u16 baseband_atten; 594 u16 radio_atten; 595 u16 txctl1; 596 u16 txctl2; 597 }; 598 /* A PHY */ 599 struct { 600 u16 txpwr_offset; 601 }; 602 }; 603 604 /* Current Interference Mitigation mode */ 605 int interfmode; 606 /* Stack of saved values from the Interference Mitigation code. 607 * Each value in the stack is layed out as follows: 608 * bit 0-11: offset 609 * bit 12-15: register ID 610 * bit 16-32: value 611 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT 612 */ 613#define BCM43xx_INTERFSTACK_SIZE 26 614 u32 interfstack[BCM43xx_INTERFSTACK_SIZE]; 615 616 /* Saved values from the NRSSI Slope calculation */ 617 s16 nrssi[2]; 618 s32 nrssislope; 619 /* In memory nrssi lookup table. */ 620 s8 nrssi_lt[64]; 621 622 /* current channel */ 623 u8 channel; 624 u8 initial_channel; 625 626 u16 lofcal; 627 628 u16 initval; 629 630 u8 enabled:1; 631 /* ACI (adjacent channel interference) flags. */ 632 u8 aci_enable:1, 633 aci_wlan_automatic:1, 634 aci_hw_rssi:1; 635}; 636 637/* Data structures for DMA transmission, per 80211 core. */ 638struct bcm43xx_dma { 639 struct bcm43xx_dmaring *tx_ring0; 640 struct bcm43xx_dmaring *tx_ring1; 641 struct bcm43xx_dmaring *tx_ring2; 642 struct bcm43xx_dmaring *tx_ring3; 643 struct bcm43xx_dmaring *tx_ring4; 644 struct bcm43xx_dmaring *tx_ring5; 645 646 struct bcm43xx_dmaring *rx_ring0; 647 struct bcm43xx_dmaring *rx_ring3; /* only available on core.rev < 5 */ 648}; 649 650/* Data structures for PIO transmission, per 80211 core. */ 651struct bcm43xx_pio { 652 struct bcm43xx_pioqueue *queue0; 653 struct bcm43xx_pioqueue *queue1; 654 struct bcm43xx_pioqueue *queue2; 655 struct bcm43xx_pioqueue *queue3; 656}; 657 658#define BCM43xx_MAX_80211_CORES 2 659 660/* Generic information about a core. */ 661struct bcm43xx_coreinfo { 662 u8 available:1, 663 enabled:1, 664 initialized:1; 665 /** core_rev revision number */ 666 u8 rev; 667 /** Index number for _switch_core() */ 668 u8 index; 669 /** core_id ID number */ 670 u16 id; 671 /** Core-specific data. */ 672 void *priv; 673}; 674 675/* Additional information for each 80211 core. */ 676struct bcm43xx_coreinfo_80211 { 677 /* PHY device. */ 678 struct bcm43xx_phyinfo phy; 679 /* Radio device. */ 680 struct bcm43xx_radioinfo radio; 681 union { 682 /* DMA context. */ 683 struct bcm43xx_dma dma; 684 /* PIO context. */ 685 struct bcm43xx_pio pio; 686 }; 687}; 688 689/* Context information for a noise calculation (Link Quality). */ 690struct bcm43xx_noise_calculation { 691 struct bcm43xx_coreinfo *core_at_start; 692 u8 channel_at_start; 693 u8 calculation_running:1; 694 u8 nr_samples; 695 s8 samples[8][4]; 696}; 697 698struct bcm43xx_stats { 699 u8 noise; 700 struct iw_statistics wstats; 701 /* Store the last TX/RX times here for updating the leds. */ 702 unsigned long last_tx; 703 unsigned long last_rx; 704}; 705 706struct bcm43xx_key { 707 u8 enabled:1; 708 u8 algorithm; 709}; 710 711/* Driver initialization status. */ 712enum { 713 BCM43xx_STAT_UNINIT, /* Uninitialized. */ 714 BCM43xx_STAT_INITIALIZING, /* init_board() in progress. */ 715 BCM43xx_STAT_INITIALIZED, /* Fully operational. */ 716 BCM43xx_STAT_SHUTTINGDOWN, /* free_board() in progress. */ 717 BCM43xx_STAT_RESTARTING, /* controller_restart() called. */ 718}; 719#define bcm43xx_status(bcm) atomic_read(&(bcm)->init_status) 720#define bcm43xx_set_status(bcm, stat) do { \ 721 atomic_set(&(bcm)->init_status, (stat)); \ 722 smp_wmb(); \ 723 } while (0) 724 725/* *** THEORY OF LOCKING *** 726 * 727 * We have two different locks in the bcm43xx driver. 728 * => bcm->mutex: General sleeping mutex. Protects struct bcm43xx_private 729 * and the device registers. This mutex does _not_ protect 730 * against concurrency from the IRQ handler. 731 * => bcm->irq_lock: IRQ spinlock. Protects against IRQ handler concurrency. 732 * 733 * Please note that, if you only take the irq_lock, you are not protected 734 * against concurrency from the periodic work handlers. 735 * Most times you want to take _both_ locks. 736 */ 737 738struct bcm43xx_private { 739 struct ieee80211_device *ieee; 740 struct ieee80211softmac_device *softmac; 741 742 struct net_device *net_dev; 743 struct pci_dev *pci_dev; 744 unsigned int irq; 745 746 void __iomem *mmio_addr; 747 748 spinlock_t irq_lock; 749 struct mutex mutex; 750 751 /* Driver initialization status BCM43xx_STAT_*** */ 752 atomic_t init_status; 753 754 u16 was_initialized:1, /* for PCI suspend/resume. */ 755 __using_pio:1, /* Internal, use bcm43xx_using_pio(). */ 756 bad_frames_preempt:1, /* Use "Bad Frames Preemption" (default off) */ 757 reg124_set_0x4:1, /* Some variable to keep track of IRQ stuff. */ 758 short_preamble:1, /* TRUE, if short preamble is enabled. */ 759 firmware_norelease:1, /* Do not release the firmware. Used on suspend. */ 760 radio_hw_enable:1; /* TRUE if radio is hardware enabled */ 761 762 struct bcm43xx_stats stats; 763 764 /* Bus type we are connected to. 765 * This is currently always BCM43xx_BUSTYPE_PCI 766 */ 767 u8 bustype; 768 u64 dma_mask; 769 770 u16 board_vendor; 771 u16 board_type; 772 u16 board_revision; 773 774 u16 chip_id; 775 u8 chip_rev; 776 u8 chip_package; 777 778 struct bcm43xx_sprominfo sprom; 779#define BCM43xx_NR_LEDS 4 780 struct bcm43xx_led leds[BCM43xx_NR_LEDS]; 781 spinlock_t leds_lock; 782 783 /* The currently active core. */ 784 struct bcm43xx_coreinfo *current_core; 785 struct bcm43xx_coreinfo *active_80211_core; 786 /* coreinfo structs for all possible cores follow. 787 * Note that a core might not exist. 788 * So check the coreinfo flags before using it. 789 */ 790 struct bcm43xx_coreinfo core_chipcommon; 791 struct bcm43xx_coreinfo core_pci; 792 struct bcm43xx_coreinfo core_80211[ BCM43xx_MAX_80211_CORES ]; 793 /* Additional information, specific to the 80211 cores. */ 794 struct bcm43xx_coreinfo_80211 core_80211_ext[ BCM43xx_MAX_80211_CORES ]; 795 /* Number of available 80211 cores. */ 796 int nr_80211_available; 797 798 u32 chipcommon_capabilities; 799 800 /* Reason code of the last interrupt. */ 801 u32 irq_reason; 802 u32 dma_reason[6]; 803 /* saved irq enable/disable state bitfield. */ 804 u32 irq_savedstate; 805 /* Link Quality calculation context. */ 806 struct bcm43xx_noise_calculation noisecalc; 807 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */ 808 int mac_suspended; 809 810 /* Threshold values. */ 811 //TODO: The RTS thr has to be _used_. Currently, it is only set via WX. 812 u32 rts_threshold; 813 814 /* Interrupt Service Routine tasklet (bottom-half) */ 815 struct tasklet_struct isr_tasklet; 816 817 /* Periodic tasks */ 818 struct delayed_work periodic_work; 819 unsigned int periodic_state; 820 821 struct work_struct restart_work; 822 823 /* Informational stuff. */ 824 char nick[IW_ESSID_MAX_SIZE + 1]; 825 826 /* encryption/decryption */ 827 u16 security_offset; 828 struct bcm43xx_key key[54]; 829 u8 default_key_idx; 830 831 /* Random Number Generator. */ 832 struct hwrng rng; 833 char rng_name[20 + 1]; 834 835 /* Debugging stuff follows. */ 836#ifdef CONFIG_BCM43XX_DEBUG 837 struct bcm43xx_dfsentry *dfsentry; 838#endif 839}; 840 841 842static inline 843struct bcm43xx_private * bcm43xx_priv(struct net_device *dev) 844{ 845 return ieee80211softmac_priv(dev); 846} 847 848struct device; 849 850static inline 851struct bcm43xx_private * dev_to_bcm(struct device *dev) 852{ 853 struct net_device *net_dev; 854 struct bcm43xx_private *bcm; 855 856 net_dev = dev_get_drvdata(dev); 857 bcm = bcm43xx_priv(net_dev); 858 859 return bcm; 860} 861 862 863/* Helper function, which returns a boolean. 864 * TRUE, if PIO is used; FALSE, if DMA is used. 865 */ 866#if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO) 867static inline 868int bcm43xx_using_pio(struct bcm43xx_private *bcm) 869{ 870 return bcm->__using_pio; 871} 872#elif defined(CONFIG_BCM43XX_DMA) 873static inline 874int bcm43xx_using_pio(struct bcm43xx_private *bcm) 875{ 876 return 0; 877} 878#elif defined(CONFIG_BCM43XX_PIO) 879static inline 880int bcm43xx_using_pio(struct bcm43xx_private *bcm) 881{ 882 return 1; 883} 884#else 885# error "Using neither DMA nor PIO? Confused..." 886#endif 887 888/* Helper functions to access data structures private to the 80211 cores. 889 * Note that we _must_ have an 80211 core mapped when calling 890 * any of these functions. 891 */ 892static inline 893struct bcm43xx_coreinfo_80211 * 894bcm43xx_current_80211_priv(struct bcm43xx_private *bcm) 895{ 896 assert(bcm->current_core->id == BCM43xx_COREID_80211); 897 return bcm->current_core->priv; 898} 899static inline 900struct bcm43xx_pio * bcm43xx_current_pio(struct bcm43xx_private *bcm) 901{ 902 assert(bcm43xx_using_pio(bcm)); 903 return &(bcm43xx_current_80211_priv(bcm)->pio); 904} 905static inline 906struct bcm43xx_dma * bcm43xx_current_dma(struct bcm43xx_private *bcm) 907{ 908 assert(!bcm43xx_using_pio(bcm)); 909 return &(bcm43xx_current_80211_priv(bcm)->dma); 910} 911static inline 912struct bcm43xx_phyinfo * bcm43xx_current_phy(struct bcm43xx_private *bcm) 913{ 914 return &(bcm43xx_current_80211_priv(bcm)->phy); 915} 916static inline 917struct bcm43xx_radioinfo * bcm43xx_current_radio(struct bcm43xx_private *bcm) 918{ 919 return &(bcm43xx_current_80211_priv(bcm)->radio); 920} 921 922 923static inline 924struct bcm43xx_lopair * bcm43xx_get_lopair(struct bcm43xx_phyinfo *phy, 925 u16 radio_attenuation, 926 u16 baseband_attenuation) 927{ 928 return phy->_lo_pairs + (radio_attenuation + 14 * (baseband_attenuation / 2)); 929} 930 931 932static inline 933u16 bcm43xx_read16(struct bcm43xx_private *bcm, u16 offset) 934{ 935 return ioread16(bcm->mmio_addr + offset); 936} 937 938static inline 939void bcm43xx_write16(struct bcm43xx_private *bcm, u16 offset, u16 value) 940{ 941 iowrite16(value, bcm->mmio_addr + offset); 942} 943 944static inline 945u32 bcm43xx_read32(struct bcm43xx_private *bcm, u16 offset) 946{ 947 return ioread32(bcm->mmio_addr + offset); 948} 949 950static inline 951void bcm43xx_write32(struct bcm43xx_private *bcm, u16 offset, u32 value) 952{ 953 iowrite32(value, bcm->mmio_addr + offset); 954} 955 956static inline 957int bcm43xx_pci_read_config16(struct bcm43xx_private *bcm, int offset, u16 *value) 958{ 959 return pci_read_config_word(bcm->pci_dev, offset, value); 960} 961 962static inline 963int bcm43xx_pci_read_config32(struct bcm43xx_private *bcm, int offset, u32 *value) 964{ 965 return pci_read_config_dword(bcm->pci_dev, offset, value); 966} 967 968static inline 969int bcm43xx_pci_write_config16(struct bcm43xx_private *bcm, int offset, u16 value) 970{ 971 return pci_write_config_word(bcm->pci_dev, offset, value); 972} 973 974static inline 975int bcm43xx_pci_write_config32(struct bcm43xx_private *bcm, int offset, u32 value) 976{ 977 return pci_write_config_dword(bcm->pci_dev, offset, value); 978} 979 980/** Limit a value between two limits */ 981#ifdef limit_value 982# undef limit_value 983#endif 984#define limit_value(value, min, max) \ 985 ({ \ 986 typeof(value) __value = (value); \ 987 typeof(value) __min = (min); \ 988 typeof(value) __max = (max); \ 989 if (__value < __min) \ 990 __value = __min; \ 991 else if (__value > __max) \ 992 __value = __max; \ 993 __value; \ 994 }) 995 996/** Helpers to print MAC addresses. */ 997#define BCM43xx_MACFMT "%02x:%02x:%02x:%02x:%02x:%02x" 998#define BCM43xx_MACARG(x) ((u8*)(x))[0], ((u8*)(x))[1], \ 999 ((u8*)(x))[2], ((u8*)(x))[3], \ 1000 ((u8*)(x))[4], ((u8*)(x))[5] 1001 1002#endif /* BCM43xx_H_ */ 1003