1/*
2 * This program is free software; you can redistribute  it and/or modify it
3 * under  the terms of  the GNU General  Public License as published by the
4 * Free Software Foundation;  either version 2 of the  License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
8 */
9#include <linux/kernel.h>
10#include <linux/mm.h>
11#include <linux/bootmem.h>
12#include <linux/init.h>
13#include <linux/types.h>
14#include <linux/pci.h>
15
16/*
17 * Indicate whether we respect the PCI setup left by the firmware.
18 *
19 * Make this long-lived  so that we know when shutting down
20 * whether we probed only or not.
21 */
22int pci_probe_only;
23
24#define PCI_ASSIGN_ALL_BUSSES	1
25
26unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
27
28/*
29 * The PCI controller list.
30 */
31
32struct pci_controller *hose_head, **hose_tail = &hose_head;
33struct pci_controller *pci_isa_hose;
34
35unsigned long PCIBIOS_MIN_IO	= 0x0000;
36unsigned long PCIBIOS_MIN_MEM	= 0;
37
38/*
39 * We need to avoid collisions with `mirrored' VGA ports
40 * and other strange ISA hardware, so we always want the
41 * addresses to be allocated in the 0x000-0x0ff region
42 * modulo 0x400.
43 *
44 * Why? Because some silly external IO cards only decode
45 * the low 10 bits of the IO address. The 0x00-0xff region
46 * is reserved for motherboard devices that decode all 16
47 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
48 * but we want to try to avoid allocating at 0x2900-0x2bff
49 * which might have be mirrored at 0x0100-0x03ff..
50 */
51void
52pcibios_align_resource(void *data, struct resource *res,
53		       resource_size_t size, resource_size_t align)
54{
55	struct pci_dev *dev = data;
56	struct pci_controller *hose = dev->sysdata;
57	resource_size_t start = res->start;
58
59	if (res->flags & IORESOURCE_IO) {
60		/* Make sure we start at our min on all hoses */
61		if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
62			start = PCIBIOS_MIN_IO + hose->io_resource->start;
63
64		/*
65		 * Put everything into 0x00-0xff region modulo 0x400
66		 */
67		if (start & 0x300)
68			start = (start + 0x3ff) & ~0x3ff;
69	} else if (res->flags & IORESOURCE_MEM) {
70		/* Make sure we start at our min on all hoses */
71		if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
72			start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
73	}
74
75	res->start = start;
76}
77
78void __init register_pci_controller(struct pci_controller *hose)
79{
80	if (request_resource(&iomem_resource, hose->mem_resource) < 0)
81		goto out;
82	if (request_resource(&ioport_resource, hose->io_resource) < 0) {
83		release_resource(hose->mem_resource);
84		goto out;
85	}
86
87	*hose_tail = hose;
88	hose_tail = &hose->next;
89
90	/*
91	 * Do not panic here but later - this might hapen before console init.
92	 */
93	if (!hose->io_map_base) {
94		printk(KERN_WARNING
95		       "registering PCI controller with io_map_base unset\n");
96	}
97	return;
98
99out:
100	printk(KERN_WARNING
101	       "Skipping PCI bus scan due to resource conflict\n");
102}
103
104/* Most MIPS systems have straight-forward swizzling needs.  */
105
106static inline u8 bridge_swizzle(u8 pin, u8 slot)
107{
108	return (((pin - 1) + slot) % 4) + 1;
109}
110
111
112extern int __init pcibios_init(void);
113subsys_initcall(pcibios_init);
114
115/*
116 *  If we set up a device for bus mastering, we need to check the latency
117 *  timer as certain crappy BIOSes forget to set it properly.
118 */
119unsigned int pcibios_max_latency = 255;
120
121void pcibios_set_master(struct pci_dev *dev)
122{
123	u8 lat;
124	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
125	if (lat < 16)
126		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
127	else if (lat > pcibios_max_latency)
128		lat = pcibios_max_latency;
129	else
130		return;
131	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
132	       pci_name(dev), lat);
133	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
134}
135
136unsigned int pcibios_assign_all_busses(void)
137{
138	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
139}
140
141
142void __init
143pcibios_update_irq(struct pci_dev *dev, int irq)
144{
145	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
146}
147
148void __devinit
149pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
150			 struct resource *res)
151{
152	struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
153	unsigned long offset = 0;
154
155	if (res->flags & IORESOURCE_IO)
156		offset = hose->io_offset;
157	else if (res->flags & IORESOURCE_MEM)
158		offset = hose->mem_offset;
159
160	region->start = res->start - offset;
161	region->end = res->end - offset;
162}
163
164void __devinit
165pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
166			struct pci_bus_region *region)
167{
168	struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
169	unsigned long offset = 0;
170
171	if (res->flags & IORESOURCE_IO)
172		offset = hose->io_offset;
173	else if (res->flags & IORESOURCE_MEM)
174		offset = hose->mem_offset;
175
176	res->start = region->start + offset;
177	res->end = region->end + offset;
178}
179
180#ifdef CONFIG_HOTPLUG
181EXPORT_SYMBOL(pcibios_resource_to_bus);
182EXPORT_SYMBOL(pcibios_bus_to_resource);
183EXPORT_SYMBOL(PCIBIOS_MIN_IO);
184EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
185#endif
186