1/* linux/arch/arm/mach-s3c2410/mach-qt2410.c
2 *
3 * Copyright (C) 2006 by OpenMoko, Inc.
4 * Author: Harald Welte <laforge@openmoko.org>
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/types.h>
26#include <linux/interrupt.h>
27#include <linux/list.h>
28#include <linux/timer.h>
29#include <linux/init.h>
30#include <linux/sysdev.h>
31#include <linux/platform_device.h>
32#include <linux/serial_core.h>
33#include <linux/spi/spi.h>
34#include <linux/spi/spi_bitbang.h>
35
36#include <linux/mtd/mtd.h>
37#include <linux/mtd/nand.h>
38#include <linux/mtd/nand_ecc.h>
39#include <linux/mtd/partitions.h>
40
41#include <asm/mach/arch.h>
42#include <asm/mach/map.h>
43#include <asm/mach/irq.h>
44
45#include <asm/hardware.h>
46#include <asm/io.h>
47#include <asm/irq.h>
48#include <asm/mach-types.h>
49
50#include <asm/arch/regs-gpio.h>
51#include <asm/arch/leds-gpio.h>
52#include <asm/arch/regs-serial.h>
53#include <asm/arch/fb.h>
54#include <asm/arch/nand.h>
55#include <asm/arch/udc.h>
56#include <asm/arch/spi.h>
57#include <asm/arch/spi-gpio.h>
58
59#include <asm/plat-s3c24xx/common-smdk.h>
60#include <asm/plat-s3c24xx/devs.h>
61#include <asm/plat-s3c24xx/cpu.h>
62#include <asm/plat-s3c24xx/pm.h>
63
64static struct map_desc qt2410_iodesc[] __initdata = {
65	{ 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
66};
67
68#define UCON S3C2410_UCON_DEFAULT
69#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
70#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
71
72static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
73	[0] = {
74		.hwport	     = 0,
75		.flags	     = 0,
76		.ucon	     = UCON,
77		.ulcon	     = ULCON,
78		.ufcon	     = UFCON,
79	},
80	[1] = {
81		.hwport	     = 1,
82		.flags	     = 0,
83		.ucon	     = UCON,
84		.ulcon	     = ULCON,
85		.ufcon	     = UFCON,
86	},
87	[2] = {
88		.hwport	     = 2,
89		.flags	     = 0,
90		.ucon	     = UCON,
91		.ulcon	     = ULCON,
92		.ufcon	     = UFCON,
93	}
94};
95
96/* LCD driver info */
97
98/* Configuration for 640x480 SHARP LQ080V3DG01 */
99static struct s3c2410fb_mach_info qt2410_biglcd_cfg __initdata = {
100	.regs	= {
101
102		.lcdcon1	= S3C2410_LCDCON1_TFT16BPP |
103				  S3C2410_LCDCON1_TFT |
104				  S3C2410_LCDCON1_CLKVAL(0x01),	/* HCLK/4 */
105
106		.lcdcon2	= S3C2410_LCDCON2_VBPD(18) |	/* 19 */
107				  S3C2410_LCDCON2_LINEVAL(479) |
108				  S3C2410_LCDCON2_VFPD(10) |	/* 11 */
109				  S3C2410_LCDCON2_VSPW(14),	/* 15 */
110
111		.lcdcon3	= S3C2410_LCDCON3_HBPD(43) |	/* 44 */
112				  S3C2410_LCDCON3_HOZVAL(639) |	/* 640 */
113				  S3C2410_LCDCON3_HFPD(115),	/* 116 */
114
115		.lcdcon4	= S3C2410_LCDCON4_MVAL(0) |
116				  S3C2410_LCDCON4_HSPW(95),	/* 96 */
117
118		.lcdcon5	= S3C2410_LCDCON5_FRM565 |
119				  S3C2410_LCDCON5_INVVLINE |
120				  S3C2410_LCDCON5_INVVFRAME |
121				  S3C2410_LCDCON5_PWREN |
122				  S3C2410_LCDCON5_HWSWP,
123	},
124
125	.lpcsel		= ((0xCE6) & ~7) | 1<<4,
126
127	.width		= 640,
128	.height		= 480,
129
130	.xres		= {
131		.min	= 640,
132		.max	= 640,
133		.defval	= 640,
134	},
135
136	.yres		= {
137		.min	= 480,
138		.max	= 480,
139		.defval = 480,
140	},
141
142	.bpp		= {
143		.min	= 16,
144		.max	= 16,
145		.defval = 16,
146	},
147};
148
149/* Configuration for 480x640 toppoly TD028TTEC1 */
150static struct s3c2410fb_mach_info qt2410_prodlcd_cfg __initdata = {
151	.regs	= {
152
153		.lcdcon1	= S3C2410_LCDCON1_TFT16BPP |
154				  S3C2410_LCDCON1_TFT |
155				  S3C2410_LCDCON1_CLKVAL(0x01),	/* HCLK/4 */
156
157		.lcdcon2	= S3C2410_LCDCON2_VBPD(1) |	/* 2 */
158				  S3C2410_LCDCON2_LINEVAL(639) |/* 640 */
159				  S3C2410_LCDCON2_VFPD(3) |	/* 4 */
160				  S3C2410_LCDCON2_VSPW(1),	/* 2 */
161
162		.lcdcon3	= S3C2410_LCDCON3_HBPD(7) |	/* 8 */
163				  S3C2410_LCDCON3_HOZVAL(479) |	/* 479 */
164				  S3C2410_LCDCON3_HFPD(23),	/* 24 */
165
166		.lcdcon4	= S3C2410_LCDCON4_MVAL(0) |
167				  S3C2410_LCDCON4_HSPW(7),	/* 8 */
168
169		.lcdcon5	= S3C2410_LCDCON5_FRM565 |
170				  S3C2410_LCDCON5_INVVLINE |
171				  S3C2410_LCDCON5_INVVFRAME |
172				  S3C2410_LCDCON5_PWREN |
173				  S3C2410_LCDCON5_HWSWP,
174	},
175
176	.lpcsel		= ((0xCE6) & ~7) | 1<<4,
177
178	.width		= 480,
179	.height		= 640,
180
181	.xres		= {
182		.min	= 480,
183		.max	= 480,
184		.defval	= 480,
185	},
186
187	.yres		= {
188		.min	= 640,
189		.max	= 640,
190		.defval = 640,
191	},
192
193	.bpp		= {
194		.min	= 16,
195		.max	= 16,
196		.defval = 16,
197	},
198};
199
200/* Config for 240x320 LCD */
201static struct s3c2410fb_mach_info qt2410_lcd_cfg __initdata = {
202	.regs	= {
203
204		.lcdcon1	= S3C2410_LCDCON1_TFT16BPP |
205				  S3C2410_LCDCON1_TFT |
206				  S3C2410_LCDCON1_CLKVAL(0x04),
207
208		.lcdcon2	= S3C2410_LCDCON2_VBPD(1) |
209				  S3C2410_LCDCON2_LINEVAL(319) |
210				  S3C2410_LCDCON2_VFPD(6) |
211				  S3C2410_LCDCON2_VSPW(3),
212
213		.lcdcon3	= S3C2410_LCDCON3_HBPD(12) |
214				  S3C2410_LCDCON3_HOZVAL(239) |
215				  S3C2410_LCDCON3_HFPD(7),
216
217		.lcdcon4	= S3C2410_LCDCON4_MVAL(0) |
218				  S3C2410_LCDCON4_HSPW(3),
219
220		.lcdcon5	= S3C2410_LCDCON5_FRM565 |
221				  S3C2410_LCDCON5_INVVLINE |
222				  S3C2410_LCDCON5_INVVFRAME |
223				  S3C2410_LCDCON5_PWREN |
224				  S3C2410_LCDCON5_HWSWP,
225	},
226
227	.lpcsel		= ((0xCE6) & ~7) | 1<<4,
228
229	.width		= 240,
230	.height		= 320,
231
232	.xres		= {
233		.min	= 240,
234		.max	= 240,
235		.defval	= 240,
236	},
237
238	.yres		= {
239		.min	= 320,
240		.max	= 320,
241		.defval = 320,
242	},
243
244	.bpp		= {
245		.min	= 16,
246		.max	= 16,
247		.defval = 16,
248	},
249};
250
251/* CS8900 */
252
253static struct resource qt2410_cs89x0_resources[] = {
254	[0] = {
255		.start	= 0x19000000,
256		.end	= 0x19000000 + 16,
257		.flags	= IORESOURCE_MEM,
258	},
259	[1] = {
260		.start	= IRQ_EINT9,
261		.end	= IRQ_EINT9,
262		.flags	= IORESOURCE_IRQ,
263	},
264};
265
266static struct platform_device qt2410_cs89x0 = {
267	.name		= "cirrus-cs89x0",
268	.num_resources	= ARRAY_SIZE(qt2410_cs89x0_resources),
269	.resource	= qt2410_cs89x0_resources,
270};
271
272/* LED */
273
274static struct s3c24xx_led_platdata qt2410_pdata_led = {
275	.gpio		= S3C2410_GPB0,
276	.flags		= S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
277	.name		= "led",
278	.def_trigger	= "timer",
279};
280
281static struct platform_device qt2410_led = {
282	.name		= "s3c24xx_led",
283	.id		= 0,
284	.dev		= {
285		.platform_data = &qt2410_pdata_led,
286	},
287};
288
289/* SPI */
290
291static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
292{
293	switch (cs) {
294	case BITBANG_CS_ACTIVE:
295		s3c2410_gpio_setpin(S3C2410_GPB5, 0);
296		break;
297	case BITBANG_CS_INACTIVE:
298		s3c2410_gpio_setpin(S3C2410_GPB5, 1);
299		break;
300	}
301}
302
303static struct s3c2410_spigpio_info spi_gpio_cfg = {
304	.pin_clk	= S3C2410_GPG7,
305	.pin_mosi	= S3C2410_GPG6,
306	.pin_miso	= S3C2410_GPG5,
307	.chip_select	= &spi_gpio_cs,
308};
309
310
311static struct platform_device qt2410_spi = {
312	.name		  = "s3c24xx-spi-gpio",
313	.id		  = 1,
314	.dev = {
315		.platform_data = &spi_gpio_cfg,
316	},
317};
318
319/* Board devices */
320
321static struct platform_device *qt2410_devices[] __initdata = {
322	&s3c_device_usb,
323	&s3c_device_lcd,
324	&s3c_device_wdt,
325	&s3c_device_i2c,
326	&s3c_device_iis,
327	&s3c_device_sdi,
328	&s3c_device_usbgadget,
329	&qt2410_spi,
330	&qt2410_cs89x0,
331	&qt2410_led,
332};
333
334static struct mtd_partition qt2410_nand_part[] = {
335	[0] = {
336		.name	= "U-Boot",
337		.size	= 0x30000,
338		.offset	= 0,
339	},
340	[1] = {
341		.name	= "U-Boot environment",
342		.offset = 0x30000,
343		.size	= 0x4000,
344	},
345	[2] = {
346		.name	= "kernel",
347		.offset = 0x34000,
348		.size	= SZ_2M,
349	},
350	[3] = {
351		.name	= "initrd",
352		.offset	= 0x234000,
353		.size	= SZ_4M,
354	},
355	[4] = {
356		.name	= "jffs2",
357		.offset = 0x634000,
358		.size	= 0x39cc000,
359	},
360};
361
362static struct s3c2410_nand_set qt2410_nand_sets[] = {
363	[0] = {
364		.name		= "NAND",
365		.nr_chips	= 1,
366		.nr_partitions	= ARRAY_SIZE(qt2410_nand_part),
367		.partitions	= qt2410_nand_part,
368	},
369};
370
371/* choose a set of timings which should suit most 512Mbit
372 * chips and beyond.
373 */
374
375static struct s3c2410_platform_nand qt2410_nand_info = {
376	.tacls		= 20,
377	.twrph0		= 60,
378	.twrph1		= 20,
379	.nr_sets	= ARRAY_SIZE(qt2410_nand_sets),
380	.sets		= qt2410_nand_sets,
381};
382
383/* UDC */
384
385static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
386};
387
388static char tft_type = 's';
389
390static int __init qt2410_tft_setup(char *str)
391{
392	tft_type = str[0];
393	return 1;
394}
395
396__setup("tft=", qt2410_tft_setup);
397
398static void __init qt2410_map_io(void)
399{
400	s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
401	s3c24xx_init_clocks(12*1000*1000);
402	s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
403}
404
405static void __init qt2410_machine_init(void)
406{
407	s3c_device_nand.dev.platform_data = &qt2410_nand_info;
408
409	switch (tft_type) {
410	case 'p': /* production */
411		s3c24xx_fb_set_platdata(&qt2410_prodlcd_cfg);
412		break;
413	case 'b': /* big */
414		s3c24xx_fb_set_platdata(&qt2410_biglcd_cfg);
415		break;
416	case 's': /* small */
417	default:
418		s3c24xx_fb_set_platdata(&qt2410_lcd_cfg);
419		break;
420	}
421
422	s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT);
423	s3c2410_gpio_setpin(S3C2410_GPB0, 1);
424
425	s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
426
427	s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
428
429	platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
430	s3c2410_pm_init();
431}
432
433MACHINE_START(QT2410, "QT2410")
434	.phys_io	= S3C2410_PA_UART,
435	.io_pg_offst	= (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
436	.boot_params	= S3C2410_SDRAM_PA + 0x100,
437	.map_io		= qt2410_map_io,
438	.init_irq	= s3c24xx_init_irq,
439	.init_machine	= qt2410_machine_init,
440	.timer		= &s3c24xx_timer,
441MACHINE_END
442