1#ifndef __ASSEMBLER__ 2typedef unsigned long bu32; 3typedef long bs32; 4typedef unsigned short bu16; 5typedef short bs16; 6typedef unsigned char bu8; 7typedef char bs8; 8#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) 9#define BFIN_MMR_16(mmr) mmr, __pad_##mmr 10#include "test-dma.h" 11#else 12#define __ADSPBF537__ /* XXX: Hack for .S files. */ 13#endif 14#ifndef __FDPIC__ 15#include <blackfin.h> 16#endif 17 18/* AZ AN AC0_COPY V_COPY CC AQ RND_MOD AC0 AC1 AV0 AV0S AV1 AV1S V VS */ 19 20#define _AZ (1 << 0) 21#define _AN (1 << 1) 22#define _AC0_COPY (1 << 2) 23#define _V_COPY (1 << 3) 24#define _CC (1 << 5) 25#define _AQ (1 << 6) 26#define _RND_MOD (1 << 8) 27#define _AC0 (1 << 12) 28#define _AC1 (1 << 13) 29#define _AV0 (1 << 16) 30#define _AV0S (1 << 17) 31#define _AV1 (1 << 18) 32#define _AV1S (1 << 19) 33#define _V (1 << 24) 34#define _VS (1 << 25) 35 36#define _SET 1 37#define _UNSET 0 38 39#define PASS do { puts ("pass"); _exit (0); } while (0) 40#define FAIL do { puts ("fail"); _exit (1); } while (0) 41#define DBG_PASS do { asm volatile ("outc 'p'; outc 'a'; outc 's'; outc 's'; outc '\n'; hlt;"); } while (1) 42#define DBG_FAIL do { asm volatile ("outc 'f'; outc 'a'; outc 'i'; outc 'l'; outc '\n'; abort;"); } while (1) 43 44#define HI(x) (((x) >> 16) & 0xffff) 45#define LO(x) ((x) & 0xffff) 46 47#define INIT_R_REGS(val) init_r_regs val 48#define INIT_P_REGS(val) init_p_regs val 49#define INIT_B_REGS(val) init_b_regs val 50#define INIT_I_REGS(val) init_i_regs val 51#define INIT_L_REGS(val) init_l_regs val 52#define INIT_M_REGS(val) init_m_regs val 53#define include(...) 54#define CHECK_INIT_DEF(...) nop; 55#define CHECK_INIT(...) nop; 56#define CHECKMEM32(...) 57#define GEN_INT_INIT(...) nop; 58 59#define LD32_LABEL(reg, sym) loadsym reg, sym 60#define LD32(reg, val) imm32 reg, val 61#define CHECKREG(reg, val) CHECKREG reg, val 62#define CHECKREG_SYM_JUMPLESS(reg, sym, scratch_reg) \ 63 loadsym scratch_reg, sym; \ 64 cc = reg == scratch_reg; \ 65 /* Need to avoid jumping for trace buffer. */ \ 66 if !cc jump fail_lvl; 67#define CHECKREG_SYM(reg, sym, scratch_reg) \ 68 loadsym scratch_reg, sym; \ 69 cc = reg == scratch_reg; \ 70 if cc jump 9f; \ 71 dbg_fail; \ 729: 73 74#define WR_MMR(mmr, val, mmr_reg, val_reg) \ 75 imm32 mmr_reg, mmr; \ 76 imm32 val_reg, val; \ 77 [mmr_reg] = val_reg; 78#define WR_MMR_LABEL(mmr, sym, mmr_reg, sym_reg) \ 79 loadsym sym_reg, sym; \ 80 imm32 mmr_reg, mmr; \ 81 [mmr_reg] = sym_reg; 82#define RD_MMR(mmr, mmr_reg, val_reg) \ 83 imm32 mmr_reg, mmr; \ 84 val_reg = [mmr_reg]; 85 86/* Legacy CPLB bits */ 87#define CPLB_L1_CACHABLE CPLB_L1_CHBL 88#define CPLB_USER_RO CPLB_USER_RD 89 90#define DATA_ADDR_1 0xff800000 91#define DATA_ADDR_2 0xff900000 92#define DATA_ADDR_3 (DATA_ADDR_1 + 0x2000) 93 94/* The libgloss headers omit these defines. */ 95#define EVT_OVERRIDE 0xFFE02100 96#define EVT_IMASK IMASK 97 98#define PAGE_SIZE_1K PAGE_SIZE_1KB 99#define PAGE_SIZE_4K PAGE_SIZE_4KB 100#define PAGE_SIZE_1M PAGE_SIZE_1MB 101#define PAGE_SIZE_4M PAGE_SIZE_4MB 102 103#define CPLB_USER_RW (CPLB_USER_RD | CPLB_USER_WR) 104 105#define DMC_AB_SRAM 0x0 106#define DMC_AB_CACHE 0xc 107#define DMC_ACACHE_BSRAM 0x8 108 109#define CPLB_L1SRAM (1 << 5) 110#define CPLB_DA0ACC (1 << 6) 111 112#define FAULT_CPLB0 (1 << 0) 113#define FAULT_CPLB1 (1 << 1) 114#define FAULT_CPLB2 (1 << 2) 115#define FAULT_CPLB3 (1 << 3) 116#define FAULT_CPLB4 (1 << 4) 117#define FAULT_CPLB5 (1 << 5) 118#define FAULT_CPLB6 (1 << 6) 119#define FAULT_CPLB7 (1 << 7) 120#define FAULT_CPLB8 (1 << 8) 121#define FAULT_CPLB9 (1 << 9) 122#define FAULT_CPLB10 (1 << 10) 123#define FAULT_CPLB11 (1 << 11) 124#define FAULT_CPLB12 (1 << 12) 125#define FAULT_CPLB13 (1 << 13) 126#define FAULT_CPLB14 (1 << 14) 127#define FAULT_CPLB15 (1 << 15) 128#define FAULT_READ (0 << 16) 129#define FAULT_WRITE (1 << 16) 130#define FAULT_USER (0 << 17) 131#define FAULT_SUPV (1 << 17) 132#define FAULT_DAG0 (0 << 18) 133#define FAULT_DAG1 (1 << 18) 134#define FAULT_ILLADDR (1 << 19) 135