1/* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007, 2 2008, 2009 Free Software Foundation, Inc. 3 Contributed by Red Hat, Inc. 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 3, or (at your option) 10any later version. 11 12GCC is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING3. If not see 19<http://www.gnu.org/licenses/>. */ 20 21#include "config.h" 22#include "system.h" 23#include "coretypes.h" 24#include "tm.h" 25#include "rtl.h" 26#include "tree.h" 27#include "regs.h" 28#include "hard-reg-set.h" 29#include "real.h" 30#include "insn-config.h" 31#include "conditions.h" 32#include "insn-flags.h" 33#include "output.h" 34#include "insn-attr.h" 35#include "flags.h" 36#include "recog.h" 37#include "reload.h" 38#include "expr.h" 39#include "obstack.h" 40#include "except.h" 41#include "function.h" 42#include "optabs.h" 43#include "toplev.h" 44#include "basic-block.h" 45#include "tm_p.h" 46#include "ggc.h" 47#include <ctype.h> 48#include "target.h" 49#include "target-def.h" 50#include "targhooks.h" 51#include "integrate.h" 52#include "langhooks.h" 53#include "df.h" 54 55#ifndef FRV_INLINE 56#define FRV_INLINE inline 57#endif 58 59/* The maximum number of distinct NOP patterns. There are three: 60 nop, fnop and mnop. */ 61#define NUM_NOP_PATTERNS 3 62 63/* Classification of instructions and units: integer, floating-point/media, 64 branch and control. */ 65enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS }; 66 67/* The DFA names of the units, in packet order. */ 68static const char *const frv_unit_names[] = 69{ 70 "c", 71 "i0", "f0", 72 "i1", "f1", 73 "i2", "f2", 74 "i3", "f3", 75 "b0", "b1" 76}; 77 78/* The classification of each unit in frv_unit_names[]. */ 79static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] = 80{ 81 GROUP_C, 82 GROUP_I, GROUP_FM, 83 GROUP_I, GROUP_FM, 84 GROUP_I, GROUP_FM, 85 GROUP_I, GROUP_FM, 86 GROUP_B, GROUP_B 87}; 88 89/* Return the DFA unit code associated with the Nth unit of integer 90 or floating-point group GROUP, */ 91#define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1] 92 93/* Return the number of integer or floating-point unit UNIT 94 (1 for I1, 2 for F2, etc.). */ 95#define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2) 96 97/* The DFA unit number for each unit in frv_unit_names[]. */ 98static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)]; 99 100/* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue 101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if 102 no instruction of type T has been seen. */ 103static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1]; 104 105/* An array of dummy nop INSNs, one for each type of nop that the 106 target supports. */ 107static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS]; 108 109/* The number of nop instructions in frv_nops[]. */ 110static unsigned int frv_num_nops; 111 112/* Information about one __builtin_read or __builtin_write access, or 113 the combination of several such accesses. The most general value 114 is all-zeros (an unknown access to an unknown address). */ 115struct frv_io { 116 /* The type of access. FRV_IO_UNKNOWN means the access can be either 117 a read or a write. */ 118 enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type; 119 120 /* The constant address being accessed, or zero if not known. */ 121 HOST_WIDE_INT const_address; 122 123 /* The run-time address, as used in operand 0 of the membar pattern. */ 124 rtx var_address; 125}; 126 127/* Return true if instruction INSN should be packed with the following 128 instruction. */ 129#define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode) 130 131/* Set the value of PACKING_FLAG_P(INSN). */ 132#define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode) 133#define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode) 134 135/* Loop with REG set to each hard register in rtx X. */ 136#define FOR_EACH_REGNO(REG, X) \ 137 for (REG = REGNO (X); \ 138 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \ 139 REG++) 140 141/* This structure contains machine specific function data. */ 142struct GTY(()) machine_function 143{ 144 /* True if we have created an rtx that relies on the stack frame. */ 145 int frame_needed; 146 147 /* True if this function contains at least one __builtin_{read,write}*. */ 148 bool has_membar_p; 149}; 150 151/* Temporary register allocation support structure. */ 152typedef struct frv_tmp_reg_struct 153 { 154 HARD_REG_SET regs; /* possible registers to allocate */ 155 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */ 156 } 157frv_tmp_reg_t; 158 159/* Register state information for VLIW re-packing phase. */ 160#define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */ 161#define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */ 162#define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */ 163#define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */ 164 165#define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE) 166 167typedef unsigned char regstate_t; 168 169/* Used in frv_frame_accessor_t to indicate the direction of a register-to- 170 memory move. */ 171enum frv_stack_op 172{ 173 FRV_LOAD, 174 FRV_STORE 175}; 176 177/* Information required by frv_frame_access. */ 178typedef struct 179{ 180 /* This field is FRV_LOAD if registers are to be loaded from the stack and 181 FRV_STORE if they should be stored onto the stack. FRV_STORE implies 182 the move is being done by the prologue code while FRV_LOAD implies it 183 is being done by the epilogue. */ 184 enum frv_stack_op op; 185 186 /* The base register to use when accessing the stack. This may be the 187 frame pointer, stack pointer, or a temporary. The choice of register 188 depends on which part of the frame is being accessed and how big the 189 frame is. */ 190 rtx base; 191 192 /* The offset of BASE from the bottom of the current frame, in bytes. */ 193 int base_offset; 194} frv_frame_accessor_t; 195 196/* Conditional execution support gathered together in one structure. */ 197typedef struct 198 { 199 /* Linked list of insns to add if the conditional execution conversion was 200 successful. Each link points to an EXPR_LIST which points to the pattern 201 of the insn to add, and the insn to be inserted before. */ 202 rtx added_insns_list; 203 204 /* Identify which registers are safe to allocate for if conversions to 205 conditional execution. We keep the last allocated register in the 206 register classes between COND_EXEC statements. This will mean we allocate 207 different registers for each different COND_EXEC group if we can. This 208 might allow the scheduler to intermix two different COND_EXEC sections. */ 209 frv_tmp_reg_t tmp_reg; 210 211 /* For nested IFs, identify which CC registers are used outside of setting 212 via a compare isnsn, and using via a check insn. This will allow us to 213 know if we can rewrite the register to use a different register that will 214 be paired with the CR register controlling the nested IF-THEN blocks. */ 215 HARD_REG_SET nested_cc_ok_rewrite; 216 217 /* Temporary registers allocated to hold constants during conditional 218 execution. */ 219 rtx scratch_regs[FIRST_PSEUDO_REGISTER]; 220 221 /* Current number of temp registers available. */ 222 int cur_scratch_regs; 223 224 /* Number of nested conditional execution blocks. */ 225 int num_nested_cond_exec; 226 227 /* Map of insns that set up constants in scratch registers. */ 228 bitmap scratch_insns_bitmap; 229 230 /* Conditional execution test register (CC0..CC7). */ 231 rtx cr_reg; 232 233 /* Conditional execution compare register that is paired with cr_reg, so that 234 nested compares can be done. The csubcc and caddcc instructions don't 235 have enough bits to specify both a CC register to be set and a CR register 236 to do the test on, so the same bit number is used for both. Needless to 237 say, this is rather inconvenient for GCC. */ 238 rtx nested_cc_reg; 239 240 /* Extra CR registers used for &&, ||. */ 241 rtx extra_int_cr; 242 rtx extra_fp_cr; 243 244 /* Previous CR used in nested if, to make sure we are dealing with the same 245 nested if as the previous statement. */ 246 rtx last_nested_if_cr; 247 } 248frv_ifcvt_t; 249 250static /* GTY(()) */ frv_ifcvt_t frv_ifcvt; 251 252/* Map register number to smallest register class. */ 253enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; 254 255/* Map class letter into register class. */ 256enum reg_class reg_class_from_letter[256]; 257 258/* Cached value of frv_stack_info. */ 259static frv_stack_t *frv_stack_cache = (frv_stack_t *)0; 260 261/* -mcpu= support */ 262frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */ 263 264/* Forward references */ 265 266static bool frv_handle_option (size_t, const char *, int); 267static bool frv_legitimate_address_p (enum machine_mode, rtx, bool); 268static int frv_default_flags_for_cpu (void); 269static int frv_string_begins_with (const_tree, const char *); 270static FRV_INLINE bool frv_small_data_reloc_p (rtx, int); 271static void frv_print_operand_memory_reference_reg 272 (FILE *, rtx); 273static void frv_print_operand_memory_reference (FILE *, rtx, int); 274static int frv_print_operand_jump_hint (rtx); 275static const char *comparison_string (enum rtx_code, rtx); 276static rtx frv_function_value (const_tree, const_tree, 277 bool); 278static rtx frv_libcall_value (enum machine_mode, 279 const_rtx); 280static FRV_INLINE int frv_regno_ok_for_base_p (int, int); 281static rtx single_set_pattern (rtx); 282static int frv_function_contains_far_jump (void); 283static rtx frv_alloc_temp_reg (frv_tmp_reg_t *, 284 enum reg_class, 285 enum machine_mode, 286 int, int); 287static rtx frv_frame_offset_rtx (int); 288static rtx frv_frame_mem (enum machine_mode, rtx, int); 289static rtx frv_dwarf_store (rtx, int); 290static void frv_frame_insn (rtx, rtx); 291static void frv_frame_access (frv_frame_accessor_t*, 292 rtx, int); 293static void frv_frame_access_multi (frv_frame_accessor_t*, 294 frv_stack_t *, int); 295static void frv_frame_access_standard_regs (enum frv_stack_op, 296 frv_stack_t *); 297static struct machine_function *frv_init_machine_status (void); 298static rtx frv_int_to_acc (enum insn_code, int, rtx); 299static enum machine_mode frv_matching_accg_mode (enum machine_mode); 300static rtx frv_read_argument (tree, unsigned int); 301static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int); 302static int frv_check_constant_argument (enum insn_code, int, rtx); 303static rtx frv_legitimize_target (enum insn_code, rtx); 304static rtx frv_legitimize_argument (enum insn_code, int, rtx); 305static rtx frv_legitimize_tls_address (rtx, enum tls_model); 306static rtx frv_legitimize_address (rtx, rtx, enum machine_mode); 307static rtx frv_expand_set_builtin (enum insn_code, tree, rtx); 308static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx); 309static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx); 310static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx); 311static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx); 312static rtx frv_expand_voidbinop_builtin (enum insn_code, tree); 313static rtx frv_expand_int_void2arg (enum insn_code, tree); 314static rtx frv_expand_prefetches (enum insn_code, tree); 315static rtx frv_expand_voidtriop_builtin (enum insn_code, tree); 316static rtx frv_expand_voidaccop_builtin (enum insn_code, tree); 317static rtx frv_expand_mclracc_builtin (tree); 318static rtx frv_expand_mrdacc_builtin (enum insn_code, tree); 319static rtx frv_expand_mwtacc_builtin (enum insn_code, tree); 320static rtx frv_expand_noargs_builtin (enum insn_code); 321static void frv_split_iacc_move (rtx, rtx); 322static rtx frv_emit_comparison (enum rtx_code, rtx, rtx); 323static int frv_clear_registers_used (rtx *, void *); 324static void frv_ifcvt_add_insn (rtx, rtx, int); 325static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx); 326static rtx frv_ifcvt_load_value (rtx, rtx); 327static int frv_acc_group_1 (rtx *, void *); 328static unsigned int frv_insn_unit (rtx); 329static bool frv_issues_to_branch_unit_p (rtx); 330static int frv_cond_flags (rtx); 331static bool frv_regstate_conflict_p (regstate_t, regstate_t); 332static int frv_registers_conflict_p_1 (rtx *, void *); 333static bool frv_registers_conflict_p (rtx); 334static void frv_registers_update_1 (rtx, const_rtx, void *); 335static void frv_registers_update (rtx); 336static void frv_start_packet (void); 337static void frv_start_packet_block (void); 338static void frv_finish_packet (void (*) (void)); 339static bool frv_pack_insn_p (rtx); 340static void frv_add_insn_to_packet (rtx); 341static void frv_insert_nop_in_packet (rtx); 342static bool frv_for_each_packet (void (*) (void)); 343static bool frv_sort_insn_group_1 (enum frv_insn_group, 344 unsigned int, unsigned int, 345 unsigned int, unsigned int, 346 state_t); 347static int frv_compare_insns (const void *, const void *); 348static void frv_sort_insn_group (enum frv_insn_group); 349static void frv_reorder_packet (void); 350static void frv_fill_unused_units (enum frv_insn_group); 351static void frv_align_label (void); 352static void frv_reorg_packet (void); 353static void frv_register_nop (rtx); 354static void frv_reorg (void); 355static void frv_pack_insns (void); 356static void frv_function_prologue (FILE *, HOST_WIDE_INT); 357static void frv_function_epilogue (FILE *, HOST_WIDE_INT); 358static bool frv_assemble_integer (rtx, unsigned, int); 359static void frv_init_builtins (void); 360static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int); 361static void frv_init_libfuncs (void); 362static bool frv_in_small_data_p (const_tree); 363static void frv_asm_output_mi_thunk 364 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); 365static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *, 366 enum machine_mode, 367 tree, int *, int); 368static rtx frv_expand_builtin_saveregs (void); 369static void frv_expand_builtin_va_start (tree, rtx); 370static bool frv_rtx_costs (rtx, int, int, int*, bool); 371static void frv_asm_out_constructor (rtx, int); 372static void frv_asm_out_destructor (rtx, int); 373static bool frv_function_symbol_referenced_p (rtx); 374static bool frv_cannot_force_const_mem (rtx); 375static const char *unspec_got_name (int); 376static void frv_output_const_unspec (FILE *, 377 const struct frv_unspec *); 378static bool frv_function_ok_for_sibcall (tree, tree); 379static rtx frv_struct_value_rtx (tree, int); 380static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type); 381static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, 382 tree, bool); 383static void frv_output_dwarf_dtprel (FILE *, int, rtx) 384 ATTRIBUTE_UNUSED; 385static bool frv_secondary_reload (bool, rtx, enum reg_class, 386 enum machine_mode, 387 secondary_reload_info *); 388static bool frv_frame_pointer_required (void); 389static bool frv_can_eliminate (const int, const int); 390static void frv_trampoline_init (rtx, tree, rtx); 391 392/* Allow us to easily change the default for -malloc-cc. */ 393#ifndef DEFAULT_NO_ALLOC_CC 394#define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC 395#else 396#define MASK_DEFAULT_ALLOC_CC 0 397#endif 398 399/* Initialize the GCC target structure. */ 400#undef TARGET_ASM_FUNCTION_PROLOGUE 401#define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue 402#undef TARGET_ASM_FUNCTION_EPILOGUE 403#define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue 404#undef TARGET_ASM_INTEGER 405#define TARGET_ASM_INTEGER frv_assemble_integer 406#undef TARGET_DEFAULT_TARGET_FLAGS 407#define TARGET_DEFAULT_TARGET_FLAGS \ 408 (MASK_DEFAULT_ALLOC_CC \ 409 | MASK_COND_MOVE \ 410 | MASK_SCC \ 411 | MASK_COND_EXEC \ 412 | MASK_VLIW_BRANCH \ 413 | MASK_MULTI_CE \ 414 | MASK_NESTED_CE) 415#undef TARGET_HANDLE_OPTION 416#define TARGET_HANDLE_OPTION frv_handle_option 417#undef TARGET_INIT_BUILTINS 418#define TARGET_INIT_BUILTINS frv_init_builtins 419#undef TARGET_EXPAND_BUILTIN 420#define TARGET_EXPAND_BUILTIN frv_expand_builtin 421#undef TARGET_INIT_LIBFUNCS 422#define TARGET_INIT_LIBFUNCS frv_init_libfuncs 423#undef TARGET_IN_SMALL_DATA_P 424#define TARGET_IN_SMALL_DATA_P frv_in_small_data_p 425#undef TARGET_RTX_COSTS 426#define TARGET_RTX_COSTS frv_rtx_costs 427#undef TARGET_ASM_CONSTRUCTOR 428#define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor 429#undef TARGET_ASM_DESTRUCTOR 430#define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor 431 432#undef TARGET_ASM_OUTPUT_MI_THUNK 433#define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk 434#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 435#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall 436 437#undef TARGET_SCHED_ISSUE_RATE 438#define TARGET_SCHED_ISSUE_RATE frv_issue_rate 439 440#undef TARGET_LEGITIMIZE_ADDRESS 441#define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address 442 443#undef TARGET_FUNCTION_OK_FOR_SIBCALL 444#define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall 445#undef TARGET_CANNOT_FORCE_CONST_MEM 446#define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem 447 448#undef TARGET_HAVE_TLS 449#define TARGET_HAVE_TLS HAVE_AS_TLS 450 451#undef TARGET_STRUCT_VALUE_RTX 452#define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx 453#undef TARGET_MUST_PASS_IN_STACK 454#define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack 455#undef TARGET_PASS_BY_REFERENCE 456#define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack 457#undef TARGET_ARG_PARTIAL_BYTES 458#define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes 459 460#undef TARGET_EXPAND_BUILTIN_SAVEREGS 461#define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs 462#undef TARGET_SETUP_INCOMING_VARARGS 463#define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs 464#undef TARGET_MACHINE_DEPENDENT_REORG 465#define TARGET_MACHINE_DEPENDENT_REORG frv_reorg 466 467#undef TARGET_EXPAND_BUILTIN_VA_START 468#define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start 469 470#if HAVE_AS_TLS 471#undef TARGET_ASM_OUTPUT_DWARF_DTPREL 472#define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel 473#endif 474 475#undef TARGET_SECONDARY_RELOAD 476#define TARGET_SECONDARY_RELOAD frv_secondary_reload 477 478#undef TARGET_LEGITIMATE_ADDRESS_P 479#define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p 480 481#undef TARGET_FRAME_POINTER_REQUIRED 482#define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required 483 484#undef TARGET_CAN_ELIMINATE 485#define TARGET_CAN_ELIMINATE frv_can_eliminate 486 487#undef TARGET_TRAMPOLINE_INIT 488#define TARGET_TRAMPOLINE_INIT frv_trampoline_init 489 490#undef TARGET_FUNCTION_VALUE 491#define TARGET_FUNCTION_VALUE frv_function_value 492#undef TARGET_LIBCALL_VALUE 493#define TARGET_LIBCALL_VALUE frv_libcall_value 494 495struct gcc_target targetm = TARGET_INITIALIZER; 496 497#define FRV_SYMBOL_REF_TLS_P(RTX) \ 498 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) 499 500 501/* Any function call that satisfies the machine-independent 502 requirements is eligible on FR-V. */ 503 504static bool 505frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED, 506 tree exp ATTRIBUTE_UNUSED) 507{ 508 return true; 509} 510 511/* Return true if SYMBOL is a small data symbol and relocation RELOC 512 can be used to access it directly in a load or store. */ 513 514static FRV_INLINE bool 515frv_small_data_reloc_p (rtx symbol, int reloc) 516{ 517 return (GET_CODE (symbol) == SYMBOL_REF 518 && SYMBOL_REF_SMALL_P (symbol) 519 && (!TARGET_FDPIC || flag_pic == 1) 520 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12)); 521} 522 523/* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC 524 appropriately. */ 525 526bool 527frv_const_unspec_p (rtx x, struct frv_unspec *unspec) 528{ 529 if (GET_CODE (x) == CONST) 530 { 531 unspec->offset = 0; 532 x = XEXP (x, 0); 533 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) 534 { 535 unspec->offset += INTVAL (XEXP (x, 1)); 536 x = XEXP (x, 0); 537 } 538 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT) 539 { 540 unspec->symbol = XVECEXP (x, 0, 0); 541 unspec->reloc = INTVAL (XVECEXP (x, 0, 1)); 542 543 if (unspec->offset == 0) 544 return true; 545 546 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc) 547 && unspec->offset > 0 548 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value) 549 return true; 550 } 551 } 552 return false; 553} 554 555/* Decide whether we can force certain constants to memory. If we 556 decide we can't, the caller should be able to cope with it in 557 another way. 558 559 We never allow constants to be forced into memory for TARGET_FDPIC. 560 This is necessary for several reasons: 561 562 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the 563 target-independent code will try to force them into the constant 564 pool, thus leading to infinite recursion. 565 566 2. We can never introduce new constant pool references during reload. 567 Any such reference would require use of the pseudo FDPIC register. 568 569 3. We can't represent a constant added to a function pointer (which is 570 not the same as a pointer to a function+constant). 571 572 4. In many cases, it's more efficient to calculate the constant in-line. */ 573 574static bool 575frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) 576{ 577 return TARGET_FDPIC; 578} 579 580/* Implement TARGET_HANDLE_OPTION. */ 581 582static bool 583frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) 584{ 585 switch (code) 586 { 587 case OPT_mcpu_: 588 if (strcmp (arg, "simple") == 0) 589 frv_cpu_type = FRV_CPU_SIMPLE; 590 else if (strcmp (arg, "tomcat") == 0) 591 frv_cpu_type = FRV_CPU_TOMCAT; 592 else if (strcmp (arg, "fr550") == 0) 593 frv_cpu_type = FRV_CPU_FR550; 594 else if (strcmp (arg, "fr500") == 0) 595 frv_cpu_type = FRV_CPU_FR500; 596 else if (strcmp (arg, "fr450") == 0) 597 frv_cpu_type = FRV_CPU_FR450; 598 else if (strcmp (arg, "fr405") == 0) 599 frv_cpu_type = FRV_CPU_FR405; 600 else if (strcmp (arg, "fr400") == 0) 601 frv_cpu_type = FRV_CPU_FR400; 602 else if (strcmp (arg, "fr300") == 0) 603 frv_cpu_type = FRV_CPU_FR300; 604 else if (strcmp (arg, "frv") == 0) 605 frv_cpu_type = FRV_CPU_GENERIC; 606 else 607 return false; 608 return true; 609 610 default: 611 return true; 612 } 613} 614 615static int 616frv_default_flags_for_cpu (void) 617{ 618 switch (frv_cpu_type) 619 { 620 case FRV_CPU_GENERIC: 621 return MASK_DEFAULT_FRV; 622 623 case FRV_CPU_FR550: 624 return MASK_DEFAULT_FR550; 625 626 case FRV_CPU_FR500: 627 case FRV_CPU_TOMCAT: 628 return MASK_DEFAULT_FR500; 629 630 case FRV_CPU_FR450: 631 return MASK_DEFAULT_FR450; 632 633 case FRV_CPU_FR405: 634 case FRV_CPU_FR400: 635 return MASK_DEFAULT_FR400; 636 637 case FRV_CPU_FR300: 638 case FRV_CPU_SIMPLE: 639 return MASK_DEFAULT_SIMPLE; 640 641 default: 642 gcc_unreachable (); 643 } 644} 645 646/* Sometimes certain combinations of command options do not make 647 sense on a particular target machine. You can define a macro 648 `OVERRIDE_OPTIONS' to take account of this. This macro, if 649 defined, is executed once just after all the command options have 650 been parsed. 651 652 Don't use this macro to turn on various extra optimizations for 653 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 654 655void 656frv_override_options (void) 657{ 658 int regno; 659 unsigned int i; 660 661 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit); 662 663 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the 664 linker about linking pic and non-pic code. */ 665 if (TARGET_LIBPIC) 666 { 667 if (!flag_pic) /* -fPIC */ 668 flag_pic = 2; 669 670 if (! g_switch_set) /* -G0 */ 671 { 672 g_switch_set = 1; 673 g_switch_value = 0; 674 } 675 } 676 677 /* A C expression whose value is a register class containing hard 678 register REGNO. In general there is more than one such class; 679 choose a class which is "minimal", meaning that no smaller class 680 also contains the register. */ 681 682 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 683 { 684 enum reg_class rclass; 685 686 if (GPR_P (regno)) 687 { 688 int gpr_reg = regno - GPR_FIRST; 689 690 if (gpr_reg == GR8_REG) 691 rclass = GR8_REGS; 692 693 else if (gpr_reg == GR9_REG) 694 rclass = GR9_REGS; 695 696 else if (gpr_reg == GR14_REG) 697 rclass = FDPIC_FPTR_REGS; 698 699 else if (gpr_reg == FDPIC_REGNO) 700 rclass = FDPIC_REGS; 701 702 else if ((gpr_reg & 3) == 0) 703 rclass = QUAD_REGS; 704 705 else if ((gpr_reg & 1) == 0) 706 rclass = EVEN_REGS; 707 708 else 709 rclass = GPR_REGS; 710 } 711 712 else if (FPR_P (regno)) 713 { 714 int fpr_reg = regno - GPR_FIRST; 715 if ((fpr_reg & 3) == 0) 716 rclass = QUAD_FPR_REGS; 717 718 else if ((fpr_reg & 1) == 0) 719 rclass = FEVEN_REGS; 720 721 else 722 rclass = FPR_REGS; 723 } 724 725 else if (regno == LR_REGNO) 726 rclass = LR_REG; 727 728 else if (regno == LCR_REGNO) 729 rclass = LCR_REG; 730 731 else if (ICC_P (regno)) 732 rclass = ICC_REGS; 733 734 else if (FCC_P (regno)) 735 rclass = FCC_REGS; 736 737 else if (ICR_P (regno)) 738 rclass = ICR_REGS; 739 740 else if (FCR_P (regno)) 741 rclass = FCR_REGS; 742 743 else if (ACC_P (regno)) 744 { 745 int r = regno - ACC_FIRST; 746 if ((r & 3) == 0) 747 rclass = QUAD_ACC_REGS; 748 else if ((r & 1) == 0) 749 rclass = EVEN_ACC_REGS; 750 else 751 rclass = ACC_REGS; 752 } 753 754 else if (ACCG_P (regno)) 755 rclass = ACCG_REGS; 756 757 else 758 rclass = NO_REGS; 759 760 regno_reg_class[regno] = rclass; 761 } 762 763 /* Check for small data option */ 764 if (!g_switch_set) 765 g_switch_value = SDATA_DEFAULT_SIZE; 766 767 /* A C expression which defines the machine-dependent operand 768 constraint letters for register classes. If CHAR is such a 769 letter, the value should be the register class corresponding to 770 it. Otherwise, the value should be `NO_REGS'. The register 771 letter `r', corresponding to class `GENERAL_REGS', will not be 772 passed to this macro; you do not need to handle it. 773 774 The following letters are unavailable, due to being used as 775 constraints: 776 '0'..'9' 777 '<', '>' 778 'E', 'F', 'G', 'H' 779 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P' 780 'Q', 'R', 'S', 'T', 'U' 781 'V', 'X' 782 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */ 783 784 for (i = 0; i < 256; i++) 785 reg_class_from_letter[i] = NO_REGS; 786 787 reg_class_from_letter['a'] = ACC_REGS; 788 reg_class_from_letter['b'] = EVEN_ACC_REGS; 789 reg_class_from_letter['c'] = CC_REGS; 790 reg_class_from_letter['d'] = GPR_REGS; 791 reg_class_from_letter['e'] = EVEN_REGS; 792 reg_class_from_letter['f'] = FPR_REGS; 793 reg_class_from_letter['h'] = FEVEN_REGS; 794 reg_class_from_letter['l'] = LR_REG; 795 reg_class_from_letter['q'] = QUAD_REGS; 796 reg_class_from_letter['t'] = ICC_REGS; 797 reg_class_from_letter['u'] = FCC_REGS; 798 reg_class_from_letter['v'] = ICR_REGS; 799 reg_class_from_letter['w'] = FCR_REGS; 800 reg_class_from_letter['x'] = QUAD_FPR_REGS; 801 reg_class_from_letter['y'] = LCR_REG; 802 reg_class_from_letter['z'] = SPR_REGS; 803 reg_class_from_letter['A'] = QUAD_ACC_REGS; 804 reg_class_from_letter['B'] = ACCG_REGS; 805 reg_class_from_letter['C'] = CR_REGS; 806 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */ 807 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */ 808 809 /* There is no single unaligned SI op for PIC code. Sometimes we 810 need to use ".4byte" and sometimes we need to use ".picptr". 811 See frv_assemble_integer for details. */ 812 if (flag_pic || TARGET_FDPIC) 813 targetm.asm_out.unaligned_op.si = 0; 814 815 if ((target_flags_explicit & MASK_LINKED_FP) == 0) 816 target_flags |= MASK_LINKED_FP; 817 818 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0) 819 target_flags |= MASK_OPTIMIZE_MEMBAR; 820 821 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++) 822 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]); 823 824 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++) 825 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes); 826 827 init_machine_status = frv_init_machine_status; 828} 829 830 831/* Some machines may desire to change what optimizations are performed for 832 various optimization levels. This macro, if defined, is executed once just 833 after the optimization level is determined and before the remainder of the 834 command options have been parsed. Values set in this macro are used as the 835 default values for the other command line options. 836 837 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if 838 `-O' is specified, and 0 if neither is specified. 839 840 SIZE is nonzero if `-Os' is specified, 0 otherwise. 841 842 You should not use this macro to change options that are not 843 machine-specific. These should uniformly selected by the same optimization 844 level on all supported machines. Use this macro to enable machine-specific 845 optimizations. 846 847 *Do not examine `write_symbols' in this macro!* The debugging options are 848 *not supposed to alter the generated code. */ 849 850/* On the FRV, possibly disable VLIW packing which is done by the 2nd 851 scheduling pass at the current time. */ 852void 853frv_optimization_options (int level, int size ATTRIBUTE_UNUSED) 854{ 855 if (level >= 2) 856 { 857#ifdef DISABLE_SCHED2 858 flag_schedule_insns_after_reload = 0; 859#endif 860#ifdef ENABLE_RCSP 861 flag_rcsp = 1; 862#endif 863 } 864} 865 866 867/* Return true if NAME (a STRING_CST node) begins with PREFIX. */ 868 869static int 870frv_string_begins_with (const_tree name, const char *prefix) 871{ 872 const int prefix_len = strlen (prefix); 873 874 /* Remember: NAME's length includes the null terminator. */ 875 return (TREE_STRING_LENGTH (name) > prefix_len 876 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0); 877} 878 879/* Zero or more C statements that may conditionally modify two variables 880 `fixed_regs' and `call_used_regs' (both of type `char []') after they have 881 been initialized from the two preceding macros. 882 883 This is necessary in case the fixed or call-clobbered registers depend on 884 target flags. 885 886 You need not define this macro if it has no work to do. 887 888 If the usage of an entire class of registers depends on the target flags, 889 you may indicate this to GCC by using this macro to modify `fixed_regs' and 890 `call_used_regs' to 1 for each of the registers in the classes which should 891 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return 892 `NO_REGS' if it is called with a letter for a class that shouldn't be used. 893 894 (However, if this class is not included in `GENERAL_REGS' and all of the 895 insn patterns whose constraints permit this class are controlled by target 896 switches, then GCC will automatically avoid using these registers when the 897 target switches are opposed to them.) */ 898 899void 900frv_conditional_register_usage (void) 901{ 902 int i; 903 904 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++) 905 fixed_regs[i] = call_used_regs[i] = 1; 906 907 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++) 908 fixed_regs[i] = call_used_regs[i] = 1; 909 910 /* Reserve the registers used for conditional execution. At present, we need 911 1 ICC and 1 ICR register. */ 912 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1; 913 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1; 914 915 if (TARGET_FIXED_CC) 916 { 917 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1; 918 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1; 919 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1; 920 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1; 921 } 922 923 if (TARGET_FDPIC) 924 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] = 925 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0; 926 927#if 0 928 /* If -fpic, SDA_BASE_REG is the PIC register. */ 929 if (g_switch_value == 0 && !flag_pic) 930 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0; 931 932 if (!flag_pic) 933 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0; 934#endif 935} 936 937 938/* 939 * Compute the stack frame layout 940 * 941 * Register setup: 942 * +---------------+-----------------------+-----------------------+ 943 * |Register |type |caller-save/callee-save| 944 * +---------------+-----------------------+-----------------------+ 945 * |GR0 |Zero register | - | 946 * |GR1 |Stack pointer(SP) | - | 947 * |GR2 |Frame pointer(FP) | - | 948 * |GR3 |Hidden parameter | caller save | 949 * |GR4-GR7 | - | caller save | 950 * |GR8-GR13 |Argument register | caller save | 951 * |GR14-GR15 | - | caller save | 952 * |GR16-GR31 | - | callee save | 953 * |GR32-GR47 | - | caller save | 954 * |GR48-GR63 | - | callee save | 955 * |FR0-FR15 | - | caller save | 956 * |FR16-FR31 | - | callee save | 957 * |FR32-FR47 | - | caller save | 958 * |FR48-FR63 | - | callee save | 959 * +---------------+-----------------------+-----------------------+ 960 * 961 * Stack frame setup: 962 * Low 963 * SP-> |-----------------------------------| 964 * | Argument area | 965 * |-----------------------------------| 966 * | Register save area | 967 * |-----------------------------------| 968 * | Local variable save area | 969 * FP-> |-----------------------------------| 970 * | Old FP | 971 * |-----------------------------------| 972 * | Hidden parameter save area | 973 * |-----------------------------------| 974 * | Return address(LR) storage area | 975 * |-----------------------------------| 976 * | Padding for alignment | 977 * |-----------------------------------| 978 * | Register argument area | 979 * OLD SP-> |-----------------------------------| 980 * | Parameter area | 981 * |-----------------------------------| 982 * High 983 * 984 * Argument area/Parameter area: 985 * 986 * When a function is called, this area is used for argument transfer. When 987 * the argument is set up by the caller function, this area is referred to as 988 * the argument area. When the argument is referenced by the callee function, 989 * this area is referred to as the parameter area. The area is allocated when 990 * all arguments cannot be placed on the argument register at the time of 991 * argument transfer. 992 * 993 * Register save area: 994 * 995 * This is a register save area that must be guaranteed for the caller 996 * function. This area is not secured when the register save operation is not 997 * needed. 998 * 999 * Local variable save area: 1000 * 1001 * This is the area for local variables and temporary variables. 1002 * 1003 * Old FP: 1004 * 1005 * This area stores the FP value of the caller function. 1006 * 1007 * Hidden parameter save area: 1008 * 1009 * This area stores the start address of the return value storage 1010 * area for a struct/union return function. 1011 * When a struct/union is used as the return value, the caller 1012 * function stores the return value storage area start address in 1013 * register GR3 and passes it to the caller function. 1014 * The callee function interprets the address stored in the GR3 1015 * as the return value storage area start address. 1016 * When register GR3 needs to be saved into memory, the callee 1017 * function saves it in the hidden parameter save area. This 1018 * area is not secured when the save operation is not needed. 1019 * 1020 * Return address(LR) storage area: 1021 * 1022 * This area saves the LR. The LR stores the address of a return to the caller 1023 * function for the purpose of function calling. 1024 * 1025 * Argument register area: 1026 * 1027 * This area saves the argument register. This area is not secured when the 1028 * save operation is not needed. 1029 * 1030 * Argument: 1031 * 1032 * Arguments, the count of which equals the count of argument registers (6 1033 * words), are positioned in registers GR8 to GR13 and delivered to the callee 1034 * function. When a struct/union return function is called, the return value 1035 * area address is stored in register GR3. Arguments not placed in the 1036 * argument registers will be stored in the stack argument area for transfer 1037 * purposes. When an 8-byte type argument is to be delivered using registers, 1038 * it is divided into two and placed in two registers for transfer. When 1039 * argument registers must be saved to memory, the callee function secures an 1040 * argument register save area in the stack. In this case, a continuous 1041 * argument register save area must be established in the parameter area. The 1042 * argument register save area must be allocated as needed to cover the size of 1043 * the argument register to be saved. If the function has a variable count of 1044 * arguments, it saves all argument registers in the argument register save 1045 * area. 1046 * 1047 * Argument Extension Format: 1048 * 1049 * When an argument is to be stored in the stack, its type is converted to an 1050 * extended type in accordance with the individual argument type. The argument 1051 * is freed by the caller function after the return from the callee function is 1052 * made. 1053 * 1054 * +-----------------------+---------------+------------------------+ 1055 * | Argument Type |Extended Type |Stack Storage Size(byte)| 1056 * +-----------------------+---------------+------------------------+ 1057 * |char |int | 4 | 1058 * |signed char |int | 4 | 1059 * |unsigned char |int | 4 | 1060 * |[signed] short int |int | 4 | 1061 * |unsigned short int |int | 4 | 1062 * |[signed] int |No extension | 4 | 1063 * |unsigned int |No extension | 4 | 1064 * |[signed] long int |No extension | 4 | 1065 * |unsigned long int |No extension | 4 | 1066 * |[signed] long long int |No extension | 8 | 1067 * |unsigned long long int |No extension | 8 | 1068 * |float |double | 8 | 1069 * |double |No extension | 8 | 1070 * |long double |No extension | 8 | 1071 * |pointer |No extension | 4 | 1072 * |struct/union |- | 4 (*1) | 1073 * +-----------------------+---------------+------------------------+ 1074 * 1075 * When a struct/union is to be delivered as an argument, the caller copies it 1076 * to the local variable area and delivers the address of that area. 1077 * 1078 * Return Value: 1079 * 1080 * +-------------------------------+----------------------+ 1081 * |Return Value Type |Return Value Interface| 1082 * +-------------------------------+----------------------+ 1083 * |void |None | 1084 * |[signed|unsigned] char |GR8 | 1085 * |[signed|unsigned] short int |GR8 | 1086 * |[signed|unsigned] int |GR8 | 1087 * |[signed|unsigned] long int |GR8 | 1088 * |pointer |GR8 | 1089 * |[signed|unsigned] long long int|GR8 & GR9 | 1090 * |float |GR8 | 1091 * |double |GR8 & GR9 | 1092 * |long double |GR8 & GR9 | 1093 * |struct/union |(*1) | 1094 * +-------------------------------+----------------------+ 1095 * 1096 * When a struct/union is used as the return value, the caller function stores 1097 * the start address of the return value storage area into GR3 and then passes 1098 * it to the callee function. The callee function interprets GR3 as the start 1099 * address of the return value storage area. When this address needs to be 1100 * saved in memory, the callee function secures the hidden parameter save area 1101 * and saves the address in that area. 1102 */ 1103 1104frv_stack_t * 1105frv_stack_info (void) 1106{ 1107 static frv_stack_t info, zero_info; 1108 frv_stack_t *info_ptr = &info; 1109 tree fndecl = current_function_decl; 1110 int varargs_p = 0; 1111 tree cur_arg; 1112 tree next_arg; 1113 int range; 1114 int alignment; 1115 int offset; 1116 1117 /* If we've already calculated the values and reload is complete, 1118 just return now. */ 1119 if (frv_stack_cache) 1120 return frv_stack_cache; 1121 1122 /* Zero all fields. */ 1123 info = zero_info; 1124 1125 /* Set up the register range information. */ 1126 info_ptr->regs[STACK_REGS_GPR].name = "gpr"; 1127 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1; 1128 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST; 1129 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE; 1130 1131 info_ptr->regs[STACK_REGS_FPR].name = "fpr"; 1132 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST; 1133 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST; 1134 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE; 1135 1136 info_ptr->regs[STACK_REGS_LR].name = "lr"; 1137 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO; 1138 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO; 1139 info_ptr->regs[STACK_REGS_LR].special_p = 1; 1140 1141 info_ptr->regs[STACK_REGS_CC].name = "cc"; 1142 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST; 1143 info_ptr->regs[STACK_REGS_CC].last = CC_LAST; 1144 info_ptr->regs[STACK_REGS_CC].field_p = TRUE; 1145 1146 info_ptr->regs[STACK_REGS_LCR].name = "lcr"; 1147 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO; 1148 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO; 1149 1150 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg"; 1151 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM; 1152 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM; 1153 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1; 1154 info_ptr->regs[STACK_REGS_STDARG].special_p = 1; 1155 1156 info_ptr->regs[STACK_REGS_STRUCT].name = "struct"; 1157 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM; 1158 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM; 1159 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1; 1160 1161 info_ptr->regs[STACK_REGS_FP].name = "fp"; 1162 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM; 1163 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM; 1164 info_ptr->regs[STACK_REGS_FP].special_p = 1; 1165 1166 /* Determine if this is a stdarg function. If so, allocate space to store 1167 the 6 arguments. */ 1168 if (cfun->stdarg) 1169 varargs_p = 1; 1170 1171 else 1172 { 1173 /* Find the last argument, and see if it is __builtin_va_alist. */ 1174 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg) 1175 { 1176 next_arg = TREE_CHAIN (cur_arg); 1177 if (next_arg == (tree)0) 1178 { 1179 if (DECL_NAME (cur_arg) 1180 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist")) 1181 varargs_p = 1; 1182 1183 break; 1184 } 1185 } 1186 } 1187 1188 /* Iterate over all of the register ranges. */ 1189 for (range = 0; range < STACK_REGS_MAX; range++) 1190 { 1191 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); 1192 int first = reg_ptr->first; 1193 int last = reg_ptr->last; 1194 int size_1word = 0; 1195 int size_2words = 0; 1196 int regno; 1197 1198 /* Calculate which registers need to be saved & save area size. */ 1199 switch (range) 1200 { 1201 default: 1202 for (regno = first; regno <= last; regno++) 1203 { 1204 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno]) 1205 || (crtl->calls_eh_return 1206 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM)) 1207 || (!TARGET_FDPIC && flag_pic 1208 && crtl->uses_pic_offset_table && regno == PIC_REGNO)) 1209 { 1210 info_ptr->save_p[regno] = REG_SAVE_1WORD; 1211 size_1word += UNITS_PER_WORD; 1212 } 1213 } 1214 break; 1215 1216 /* Calculate whether we need to create a frame after everything else 1217 has been processed. */ 1218 case STACK_REGS_FP: 1219 break; 1220 1221 case STACK_REGS_LR: 1222 if (df_regs_ever_live_p (LR_REGNO) 1223 || profile_flag 1224 /* This is set for __builtin_return_address, etc. */ 1225 || cfun->machine->frame_needed 1226 || (TARGET_LINKED_FP && frame_pointer_needed) 1227 || (!TARGET_FDPIC && flag_pic 1228 && crtl->uses_pic_offset_table)) 1229 { 1230 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD; 1231 size_1word += UNITS_PER_WORD; 1232 } 1233 break; 1234 1235 case STACK_REGS_STDARG: 1236 if (varargs_p) 1237 { 1238 /* If this is a stdarg function with a non varardic 1239 argument split between registers and the stack, 1240 adjust the saved registers downward. */ 1241 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD) 1242 / UNITS_PER_WORD); 1243 1244 for (regno = first; regno <= last; regno++) 1245 { 1246 info_ptr->save_p[regno] = REG_SAVE_1WORD; 1247 size_1word += UNITS_PER_WORD; 1248 } 1249 1250 info_ptr->stdarg_size = size_1word; 1251 } 1252 break; 1253 1254 case STACK_REGS_STRUCT: 1255 if (cfun->returns_struct) 1256 { 1257 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD; 1258 size_1word += UNITS_PER_WORD; 1259 } 1260 break; 1261 } 1262 1263 1264 if (size_1word) 1265 { 1266 /* If this is a field, it only takes one word. */ 1267 if (reg_ptr->field_p) 1268 size_1word = UNITS_PER_WORD; 1269 1270 /* Determine which register pairs can be saved together. */ 1271 else if (reg_ptr->dword_p && TARGET_DWORD) 1272 { 1273 for (regno = first; regno < last; regno += 2) 1274 { 1275 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1]) 1276 { 1277 size_2words += 2 * UNITS_PER_WORD; 1278 size_1word -= 2 * UNITS_PER_WORD; 1279 info_ptr->save_p[regno] = REG_SAVE_2WORDS; 1280 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE; 1281 } 1282 } 1283 } 1284 1285 reg_ptr->size_1word = size_1word; 1286 reg_ptr->size_2words = size_2words; 1287 1288 if (! reg_ptr->special_p) 1289 { 1290 info_ptr->regs_size_1word += size_1word; 1291 info_ptr->regs_size_2words += size_2words; 1292 } 1293 } 1294 } 1295 1296 /* Set up the sizes of each each field in the frame body, making the sizes 1297 of each be divisible by the size of a dword if dword operations might 1298 be used, or the size of a word otherwise. */ 1299 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD); 1300 1301 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment); 1302 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words 1303 + info_ptr->regs_size_1word, 1304 alignment); 1305 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment); 1306 1307 info_ptr->pretend_size = crtl->args.pretend_args_size; 1308 1309 /* Work out the size of the frame, excluding the header. Both the frame 1310 body and register parameter area will be dword-aligned. */ 1311 info_ptr->total_size 1312 = (ADDR_ALIGN (info_ptr->parameter_size 1313 + info_ptr->regs_size 1314 + info_ptr->vars_size, 1315 2 * UNITS_PER_WORD) 1316 + ADDR_ALIGN (info_ptr->pretend_size 1317 + info_ptr->stdarg_size, 1318 2 * UNITS_PER_WORD)); 1319 1320 /* See if we need to create a frame at all, if so add header area. */ 1321 if (info_ptr->total_size > 0 1322 || frame_pointer_needed 1323 || info_ptr->regs[STACK_REGS_LR].size_1word > 0 1324 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0) 1325 { 1326 offset = info_ptr->parameter_size; 1327 info_ptr->header_size = 4 * UNITS_PER_WORD; 1328 info_ptr->total_size += 4 * UNITS_PER_WORD; 1329 1330 /* Calculate the offsets to save normal register pairs. */ 1331 for (range = 0; range < STACK_REGS_MAX; range++) 1332 { 1333 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); 1334 if (! reg_ptr->special_p) 1335 { 1336 int first = reg_ptr->first; 1337 int last = reg_ptr->last; 1338 int regno; 1339 1340 for (regno = first; regno <= last; regno++) 1341 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS 1342 && regno != FRAME_POINTER_REGNUM 1343 && (regno < FIRST_ARG_REGNUM 1344 || regno > LAST_ARG_REGNUM)) 1345 { 1346 info_ptr->reg_offset[regno] = offset; 1347 offset += 2 * UNITS_PER_WORD; 1348 } 1349 } 1350 } 1351 1352 /* Calculate the offsets to save normal single registers. */ 1353 for (range = 0; range < STACK_REGS_MAX; range++) 1354 { 1355 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); 1356 if (! reg_ptr->special_p) 1357 { 1358 int first = reg_ptr->first; 1359 int last = reg_ptr->last; 1360 int regno; 1361 1362 for (regno = first; regno <= last; regno++) 1363 if (info_ptr->save_p[regno] == REG_SAVE_1WORD 1364 && regno != FRAME_POINTER_REGNUM 1365 && (regno < FIRST_ARG_REGNUM 1366 || regno > LAST_ARG_REGNUM)) 1367 { 1368 info_ptr->reg_offset[regno] = offset; 1369 offset += UNITS_PER_WORD; 1370 } 1371 } 1372 } 1373 1374 /* Calculate the offset to save the local variables at. */ 1375 offset = ADDR_ALIGN (offset, alignment); 1376 if (info_ptr->vars_size) 1377 { 1378 info_ptr->vars_offset = offset; 1379 offset += info_ptr->vars_size; 1380 } 1381 1382 /* Align header to a dword-boundary. */ 1383 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD); 1384 1385 /* Calculate the offsets in the fixed frame. */ 1386 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD; 1387 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset; 1388 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD; 1389 1390 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD; 1391 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD; 1392 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD; 1393 1394 if (cfun->returns_struct) 1395 { 1396 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD; 1397 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD; 1398 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD; 1399 } 1400 1401 /* Calculate the offsets to store the arguments passed in registers 1402 for stdarg functions. The register pairs are first and the single 1403 register if any is last. The register save area starts on a 1404 dword-boundary. */ 1405 if (info_ptr->stdarg_size) 1406 { 1407 int first = info_ptr->regs[STACK_REGS_STDARG].first; 1408 int last = info_ptr->regs[STACK_REGS_STDARG].last; 1409 int regno; 1410 1411 /* Skip the header. */ 1412 offset += 4 * UNITS_PER_WORD; 1413 for (regno = first; regno <= last; regno++) 1414 { 1415 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS) 1416 { 1417 info_ptr->reg_offset[regno] = offset; 1418 offset += 2 * UNITS_PER_WORD; 1419 } 1420 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD) 1421 { 1422 info_ptr->reg_offset[regno] = offset; 1423 offset += UNITS_PER_WORD; 1424 } 1425 } 1426 } 1427 } 1428 1429 if (reload_completed) 1430 frv_stack_cache = info_ptr; 1431 1432 return info_ptr; 1433} 1434 1435 1436/* Print the information about the frv stack offsets, etc. when debugging. */ 1437 1438void 1439frv_debug_stack (frv_stack_t *info) 1440{ 1441 int range; 1442 1443 if (!info) 1444 info = frv_stack_info (); 1445 1446 fprintf (stderr, "\nStack information for function %s:\n", 1447 ((current_function_decl && DECL_NAME (current_function_decl)) 1448 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) 1449 : "<unknown>")); 1450 1451 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size); 1452 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size); 1453 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size); 1454 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n", 1455 info->regs_size, info->regs_size_1word, info->regs_size_2words); 1456 1457 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size); 1458 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size); 1459 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset); 1460 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset); 1461 1462 for (range = 0; range < STACK_REGS_MAX; range++) 1463 { 1464 frv_stack_regs_t *regs = &(info->regs[range]); 1465 if ((regs->size_1word + regs->size_2words) > 0) 1466 { 1467 int first = regs->first; 1468 int last = regs->last; 1469 int regno; 1470 1471 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =", 1472 regs->name, regs->size_1word + regs->size_2words, 1473 regs->size_1word, regs->size_2words); 1474 1475 for (regno = first; regno <= last; regno++) 1476 { 1477 if (info->save_p[regno] == REG_SAVE_1WORD) 1478 fprintf (stderr, " %s (%d)", reg_names[regno], 1479 info->reg_offset[regno]); 1480 1481 else if (info->save_p[regno] == REG_SAVE_2WORDS) 1482 fprintf (stderr, " %s-%s (%d)", reg_names[regno], 1483 reg_names[regno+1], info->reg_offset[regno]); 1484 } 1485 1486 fputc ('\n', stderr); 1487 } 1488 } 1489 1490 fflush (stderr); 1491} 1492 1493 1494 1495 1496/* Used during final to control the packing of insns. The value is 1497 1 if the current instruction should be packed with the next one, 1498 0 if it shouldn't or -1 if packing is disabled altogether. */ 1499 1500static int frv_insn_packing_flag; 1501 1502/* True if the current function contains a far jump. */ 1503 1504static int 1505frv_function_contains_far_jump (void) 1506{ 1507 rtx insn = get_insns (); 1508 while (insn != NULL 1509 && !(GET_CODE (insn) == JUMP_INSN 1510 /* Ignore tablejump patterns. */ 1511 && GET_CODE (PATTERN (insn)) != ADDR_VEC 1512 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC 1513 && get_attr_far_jump (insn) == FAR_JUMP_YES)) 1514 insn = NEXT_INSN (insn); 1515 return (insn != NULL); 1516} 1517 1518/* For the FRV, this function makes sure that a function with far jumps 1519 will return correctly. It also does the VLIW packing. */ 1520 1521static void 1522frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) 1523{ 1524 /* If no frame was created, check whether the function uses a call 1525 instruction to implement a far jump. If so, save the link in gr3 and 1526 replace all returns to LR with returns to GR3. GR3 is used because it 1527 is call-clobbered, because is not available to the register allocator, 1528 and because all functions that take a hidden argument pointer will have 1529 a stack frame. */ 1530 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ()) 1531 { 1532 rtx insn; 1533 1534 /* Just to check that the above comment is true. */ 1535 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3)); 1536 1537 /* Generate the instruction that saves the link register. */ 1538 fprintf (file, "\tmovsg lr,gr3\n"); 1539 1540 /* Replace the LR with GR3 in *return_internal patterns. The insn 1541 will now return using jmpl @(gr3,0) rather than bralr. We cannot 1542 simply emit a different assembly directive because bralr and jmpl 1543 execute in different units. */ 1544 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn)) 1545 if (GET_CODE (insn) == JUMP_INSN) 1546 { 1547 rtx pattern = PATTERN (insn); 1548 if (GET_CODE (pattern) == PARALLEL 1549 && XVECLEN (pattern, 0) >= 2 1550 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN 1551 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE) 1552 { 1553 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0); 1554 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO) 1555 SET_REGNO (address, GPR_FIRST + 3); 1556 } 1557 } 1558 } 1559 1560 frv_pack_insns (); 1561 1562 /* Allow the garbage collector to free the nops created by frv_reorg. */ 1563 memset (frv_nops, 0, sizeof (frv_nops)); 1564} 1565 1566 1567/* Return the next available temporary register in a given class. */ 1568 1569static rtx 1570frv_alloc_temp_reg ( 1571 frv_tmp_reg_t *info, /* which registers are available */ 1572 enum reg_class rclass, /* register class desired */ 1573 enum machine_mode mode, /* mode to allocate register with */ 1574 int mark_as_used, /* register not available after allocation */ 1575 int no_abort) /* return NULL instead of aborting */ 1576{ 1577 int regno = info->next_reg[ (int)rclass ]; 1578 int orig_regno = regno; 1579 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ]; 1580 int i, nr; 1581 1582 for (;;) 1583 { 1584 if (TEST_HARD_REG_BIT (*reg_in_class, regno) 1585 && TEST_HARD_REG_BIT (info->regs, regno)) 1586 break; 1587 1588 if (++regno >= FIRST_PSEUDO_REGISTER) 1589 regno = 0; 1590 if (regno == orig_regno) 1591 { 1592 gcc_assert (no_abort); 1593 return NULL_RTX; 1594 } 1595 } 1596 1597 nr = HARD_REGNO_NREGS (regno, mode); 1598 info->next_reg[ (int)rclass ] = regno + nr; 1599 1600 if (mark_as_used) 1601 for (i = 0; i < nr; i++) 1602 CLEAR_HARD_REG_BIT (info->regs, regno+i); 1603 1604 return gen_rtx_REG (mode, regno); 1605} 1606 1607 1608/* Return an rtx with the value OFFSET, which will either be a register or a 1609 signed 12-bit integer. It can be used as the second operand in an "add" 1610 instruction, or as the index in a load or store. 1611 1612 The function returns a constant rtx if OFFSET is small enough, otherwise 1613 it loads the constant into register OFFSET_REGNO and returns that. */ 1614static rtx 1615frv_frame_offset_rtx (int offset) 1616{ 1617 rtx offset_rtx = GEN_INT (offset); 1618 if (IN_RANGE_P (offset, -2048, 2047)) 1619 return offset_rtx; 1620 else 1621 { 1622 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO); 1623 if (IN_RANGE_P (offset, -32768, 32767)) 1624 emit_insn (gen_movsi (reg_rtx, offset_rtx)); 1625 else 1626 { 1627 emit_insn (gen_movsi_high (reg_rtx, offset_rtx)); 1628 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx)); 1629 } 1630 return reg_rtx; 1631 } 1632} 1633 1634/* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The 1635 prologue and epilogue uses such expressions to access the stack. */ 1636static rtx 1637frv_frame_mem (enum machine_mode mode, rtx base, int offset) 1638{ 1639 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, 1640 base, 1641 frv_frame_offset_rtx (offset))); 1642} 1643 1644/* Generate a frame-related expression: 1645 1646 (set REG (mem (plus (sp) (const_int OFFSET)))). 1647 1648 Such expressions are used in FRAME_RELATED_EXPR notes for more complex 1649 instructions. Marking the expressions as frame-related is superfluous if 1650 the note contains just a single set. But if the note contains a PARALLEL 1651 or SEQUENCE that has several sets, each set must be individually marked 1652 as frame-related. */ 1653static rtx 1654frv_dwarf_store (rtx reg, int offset) 1655{ 1656 rtx set = gen_rtx_SET (VOIDmode, 1657 gen_rtx_MEM (GET_MODE (reg), 1658 plus_constant (stack_pointer_rtx, 1659 offset)), 1660 reg); 1661 RTX_FRAME_RELATED_P (set) = 1; 1662 return set; 1663} 1664 1665/* Emit a frame-related instruction whose pattern is PATTERN. The 1666 instruction is the last in a sequence that cumulatively performs the 1667 operation described by DWARF_PATTERN. The instruction is marked as 1668 frame-related and has a REG_FRAME_RELATED_EXPR note containing 1669 DWARF_PATTERN. */ 1670static void 1671frv_frame_insn (rtx pattern, rtx dwarf_pattern) 1672{ 1673 rtx insn = emit_insn (pattern); 1674 RTX_FRAME_RELATED_P (insn) = 1; 1675 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, 1676 dwarf_pattern, 1677 REG_NOTES (insn)); 1678} 1679 1680/* Emit instructions that transfer REG to or from the memory location (sp + 1681 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is 1682 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this 1683 function to store registers and only the epilogue uses it to load them. 1684 1685 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET). 1686 The generated instruction will use BASE as its base register. BASE may 1687 simply be the stack pointer, but if several accesses are being made to a 1688 region far away from the stack pointer, it may be more efficient to set 1689 up a temporary instead. 1690 1691 Store instructions will be frame-related and will be annotated with the 1692 overall effect of the store. Load instructions will be followed by a 1693 (use) to prevent later optimizations from zapping them. 1694 1695 The function takes care of the moves to and from SPRs, using TEMP_REGNO 1696 as a temporary in such cases. */ 1697static void 1698frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset) 1699{ 1700 enum machine_mode mode = GET_MODE (reg); 1701 rtx mem = frv_frame_mem (mode, 1702 accessor->base, 1703 stack_offset - accessor->base_offset); 1704 1705 if (accessor->op == FRV_LOAD) 1706 { 1707 if (SPR_P (REGNO (reg))) 1708 { 1709 rtx temp = gen_rtx_REG (mode, TEMP_REGNO); 1710 emit_insn (gen_rtx_SET (VOIDmode, temp, mem)); 1711 emit_insn (gen_rtx_SET (VOIDmode, reg, temp)); 1712 } 1713 else 1714 { 1715 /* We cannot use reg+reg addressing for DImode access. */ 1716 if (mode == DImode 1717 && GET_CODE (XEXP (mem, 0)) == PLUS 1718 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG 1719 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG) 1720 { 1721 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO); 1722 rtx insn = emit_move_insn (temp, 1723 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0), 1724 XEXP (XEXP (mem, 0), 1))); 1725 mem = gen_rtx_MEM (DImode, temp); 1726 } 1727 emit_insn (gen_rtx_SET (VOIDmode, reg, mem)); 1728 } 1729 emit_use (reg); 1730 } 1731 else 1732 { 1733 if (SPR_P (REGNO (reg))) 1734 { 1735 rtx temp = gen_rtx_REG (mode, TEMP_REGNO); 1736 emit_insn (gen_rtx_SET (VOIDmode, temp, reg)); 1737 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp), 1738 frv_dwarf_store (reg, stack_offset)); 1739 } 1740 else if (mode == DImode) 1741 { 1742 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE 1743 with a separate save for each register. */ 1744 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg)); 1745 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1); 1746 rtx set1 = frv_dwarf_store (reg1, stack_offset); 1747 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4); 1748 1749 /* Also we cannot use reg+reg addressing. */ 1750 if (GET_CODE (XEXP (mem, 0)) == PLUS 1751 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG 1752 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG) 1753 { 1754 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO); 1755 rtx insn = emit_move_insn (temp, 1756 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0), 1757 XEXP (XEXP (mem, 0), 1))); 1758 mem = gen_rtx_MEM (DImode, temp); 1759 } 1760 1761 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg), 1762 gen_rtx_PARALLEL (VOIDmode, 1763 gen_rtvec (2, set1, set2))); 1764 } 1765 else 1766 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg), 1767 frv_dwarf_store (reg, stack_offset)); 1768 } 1769} 1770 1771/* A function that uses frv_frame_access to transfer a group of registers to 1772 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO 1773 is the stack information generated by frv_stack_info, and REG_SET is the 1774 number of the register set to transfer. */ 1775static void 1776frv_frame_access_multi (frv_frame_accessor_t *accessor, 1777 frv_stack_t *info, 1778 int reg_set) 1779{ 1780 frv_stack_regs_t *regs_info; 1781 int regno; 1782 1783 regs_info = &info->regs[reg_set]; 1784 for (regno = regs_info->first; regno <= regs_info->last; regno++) 1785 if (info->save_p[regno]) 1786 frv_frame_access (accessor, 1787 info->save_p[regno] == REG_SAVE_2WORDS 1788 ? gen_rtx_REG (DImode, regno) 1789 : gen_rtx_REG (SImode, regno), 1790 info->reg_offset[regno]); 1791} 1792 1793/* Save or restore callee-saved registers that are kept outside the frame 1794 header. The function saves the registers if OP is FRV_STORE and restores 1795 them if OP is FRV_LOAD. INFO is the stack information generated by 1796 frv_stack_info. */ 1797static void 1798frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info) 1799{ 1800 frv_frame_accessor_t accessor; 1801 1802 accessor.op = op; 1803 accessor.base = stack_pointer_rtx; 1804 accessor.base_offset = 0; 1805 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR); 1806 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR); 1807 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR); 1808} 1809 1810 1811/* Called after register allocation to add any instructions needed for the 1812 prologue. Using a prologue insn is favored compared to putting all of the 1813 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since 1814 it allows the scheduler to intermix instructions with the saves of 1815 the caller saved registers. In some cases, it might be necessary 1816 to emit a barrier instruction as the last insn to prevent such 1817 scheduling. 1818 1819 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1 1820 so that the debug info generation code can handle them properly. */ 1821void 1822frv_expand_prologue (void) 1823{ 1824 frv_stack_t *info = frv_stack_info (); 1825 rtx sp = stack_pointer_rtx; 1826 rtx fp = frame_pointer_rtx; 1827 frv_frame_accessor_t accessor; 1828 1829 if (TARGET_DEBUG_STACK) 1830 frv_debug_stack (info); 1831 1832 if (info->total_size == 0) 1833 return; 1834 1835 /* We're interested in three areas of the frame here: 1836 1837 A: the register save area 1838 B: the old FP 1839 C: the header after B 1840 1841 If the frame pointer isn't used, we'll have to set up A, B and C 1842 using the stack pointer. If the frame pointer is used, we'll access 1843 them as follows: 1844 1845 A: set up using sp 1846 B: set up using sp or a temporary (see below) 1847 C: set up using fp 1848 1849 We set up B using the stack pointer if the frame is small enough. 1850 Otherwise, it's more efficient to copy the old stack pointer into a 1851 temporary and use that. 1852 1853 Note that it's important to make sure the prologue and epilogue use the 1854 same registers to access A and C, since doing otherwise will confuse 1855 the aliasing code. */ 1856 1857 /* Set up ACCESSOR for accessing region B above. If the frame pointer 1858 isn't used, the same method will serve for C. */ 1859 accessor.op = FRV_STORE; 1860 if (frame_pointer_needed && info->total_size > 2048) 1861 { 1862 rtx insn; 1863 1864 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO); 1865 accessor.base_offset = info->total_size; 1866 insn = emit_insn (gen_movsi (accessor.base, sp)); 1867 } 1868 else 1869 { 1870 accessor.base = stack_pointer_rtx; 1871 accessor.base_offset = 0; 1872 } 1873 1874 /* Allocate the stack space. */ 1875 { 1876 rtx asm_offset = frv_frame_offset_rtx (-info->total_size); 1877 rtx dwarf_offset = GEN_INT (-info->total_size); 1878 1879 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset), 1880 gen_rtx_SET (Pmode, 1881 sp, 1882 gen_rtx_PLUS (Pmode, sp, dwarf_offset))); 1883 } 1884 1885 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET) 1886 and point the new one to that location. */ 1887 if (frame_pointer_needed) 1888 { 1889 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM]; 1890 1891 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is 1892 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack 1893 pointer. */ 1894 rtx asm_src = plus_constant (accessor.base, 1895 fp_offset - accessor.base_offset); 1896 rtx dwarf_src = plus_constant (sp, fp_offset); 1897 1898 /* Store the old frame pointer at (sp + FP_OFFSET). */ 1899 frv_frame_access (&accessor, fp, fp_offset); 1900 1901 /* Set up the new frame pointer. */ 1902 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src), 1903 gen_rtx_SET (VOIDmode, fp, dwarf_src)); 1904 1905 /* Access region C from the frame pointer. */ 1906 accessor.base = fp; 1907 accessor.base_offset = fp_offset; 1908 } 1909 1910 /* Set up region C. */ 1911 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT); 1912 frv_frame_access_multi (&accessor, info, STACK_REGS_LR); 1913 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG); 1914 1915 /* Set up region A. */ 1916 frv_frame_access_standard_regs (FRV_STORE, info); 1917 1918 /* If this is a varargs/stdarg function, issue a blockage to prevent the 1919 scheduler from moving loads before the stores saving the registers. */ 1920 if (info->stdarg_size > 0) 1921 emit_insn (gen_blockage ()); 1922 1923 /* Set up pic register/small data register for this function. */ 1924 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table) 1925 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO), 1926 gen_rtx_REG (Pmode, LR_REGNO), 1927 gen_rtx_REG (SImode, OFFSET_REGNO))); 1928} 1929 1930 1931/* Under frv, all of the work is done via frv_expand_epilogue, but 1932 this function provides a convenient place to do cleanup. */ 1933 1934static void 1935frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED, 1936 HOST_WIDE_INT size ATTRIBUTE_UNUSED) 1937{ 1938 frv_stack_cache = (frv_stack_t *)0; 1939 1940 /* Zap last used registers for conditional execution. */ 1941 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg)); 1942 1943 /* Release the bitmap of created insns. */ 1944 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap); 1945} 1946 1947 1948/* Called after register allocation to add any instructions needed for the 1949 epilogue. Using an epilogue insn is favored compared to putting all of the 1950 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since 1951 it allows the scheduler to intermix instructions with the saves of 1952 the caller saved registers. In some cases, it might be necessary 1953 to emit a barrier instruction as the last insn to prevent such 1954 scheduling. */ 1955 1956void 1957frv_expand_epilogue (bool emit_return) 1958{ 1959 frv_stack_t *info = frv_stack_info (); 1960 rtx fp = frame_pointer_rtx; 1961 rtx sp = stack_pointer_rtx; 1962 rtx return_addr; 1963 int fp_offset; 1964 1965 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM]; 1966 1967 /* Restore the stack pointer to its original value if alloca or the like 1968 is used. */ 1969 if (! current_function_sp_is_unchanging) 1970 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset))); 1971 1972 /* Restore the callee-saved registers that were used in this function. */ 1973 frv_frame_access_standard_regs (FRV_LOAD, info); 1974 1975 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if 1976 no return instruction should be emitted. */ 1977 if (info->save_p[LR_REGNO]) 1978 { 1979 int lr_offset; 1980 rtx mem; 1981 1982 /* Use the same method to access the link register's slot as we did in 1983 the prologue. In other words, use the frame pointer if available, 1984 otherwise use the stack pointer. 1985 1986 LR_OFFSET is the offset of the link register's slot from the start 1987 of the frame and MEM is a memory rtx for it. */ 1988 lr_offset = info->reg_offset[LR_REGNO]; 1989 if (frame_pointer_needed) 1990 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset); 1991 else 1992 mem = frv_frame_mem (Pmode, sp, lr_offset); 1993 1994 /* Load the old link register into a GPR. */ 1995 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO); 1996 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem)); 1997 } 1998 else 1999 return_addr = gen_rtx_REG (Pmode, LR_REGNO); 2000 2001 /* Restore the old frame pointer. Emit a USE afterwards to make sure 2002 the load is preserved. */ 2003 if (frame_pointer_needed) 2004 { 2005 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp))); 2006 emit_use (fp); 2007 } 2008 2009 /* Deallocate the stack frame. */ 2010 if (info->total_size != 0) 2011 { 2012 rtx offset = frv_frame_offset_rtx (info->total_size); 2013 emit_insn (gen_stack_adjust (sp, sp, offset)); 2014 } 2015 2016 /* If this function uses eh_return, add the final stack adjustment now. */ 2017 if (crtl->calls_eh_return) 2018 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX)); 2019 2020 if (emit_return) 2021 emit_jump_insn (gen_epilogue_return (return_addr)); 2022 else 2023 { 2024 rtx lr = return_addr; 2025 2026 if (REGNO (return_addr) != LR_REGNO) 2027 { 2028 lr = gen_rtx_REG (Pmode, LR_REGNO); 2029 emit_move_insn (lr, return_addr); 2030 } 2031 2032 emit_use (lr); 2033 } 2034} 2035 2036 2037/* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */ 2038 2039static void 2040frv_asm_output_mi_thunk (FILE *file, 2041 tree thunk_fndecl ATTRIBUTE_UNUSED, 2042 HOST_WIDE_INT delta, 2043 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, 2044 tree function) 2045{ 2046 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0); 2047 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM]; 2048 const char *name_jmp = reg_names[JUMP_REGNO]; 2049 const char *parallel = (frv_issue_rate () > 1 ? ".p" : ""); 2050 2051 /* Do the add using an addi if possible. */ 2052 if (IN_RANGE_P (delta, -2048, 2047)) 2053 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0); 2054 else 2055 { 2056 const char *const name_add = reg_names[TEMP_REGNO]; 2057 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n", 2058 parallel, delta, name_add); 2059 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n", 2060 delta, name_add); 2061 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0); 2062 } 2063 2064 if (TARGET_FDPIC) 2065 { 2066 const char *name_pic = reg_names[FDPIC_REGNO]; 2067 name_jmp = reg_names[FDPIC_FPTR_REGNO]; 2068 2069 if (flag_pic != 1) 2070 { 2071 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel); 2072 assemble_name (file, name_func); 2073 fprintf (file, "),%s\n", name_jmp); 2074 2075 fprintf (file, "\tsetlo #gotofffuncdesclo("); 2076 assemble_name (file, name_func); 2077 fprintf (file, "),%s\n", name_jmp); 2078 2079 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp); 2080 } 2081 else 2082 { 2083 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic); 2084 assemble_name (file, name_func); 2085 fprintf (file, "\t)), %s\n", name_jmp); 2086 } 2087 } 2088 else if (!flag_pic) 2089 { 2090 fprintf (file, "\tsethi%s #hi(", parallel); 2091 assemble_name (file, name_func); 2092 fprintf (file, "),%s\n", name_jmp); 2093 2094 fprintf (file, "\tsetlo #lo("); 2095 assemble_name (file, name_func); 2096 fprintf (file, "),%s\n", name_jmp); 2097 } 2098 else 2099 { 2100 /* Use JUMP_REGNO as a temporary PIC register. */ 2101 const char *name_lr = reg_names[LR_REGNO]; 2102 const char *name_gppic = name_jmp; 2103 const char *name_tmp = reg_names[TEMP_REGNO]; 2104 2105 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp); 2106 fprintf (file, "\tcall 1f\n"); 2107 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic); 2108 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr); 2109 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp); 2110 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp); 2111 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic); 2112 2113 fprintf (file, "\tsethi%s #gprelhi(", parallel); 2114 assemble_name (file, name_func); 2115 fprintf (file, "),%s\n", name_tmp); 2116 2117 fprintf (file, "\tsetlo #gprello("); 2118 assemble_name (file, name_func); 2119 fprintf (file, "),%s\n", name_tmp); 2120 2121 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp); 2122 } 2123 2124 /* Jump to the function address. */ 2125 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]); 2126} 2127 2128 2129 2130/* On frv, create a frame whenever we need to create stack. */ 2131 2132static bool 2133frv_frame_pointer_required (void) 2134{ 2135 /* If we forgoing the usual linkage requirements, we only need 2136 a frame pointer if the stack pointer might change. */ 2137 if (!TARGET_LINKED_FP) 2138 return !current_function_sp_is_unchanging; 2139 2140 if (! current_function_is_leaf) 2141 return true; 2142 2143 if (get_frame_size () != 0) 2144 return true; 2145 2146 if (cfun->stdarg) 2147 return true; 2148 2149 if (!current_function_sp_is_unchanging) 2150 return true; 2151 2152 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table) 2153 return true; 2154 2155 if (profile_flag) 2156 return true; 2157 2158 if (cfun->machine->frame_needed) 2159 return true; 2160 2161 return false; 2162} 2163 2164 2165/* Worker function for TARGET_CAN_ELIMINATE. */ 2166 2167bool 2168frv_can_eliminate (const int from, const int to) 2169{ 2170 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM 2171 ? ! frame_pointer_needed 2172 : true); 2173} 2174 2175/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the 2176 initial difference between the specified pair of registers. This macro must 2177 be defined if `ELIMINABLE_REGS' is defined. */ 2178 2179/* See frv_stack_info for more details on the frv stack frame. */ 2180 2181int 2182frv_initial_elimination_offset (int from, int to) 2183{ 2184 frv_stack_t *info = frv_stack_info (); 2185 int ret = 0; 2186 2187 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM) 2188 ret = info->total_size - info->pretend_size; 2189 2190 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM) 2191 ret = info->reg_offset[FRAME_POINTER_REGNUM]; 2192 2193 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM) 2194 ret = (info->total_size 2195 - info->reg_offset[FRAME_POINTER_REGNUM] 2196 - info->pretend_size); 2197 2198 else 2199 gcc_unreachable (); 2200 2201 if (TARGET_DEBUG_STACK) 2202 fprintf (stderr, "Eliminate %s to %s by adding %d\n", 2203 reg_names [from], reg_names[to], ret); 2204 2205 return ret; 2206} 2207 2208 2209/* Worker function for TARGET_SETUP_INCOMING_VARARGS. */ 2210 2211static void 2212frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum, 2213 enum machine_mode mode, 2214 tree type ATTRIBUTE_UNUSED, 2215 int *pretend_size, 2216 int second_time) 2217{ 2218 if (TARGET_DEBUG_ARG) 2219 fprintf (stderr, 2220 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n", 2221 *cum, GET_MODE_NAME (mode), *pretend_size, second_time); 2222} 2223 2224 2225/* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */ 2226 2227static rtx 2228frv_expand_builtin_saveregs (void) 2229{ 2230 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS; 2231 2232 if (TARGET_DEBUG_ARG) 2233 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n", 2234 offset); 2235 2236 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset)); 2237} 2238 2239 2240/* Expand __builtin_va_start to do the va_start macro. */ 2241 2242static void 2243frv_expand_builtin_va_start (tree valist, rtx nextarg) 2244{ 2245 tree t; 2246 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS; 2247 2248 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, 2249 GEN_INT (UNITS_PER_WORD * num)); 2250 2251 if (TARGET_DEBUG_ARG) 2252 { 2253 fprintf (stderr, "va_start: args_info = %d, num = %d\n", 2254 crtl->args.info, num); 2255 2256 debug_rtx (nextarg); 2257 } 2258 2259 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, 2260 fold_convert (TREE_TYPE (valist), 2261 make_tree (sizetype, nextarg))); 2262 TREE_SIDE_EFFECTS (t) = 1; 2263 2264 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 2265} 2266 2267 2268/* Expand a block move operation, and return 1 if successful. Return 0 2269 if we should let the compiler generate normal code. 2270 2271 operands[0] is the destination 2272 operands[1] is the source 2273 operands[2] is the length 2274 operands[3] is the alignment */ 2275 2276/* Maximum number of loads to do before doing the stores */ 2277#ifndef MAX_MOVE_REG 2278#define MAX_MOVE_REG 4 2279#endif 2280 2281/* Maximum number of total loads to do. */ 2282#ifndef TOTAL_MOVE_REG 2283#define TOTAL_MOVE_REG 8 2284#endif 2285 2286int 2287frv_expand_block_move (rtx operands[]) 2288{ 2289 rtx orig_dest = operands[0]; 2290 rtx orig_src = operands[1]; 2291 rtx bytes_rtx = operands[2]; 2292 rtx align_rtx = operands[3]; 2293 int constp = (GET_CODE (bytes_rtx) == CONST_INT); 2294 int align; 2295 int bytes; 2296 int offset; 2297 int num_reg; 2298 int i; 2299 rtx src_reg; 2300 rtx dest_reg; 2301 rtx src_addr; 2302 rtx dest_addr; 2303 rtx src_mem; 2304 rtx dest_mem; 2305 rtx tmp_reg; 2306 rtx stores[MAX_MOVE_REG]; 2307 int move_bytes; 2308 enum machine_mode mode; 2309 2310 /* If this is not a fixed size move, just call memcpy. */ 2311 if (! constp) 2312 return FALSE; 2313 2314 /* This should be a fixed size alignment. */ 2315 gcc_assert (GET_CODE (align_rtx) == CONST_INT); 2316 2317 align = INTVAL (align_rtx); 2318 2319 /* Anything to move? */ 2320 bytes = INTVAL (bytes_rtx); 2321 if (bytes <= 0) 2322 return TRUE; 2323 2324 /* Don't support real large moves. */ 2325 if (bytes > TOTAL_MOVE_REG*align) 2326 return FALSE; 2327 2328 /* Move the address into scratch registers. */ 2329 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); 2330 src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); 2331 2332 num_reg = offset = 0; 2333 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) 2334 { 2335 /* Calculate the correct offset for src/dest. */ 2336 if (offset == 0) 2337 { 2338 src_addr = src_reg; 2339 dest_addr = dest_reg; 2340 } 2341 else 2342 { 2343 src_addr = plus_constant (src_reg, offset); 2344 dest_addr = plus_constant (dest_reg, offset); 2345 } 2346 2347 /* Generate the appropriate load and store, saving the stores 2348 for later. */ 2349 if (bytes >= 4 && align >= 4) 2350 mode = SImode; 2351 else if (bytes >= 2 && align >= 2) 2352 mode = HImode; 2353 else 2354 mode = QImode; 2355 2356 move_bytes = GET_MODE_SIZE (mode); 2357 tmp_reg = gen_reg_rtx (mode); 2358 src_mem = change_address (orig_src, mode, src_addr); 2359 dest_mem = change_address (orig_dest, mode, dest_addr); 2360 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem)); 2361 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg); 2362 2363 if (num_reg >= MAX_MOVE_REG) 2364 { 2365 for (i = 0; i < num_reg; i++) 2366 emit_insn (stores[i]); 2367 num_reg = 0; 2368 } 2369 } 2370 2371 for (i = 0; i < num_reg; i++) 2372 emit_insn (stores[i]); 2373 2374 return TRUE; 2375} 2376 2377 2378/* Expand a block clear operation, and return 1 if successful. Return 0 2379 if we should let the compiler generate normal code. 2380 2381 operands[0] is the destination 2382 operands[1] is the length 2383 operands[3] is the alignment */ 2384 2385int 2386frv_expand_block_clear (rtx operands[]) 2387{ 2388 rtx orig_dest = operands[0]; 2389 rtx bytes_rtx = operands[1]; 2390 rtx align_rtx = operands[3]; 2391 int constp = (GET_CODE (bytes_rtx) == CONST_INT); 2392 int align; 2393 int bytes; 2394 int offset; 2395 int num_reg; 2396 rtx dest_reg; 2397 rtx dest_addr; 2398 rtx dest_mem; 2399 int clear_bytes; 2400 enum machine_mode mode; 2401 2402 /* If this is not a fixed size move, just call memcpy. */ 2403 if (! constp) 2404 return FALSE; 2405 2406 /* This should be a fixed size alignment. */ 2407 gcc_assert (GET_CODE (align_rtx) == CONST_INT); 2408 2409 align = INTVAL (align_rtx); 2410 2411 /* Anything to move? */ 2412 bytes = INTVAL (bytes_rtx); 2413 if (bytes <= 0) 2414 return TRUE; 2415 2416 /* Don't support real large clears. */ 2417 if (bytes > TOTAL_MOVE_REG*align) 2418 return FALSE; 2419 2420 /* Move the address into a scratch register. */ 2421 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); 2422 2423 num_reg = offset = 0; 2424 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes)) 2425 { 2426 /* Calculate the correct offset for src/dest. */ 2427 dest_addr = ((offset == 0) 2428 ? dest_reg 2429 : plus_constant (dest_reg, offset)); 2430 2431 /* Generate the appropriate store of gr0. */ 2432 if (bytes >= 4 && align >= 4) 2433 mode = SImode; 2434 else if (bytes >= 2 && align >= 2) 2435 mode = HImode; 2436 else 2437 mode = QImode; 2438 2439 clear_bytes = GET_MODE_SIZE (mode); 2440 dest_mem = change_address (orig_dest, mode, dest_addr); 2441 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx)); 2442 } 2443 2444 return TRUE; 2445} 2446 2447 2448/* The following variable is used to output modifiers of assembler 2449 code of the current output insn. */ 2450 2451static rtx *frv_insn_operands; 2452 2453/* The following function is used to add assembler insn code suffix .p 2454 if it is necessary. */ 2455 2456const char * 2457frv_asm_output_opcode (FILE *f, const char *ptr) 2458{ 2459 int c; 2460 2461 if (frv_insn_packing_flag <= 0) 2462 return ptr; 2463 2464 for (; *ptr && *ptr != ' ' && *ptr != '\t';) 2465 { 2466 c = *ptr++; 2467 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z') 2468 || (*ptr >= 'A' && *ptr <= 'Z'))) 2469 { 2470 int letter = *ptr++; 2471 2472 c = atoi (ptr); 2473 frv_print_operand (f, frv_insn_operands [c], letter); 2474 while ((c = *ptr) >= '0' && c <= '9') 2475 ptr++; 2476 } 2477 else 2478 fputc (c, f); 2479 } 2480 2481 fprintf (f, ".p"); 2482 2483 return ptr; 2484} 2485 2486/* Set up the packing bit for the current output insn. Note that this 2487 function is not called for asm insns. */ 2488 2489void 2490frv_final_prescan_insn (rtx insn, rtx *opvec, 2491 int noperands ATTRIBUTE_UNUSED) 2492{ 2493 if (INSN_P (insn)) 2494 { 2495 if (frv_insn_packing_flag >= 0) 2496 { 2497 frv_insn_operands = opvec; 2498 frv_insn_packing_flag = PACKING_FLAG_P (insn); 2499 } 2500 else if (recog_memoized (insn) >= 0 2501 && get_attr_acc_group (insn) == ACC_GROUP_ODD) 2502 /* Packing optimizations have been disabled, but INSN can only 2503 be issued in M1. Insert an mnop in M0. */ 2504 fprintf (asm_out_file, "\tmnop.p\n"); 2505 } 2506} 2507 2508 2509 2510/* A C expression whose value is RTL representing the address in a stack frame 2511 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is 2512 an RTL expression for the address of the stack frame itself. 2513 2514 If you don't define this macro, the default is to return the value of 2515 FRAMEADDR--that is, the stack frame address is also the address of the stack 2516 word that points to the previous frame. */ 2517 2518/* The default is correct, but we need to make sure the frame gets created. */ 2519rtx 2520frv_dynamic_chain_address (rtx frame) 2521{ 2522 cfun->machine->frame_needed = 1; 2523 return frame; 2524} 2525 2526 2527/* A C expression whose value is RTL representing the value of the return 2528 address for the frame COUNT steps up from the current frame, after the 2529 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame 2530 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is 2531 defined. 2532 2533 The value of the expression must always be the correct address when COUNT is 2534 zero, but may be `NULL_RTX' if there is not way to determine the return 2535 address of other frames. */ 2536 2537rtx 2538frv_return_addr_rtx (int count, rtx frame) 2539{ 2540 if (count != 0) 2541 return const0_rtx; 2542 cfun->machine->frame_needed = 1; 2543 return gen_rtx_MEM (Pmode, plus_constant (frame, 8)); 2544} 2545 2546/* Given a memory reference MEMREF, interpret the referenced memory as 2547 an array of MODE values, and return a reference to the element 2548 specified by INDEX. Assume that any pre-modification implicit in 2549 MEMREF has already happened. 2550 2551 MEMREF must be a legitimate operand for modes larger than SImode. 2552 frv_legitimate_address_p forbids register+register addresses, which 2553 this function cannot handle. */ 2554rtx 2555frv_index_memory (rtx memref, enum machine_mode mode, int index) 2556{ 2557 rtx base = XEXP (memref, 0); 2558 if (GET_CODE (base) == PRE_MODIFY) 2559 base = XEXP (base, 0); 2560 return change_address (memref, mode, 2561 plus_constant (base, index * GET_MODE_SIZE (mode))); 2562} 2563 2564 2565/* Print a memory address as an operand to reference that memory location. */ 2566void 2567frv_print_operand_address (FILE * stream, rtx x) 2568{ 2569 if (GET_CODE (x) == MEM) 2570 x = XEXP (x, 0); 2571 2572 switch (GET_CODE (x)) 2573 { 2574 case REG: 2575 fputs (reg_names [ REGNO (x)], stream); 2576 return; 2577 2578 case CONST_INT: 2579 fprintf (stream, "%ld", (long) INTVAL (x)); 2580 return; 2581 2582 case SYMBOL_REF: 2583 assemble_name (stream, XSTR (x, 0)); 2584 return; 2585 2586 case LABEL_REF: 2587 case CONST: 2588 output_addr_const (stream, x); 2589 return; 2590 2591 case PLUS: 2592 /* Poorly constructed asm statements can trigger this alternative. 2593 See gcc/testsuite/gcc.dg/asm-4.c for an example. */ 2594 frv_print_operand_memory_reference (stream, x, 0); 2595 return; 2596 2597 default: 2598 break; 2599 } 2600 2601 fatal_insn ("bad insn to frv_print_operand_address:", x); 2602} 2603 2604 2605static void 2606frv_print_operand_memory_reference_reg (FILE * stream, rtx x) 2607{ 2608 int regno = true_regnum (x); 2609 if (GPR_P (regno)) 2610 fputs (reg_names[regno], stream); 2611 else 2612 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x); 2613} 2614 2615/* Print a memory reference suitable for the ld/st instructions. */ 2616 2617static void 2618frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset) 2619{ 2620 struct frv_unspec unspec; 2621 rtx x0 = NULL_RTX; 2622 rtx x1 = NULL_RTX; 2623 2624 switch (GET_CODE (x)) 2625 { 2626 case SUBREG: 2627 case REG: 2628 x0 = x; 2629 break; 2630 2631 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */ 2632 x0 = XEXP (x, 0); 2633 x1 = XEXP (XEXP (x, 1), 1); 2634 break; 2635 2636 case CONST_INT: 2637 x1 = x; 2638 break; 2639 2640 case PLUS: 2641 x0 = XEXP (x, 0); 2642 x1 = XEXP (x, 1); 2643 if (GET_CODE (x0) == CONST_INT) 2644 { 2645 x0 = XEXP (x, 1); 2646 x1 = XEXP (x, 0); 2647 } 2648 break; 2649 2650 default: 2651 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x); 2652 break; 2653 2654 } 2655 2656 if (addr_offset) 2657 { 2658 if (!x1) 2659 x1 = const0_rtx; 2660 else if (GET_CODE (x1) != CONST_INT) 2661 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x); 2662 } 2663 2664 fputs ("@(", stream); 2665 if (!x0) 2666 fputs (reg_names[GPR_R0], stream); 2667 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG) 2668 frv_print_operand_memory_reference_reg (stream, x0); 2669 else 2670 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x); 2671 2672 fputs (",", stream); 2673 if (!x1) 2674 fputs (reg_names [GPR_R0], stream); 2675 2676 else 2677 { 2678 switch (GET_CODE (x1)) 2679 { 2680 case SUBREG: 2681 case REG: 2682 frv_print_operand_memory_reference_reg (stream, x1); 2683 break; 2684 2685 case CONST_INT: 2686 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset)); 2687 break; 2688 2689 case CONST: 2690 if (!frv_const_unspec_p (x1, &unspec)) 2691 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1); 2692 frv_output_const_unspec (stream, &unspec); 2693 break; 2694 2695 default: 2696 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x); 2697 } 2698 } 2699 2700 fputs (")", stream); 2701} 2702 2703 2704/* Return 2 for likely branches and 0 for non-likely branches */ 2705 2706#define FRV_JUMP_LIKELY 2 2707#define FRV_JUMP_NOT_LIKELY 0 2708 2709static int 2710frv_print_operand_jump_hint (rtx insn) 2711{ 2712 rtx note; 2713 rtx labelref; 2714 int ret; 2715 HOST_WIDE_INT prob = -1; 2716 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN; 2717 2718 gcc_assert (GET_CODE (insn) == JUMP_INSN); 2719 2720 /* Assume any non-conditional jump is likely. */ 2721 if (! any_condjump_p (insn)) 2722 ret = FRV_JUMP_LIKELY; 2723 2724 else 2725 { 2726 labelref = condjump_label (insn); 2727 if (labelref) 2728 { 2729 rtx label = XEXP (labelref, 0); 2730 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label)) 2731 ? BACKWARD 2732 : FORWARD); 2733 } 2734 2735 note = find_reg_note (insn, REG_BR_PROB, 0); 2736 if (!note) 2737 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY); 2738 2739 else 2740 { 2741 prob = INTVAL (XEXP (note, 0)); 2742 ret = ((prob >= (REG_BR_PROB_BASE / 2)) 2743 ? FRV_JUMP_LIKELY 2744 : FRV_JUMP_NOT_LIKELY); 2745 } 2746 } 2747 2748#if 0 2749 if (TARGET_DEBUG) 2750 { 2751 char *direction; 2752 2753 switch (jump_type) 2754 { 2755 default: 2756 case UNKNOWN: direction = "unknown jump direction"; break; 2757 case BACKWARD: direction = "jump backward"; break; 2758 case FORWARD: direction = "jump forward"; break; 2759 } 2760 2761 fprintf (stderr, 2762 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n", 2763 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)), 2764 (long)INSN_UID (insn), direction, (long)prob, 2765 (long)REG_BR_PROB_BASE, ret); 2766 } 2767#endif 2768 2769 return ret; 2770} 2771 2772 2773/* Return the comparison operator to use for CODE given that the ICC 2774 register is OP0. */ 2775 2776static const char * 2777comparison_string (enum rtx_code code, rtx op0) 2778{ 2779 bool is_nz_p = GET_MODE (op0) == CC_NZmode; 2780 switch (code) 2781 { 2782 default: output_operand_lossage ("bad condition code"); 2783 case EQ: return "eq"; 2784 case NE: return "ne"; 2785 case LT: return is_nz_p ? "n" : "lt"; 2786 case LE: return "le"; 2787 case GT: return "gt"; 2788 case GE: return is_nz_p ? "p" : "ge"; 2789 case LTU: return is_nz_p ? "no" : "c"; 2790 case LEU: return is_nz_p ? "eq" : "ls"; 2791 case GTU: return is_nz_p ? "ne" : "hi"; 2792 case GEU: return is_nz_p ? "ra" : "nc"; 2793 } 2794} 2795 2796/* Print an operand to an assembler instruction. 2797 2798 `%' followed by a letter and a digit says to output an operand in an 2799 alternate fashion. Four letters have standard, built-in meanings described 2800 below. The machine description macro `PRINT_OPERAND' can define additional 2801 letters with nonstandard meanings. 2802 2803 `%cDIGIT' can be used to substitute an operand that is a constant value 2804 without the syntax that normally indicates an immediate operand. 2805 2806 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated 2807 before printing. 2808 2809 `%aDIGIT' can be used to substitute an operand as if it were a memory 2810 reference, with the actual operand treated as the address. This may be 2811 useful when outputting a "load address" instruction, because often the 2812 assembler syntax for such an instruction requires you to write the operand 2813 as if it were a memory reference. 2814 2815 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction. 2816 2817 `%=' outputs a number which is unique to each instruction in the entire 2818 compilation. This is useful for making local labels to be referred to more 2819 than once in a single template that generates multiple assembler 2820 instructions. 2821 2822 `%' followed by a punctuation character specifies a substitution that does 2823 not use an operand. Only one case is standard: `%%' outputs a `%' into the 2824 assembler code. Other nonstandard cases can be defined in the 2825 `PRINT_OPERAND' macro. You must also define which punctuation characters 2826 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */ 2827 2828void 2829frv_print_operand (FILE * file, rtx x, int code) 2830{ 2831 struct frv_unspec unspec; 2832 HOST_WIDE_INT value; 2833 int offset; 2834 2835 if (code != 0 && !ISALPHA (code)) 2836 value = 0; 2837 2838 else if (GET_CODE (x) == CONST_INT) 2839 value = INTVAL (x); 2840 2841 else if (GET_CODE (x) == CONST_DOUBLE) 2842 { 2843 if (GET_MODE (x) == SFmode) 2844 { 2845 REAL_VALUE_TYPE rv; 2846 long l; 2847 2848 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 2849 REAL_VALUE_TO_TARGET_SINGLE (rv, l); 2850 value = l; 2851 } 2852 2853 else if (GET_MODE (x) == VOIDmode) 2854 value = CONST_DOUBLE_LOW (x); 2855 2856 else 2857 fatal_insn ("bad insn in frv_print_operand, bad const_double", x); 2858 } 2859 2860 else 2861 value = 0; 2862 2863 switch (code) 2864 { 2865 2866 case '.': 2867 /* Output r0. */ 2868 fputs (reg_names[GPR_R0], file); 2869 break; 2870 2871 case '#': 2872 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn)); 2873 break; 2874 2875 case '@': 2876 /* Output small data area base register (gr16). */ 2877 fputs (reg_names[SDA_BASE_REG], file); 2878 break; 2879 2880 case '~': 2881 /* Output pic register (gr17). */ 2882 fputs (reg_names[PIC_REGNO], file); 2883 break; 2884 2885 case '*': 2886 /* Output the temporary integer CCR register. */ 2887 fputs (reg_names[ICR_TEMP], file); 2888 break; 2889 2890 case '&': 2891 /* Output the temporary integer CC register. */ 2892 fputs (reg_names[ICC_TEMP], file); 2893 break; 2894 2895 /* case 'a': print an address. */ 2896 2897 case 'C': 2898 /* Print appropriate test for integer branch false operation. */ 2899 fputs (comparison_string (reverse_condition (GET_CODE (x)), 2900 XEXP (x, 0)), file); 2901 break; 2902 2903 case 'c': 2904 /* Print appropriate test for integer branch true operation. */ 2905 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file); 2906 break; 2907 2908 case 'e': 2909 /* Print 1 for a NE and 0 for an EQ to give the final argument 2910 for a conditional instruction. */ 2911 if (GET_CODE (x) == NE) 2912 fputs ("1", file); 2913 2914 else if (GET_CODE (x) == EQ) 2915 fputs ("0", file); 2916 2917 else 2918 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x); 2919 break; 2920 2921 case 'F': 2922 /* Print appropriate test for floating point branch false operation. */ 2923 switch (GET_CODE (x)) 2924 { 2925 default: 2926 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x); 2927 2928 case EQ: fputs ("ne", file); break; 2929 case NE: fputs ("eq", file); break; 2930 case LT: fputs ("uge", file); break; 2931 case LE: fputs ("ug", file); break; 2932 case GT: fputs ("ule", file); break; 2933 case GE: fputs ("ul", file); break; 2934 } 2935 break; 2936 2937 case 'f': 2938 /* Print appropriate test for floating point branch true operation. */ 2939 switch (GET_CODE (x)) 2940 { 2941 default: 2942 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x); 2943 2944 case EQ: fputs ("eq", file); break; 2945 case NE: fputs ("ne", file); break; 2946 case LT: fputs ("lt", file); break; 2947 case LE: fputs ("le", file); break; 2948 case GT: fputs ("gt", file); break; 2949 case GE: fputs ("ge", file); break; 2950 } 2951 break; 2952 2953 case 'g': 2954 /* Print appropriate GOT function. */ 2955 if (GET_CODE (x) != CONST_INT) 2956 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x); 2957 fputs (unspec_got_name (INTVAL (x)), file); 2958 break; 2959 2960 case 'I': 2961 /* Print 'i' if the operand is a constant, or is a memory reference that 2962 adds a constant. */ 2963 if (GET_CODE (x) == MEM) 2964 x = ((GET_CODE (XEXP (x, 0)) == PLUS) 2965 ? XEXP (XEXP (x, 0), 1) 2966 : XEXP (x, 0)); 2967 else if (GET_CODE (x) == PLUS) 2968 x = XEXP (x, 1); 2969 2970 switch (GET_CODE (x)) 2971 { 2972 default: 2973 break; 2974 2975 case CONST_INT: 2976 case SYMBOL_REF: 2977 case CONST: 2978 fputs ("i", file); 2979 break; 2980 } 2981 break; 2982 2983 case 'i': 2984 /* For jump instructions, print 'i' if the operand is a constant or 2985 is an expression that adds a constant. */ 2986 if (GET_CODE (x) == CONST_INT) 2987 fputs ("i", file); 2988 2989 else 2990 { 2991 if (GET_CODE (x) == CONST_INT 2992 || (GET_CODE (x) == PLUS 2993 && (GET_CODE (XEXP (x, 1)) == CONST_INT 2994 || GET_CODE (XEXP (x, 0)) == CONST_INT))) 2995 fputs ("i", file); 2996 } 2997 break; 2998 2999 case 'L': 3000 /* Print the lower register of a double word register pair */ 3001 if (GET_CODE (x) == REG) 3002 fputs (reg_names[ REGNO (x)+1 ], file); 3003 else 3004 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x); 3005 break; 3006 3007 /* case 'l': print a LABEL_REF. */ 3008 3009 case 'M': 3010 case 'N': 3011 /* Print a memory reference for ld/st/jmp, %N prints a memory reference 3012 for the second word of double memory operations. */ 3013 offset = (code == 'M') ? 0 : UNITS_PER_WORD; 3014 switch (GET_CODE (x)) 3015 { 3016 default: 3017 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x); 3018 3019 case MEM: 3020 frv_print_operand_memory_reference (file, XEXP (x, 0), offset); 3021 break; 3022 3023 case REG: 3024 case SUBREG: 3025 case CONST_INT: 3026 case PLUS: 3027 case SYMBOL_REF: 3028 frv_print_operand_memory_reference (file, x, offset); 3029 break; 3030 } 3031 break; 3032 3033 case 'O': 3034 /* Print the opcode of a command. */ 3035 switch (GET_CODE (x)) 3036 { 3037 default: 3038 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x); 3039 3040 case PLUS: fputs ("add", file); break; 3041 case MINUS: fputs ("sub", file); break; 3042 case AND: fputs ("and", file); break; 3043 case IOR: fputs ("or", file); break; 3044 case XOR: fputs ("xor", file); break; 3045 case ASHIFT: fputs ("sll", file); break; 3046 case ASHIFTRT: fputs ("sra", file); break; 3047 case LSHIFTRT: fputs ("srl", file); break; 3048 } 3049 break; 3050 3051 /* case 'n': negate and print a constant int. */ 3052 3053 case 'P': 3054 /* Print PIC label using operand as the number. */ 3055 if (GET_CODE (x) != CONST_INT) 3056 fatal_insn ("bad insn to frv_print_operand, P modifier:", x); 3057 3058 fprintf (file, ".LCF%ld", (long)INTVAL (x)); 3059 break; 3060 3061 case 'U': 3062 /* Print 'u' if the operand is a update load/store. */ 3063 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY) 3064 fputs ("u", file); 3065 break; 3066 3067 case 'z': 3068 /* If value is 0, print gr0, otherwise it must be a register. */ 3069 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0) 3070 fputs (reg_names[GPR_R0], file); 3071 3072 else if (GET_CODE (x) == REG) 3073 fputs (reg_names [REGNO (x)], file); 3074 3075 else 3076 fatal_insn ("bad insn in frv_print_operand, z case", x); 3077 break; 3078 3079 case 'x': 3080 /* Print constant in hex. */ 3081 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) 3082 { 3083 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value); 3084 break; 3085 } 3086 3087 /* Fall through. */ 3088 3089 case '\0': 3090 if (GET_CODE (x) == REG) 3091 fputs (reg_names [REGNO (x)], file); 3092 3093 else if (GET_CODE (x) == CONST_INT 3094 || GET_CODE (x) == CONST_DOUBLE) 3095 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value); 3096 3097 else if (frv_const_unspec_p (x, &unspec)) 3098 frv_output_const_unspec (file, &unspec); 3099 3100 else if (GET_CODE (x) == MEM) 3101 frv_print_operand_address (file, XEXP (x, 0)); 3102 3103 else if (CONSTANT_ADDRESS_P (x)) 3104 frv_print_operand_address (file, x); 3105 3106 else 3107 fatal_insn ("bad insn in frv_print_operand, 0 case", x); 3108 3109 break; 3110 3111 default: 3112 fatal_insn ("frv_print_operand: unknown code", x); 3113 break; 3114 } 3115 3116 return; 3117} 3118 3119 3120/* A C statement (sans semicolon) for initializing the variable CUM for the 3121 state at the beginning of the argument list. The variable has type 3122 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type 3123 of the function which will receive the args, or 0 if the args are to a 3124 compiler support library function. The value of INDIRECT is nonzero when 3125 processing an indirect call, for example a call through a function pointer. 3126 The value of INDIRECT is zero for a call to an explicitly named function, a 3127 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find 3128 arguments for the function being compiled. 3129 3130 When processing a call to a compiler support library function, LIBNAME 3131 identifies which one. It is a `symbol_ref' rtx which contains the name of 3132 the function, as a string. LIBNAME is 0 when an ordinary C function call is 3133 being processed. Thus, each time this macro is called, either LIBNAME or 3134 FNTYPE is nonzero, but never both of them at once. */ 3135 3136void 3137frv_init_cumulative_args (CUMULATIVE_ARGS *cum, 3138 tree fntype, 3139 rtx libname, 3140 tree fndecl, 3141 int incoming) 3142{ 3143 *cum = FIRST_ARG_REGNUM; 3144 3145 if (TARGET_DEBUG_ARG) 3146 { 3147 fprintf (stderr, "\ninit_cumulative_args:"); 3148 if (!fndecl && fntype) 3149 fputs (" indirect", stderr); 3150 3151 if (incoming) 3152 fputs (" incoming", stderr); 3153 3154 if (fntype) 3155 { 3156 tree ret_type = TREE_TYPE (fntype); 3157 fprintf (stderr, " return=%s,", 3158 tree_code_name[ (int)TREE_CODE (ret_type) ]); 3159 } 3160 3161 if (libname && GET_CODE (libname) == SYMBOL_REF) 3162 fprintf (stderr, " libname=%s", XSTR (libname, 0)); 3163 3164 if (cfun->returns_struct) 3165 fprintf (stderr, " return-struct"); 3166 3167 putc ('\n', stderr); 3168 } 3169} 3170 3171 3172/* Return true if we should pass an argument on the stack rather than 3173 in registers. */ 3174 3175static bool 3176frv_must_pass_in_stack (enum machine_mode mode, const_tree type) 3177{ 3178 if (mode == BLKmode) 3179 return true; 3180 if (type == NULL) 3181 return false; 3182 return AGGREGATE_TYPE_P (type); 3183} 3184 3185/* If defined, a C expression that gives the alignment boundary, in bits, of an 3186 argument with the specified mode and type. If it is not defined, 3187 `PARM_BOUNDARY' is used for all arguments. */ 3188 3189int 3190frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED, 3191 tree type ATTRIBUTE_UNUSED) 3192{ 3193 return BITS_PER_WORD; 3194} 3195 3196rtx 3197frv_function_arg (CUMULATIVE_ARGS *cum, 3198 enum machine_mode mode, 3199 tree type ATTRIBUTE_UNUSED, 3200 int named, 3201 int incoming ATTRIBUTE_UNUSED) 3202{ 3203 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; 3204 int arg_num = *cum; 3205 rtx ret; 3206 const char *debstr; 3207 3208 /* Return a marker for use in the call instruction. */ 3209 if (xmode == VOIDmode) 3210 { 3211 ret = const0_rtx; 3212 debstr = "<0>"; 3213 } 3214 3215 else if (arg_num <= LAST_ARG_REGNUM) 3216 { 3217 ret = gen_rtx_REG (xmode, arg_num); 3218 debstr = reg_names[arg_num]; 3219 } 3220 3221 else 3222 { 3223 ret = NULL_RTX; 3224 debstr = "memory"; 3225 } 3226 3227 if (TARGET_DEBUG_ARG) 3228 fprintf (stderr, 3229 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n", 3230 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr); 3231 3232 return ret; 3233} 3234 3235 3236/* A C statement (sans semicolon) to update the summarizer variable CUM to 3237 advance past an argument in the argument list. The values MODE, TYPE and 3238 NAMED describe that argument. Once this is done, the variable CUM is 3239 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc. 3240 3241 This macro need not do anything if the argument in question was passed on 3242 the stack. The compiler knows how to track the amount of stack space used 3243 for arguments without any special help. */ 3244 3245void 3246frv_function_arg_advance (CUMULATIVE_ARGS *cum, 3247 enum machine_mode mode, 3248 tree type ATTRIBUTE_UNUSED, 3249 int named) 3250{ 3251 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; 3252 int bytes = GET_MODE_SIZE (xmode); 3253 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 3254 int arg_num = *cum; 3255 3256 *cum = arg_num + words; 3257 3258 if (TARGET_DEBUG_ARG) 3259 fprintf (stderr, 3260 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n", 3261 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD); 3262} 3263 3264 3265/* A C expression for the number of words, at the beginning of an argument, 3266 must be put in registers. The value must be zero for arguments that are 3267 passed entirely in registers or that are entirely pushed on the stack. 3268 3269 On some machines, certain arguments must be passed partially in registers 3270 and partially in memory. On these machines, typically the first N words of 3271 arguments are passed in registers, and the rest on the stack. If a 3272 multi-word argument (a `double' or a structure) crosses that boundary, its 3273 first few words must be passed in registers and the rest must be pushed. 3274 This macro tells the compiler when this occurs, and how many of the words 3275 should go in registers. 3276 3277 `FUNCTION_ARG' for these arguments should return the first register to be 3278 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for 3279 the called function. */ 3280 3281static int 3282frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, 3283 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED) 3284{ 3285 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; 3286 int bytes = GET_MODE_SIZE (xmode); 3287 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 3288 int arg_num = *cum; 3289 int ret; 3290 3291 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1) 3292 ? LAST_ARG_REGNUM - arg_num + 1 3293 : 0); 3294 ret *= UNITS_PER_WORD; 3295 3296 if (TARGET_DEBUG_ARG && ret) 3297 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret); 3298 3299 return ret; 3300} 3301 3302 3303/* Implements TARGET_FUNCTION_VALUE. */ 3304 3305static rtx 3306frv_function_value (const_tree valtype, 3307 const_tree fn_decl_or_type ATTRIBUTE_UNUSED, 3308 bool outgoing ATTRIBUTE_UNUSED) 3309{ 3310 return gen_rtx_REG (TYPE_MODE (valtype), RETURN_VALUE_REGNUM); 3311} 3312 3313 3314/* Implements TARGET_LIBCALL_VALUE. */ 3315 3316static rtx 3317frv_libcall_value (enum machine_mode mode, 3318 const_rtx fun ATTRIBUTE_UNUSED) 3319{ 3320 return gen_rtx_REG (mode, RETURN_VALUE_REGNUM); 3321} 3322 3323 3324/* Implements FUNCTION_VALUE_REGNO_P. */ 3325 3326bool 3327frv_function_value_regno_p (const unsigned int regno) 3328{ 3329 return (regno == RETURN_VALUE_REGNUM); 3330} 3331 3332/* Return true if a register is ok to use as a base or index register. */ 3333 3334static FRV_INLINE int 3335frv_regno_ok_for_base_p (int regno, int strict_p) 3336{ 3337 if (GPR_P (regno)) 3338 return TRUE; 3339 3340 if (strict_p) 3341 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno])); 3342 3343 if (regno == ARG_POINTER_REGNUM) 3344 return TRUE; 3345 3346 return (regno >= FIRST_PSEUDO_REGISTER); 3347} 3348 3349 3350/* A C compound statement with a conditional `goto LABEL;' executed if X (an 3351 RTX) is a legitimate memory address on the target machine for a memory 3352 operand of mode MODE. 3353 3354 It usually pays to define several simpler macros to serve as subroutines for 3355 this one. Otherwise it may be too complicated to understand. 3356 3357 This macro must exist in two variants: a strict variant and a non-strict 3358 one. The strict variant is used in the reload pass. It must be defined so 3359 that any pseudo-register that has not been allocated a hard register is 3360 considered a memory reference. In contexts where some kind of register is 3361 required, a pseudo-register with no hard register must be rejected. 3362 3363 The non-strict variant is used in other passes. It must be defined to 3364 accept all pseudo-registers in every context where some kind of register is 3365 required. 3366 3367 Compiler source files that want to use the strict variant of this macro 3368 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT' 3369 conditional to define the strict variant in that case and the non-strict 3370 variant otherwise. 3371 3372 Normally, constant addresses which are the sum of a `symbol_ref' and an 3373 integer are stored inside a `const' RTX to mark them as constant. 3374 Therefore, there is no need to recognize such sums specifically as 3375 legitimate addresses. Normally you would simply recognize any `const' as 3376 legitimate. 3377 3378 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that 3379 are not marked with `const'. It assumes that a naked `plus' indicates 3380 indexing. If so, then you *must* reject such naked constant sums as 3381 illegitimate addresses, so that none of them will be given to 3382 `PRINT_OPERAND_ADDRESS'. */ 3383 3384int 3385frv_legitimate_address_p_1 (enum machine_mode mode, 3386 rtx x, 3387 int strict_p, 3388 int condexec_p, 3389 int allow_double_reg_p) 3390{ 3391 rtx x0, x1; 3392 int ret = 0; 3393 HOST_WIDE_INT value; 3394 unsigned regno0; 3395 3396 if (FRV_SYMBOL_REF_TLS_P (x)) 3397 return 0; 3398 3399 switch (GET_CODE (x)) 3400 { 3401 default: 3402 break; 3403 3404 case SUBREG: 3405 x = SUBREG_REG (x); 3406 if (GET_CODE (x) != REG) 3407 break; 3408 3409 /* Fall through. */ 3410 3411 case REG: 3412 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p); 3413 break; 3414 3415 case PRE_MODIFY: 3416 x0 = XEXP (x, 0); 3417 x1 = XEXP (x, 1); 3418 if (GET_CODE (x0) != REG 3419 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p) 3420 || GET_CODE (x1) != PLUS 3421 || ! rtx_equal_p (x0, XEXP (x1, 0)) 3422 || GET_CODE (XEXP (x1, 1)) != REG 3423 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p)) 3424 break; 3425 3426 ret = 1; 3427 break; 3428 3429 case CONST_INT: 3430 /* 12-bit immediate */ 3431 if (condexec_p) 3432 ret = FALSE; 3433 else 3434 { 3435 ret = IN_RANGE_P (INTVAL (x), -2048, 2047); 3436 3437 /* If we can't use load/store double operations, make sure we can 3438 address the second word. */ 3439 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) 3440 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1, 3441 -2048, 2047); 3442 } 3443 break; 3444 3445 case PLUS: 3446 x0 = XEXP (x, 0); 3447 x1 = XEXP (x, 1); 3448 3449 if (GET_CODE (x0) == SUBREG) 3450 x0 = SUBREG_REG (x0); 3451 3452 if (GET_CODE (x0) != REG) 3453 break; 3454 3455 regno0 = REGNO (x0); 3456 if (!frv_regno_ok_for_base_p (regno0, strict_p)) 3457 break; 3458 3459 switch (GET_CODE (x1)) 3460 { 3461 default: 3462 break; 3463 3464 case SUBREG: 3465 x1 = SUBREG_REG (x1); 3466 if (GET_CODE (x1) != REG) 3467 break; 3468 3469 /* Fall through. */ 3470 3471 case REG: 3472 /* Do not allow reg+reg addressing for modes > 1 word if we 3473 can't depend on having move double instructions. */ 3474 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD) 3475 ret = FALSE; 3476 else 3477 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p); 3478 break; 3479 3480 case CONST_INT: 3481 /* 12-bit immediate */ 3482 if (condexec_p) 3483 ret = FALSE; 3484 else 3485 { 3486 value = INTVAL (x1); 3487 ret = IN_RANGE_P (value, -2048, 2047); 3488 3489 /* If we can't use load/store double operations, make sure we can 3490 address the second word. */ 3491 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD) 3492 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047); 3493 } 3494 break; 3495 3496 case CONST: 3497 if (!condexec_p && got12_operand (x1, VOIDmode)) 3498 ret = TRUE; 3499 break; 3500 3501 } 3502 break; 3503 } 3504 3505 if (TARGET_DEBUG_ADDR) 3506 { 3507 fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n", 3508 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ", 3509 (condexec_p) ? ", inside conditional code" : ""); 3510 debug_rtx (x); 3511 } 3512 3513 return ret; 3514} 3515 3516bool 3517frv_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p) 3518{ 3519 return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE); 3520} 3521 3522/* Given an ADDR, generate code to inline the PLT. */ 3523static rtx 3524gen_inlined_tls_plt (rtx addr) 3525{ 3526 rtx retval, dest; 3527 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG); 3528 3529 3530 dest = gen_reg_rtx (DImode); 3531 3532 if (flag_pic == 1) 3533 { 3534 /* 3535 -fpic version: 3536 3537 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8 3538 calll #gettlsoff(ADDR)@(gr8, gr0) 3539 */ 3540 emit_insn (gen_tls_lddi (dest, addr, picreg)); 3541 } 3542 else 3543 { 3544 /* 3545 -fPIC version: 3546 3547 sethi.p #gottlsdeschi(ADDR), gr8 3548 setlo #gottlsdesclo(ADDR), gr8 3549 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8 3550 calll #gettlsoff(ADDR)@(gr8, gr0) 3551 */ 3552 rtx reguse = gen_reg_rtx (Pmode); 3553 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI))); 3554 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr)); 3555 } 3556 3557 retval = gen_reg_rtx (Pmode); 3558 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg)); 3559 return retval; 3560} 3561 3562/* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns 3563 the destination address. */ 3564static rtx 3565gen_tlsmoff (rtx addr, rtx reg) 3566{ 3567 rtx dest = gen_reg_rtx (Pmode); 3568 3569 if (TARGET_BIG_TLS) 3570 { 3571 /* sethi.p #tlsmoffhi(x), grA 3572 setlo #tlsmofflo(x), grA 3573 */ 3574 dest = gen_reg_rtx (Pmode); 3575 emit_insn (gen_tlsoff_hilo (dest, addr, 3576 GEN_INT (R_FRV_TLSMOFFHI))); 3577 dest = gen_rtx_PLUS (Pmode, dest, reg); 3578 } 3579 else 3580 { 3581 /* addi grB, #tlsmoff12(x), grC 3582 -or- 3583 ld/st @(grB, #tlsmoff12(x)), grC 3584 */ 3585 dest = gen_reg_rtx (Pmode); 3586 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg, 3587 GEN_INT (R_FRV_TLSMOFF12))); 3588 } 3589 return dest; 3590} 3591 3592/* Generate code for a TLS address. */ 3593static rtx 3594frv_legitimize_tls_address (rtx addr, enum tls_model model) 3595{ 3596 rtx dest, tp = gen_rtx_REG (Pmode, 29); 3597 rtx picreg = get_hard_reg_initial_val (Pmode, 15); 3598 3599 switch (model) 3600 { 3601 case TLS_MODEL_INITIAL_EXEC: 3602 if (flag_pic == 1) 3603 { 3604 /* -fpic version. 3605 ldi @(gr15, #gottlsoff12(x)), gr5 3606 */ 3607 dest = gen_reg_rtx (Pmode); 3608 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg)); 3609 dest = gen_rtx_PLUS (Pmode, tp, dest); 3610 } 3611 else 3612 { 3613 /* -fPIC or anything else. 3614 3615 sethi.p #gottlsoffhi(x), gr14 3616 setlo #gottlsofflo(x), gr14 3617 ld #tlsoff(x)@(gr15, gr14), gr9 3618 */ 3619 rtx tmp = gen_reg_rtx (Pmode); 3620 dest = gen_reg_rtx (Pmode); 3621 emit_insn (gen_tlsoff_hilo (tmp, addr, 3622 GEN_INT (R_FRV_GOTTLSOFF_HI))); 3623 3624 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr)); 3625 dest = gen_rtx_PLUS (Pmode, tp, dest); 3626 } 3627 break; 3628 case TLS_MODEL_LOCAL_DYNAMIC: 3629 { 3630 rtx reg, retval; 3631 3632 if (TARGET_INLINE_PLT) 3633 retval = gen_inlined_tls_plt (GEN_INT (0)); 3634 else 3635 { 3636 /* call #gettlsoff(0) */ 3637 retval = gen_reg_rtx (Pmode); 3638 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg)); 3639 } 3640 3641 reg = gen_reg_rtx (Pmode); 3642 emit_insn (gen_rtx_SET (VOIDmode, reg, 3643 gen_rtx_PLUS (Pmode, 3644 retval, tp))); 3645 3646 dest = gen_tlsmoff (addr, reg); 3647 3648 /* 3649 dest = gen_reg_rtx (Pmode); 3650 emit_insn (gen_tlsoff_hilo (dest, addr, 3651 GEN_INT (R_FRV_TLSMOFFHI))); 3652 dest = gen_rtx_PLUS (Pmode, dest, reg); 3653 */ 3654 break; 3655 } 3656 case TLS_MODEL_LOCAL_EXEC: 3657 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29)); 3658 break; 3659 case TLS_MODEL_GLOBAL_DYNAMIC: 3660 { 3661 rtx retval; 3662 3663 if (TARGET_INLINE_PLT) 3664 retval = gen_inlined_tls_plt (addr); 3665 else 3666 { 3667 /* call #gettlsoff(x) */ 3668 retval = gen_reg_rtx (Pmode); 3669 emit_insn (gen_call_gettlsoff (retval, addr, picreg)); 3670 } 3671 dest = gen_rtx_PLUS (Pmode, retval, tp); 3672 break; 3673 } 3674 default: 3675 gcc_unreachable (); 3676 } 3677 3678 return dest; 3679} 3680 3681rtx 3682frv_legitimize_address (rtx x, 3683 rtx oldx ATTRIBUTE_UNUSED, 3684 enum machine_mode mode ATTRIBUTE_UNUSED) 3685{ 3686 if (GET_CODE (x) == SYMBOL_REF) 3687 { 3688 enum tls_model model = SYMBOL_REF_TLS_MODEL (x); 3689 if (model != 0) 3690 return frv_legitimize_tls_address (x, model); 3691 } 3692 3693 return x; 3694} 3695 3696/* Test whether a local function descriptor is canonical, i.e., 3697 whether we can use FUNCDESC_GOTOFF to compute the address of the 3698 function. */ 3699 3700static bool 3701frv_local_funcdesc_p (rtx fnx) 3702{ 3703 tree fn; 3704 enum symbol_visibility vis; 3705 bool ret; 3706 3707 if (! SYMBOL_REF_LOCAL_P (fnx)) 3708 return FALSE; 3709 3710 fn = SYMBOL_REF_DECL (fnx); 3711 3712 if (! fn) 3713 return FALSE; 3714 3715 vis = DECL_VISIBILITY (fn); 3716 3717 if (vis == VISIBILITY_PROTECTED) 3718 /* Private function descriptors for protected functions are not 3719 canonical. Temporarily change the visibility to global. */ 3720 vis = VISIBILITY_DEFAULT; 3721 else if (flag_shlib) 3722 /* If we're already compiling for a shared library (that, unlike 3723 executables, can't assume that the existence of a definition 3724 implies local binding), we can skip the re-testing. */ 3725 return TRUE; 3726 3727 ret = default_binds_local_p_1 (fn, flag_pic); 3728 3729 DECL_VISIBILITY (fn) = vis; 3730 3731 return ret; 3732} 3733 3734/* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC 3735 register. */ 3736 3737rtx 3738frv_gen_GPsym2reg (rtx dest, rtx src) 3739{ 3740 tree gp = get_identifier ("_gp"); 3741 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp)); 3742 3743 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12)); 3744} 3745 3746static const char * 3747unspec_got_name (int i) 3748{ 3749 switch (i) 3750 { 3751 case R_FRV_GOT12: return "got12"; 3752 case R_FRV_GOTHI: return "gothi"; 3753 case R_FRV_GOTLO: return "gotlo"; 3754 case R_FRV_FUNCDESC: return "funcdesc"; 3755 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12"; 3756 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi"; 3757 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo"; 3758 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue"; 3759 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12"; 3760 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi"; 3761 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo"; 3762 case R_FRV_GOTOFF12: return "gotoff12"; 3763 case R_FRV_GOTOFFHI: return "gotoffhi"; 3764 case R_FRV_GOTOFFLO: return "gotofflo"; 3765 case R_FRV_GPREL12: return "gprel12"; 3766 case R_FRV_GPRELHI: return "gprelhi"; 3767 case R_FRV_GPRELLO: return "gprello"; 3768 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi"; 3769 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo"; 3770 case R_FRV_TLSMOFFHI: return "tlsmoffhi"; 3771 case R_FRV_TLSMOFFLO: return "tlsmofflo"; 3772 case R_FRV_TLSMOFF12: return "tlsmoff12"; 3773 case R_FRV_TLSDESCHI: return "tlsdeschi"; 3774 case R_FRV_TLSDESCLO: return "tlsdesclo"; 3775 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi"; 3776 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo"; 3777 default: gcc_unreachable (); 3778 } 3779} 3780 3781/* Write the assembler syntax for UNSPEC to STREAM. Note that any offset 3782 is added inside the relocation operator. */ 3783 3784static void 3785frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec) 3786{ 3787 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc)); 3788 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset)); 3789 fputs (")", stream); 3790} 3791 3792/* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo) 3793 or #gotoff12(foo) for some small data symbol foo. If so, return foo, 3794 otherwise return ORIG_X. */ 3795 3796rtx 3797frv_find_base_term (rtx x) 3798{ 3799 struct frv_unspec unspec; 3800 3801 if (frv_const_unspec_p (x, &unspec) 3802 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc)) 3803 return plus_constant (unspec.symbol, unspec.offset); 3804 3805 return x; 3806} 3807 3808/* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if 3809 the operand is used by a predicated instruction. */ 3810 3811int 3812frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p) 3813{ 3814 return ((GET_MODE (op) == mode || mode == VOIDmode) 3815 && GET_CODE (op) == MEM 3816 && frv_legitimate_address_p_1 (mode, XEXP (op, 0), 3817 reload_completed, condexec_p, FALSE)); 3818} 3819 3820void 3821frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall) 3822{ 3823 rtx lr = gen_rtx_REG (Pmode, LR_REGNO); 3824 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG); 3825 rtx c, rvrtx=0; 3826 rtx addr; 3827 3828 if (ret_value) 3829 { 3830 rvrtx = operands[0]; 3831 operands ++; 3832 } 3833 3834 addr = XEXP (operands[0], 0); 3835 3836 /* Inline PLTs if we're optimizing for speed. We'd like to inline 3837 any calls that would involve a PLT, but can't tell, since we 3838 don't know whether an extern function is going to be provided by 3839 a separate translation unit or imported from a separate module. 3840 When compiling for shared libraries, if the function has default 3841 visibility, we assume it's overridable, so we inline the PLT, but 3842 for executables, we don't really have a way to make a good 3843 decision: a function is as likely to be imported from a shared 3844 library as it is to be defined in the executable itself. We 3845 assume executables will get global functions defined locally, 3846 whereas shared libraries will have them potentially overridden, 3847 so we only inline PLTs when compiling for shared libraries. 3848 3849 In order to mark a function as local to a shared library, any 3850 non-default visibility attribute suffices. Unfortunately, 3851 there's no simple way to tag a function declaration as ``in a 3852 different module'', which we could then use to trigger PLT 3853 inlining on executables. There's -minline-plt, but it affects 3854 all external functions, so one would have to also mark function 3855 declarations available in the same module with non-default 3856 visibility, which is advantageous in itself. */ 3857 if (GET_CODE (addr) == SYMBOL_REF 3858 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT) 3859 || sibcall)) 3860 { 3861 rtx x, dest; 3862 dest = gen_reg_rtx (SImode); 3863 if (flag_pic != 1) 3864 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG, 3865 GEN_INT (R_FRV_FUNCDESC_GOTOFF12)); 3866 else 3867 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG, 3868 GEN_INT (R_FRV_FUNCDESC_GOTOFF12)); 3869 emit_insn (x); 3870 crtl->uses_pic_offset_table = TRUE; 3871 addr = dest; 3872 } 3873 else if (GET_CODE (addr) == SYMBOL_REF) 3874 { 3875 /* These are always either local, or handled through a local 3876 PLT. */ 3877 if (ret_value) 3878 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1], 3879 operands[2], picreg, lr); 3880 else 3881 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr); 3882 emit_call_insn (c); 3883 return; 3884 } 3885 else if (! ldd_address_operand (addr, Pmode)) 3886 addr = force_reg (Pmode, addr); 3887 3888 picreg = gen_reg_rtx (DImode); 3889 emit_insn (gen_movdi_ldd (picreg, addr)); 3890 3891 if (sibcall && ret_value) 3892 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx); 3893 else if (sibcall) 3894 c = gen_sibcall_fdpicdi (picreg, const0_rtx); 3895 else if (ret_value) 3896 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr); 3897 else 3898 c = gen_call_fdpicdi (picreg, const0_rtx, lr); 3899 emit_call_insn (c); 3900} 3901 3902/* Look for a SYMBOL_REF of a function in an rtx. We always want to 3903 process these separately from any offsets, such that we add any 3904 offsets to the function descriptor (the actual pointer), not to the 3905 function address. */ 3906 3907static bool 3908frv_function_symbol_referenced_p (rtx x) 3909{ 3910 const char *format; 3911 int length; 3912 int j; 3913 3914 if (GET_CODE (x) == SYMBOL_REF) 3915 return SYMBOL_REF_FUNCTION_P (x); 3916 3917 length = GET_RTX_LENGTH (GET_CODE (x)); 3918 format = GET_RTX_FORMAT (GET_CODE (x)); 3919 3920 for (j = 0; j < length; ++j) 3921 { 3922 switch (format[j]) 3923 { 3924 case 'e': 3925 if (frv_function_symbol_referenced_p (XEXP (x, j))) 3926 return TRUE; 3927 break; 3928 3929 case 'V': 3930 case 'E': 3931 if (XVEC (x, j) != 0) 3932 { 3933 int k; 3934 for (k = 0; k < XVECLEN (x, j); ++k) 3935 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k))) 3936 return TRUE; 3937 } 3938 break; 3939 3940 default: 3941 /* Nothing to do. */ 3942 break; 3943 } 3944 } 3945 3946 return FALSE; 3947} 3948 3949/* Return true if the memory operand is one that can be conditionally 3950 executed. */ 3951 3952int 3953condexec_memory_operand (rtx op, enum machine_mode mode) 3954{ 3955 enum machine_mode op_mode = GET_MODE (op); 3956 rtx addr; 3957 3958 if (mode != VOIDmode && op_mode != mode) 3959 return FALSE; 3960 3961 switch (op_mode) 3962 { 3963 default: 3964 return FALSE; 3965 3966 case QImode: 3967 case HImode: 3968 case SImode: 3969 case SFmode: 3970 break; 3971 } 3972 3973 if (GET_CODE (op) != MEM) 3974 return FALSE; 3975 3976 addr = XEXP (op, 0); 3977 return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE); 3978} 3979 3980/* Return true if the bare return instruction can be used outside of the 3981 epilog code. For frv, we only do it if there was no stack allocation. */ 3982 3983int 3984direct_return_p (void) 3985{ 3986 frv_stack_t *info; 3987 3988 if (!reload_completed) 3989 return FALSE; 3990 3991 info = frv_stack_info (); 3992 return (info->total_size == 0); 3993} 3994 3995 3996void 3997frv_emit_move (enum machine_mode mode, rtx dest, rtx src) 3998{ 3999 if (GET_CODE (src) == SYMBOL_REF) 4000 { 4001 enum tls_model model = SYMBOL_REF_TLS_MODEL (src); 4002 if (model != 0) 4003 src = frv_legitimize_tls_address (src, model); 4004 } 4005 4006 switch (mode) 4007 { 4008 case SImode: 4009 if (frv_emit_movsi (dest, src)) 4010 return; 4011 break; 4012 4013 case QImode: 4014 case HImode: 4015 case DImode: 4016 case SFmode: 4017 case DFmode: 4018 if (!reload_in_progress 4019 && !reload_completed 4020 && !register_operand (dest, mode) 4021 && !reg_or_0_operand (src, mode)) 4022 src = copy_to_mode_reg (mode, src); 4023 break; 4024 4025 default: 4026 gcc_unreachable (); 4027 } 4028 4029 emit_insn (gen_rtx_SET (VOIDmode, dest, src)); 4030} 4031 4032/* Emit code to handle a MOVSI, adding in the small data register or pic 4033 register if needed to load up addresses. Return TRUE if the appropriate 4034 instructions are emitted. */ 4035 4036int 4037frv_emit_movsi (rtx dest, rtx src) 4038{ 4039 int base_regno = -1; 4040 int unspec = 0; 4041 rtx sym = src; 4042 struct frv_unspec old_unspec; 4043 4044 if (!reload_in_progress 4045 && !reload_completed 4046 && !register_operand (dest, SImode) 4047 && (!reg_or_0_operand (src, SImode) 4048 /* Virtual registers will almost always be replaced by an 4049 add instruction, so expose this to CSE by copying to 4050 an intermediate register. */ 4051 || (GET_CODE (src) == REG 4052 && IN_RANGE_P (REGNO (src), 4053 FIRST_VIRTUAL_REGISTER, 4054 LAST_VIRTUAL_REGISTER)))) 4055 { 4056 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src))); 4057 return TRUE; 4058 } 4059 4060 /* Explicitly add in the PIC or small data register if needed. */ 4061 switch (GET_CODE (src)) 4062 { 4063 default: 4064 break; 4065 4066 case LABEL_REF: 4067 handle_label: 4068 if (TARGET_FDPIC) 4069 { 4070 /* Using GPREL12, we use a single GOT entry for all symbols 4071 in read-only sections, but trade sequences such as: 4072 4073 sethi #gothi(label), gr# 4074 setlo #gotlo(label), gr# 4075 ld @(gr15,gr#), gr# 4076 4077 for 4078 4079 ld @(gr15,#got12(_gp)), gr# 4080 sethi #gprelhi(label), gr## 4081 setlo #gprello(label), gr## 4082 add gr#, gr##, gr## 4083 4084 We may often be able to share gr# for multiple 4085 computations of GPREL addresses, and we may often fold 4086 the final add into the pair of registers of a load or 4087 store instruction, so it's often profitable. Even when 4088 optimizing for size, we're trading a GOT entry for an 4089 additional instruction, which trades GOT space 4090 (read-write) for code size (read-only, shareable), as 4091 long as the symbol is not used in more than two different 4092 locations. 4093 4094 With -fpie/-fpic, we'd be trading a single load for a 4095 sequence of 4 instructions, because the offset of the 4096 label can't be assumed to be addressable with 12 bits, so 4097 we don't do this. */ 4098 if (TARGET_GPREL_RO) 4099 unspec = R_FRV_GPREL12; 4100 else 4101 unspec = R_FRV_GOT12; 4102 } 4103 else if (flag_pic) 4104 base_regno = PIC_REGNO; 4105 4106 break; 4107 4108 case CONST: 4109 if (frv_const_unspec_p (src, &old_unspec)) 4110 break; 4111 4112 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0))) 4113 { 4114 handle_whatever: 4115 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0)); 4116 emit_move_insn (dest, src); 4117 return TRUE; 4118 } 4119 else 4120 { 4121 sym = XEXP (sym, 0); 4122 if (GET_CODE (sym) == PLUS 4123 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF 4124 && GET_CODE (XEXP (sym, 1)) == CONST_INT) 4125 sym = XEXP (sym, 0); 4126 if (GET_CODE (sym) == SYMBOL_REF) 4127 goto handle_sym; 4128 else if (GET_CODE (sym) == LABEL_REF) 4129 goto handle_label; 4130 else 4131 goto handle_whatever; 4132 } 4133 break; 4134 4135 case SYMBOL_REF: 4136 handle_sym: 4137 if (TARGET_FDPIC) 4138 { 4139 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym); 4140 4141 if (model != 0) 4142 { 4143 src = frv_legitimize_tls_address (src, model); 4144 emit_move_insn (dest, src); 4145 return TRUE; 4146 } 4147 4148 if (SYMBOL_REF_FUNCTION_P (sym)) 4149 { 4150 if (frv_local_funcdesc_p (sym)) 4151 unspec = R_FRV_FUNCDESC_GOTOFF12; 4152 else 4153 unspec = R_FRV_FUNCDESC_GOT12; 4154 } 4155 else 4156 { 4157 if (CONSTANT_POOL_ADDRESS_P (sym)) 4158 switch (GET_CODE (get_pool_constant (sym))) 4159 { 4160 case CONST: 4161 case SYMBOL_REF: 4162 case LABEL_REF: 4163 if (flag_pic) 4164 { 4165 unspec = R_FRV_GOTOFF12; 4166 break; 4167 } 4168 /* Fall through. */ 4169 default: 4170 if (TARGET_GPREL_RO) 4171 unspec = R_FRV_GPREL12; 4172 else 4173 unspec = R_FRV_GOT12; 4174 break; 4175 } 4176 else if (SYMBOL_REF_LOCAL_P (sym) 4177 && !SYMBOL_REF_EXTERNAL_P (sym) 4178 && SYMBOL_REF_DECL (sym) 4179 && (!DECL_P (SYMBOL_REF_DECL (sym)) 4180 || !DECL_COMMON (SYMBOL_REF_DECL (sym)))) 4181 { 4182 tree decl = SYMBOL_REF_DECL (sym); 4183 tree init = TREE_CODE (decl) == VAR_DECL 4184 ? DECL_INITIAL (decl) 4185 : TREE_CODE (decl) == CONSTRUCTOR 4186 ? decl : 0; 4187 int reloc = 0; 4188 bool named_section, readonly; 4189 4190 if (init && init != error_mark_node) 4191 reloc = compute_reloc_for_constant (init); 4192 4193 named_section = TREE_CODE (decl) == VAR_DECL 4194 && lookup_attribute ("section", DECL_ATTRIBUTES (decl)); 4195 readonly = decl_readonly_section (decl, reloc); 4196 4197 if (named_section) 4198 unspec = R_FRV_GOT12; 4199 else if (!readonly) 4200 unspec = R_FRV_GOTOFF12; 4201 else if (readonly && TARGET_GPREL_RO) 4202 unspec = R_FRV_GPREL12; 4203 else 4204 unspec = R_FRV_GOT12; 4205 } 4206 else 4207 unspec = R_FRV_GOT12; 4208 } 4209 } 4210 4211 else if (SYMBOL_REF_SMALL_P (sym)) 4212 base_regno = SDA_BASE_REG; 4213 4214 else if (flag_pic) 4215 base_regno = PIC_REGNO; 4216 4217 break; 4218 } 4219 4220 if (base_regno >= 0) 4221 { 4222 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym)) 4223 emit_insn (gen_symGOTOFF2reg (dest, src, 4224 gen_rtx_REG (Pmode, base_regno), 4225 GEN_INT (R_FRV_GPREL12))); 4226 else 4227 emit_insn (gen_symGOTOFF2reg_hilo (dest, src, 4228 gen_rtx_REG (Pmode, base_regno), 4229 GEN_INT (R_FRV_GPREL12))); 4230 if (base_regno == PIC_REGNO) 4231 crtl->uses_pic_offset_table = TRUE; 4232 return TRUE; 4233 } 4234 4235 if (unspec) 4236 { 4237 rtx x; 4238 4239 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce 4240 new uses of it once reload has begun. */ 4241 gcc_assert (!reload_in_progress && !reload_completed); 4242 4243 switch (unspec) 4244 { 4245 case R_FRV_GOTOFF12: 4246 if (!frv_small_data_reloc_p (sym, unspec)) 4247 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG, 4248 GEN_INT (unspec)); 4249 else 4250 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); 4251 break; 4252 case R_FRV_GPREL12: 4253 if (!frv_small_data_reloc_p (sym, unspec)) 4254 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG, 4255 GEN_INT (unspec)); 4256 else 4257 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); 4258 break; 4259 case R_FRV_FUNCDESC_GOTOFF12: 4260 if (flag_pic != 1) 4261 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG, 4262 GEN_INT (unspec)); 4263 else 4264 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); 4265 break; 4266 default: 4267 if (flag_pic != 1) 4268 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG, 4269 GEN_INT (unspec)); 4270 else 4271 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec)); 4272 break; 4273 } 4274 emit_insn (x); 4275 crtl->uses_pic_offset_table = TRUE; 4276 return TRUE; 4277 } 4278 4279 4280 return FALSE; 4281} 4282 4283 4284/* Return a string to output a single word move. */ 4285 4286const char * 4287output_move_single (rtx operands[], rtx insn) 4288{ 4289 rtx dest = operands[0]; 4290 rtx src = operands[1]; 4291 4292 if (GET_CODE (dest) == REG) 4293 { 4294 int dest_regno = REGNO (dest); 4295 enum machine_mode mode = GET_MODE (dest); 4296 4297 if (GPR_P (dest_regno)) 4298 { 4299 if (GET_CODE (src) == REG) 4300 { 4301 /* gpr <- some sort of register */ 4302 int src_regno = REGNO (src); 4303 4304 if (GPR_P (src_regno)) 4305 return "mov %1, %0"; 4306 4307 else if (FPR_P (src_regno)) 4308 return "movfg %1, %0"; 4309 4310 else if (SPR_P (src_regno)) 4311 return "movsg %1, %0"; 4312 } 4313 4314 else if (GET_CODE (src) == MEM) 4315 { 4316 /* gpr <- memory */ 4317 switch (mode) 4318 { 4319 default: 4320 break; 4321 4322 case QImode: 4323 return "ldsb%I1%U1 %M1,%0"; 4324 4325 case HImode: 4326 return "ldsh%I1%U1 %M1,%0"; 4327 4328 case SImode: 4329 case SFmode: 4330 return "ld%I1%U1 %M1, %0"; 4331 } 4332 } 4333 4334 else if (GET_CODE (src) == CONST_INT 4335 || GET_CODE (src) == CONST_DOUBLE) 4336 { 4337 /* gpr <- integer/floating constant */ 4338 HOST_WIDE_INT value; 4339 4340 if (GET_CODE (src) == CONST_INT) 4341 value = INTVAL (src); 4342 4343 else if (mode == SFmode) 4344 { 4345 REAL_VALUE_TYPE rv; 4346 long l; 4347 4348 REAL_VALUE_FROM_CONST_DOUBLE (rv, src); 4349 REAL_VALUE_TO_TARGET_SINGLE (rv, l); 4350 value = l; 4351 } 4352 4353 else 4354 value = CONST_DOUBLE_LOW (src); 4355 4356 if (IN_RANGE_P (value, -32768, 32767)) 4357 return "setlos %1, %0"; 4358 4359 return "#"; 4360 } 4361 4362 else if (GET_CODE (src) == SYMBOL_REF 4363 || GET_CODE (src) == LABEL_REF 4364 || GET_CODE (src) == CONST) 4365 { 4366 return "#"; 4367 } 4368 } 4369 4370 else if (FPR_P (dest_regno)) 4371 { 4372 if (GET_CODE (src) == REG) 4373 { 4374 /* fpr <- some sort of register */ 4375 int src_regno = REGNO (src); 4376 4377 if (GPR_P (src_regno)) 4378 return "movgf %1, %0"; 4379 4380 else if (FPR_P (src_regno)) 4381 { 4382 if (TARGET_HARD_FLOAT) 4383 return "fmovs %1, %0"; 4384 else 4385 return "mor %1, %1, %0"; 4386 } 4387 } 4388 4389 else if (GET_CODE (src) == MEM) 4390 { 4391 /* fpr <- memory */ 4392 switch (mode) 4393 { 4394 default: 4395 break; 4396 4397 case QImode: 4398 return "ldbf%I1%U1 %M1,%0"; 4399 4400 case HImode: 4401 return "ldhf%I1%U1 %M1,%0"; 4402 4403 case SImode: 4404 case SFmode: 4405 return "ldf%I1%U1 %M1, %0"; 4406 } 4407 } 4408 4409 else if (ZERO_P (src)) 4410 return "movgf %., %0"; 4411 } 4412 4413 else if (SPR_P (dest_regno)) 4414 { 4415 if (GET_CODE (src) == REG) 4416 { 4417 /* spr <- some sort of register */ 4418 int src_regno = REGNO (src); 4419 4420 if (GPR_P (src_regno)) 4421 return "movgs %1, %0"; 4422 } 4423 else if (ZERO_P (src)) 4424 return "movgs %., %0"; 4425 } 4426 } 4427 4428 else if (GET_CODE (dest) == MEM) 4429 { 4430 if (GET_CODE (src) == REG) 4431 { 4432 int src_regno = REGNO (src); 4433 enum machine_mode mode = GET_MODE (dest); 4434 4435 if (GPR_P (src_regno)) 4436 { 4437 switch (mode) 4438 { 4439 default: 4440 break; 4441 4442 case QImode: 4443 return "stb%I0%U0 %1, %M0"; 4444 4445 case HImode: 4446 return "sth%I0%U0 %1, %M0"; 4447 4448 case SImode: 4449 case SFmode: 4450 return "st%I0%U0 %1, %M0"; 4451 } 4452 } 4453 4454 else if (FPR_P (src_regno)) 4455 { 4456 switch (mode) 4457 { 4458 default: 4459 break; 4460 4461 case QImode: 4462 return "stbf%I0%U0 %1, %M0"; 4463 4464 case HImode: 4465 return "sthf%I0%U0 %1, %M0"; 4466 4467 case SImode: 4468 case SFmode: 4469 return "stf%I0%U0 %1, %M0"; 4470 } 4471 } 4472 } 4473 4474 else if (ZERO_P (src)) 4475 { 4476 switch (GET_MODE (dest)) 4477 { 4478 default: 4479 break; 4480 4481 case QImode: 4482 return "stb%I0%U0 %., %M0"; 4483 4484 case HImode: 4485 return "sth%I0%U0 %., %M0"; 4486 4487 case SImode: 4488 case SFmode: 4489 return "st%I0%U0 %., %M0"; 4490 } 4491 } 4492 } 4493 4494 fatal_insn ("bad output_move_single operand", insn); 4495 return ""; 4496} 4497 4498 4499/* Return a string to output a double word move. */ 4500 4501const char * 4502output_move_double (rtx operands[], rtx insn) 4503{ 4504 rtx dest = operands[0]; 4505 rtx src = operands[1]; 4506 enum machine_mode mode = GET_MODE (dest); 4507 4508 if (GET_CODE (dest) == REG) 4509 { 4510 int dest_regno = REGNO (dest); 4511 4512 if (GPR_P (dest_regno)) 4513 { 4514 if (GET_CODE (src) == REG) 4515 { 4516 /* gpr <- some sort of register */ 4517 int src_regno = REGNO (src); 4518 4519 if (GPR_P (src_regno)) 4520 return "#"; 4521 4522 else if (FPR_P (src_regno)) 4523 { 4524 if (((dest_regno - GPR_FIRST) & 1) == 0 4525 && ((src_regno - FPR_FIRST) & 1) == 0) 4526 return "movfgd %1, %0"; 4527 4528 return "#"; 4529 } 4530 } 4531 4532 else if (GET_CODE (src) == MEM) 4533 { 4534 /* gpr <- memory */ 4535 if (dbl_memory_one_insn_operand (src, mode)) 4536 return "ldd%I1%U1 %M1, %0"; 4537 4538 return "#"; 4539 } 4540 4541 else if (GET_CODE (src) == CONST_INT 4542 || GET_CODE (src) == CONST_DOUBLE) 4543 return "#"; 4544 } 4545 4546 else if (FPR_P (dest_regno)) 4547 { 4548 if (GET_CODE (src) == REG) 4549 { 4550 /* fpr <- some sort of register */ 4551 int src_regno = REGNO (src); 4552 4553 if (GPR_P (src_regno)) 4554 { 4555 if (((dest_regno - FPR_FIRST) & 1) == 0 4556 && ((src_regno - GPR_FIRST) & 1) == 0) 4557 return "movgfd %1, %0"; 4558 4559 return "#"; 4560 } 4561 4562 else if (FPR_P (src_regno)) 4563 { 4564 if (TARGET_DOUBLE 4565 && ((dest_regno - FPR_FIRST) & 1) == 0 4566 && ((src_regno - FPR_FIRST) & 1) == 0) 4567 return "fmovd %1, %0"; 4568 4569 return "#"; 4570 } 4571 } 4572 4573 else if (GET_CODE (src) == MEM) 4574 { 4575 /* fpr <- memory */ 4576 if (dbl_memory_one_insn_operand (src, mode)) 4577 return "lddf%I1%U1 %M1, %0"; 4578 4579 return "#"; 4580 } 4581 4582 else if (ZERO_P (src)) 4583 return "#"; 4584 } 4585 } 4586 4587 else if (GET_CODE (dest) == MEM) 4588 { 4589 if (GET_CODE (src) == REG) 4590 { 4591 int src_regno = REGNO (src); 4592 4593 if (GPR_P (src_regno)) 4594 { 4595 if (((src_regno - GPR_FIRST) & 1) == 0 4596 && dbl_memory_one_insn_operand (dest, mode)) 4597 return "std%I0%U0 %1, %M0"; 4598 4599 return "#"; 4600 } 4601 4602 if (FPR_P (src_regno)) 4603 { 4604 if (((src_regno - FPR_FIRST) & 1) == 0 4605 && dbl_memory_one_insn_operand (dest, mode)) 4606 return "stdf%I0%U0 %1, %M0"; 4607 4608 return "#"; 4609 } 4610 } 4611 4612 else if (ZERO_P (src)) 4613 { 4614 if (dbl_memory_one_insn_operand (dest, mode)) 4615 return "std%I0%U0 %., %M0"; 4616 4617 return "#"; 4618 } 4619 } 4620 4621 fatal_insn ("bad output_move_double operand", insn); 4622 return ""; 4623} 4624 4625 4626/* Return a string to output a single word conditional move. 4627 Operand0 -- EQ/NE of ccr register and 0 4628 Operand1 -- CCR register 4629 Operand2 -- destination 4630 Operand3 -- source */ 4631 4632const char * 4633output_condmove_single (rtx operands[], rtx insn) 4634{ 4635 rtx dest = operands[2]; 4636 rtx src = operands[3]; 4637 4638 if (GET_CODE (dest) == REG) 4639 { 4640 int dest_regno = REGNO (dest); 4641 enum machine_mode mode = GET_MODE (dest); 4642 4643 if (GPR_P (dest_regno)) 4644 { 4645 if (GET_CODE (src) == REG) 4646 { 4647 /* gpr <- some sort of register */ 4648 int src_regno = REGNO (src); 4649 4650 if (GPR_P (src_regno)) 4651 return "cmov %z3, %2, %1, %e0"; 4652 4653 else if (FPR_P (src_regno)) 4654 return "cmovfg %3, %2, %1, %e0"; 4655 } 4656 4657 else if (GET_CODE (src) == MEM) 4658 { 4659 /* gpr <- memory */ 4660 switch (mode) 4661 { 4662 default: 4663 break; 4664 4665 case QImode: 4666 return "cldsb%I3%U3 %M3, %2, %1, %e0"; 4667 4668 case HImode: 4669 return "cldsh%I3%U3 %M3, %2, %1, %e0"; 4670 4671 case SImode: 4672 case SFmode: 4673 return "cld%I3%U3 %M3, %2, %1, %e0"; 4674 } 4675 } 4676 4677 else if (ZERO_P (src)) 4678 return "cmov %., %2, %1, %e0"; 4679 } 4680 4681 else if (FPR_P (dest_regno)) 4682 { 4683 if (GET_CODE (src) == REG) 4684 { 4685 /* fpr <- some sort of register */ 4686 int src_regno = REGNO (src); 4687 4688 if (GPR_P (src_regno)) 4689 return "cmovgf %3, %2, %1, %e0"; 4690 4691 else if (FPR_P (src_regno)) 4692 { 4693 if (TARGET_HARD_FLOAT) 4694 return "cfmovs %3,%2,%1,%e0"; 4695 else 4696 return "cmor %3, %3, %2, %1, %e0"; 4697 } 4698 } 4699 4700 else if (GET_CODE (src) == MEM) 4701 { 4702 /* fpr <- memory */ 4703 if (mode == SImode || mode == SFmode) 4704 return "cldf%I3%U3 %M3, %2, %1, %e0"; 4705 } 4706 4707 else if (ZERO_P (src)) 4708 return "cmovgf %., %2, %1, %e0"; 4709 } 4710 } 4711 4712 else if (GET_CODE (dest) == MEM) 4713 { 4714 if (GET_CODE (src) == REG) 4715 { 4716 int src_regno = REGNO (src); 4717 enum machine_mode mode = GET_MODE (dest); 4718 4719 if (GPR_P (src_regno)) 4720 { 4721 switch (mode) 4722 { 4723 default: 4724 break; 4725 4726 case QImode: 4727 return "cstb%I2%U2 %3, %M2, %1, %e0"; 4728 4729 case HImode: 4730 return "csth%I2%U2 %3, %M2, %1, %e0"; 4731 4732 case SImode: 4733 case SFmode: 4734 return "cst%I2%U2 %3, %M2, %1, %e0"; 4735 } 4736 } 4737 4738 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode)) 4739 return "cstf%I2%U2 %3, %M2, %1, %e0"; 4740 } 4741 4742 else if (ZERO_P (src)) 4743 { 4744 enum machine_mode mode = GET_MODE (dest); 4745 switch (mode) 4746 { 4747 default: 4748 break; 4749 4750 case QImode: 4751 return "cstb%I2%U2 %., %M2, %1, %e0"; 4752 4753 case HImode: 4754 return "csth%I2%U2 %., %M2, %1, %e0"; 4755 4756 case SImode: 4757 case SFmode: 4758 return "cst%I2%U2 %., %M2, %1, %e0"; 4759 } 4760 } 4761 } 4762 4763 fatal_insn ("bad output_condmove_single operand", insn); 4764 return ""; 4765} 4766 4767 4768/* Emit the appropriate code to do a comparison, returning the register the 4769 comparison was done it. */ 4770 4771static rtx 4772frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1) 4773{ 4774 enum machine_mode cc_mode; 4775 rtx cc_reg; 4776 4777 /* Floating point doesn't have comparison against a constant. */ 4778 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG) 4779 op1 = force_reg (GET_MODE (op0), op1); 4780 4781 /* Possibly disable using anything but a fixed register in order to work 4782 around cse moving comparisons past function calls. */ 4783 cc_mode = SELECT_CC_MODE (test, op0, op1); 4784 cc_reg = ((TARGET_ALLOC_CC) 4785 ? gen_reg_rtx (cc_mode) 4786 : gen_rtx_REG (cc_mode, 4787 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST)); 4788 4789 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, 4790 gen_rtx_COMPARE (cc_mode, op0, op1))); 4791 4792 return cc_reg; 4793} 4794 4795 4796/* Emit code for a conditional branch. 4797 XXX: I originally wanted to add a clobber of a CCR register to use in 4798 conditional execution, but that confuses the rest of the compiler. */ 4799 4800int 4801frv_emit_cond_branch (rtx operands[]) 4802{ 4803 rtx test_rtx; 4804 rtx label_ref; 4805 rtx if_else; 4806 enum rtx_code test = GET_CODE (operands[0]); 4807 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]); 4808 enum machine_mode cc_mode = GET_MODE (cc_reg); 4809 4810 /* Branches generate: 4811 (set (pc) 4812 (if_then_else (<test>, <cc_reg>, (const_int 0)) 4813 (label_ref <branch_label>) 4814 (pc))) */ 4815 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]); 4816 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx); 4817 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx); 4818 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else)); 4819 return TRUE; 4820} 4821 4822 4823/* Emit code to set a gpr to 1/0 based on a comparison. */ 4824 4825int 4826frv_emit_scc (rtx operands[]) 4827{ 4828 rtx set; 4829 rtx test_rtx; 4830 rtx clobber; 4831 rtx cr_reg; 4832 enum rtx_code test = GET_CODE (operands[1]); 4833 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]); 4834 4835 /* SCC instructions generate: 4836 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0)) 4837 (clobber (<ccr_reg>))]) */ 4838 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx); 4839 set = gen_rtx_SET (VOIDmode, operands[0], test_rtx); 4840 4841 cr_reg = ((TARGET_ALLOC_CC) 4842 ? gen_reg_rtx (CC_CCRmode) 4843 : gen_rtx_REG (CC_CCRmode, 4844 ((GET_MODE (cc_reg) == CC_FPmode) 4845 ? FCR_FIRST 4846 : ICR_FIRST))); 4847 4848 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg); 4849 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); 4850 return TRUE; 4851} 4852 4853 4854/* Split a SCC instruction into component parts, returning a SEQUENCE to hold 4855 the separate insns. */ 4856 4857rtx 4858frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value) 4859{ 4860 rtx ret; 4861 4862 start_sequence (); 4863 4864 /* Set the appropriate CCR bit. */ 4865 emit_insn (gen_rtx_SET (VOIDmode, 4866 cr_reg, 4867 gen_rtx_fmt_ee (GET_CODE (test), 4868 GET_MODE (cr_reg), 4869 cc_reg, 4870 const0_rtx))); 4871 4872 /* Move the value into the destination. */ 4873 emit_move_insn (dest, GEN_INT (value)); 4874 4875 /* Move 0 into the destination if the test failed */ 4876 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 4877 gen_rtx_EQ (GET_MODE (cr_reg), 4878 cr_reg, 4879 const0_rtx), 4880 gen_rtx_SET (VOIDmode, dest, const0_rtx))); 4881 4882 /* Finish up, return sequence. */ 4883 ret = get_insns (); 4884 end_sequence (); 4885 return ret; 4886} 4887 4888 4889/* Emit the code for a conditional move, return TRUE if we could do the 4890 move. */ 4891 4892int 4893frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2) 4894{ 4895 rtx set; 4896 rtx clobber_cc; 4897 rtx test2; 4898 rtx cr_reg; 4899 rtx if_rtx; 4900 enum rtx_code test = GET_CODE (test_rtx); 4901 rtx cc_reg = frv_emit_comparison (test, 4902 XEXP (test_rtx, 0), XEXP (test_rtx, 1)); 4903 enum machine_mode cc_mode = GET_MODE (cc_reg); 4904 4905 /* Conditional move instructions generate: 4906 (parallel [(set <target> 4907 (if_then_else (<test> <cc_reg> (const_int 0)) 4908 <src1> 4909 <src2>)) 4910 (clobber (<ccr_reg>))]) */ 4911 4912 /* Handle various cases of conditional move involving two constants. */ 4913 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT) 4914 { 4915 HOST_WIDE_INT value1 = INTVAL (src1); 4916 HOST_WIDE_INT value2 = INTVAL (src2); 4917 4918 /* Having 0 as one of the constants can be done by loading the other 4919 constant, and optionally moving in gr0. */ 4920 if (value1 == 0 || value2 == 0) 4921 ; 4922 4923 /* If the first value is within an addi range and also the difference 4924 between the two fits in an addi's range, load up the difference, then 4925 conditionally move in 0, and then unconditionally add the first 4926 value. */ 4927 else if (IN_RANGE_P (value1, -2048, 2047) 4928 && IN_RANGE_P (value2 - value1, -2048, 2047)) 4929 ; 4930 4931 /* If neither condition holds, just force the constant into a 4932 register. */ 4933 else 4934 { 4935 src1 = force_reg (GET_MODE (dest), src1); 4936 src2 = force_reg (GET_MODE (dest), src2); 4937 } 4938 } 4939 4940 /* If one value is a register, insure the other value is either 0 or a 4941 register. */ 4942 else 4943 { 4944 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0) 4945 src1 = force_reg (GET_MODE (dest), src1); 4946 4947 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0) 4948 src2 = force_reg (GET_MODE (dest), src2); 4949 } 4950 4951 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx); 4952 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2); 4953 4954 set = gen_rtx_SET (VOIDmode, dest, if_rtx); 4955 4956 cr_reg = ((TARGET_ALLOC_CC) 4957 ? gen_reg_rtx (CC_CCRmode) 4958 : gen_rtx_REG (CC_CCRmode, 4959 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST)); 4960 4961 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg); 4962 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc))); 4963 return TRUE; 4964} 4965 4966 4967/* Split a conditional move into constituent parts, returning a SEQUENCE 4968 containing all of the insns. */ 4969 4970rtx 4971frv_split_cond_move (rtx operands[]) 4972{ 4973 rtx dest = operands[0]; 4974 rtx test = operands[1]; 4975 rtx cc_reg = operands[2]; 4976 rtx src1 = operands[3]; 4977 rtx src2 = operands[4]; 4978 rtx cr_reg = operands[5]; 4979 rtx ret; 4980 enum machine_mode cr_mode = GET_MODE (cr_reg); 4981 4982 start_sequence (); 4983 4984 /* Set the appropriate CCR bit. */ 4985 emit_insn (gen_rtx_SET (VOIDmode, 4986 cr_reg, 4987 gen_rtx_fmt_ee (GET_CODE (test), 4988 GET_MODE (cr_reg), 4989 cc_reg, 4990 const0_rtx))); 4991 4992 /* Handle various cases of conditional move involving two constants. */ 4993 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT) 4994 { 4995 HOST_WIDE_INT value1 = INTVAL (src1); 4996 HOST_WIDE_INT value2 = INTVAL (src2); 4997 4998 /* Having 0 as one of the constants can be done by loading the other 4999 constant, and optionally moving in gr0. */ 5000 if (value1 == 0) 5001 { 5002 emit_move_insn (dest, src2); 5003 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 5004 gen_rtx_NE (cr_mode, cr_reg, 5005 const0_rtx), 5006 gen_rtx_SET (VOIDmode, dest, src1))); 5007 } 5008 5009 else if (value2 == 0) 5010 { 5011 emit_move_insn (dest, src1); 5012 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 5013 gen_rtx_EQ (cr_mode, cr_reg, 5014 const0_rtx), 5015 gen_rtx_SET (VOIDmode, dest, src2))); 5016 } 5017 5018 /* If the first value is within an addi range and also the difference 5019 between the two fits in an addi's range, load up the difference, then 5020 conditionally move in 0, and then unconditionally add the first 5021 value. */ 5022 else if (IN_RANGE_P (value1, -2048, 2047) 5023 && IN_RANGE_P (value2 - value1, -2048, 2047)) 5024 { 5025 rtx dest_si = ((GET_MODE (dest) == SImode) 5026 ? dest 5027 : gen_rtx_SUBREG (SImode, dest, 0)); 5028 5029 emit_move_insn (dest_si, GEN_INT (value2 - value1)); 5030 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 5031 gen_rtx_NE (cr_mode, cr_reg, 5032 const0_rtx), 5033 gen_rtx_SET (VOIDmode, dest_si, 5034 const0_rtx))); 5035 emit_insn (gen_addsi3 (dest_si, dest_si, src1)); 5036 } 5037 5038 else 5039 gcc_unreachable (); 5040 } 5041 else 5042 { 5043 /* Emit the conditional move for the test being true if needed. */ 5044 if (! rtx_equal_p (dest, src1)) 5045 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 5046 gen_rtx_NE (cr_mode, cr_reg, const0_rtx), 5047 gen_rtx_SET (VOIDmode, dest, src1))); 5048 5049 /* Emit the conditional move for the test being false if needed. */ 5050 if (! rtx_equal_p (dest, src2)) 5051 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 5052 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx), 5053 gen_rtx_SET (VOIDmode, dest, src2))); 5054 } 5055 5056 /* Finish up, return sequence. */ 5057 ret = get_insns (); 5058 end_sequence (); 5059 return ret; 5060} 5061 5062 5063/* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a 5064 memory location that is not known to be dword-aligned. */ 5065void 5066frv_split_double_load (rtx dest, rtx source) 5067{ 5068 int regno = REGNO (dest); 5069 rtx dest1 = gen_highpart (SImode, dest); 5070 rtx dest2 = gen_lowpart (SImode, dest); 5071 rtx address = XEXP (source, 0); 5072 5073 /* If the address is pre-modified, load the lower-numbered register 5074 first, then load the other register using an integer offset from 5075 the modified base register. This order should always be safe, 5076 since the pre-modification cannot affect the same registers as the 5077 load does. 5078 5079 The situation for other loads is more complicated. Loading one 5080 of the registers could affect the value of ADDRESS, so we must 5081 be careful which order we do them in. */ 5082 if (GET_CODE (address) == PRE_MODIFY 5083 || ! refers_to_regno_p (regno, regno + 1, address, NULL)) 5084 { 5085 /* It is safe to load the lower-numbered register first. */ 5086 emit_move_insn (dest1, change_address (source, SImode, NULL)); 5087 emit_move_insn (dest2, frv_index_memory (source, SImode, 1)); 5088 } 5089 else 5090 { 5091 /* ADDRESS is not pre-modified and the address depends on the 5092 lower-numbered register. Load the higher-numbered register 5093 first. */ 5094 emit_move_insn (dest2, frv_index_memory (source, SImode, 1)); 5095 emit_move_insn (dest1, change_address (source, SImode, NULL)); 5096 } 5097} 5098 5099/* Split (set DEST SOURCE), where DEST refers to a dword memory location 5100 and SOURCE is either a double register or the constant zero. */ 5101void 5102frv_split_double_store (rtx dest, rtx source) 5103{ 5104 rtx dest1 = change_address (dest, SImode, NULL); 5105 rtx dest2 = frv_index_memory (dest, SImode, 1); 5106 if (ZERO_P (source)) 5107 { 5108 emit_move_insn (dest1, CONST0_RTX (SImode)); 5109 emit_move_insn (dest2, CONST0_RTX (SImode)); 5110 } 5111 else 5112 { 5113 emit_move_insn (dest1, gen_highpart (SImode, source)); 5114 emit_move_insn (dest2, gen_lowpart (SImode, source)); 5115 } 5116} 5117 5118 5119/* Split a min/max operation returning a SEQUENCE containing all of the 5120 insns. */ 5121 5122rtx 5123frv_split_minmax (rtx operands[]) 5124{ 5125 rtx dest = operands[0]; 5126 rtx minmax = operands[1]; 5127 rtx src1 = operands[2]; 5128 rtx src2 = operands[3]; 5129 rtx cc_reg = operands[4]; 5130 rtx cr_reg = operands[5]; 5131 rtx ret; 5132 enum rtx_code test_code; 5133 enum machine_mode cr_mode = GET_MODE (cr_reg); 5134 5135 start_sequence (); 5136 5137 /* Figure out which test to use. */ 5138 switch (GET_CODE (minmax)) 5139 { 5140 default: 5141 gcc_unreachable (); 5142 5143 case SMIN: test_code = LT; break; 5144 case SMAX: test_code = GT; break; 5145 case UMIN: test_code = LTU; break; 5146 case UMAX: test_code = GTU; break; 5147 } 5148 5149 /* Issue the compare instruction. */ 5150 emit_insn (gen_rtx_SET (VOIDmode, 5151 cc_reg, 5152 gen_rtx_COMPARE (GET_MODE (cc_reg), 5153 src1, src2))); 5154 5155 /* Set the appropriate CCR bit. */ 5156 emit_insn (gen_rtx_SET (VOIDmode, 5157 cr_reg, 5158 gen_rtx_fmt_ee (test_code, 5159 GET_MODE (cr_reg), 5160 cc_reg, 5161 const0_rtx))); 5162 5163 /* If are taking the min/max of a nonzero constant, load that first, and 5164 then do a conditional move of the other value. */ 5165 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0) 5166 { 5167 gcc_assert (!rtx_equal_p (dest, src1)); 5168 5169 emit_move_insn (dest, src2); 5170 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 5171 gen_rtx_NE (cr_mode, cr_reg, const0_rtx), 5172 gen_rtx_SET (VOIDmode, dest, src1))); 5173 } 5174 5175 /* Otherwise, do each half of the move. */ 5176 else 5177 { 5178 /* Emit the conditional move for the test being true if needed. */ 5179 if (! rtx_equal_p (dest, src1)) 5180 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 5181 gen_rtx_NE (cr_mode, cr_reg, const0_rtx), 5182 gen_rtx_SET (VOIDmode, dest, src1))); 5183 5184 /* Emit the conditional move for the test being false if needed. */ 5185 if (! rtx_equal_p (dest, src2)) 5186 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 5187 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx), 5188 gen_rtx_SET (VOIDmode, dest, src2))); 5189 } 5190 5191 /* Finish up, return sequence. */ 5192 ret = get_insns (); 5193 end_sequence (); 5194 return ret; 5195} 5196 5197 5198/* Split an integer abs operation returning a SEQUENCE containing all of the 5199 insns. */ 5200 5201rtx 5202frv_split_abs (rtx operands[]) 5203{ 5204 rtx dest = operands[0]; 5205 rtx src = operands[1]; 5206 rtx cc_reg = operands[2]; 5207 rtx cr_reg = operands[3]; 5208 rtx ret; 5209 5210 start_sequence (); 5211 5212 /* Issue the compare < 0 instruction. */ 5213 emit_insn (gen_rtx_SET (VOIDmode, 5214 cc_reg, 5215 gen_rtx_COMPARE (CCmode, src, const0_rtx))); 5216 5217 /* Set the appropriate CCR bit. */ 5218 emit_insn (gen_rtx_SET (VOIDmode, 5219 cr_reg, 5220 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx))); 5221 5222 /* Emit the conditional negate if the value is negative. */ 5223 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 5224 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx), 5225 gen_negsi2 (dest, src))); 5226 5227 /* Emit the conditional move for the test being false if needed. */ 5228 if (! rtx_equal_p (dest, src)) 5229 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 5230 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx), 5231 gen_rtx_SET (VOIDmode, dest, src))); 5232 5233 /* Finish up, return sequence. */ 5234 ret = get_insns (); 5235 end_sequence (); 5236 return ret; 5237} 5238 5239 5240/* An internal function called by for_each_rtx to clear in a hard_reg set each 5241 register used in an insn. */ 5242 5243static int 5244frv_clear_registers_used (rtx *ptr, void *data) 5245{ 5246 if (GET_CODE (*ptr) == REG) 5247 { 5248 int regno = REGNO (*ptr); 5249 HARD_REG_SET *p_regs = (HARD_REG_SET *)data; 5250 5251 if (regno < FIRST_PSEUDO_REGISTER) 5252 { 5253 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr)); 5254 5255 while (regno < reg_max) 5256 { 5257 CLEAR_HARD_REG_BIT (*p_regs, regno); 5258 regno++; 5259 } 5260 } 5261 } 5262 5263 return 0; 5264} 5265 5266 5267/* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */ 5268 5269/* On the FR-V, we don't have any extra fields per se, but it is useful hook to 5270 initialize the static storage. */ 5271void 5272frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) 5273{ 5274 frv_ifcvt.added_insns_list = NULL_RTX; 5275 frv_ifcvt.cur_scratch_regs = 0; 5276 frv_ifcvt.num_nested_cond_exec = 0; 5277 frv_ifcvt.cr_reg = NULL_RTX; 5278 frv_ifcvt.nested_cc_reg = NULL_RTX; 5279 frv_ifcvt.extra_int_cr = NULL_RTX; 5280 frv_ifcvt.extra_fp_cr = NULL_RTX; 5281 frv_ifcvt.last_nested_if_cr = NULL_RTX; 5282} 5283 5284 5285/* Internal function to add a potential insn to the list of insns to be inserted 5286 if the conditional execution conversion is successful. */ 5287 5288static void 5289frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p) 5290{ 5291 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn); 5292 5293 link->jump = before_p; /* Mark to add this before or after insn. */ 5294 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link, 5295 frv_ifcvt.added_insns_list); 5296 5297 if (TARGET_DEBUG_COND_EXEC) 5298 { 5299 fprintf (stderr, 5300 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n", 5301 (before_p) ? "before" : "after", 5302 (int)INSN_UID (insn)); 5303 5304 debug_rtx (pattern); 5305 } 5306} 5307 5308 5309/* A C expression to modify the code described by the conditional if 5310 information CE_INFO, possibly updating the tests in TRUE_EXPR, and 5311 FALSE_EXPR for converting if-then and if-then-else code to conditional 5312 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the 5313 tests cannot be converted. */ 5314 5315void 5316frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false) 5317{ 5318 basic_block test_bb = ce_info->test_bb; /* test basic block */ 5319 basic_block then_bb = ce_info->then_bb; /* THEN */ 5320 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */ 5321 basic_block join_bb = ce_info->join_bb; /* join block or NULL */ 5322 rtx true_expr = *p_true; 5323 rtx cr; 5324 rtx cc; 5325 rtx nested_cc; 5326 enum machine_mode mode = GET_MODE (true_expr); 5327 int j; 5328 basic_block *bb; 5329 int num_bb; 5330 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg; 5331 rtx check_insn; 5332 rtx sub_cond_exec_reg; 5333 enum rtx_code code; 5334 enum rtx_code code_true; 5335 enum rtx_code code_false; 5336 enum reg_class cc_class; 5337 enum reg_class cr_class; 5338 int cc_first; 5339 int cc_last; 5340 reg_set_iterator rsi; 5341 5342 /* Make sure we are only dealing with hard registers. Also honor the 5343 -mno-cond-exec switch, and -mno-nested-cond-exec switches if 5344 applicable. */ 5345 if (!reload_completed || !TARGET_COND_EXEC 5346 || (!TARGET_NESTED_CE && ce_info->pass > 1)) 5347 goto fail; 5348 5349 /* Figure out which registers we can allocate for our own purposes. Only 5350 consider registers that are not preserved across function calls and are 5351 not fixed. However, allow the ICC/ICR temporary registers to be allocated 5352 if we did not need to use them in reloading other registers. */ 5353 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs)); 5354 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set); 5355 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set); 5356 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP); 5357 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP); 5358 5359 /* If this is a nested IF, we need to discover whether the CC registers that 5360 are set/used inside of the block are used anywhere else. If not, we can 5361 change them to be the CC register that is paired with the CR register that 5362 controls the outermost IF block. */ 5363 if (ce_info->pass > 1) 5364 { 5365 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite); 5366 for (j = CC_FIRST; j <= CC_LAST; j++) 5367 if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) 5368 { 5369 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j)) 5370 continue; 5371 5372 if (else_bb 5373 && REGNO_REG_SET_P (df_get_live_in (else_bb), j)) 5374 continue; 5375 5376 if (join_bb 5377 && REGNO_REG_SET_P (df_get_live_in (join_bb), j)) 5378 continue; 5379 5380 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j); 5381 } 5382 } 5383 5384 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++) 5385 frv_ifcvt.scratch_regs[j] = NULL_RTX; 5386 5387 frv_ifcvt.added_insns_list = NULL_RTX; 5388 frv_ifcvt.cur_scratch_regs = 0; 5389 5390 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks) 5391 * sizeof (basic_block)); 5392 5393 if (join_bb) 5394 { 5395 unsigned int regno; 5396 5397 /* Remove anything live at the beginning of the join block from being 5398 available for allocation. */ 5399 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi) 5400 { 5401 if (regno < FIRST_PSEUDO_REGISTER) 5402 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno); 5403 } 5404 } 5405 5406 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */ 5407 num_bb = 0; 5408 if (ce_info->num_multiple_test_blocks) 5409 { 5410 basic_block multiple_test_bb = ce_info->last_test_bb; 5411 5412 while (multiple_test_bb != test_bb) 5413 { 5414 bb[num_bb++] = multiple_test_bb; 5415 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src; 5416 } 5417 } 5418 5419 /* Add in the THEN and ELSE blocks to be scanned. */ 5420 bb[num_bb++] = then_bb; 5421 if (else_bb) 5422 bb[num_bb++] = else_bb; 5423 5424 sub_cond_exec_reg = NULL_RTX; 5425 frv_ifcvt.num_nested_cond_exec = 0; 5426 5427 /* Scan all of the blocks for registers that must not be allocated. */ 5428 for (j = 0; j < num_bb; j++) 5429 { 5430 rtx last_insn = BB_END (bb[j]); 5431 rtx insn = BB_HEAD (bb[j]); 5432 unsigned int regno; 5433 5434 if (dump_file) 5435 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n", 5436 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"), 5437 (int) bb[j]->index, 5438 (int) INSN_UID (BB_HEAD (bb[j])), 5439 (int) INSN_UID (BB_END (bb[j]))); 5440 5441 /* Anything live at the beginning of the block is obviously unavailable 5442 for allocation. */ 5443 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi) 5444 { 5445 if (regno < FIRST_PSEUDO_REGISTER) 5446 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno); 5447 } 5448 5449 /* Loop through the insns in the block. */ 5450 for (;;) 5451 { 5452 /* Mark any new registers that are created as being unavailable for 5453 allocation. Also see if the CC register used in nested IFs can be 5454 reallocated. */ 5455 if (INSN_P (insn)) 5456 { 5457 rtx pattern; 5458 rtx set; 5459 int skip_nested_if = FALSE; 5460 5461 for_each_rtx (&PATTERN (insn), frv_clear_registers_used, 5462 (void *)&tmp_reg->regs); 5463 5464 pattern = PATTERN (insn); 5465 if (GET_CODE (pattern) == COND_EXEC) 5466 { 5467 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0); 5468 5469 if (reg != sub_cond_exec_reg) 5470 { 5471 sub_cond_exec_reg = reg; 5472 frv_ifcvt.num_nested_cond_exec++; 5473 } 5474 } 5475 5476 set = single_set_pattern (pattern); 5477 if (set) 5478 { 5479 rtx dest = SET_DEST (set); 5480 rtx src = SET_SRC (set); 5481 5482 if (GET_CODE (dest) == REG) 5483 { 5484 int regno = REGNO (dest); 5485 enum rtx_code src_code = GET_CODE (src); 5486 5487 if (CC_P (regno) && src_code == COMPARE) 5488 skip_nested_if = TRUE; 5489 5490 else if (CR_P (regno) 5491 && (src_code == IF_THEN_ELSE 5492 || COMPARISON_P (src))) 5493 skip_nested_if = TRUE; 5494 } 5495 } 5496 5497 if (! skip_nested_if) 5498 for_each_rtx (&PATTERN (insn), frv_clear_registers_used, 5499 (void *)&frv_ifcvt.nested_cc_ok_rewrite); 5500 } 5501 5502 if (insn == last_insn) 5503 break; 5504 5505 insn = NEXT_INSN (insn); 5506 } 5507 } 5508 5509 /* If this is a nested if, rewrite the CC registers that are available to 5510 include the ones that can be rewritten, to increase the chance of being 5511 able to allocate a paired CC/CR register combination. */ 5512 if (ce_info->pass > 1) 5513 { 5514 for (j = CC_FIRST; j <= CC_LAST; j++) 5515 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j)) 5516 SET_HARD_REG_BIT (tmp_reg->regs, j); 5517 else 5518 CLEAR_HARD_REG_BIT (tmp_reg->regs, j); 5519 } 5520 5521 if (dump_file) 5522 { 5523 int num_gprs = 0; 5524 fprintf (dump_file, "Available GPRs: "); 5525 5526 for (j = GPR_FIRST; j <= GPR_LAST; j++) 5527 if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) 5528 { 5529 fprintf (dump_file, " %d [%s]", j, reg_names[j]); 5530 if (++num_gprs > GPR_TEMP_NUM+2) 5531 break; 5532 } 5533 5534 fprintf (dump_file, "%s\nAvailable CRs: ", 5535 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : ""); 5536 5537 for (j = CR_FIRST; j <= CR_LAST; j++) 5538 if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) 5539 fprintf (dump_file, " %d [%s]", j, reg_names[j]); 5540 5541 fputs ("\n", dump_file); 5542 5543 if (ce_info->pass > 1) 5544 { 5545 fprintf (dump_file, "Modifiable CCs: "); 5546 for (j = CC_FIRST; j <= CC_LAST; j++) 5547 if (TEST_HARD_REG_BIT (tmp_reg->regs, j)) 5548 fprintf (dump_file, " %d [%s]", j, reg_names[j]); 5549 5550 fprintf (dump_file, "\n%d nested COND_EXEC statements\n", 5551 frv_ifcvt.num_nested_cond_exec); 5552 } 5553 } 5554 5555 /* Allocate the appropriate temporary condition code register. Try to 5556 allocate the ICR/FCR register that corresponds to the ICC/FCC register so 5557 that conditional cmp's can be done. */ 5558 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode) 5559 { 5560 cr_class = ICR_REGS; 5561 cc_class = ICC_REGS; 5562 cc_first = ICC_FIRST; 5563 cc_last = ICC_LAST; 5564 } 5565 else if (mode == CC_FPmode) 5566 { 5567 cr_class = FCR_REGS; 5568 cc_class = FCC_REGS; 5569 cc_first = FCC_FIRST; 5570 cc_last = FCC_LAST; 5571 } 5572 else 5573 { 5574 cc_first = cc_last = 0; 5575 cr_class = cc_class = NO_REGS; 5576 } 5577 5578 cc = XEXP (true_expr, 0); 5579 nested_cc = cr = NULL_RTX; 5580 if (cc_class != NO_REGS) 5581 { 5582 /* For nested IFs and &&/||, see if we can find a CC and CR register pair 5583 so we can execute a csubcc/caddcc/cfcmps instruction. */ 5584 int cc_regno; 5585 5586 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++) 5587 { 5588 int cr_regno = cc_regno - CC_FIRST + CR_FIRST; 5589 5590 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno) 5591 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno)) 5592 { 5593 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno; 5594 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE, 5595 TRUE); 5596 5597 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno; 5598 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode, 5599 TRUE, TRUE); 5600 break; 5601 } 5602 } 5603 } 5604 5605 if (! cr) 5606 { 5607 if (dump_file) 5608 fprintf (dump_file, "Could not allocate a CR temporary register\n"); 5609 5610 goto fail; 5611 } 5612 5613 if (dump_file) 5614 fprintf (dump_file, 5615 "Will use %s for conditional execution, %s for nested comparisons\n", 5616 reg_names[ REGNO (cr)], 5617 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>"); 5618 5619 /* Set the CCR bit. Note for integer tests, we reverse the condition so that 5620 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR 5621 bit being true. We don't do this for floating point, because of NaNs. */ 5622 code = GET_CODE (true_expr); 5623 if (GET_MODE (cc) != CC_FPmode) 5624 { 5625 code = reverse_condition (code); 5626 code_true = EQ; 5627 code_false = NE; 5628 } 5629 else 5630 { 5631 code_true = NE; 5632 code_false = EQ; 5633 } 5634 5635 check_insn = gen_rtx_SET (VOIDmode, cr, 5636 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx)); 5637 5638 /* Record the check insn to be inserted later. */ 5639 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE); 5640 5641 /* Update the tests. */ 5642 frv_ifcvt.cr_reg = cr; 5643 frv_ifcvt.nested_cc_reg = nested_cc; 5644 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx); 5645 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx); 5646 return; 5647 5648 /* Fail, don't do this conditional execution. */ 5649 fail: 5650 *p_true = NULL_RTX; 5651 *p_false = NULL_RTX; 5652 if (dump_file) 5653 fprintf (dump_file, "Disabling this conditional execution.\n"); 5654 5655 return; 5656} 5657 5658 5659/* A C expression to modify the code described by the conditional if 5660 information CE_INFO, for the basic block BB, possibly updating the tests in 5661 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or 5662 if-then-else code to conditional instructions. Set either TRUE_EXPR or 5663 FALSE_EXPR to a null pointer if the tests cannot be converted. */ 5664 5665/* p_true and p_false are given expressions of the form: 5666 5667 (and (eq:CC_CCR (reg:CC_CCR) 5668 (const_int 0)) 5669 (eq:CC (reg:CC) 5670 (const_int 0))) */ 5671 5672void 5673frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info, 5674 basic_block bb, 5675 rtx *p_true, 5676 rtx *p_false) 5677{ 5678 rtx old_true = XEXP (*p_true, 0); 5679 rtx old_false = XEXP (*p_false, 0); 5680 rtx true_expr = XEXP (*p_true, 1); 5681 rtx false_expr = XEXP (*p_false, 1); 5682 rtx test_expr; 5683 rtx old_test; 5684 rtx cr = XEXP (old_true, 0); 5685 rtx check_insn; 5686 rtx new_cr = NULL_RTX; 5687 rtx *p_new_cr = (rtx *)0; 5688 rtx if_else; 5689 rtx compare; 5690 rtx cc; 5691 enum reg_class cr_class; 5692 enum machine_mode mode = GET_MODE (true_expr); 5693 rtx (*logical_func)(rtx, rtx, rtx); 5694 5695 if (TARGET_DEBUG_COND_EXEC) 5696 { 5697 fprintf (stderr, 5698 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n", 5699 ce_info->and_and_p ? "&&" : "||"); 5700 5701 debug_rtx (*p_true); 5702 5703 fputs ("\nfalse insn:\n", stderr); 5704 debug_rtx (*p_false); 5705 } 5706 5707 if (!TARGET_MULTI_CE) 5708 goto fail; 5709 5710 if (GET_CODE (cr) != REG) 5711 goto fail; 5712 5713 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode) 5714 { 5715 cr_class = ICR_REGS; 5716 p_new_cr = &frv_ifcvt.extra_int_cr; 5717 } 5718 else if (mode == CC_FPmode) 5719 { 5720 cr_class = FCR_REGS; 5721 p_new_cr = &frv_ifcvt.extra_fp_cr; 5722 } 5723 else 5724 goto fail; 5725 5726 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or 5727 more &&/|| tests. */ 5728 new_cr = *p_new_cr; 5729 if (! new_cr) 5730 { 5731 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class, 5732 CC_CCRmode, TRUE, TRUE); 5733 if (! new_cr) 5734 goto fail; 5735 } 5736 5737 if (ce_info->and_and_p) 5738 { 5739 old_test = old_false; 5740 test_expr = true_expr; 5741 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr; 5742 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx); 5743 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx); 5744 } 5745 else 5746 { 5747 old_test = old_false; 5748 test_expr = false_expr; 5749 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr; 5750 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx); 5751 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx); 5752 } 5753 5754 /* First add the andcr/andncr/orcr/orncr, which will be added after the 5755 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO 5756 stack. */ 5757 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE); 5758 5759 /* Now add the conditional check insn. */ 5760 cc = XEXP (test_expr, 0); 5761 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx); 5762 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx); 5763 5764 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else); 5765 5766 /* Add the new check insn to the list of check insns that need to be 5767 inserted. */ 5768 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE); 5769 5770 if (TARGET_DEBUG_COND_EXEC) 5771 { 5772 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n", 5773 stderr); 5774 5775 debug_rtx (*p_true); 5776 5777 fputs ("\nfalse insn:\n", stderr); 5778 debug_rtx (*p_false); 5779 } 5780 5781 return; 5782 5783 fail: 5784 *p_true = *p_false = NULL_RTX; 5785 5786 /* If we allocated a CR register, release it. */ 5787 if (new_cr) 5788 { 5789 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr)); 5790 *p_new_cr = NULL_RTX; 5791 } 5792 5793 if (TARGET_DEBUG_COND_EXEC) 5794 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr); 5795 5796 return; 5797} 5798 5799 5800/* Return a register which will be loaded with a value if an IF block is 5801 converted to conditional execution. This is used to rewrite instructions 5802 that use constants to ones that just use registers. */ 5803 5804static rtx 5805frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED) 5806{ 5807 int num_alloc = frv_ifcvt.cur_scratch_regs; 5808 int i; 5809 rtx reg; 5810 5811 /* We know gr0 == 0, so replace any errant uses. */ 5812 if (value == const0_rtx) 5813 return gen_rtx_REG (SImode, GPR_FIRST); 5814 5815 /* First search all registers currently loaded to see if we have an 5816 applicable constant. */ 5817 if (CONSTANT_P (value) 5818 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)) 5819 { 5820 for (i = 0; i < num_alloc; i++) 5821 { 5822 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value)) 5823 return SET_DEST (frv_ifcvt.scratch_regs[i]); 5824 } 5825 } 5826 5827 /* Have we exhausted the number of registers available? */ 5828 if (num_alloc >= GPR_TEMP_NUM) 5829 { 5830 if (dump_file) 5831 fprintf (dump_file, "Too many temporary registers allocated\n"); 5832 5833 return NULL_RTX; 5834 } 5835 5836 /* Allocate the new register. */ 5837 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE); 5838 if (! reg) 5839 { 5840 if (dump_file) 5841 fputs ("Could not find a scratch register\n", dump_file); 5842 5843 return NULL_RTX; 5844 } 5845 5846 frv_ifcvt.cur_scratch_regs++; 5847 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value); 5848 5849 if (dump_file) 5850 { 5851 if (GET_CODE (value) == CONST_INT) 5852 fprintf (dump_file, "Register %s will hold %ld\n", 5853 reg_names[ REGNO (reg)], (long)INTVAL (value)); 5854 5855 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO) 5856 fprintf (dump_file, "Register %s will hold LR\n", 5857 reg_names[ REGNO (reg)]); 5858 5859 else 5860 fprintf (dump_file, "Register %s will hold a saved value\n", 5861 reg_names[ REGNO (reg)]); 5862 } 5863 5864 return reg; 5865} 5866 5867 5868/* Update a MEM used in conditional code that might contain an offset to put 5869 the offset into a scratch register, so that the conditional load/store 5870 operations can be used. This function returns the original pointer if the 5871 MEM is valid to use in conditional code, NULL if we can't load up the offset 5872 into a temporary register, or the new MEM if we were successful. */ 5873 5874static rtx 5875frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn) 5876{ 5877 rtx addr = XEXP (mem, 0); 5878 5879 if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE)) 5880 { 5881 if (GET_CODE (addr) == PLUS) 5882 { 5883 rtx addr_op0 = XEXP (addr, 0); 5884 rtx addr_op1 = XEXP (addr, 1); 5885 5886 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1)) 5887 { 5888 rtx reg = frv_ifcvt_load_value (addr_op1, insn); 5889 if (!reg) 5890 return NULL_RTX; 5891 5892 addr = gen_rtx_PLUS (Pmode, addr_op0, reg); 5893 } 5894 5895 else 5896 return NULL_RTX; 5897 } 5898 5899 else if (CONSTANT_P (addr)) 5900 addr = frv_ifcvt_load_value (addr, insn); 5901 5902 else 5903 return NULL_RTX; 5904 5905 if (addr == NULL_RTX) 5906 return NULL_RTX; 5907 5908 else if (XEXP (mem, 0) != addr) 5909 return change_address (mem, mode, addr); 5910 } 5911 5912 return mem; 5913} 5914 5915 5916/* Given a PATTERN, return a SET expression if this PATTERN has only a single 5917 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */ 5918 5919static rtx 5920single_set_pattern (rtx pattern) 5921{ 5922 rtx set; 5923 int i; 5924 5925 if (GET_CODE (pattern) == COND_EXEC) 5926 pattern = COND_EXEC_CODE (pattern); 5927 5928 if (GET_CODE (pattern) == SET) 5929 return pattern; 5930 5931 else if (GET_CODE (pattern) == PARALLEL) 5932 { 5933 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++) 5934 { 5935 rtx sub = XVECEXP (pattern, 0, i); 5936 5937 switch (GET_CODE (sub)) 5938 { 5939 case USE: 5940 case CLOBBER: 5941 break; 5942 5943 case SET: 5944 if (set) 5945 return 0; 5946 else 5947 set = sub; 5948 break; 5949 5950 default: 5951 return 0; 5952 } 5953 } 5954 return set; 5955 } 5956 5957 return 0; 5958} 5959 5960 5961/* A C expression to modify the code described by the conditional if 5962 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null 5963 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that 5964 insn cannot be converted to be executed conditionally. */ 5965 5966rtx 5967frv_ifcvt_modify_insn (ce_if_block_t *ce_info, 5968 rtx pattern, 5969 rtx insn) 5970{ 5971 rtx orig_ce_pattern = pattern; 5972 rtx set; 5973 rtx op0; 5974 rtx op1; 5975 rtx test; 5976 5977 gcc_assert (GET_CODE (pattern) == COND_EXEC); 5978 5979 test = COND_EXEC_TEST (pattern); 5980 if (GET_CODE (test) == AND) 5981 { 5982 rtx cr = frv_ifcvt.cr_reg; 5983 rtx test_reg; 5984 5985 op0 = XEXP (test, 0); 5986 if (! rtx_equal_p (cr, XEXP (op0, 0))) 5987 goto fail; 5988 5989 op1 = XEXP (test, 1); 5990 test_reg = XEXP (op1, 0); 5991 if (GET_CODE (test_reg) != REG) 5992 goto fail; 5993 5994 /* Is this the first nested if block in this sequence? If so, generate 5995 an andcr or andncr. */ 5996 if (! frv_ifcvt.last_nested_if_cr) 5997 { 5998 rtx and_op; 5999 6000 frv_ifcvt.last_nested_if_cr = test_reg; 6001 if (GET_CODE (op0) == NE) 6002 and_op = gen_andcr (test_reg, cr, test_reg); 6003 else 6004 and_op = gen_andncr (test_reg, cr, test_reg); 6005 6006 frv_ifcvt_add_insn (and_op, insn, TRUE); 6007 } 6008 6009 /* If this isn't the first statement in the nested if sequence, see if we 6010 are dealing with the same register. */ 6011 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr)) 6012 goto fail; 6013 6014 COND_EXEC_TEST (pattern) = test = op1; 6015 } 6016 6017 /* If this isn't a nested if, reset state variables. */ 6018 else 6019 { 6020 frv_ifcvt.last_nested_if_cr = NULL_RTX; 6021 } 6022 6023 set = single_set_pattern (pattern); 6024 if (set) 6025 { 6026 rtx dest = SET_DEST (set); 6027 rtx src = SET_SRC (set); 6028 enum machine_mode mode = GET_MODE (dest); 6029 6030 /* Check for normal binary operators. */ 6031 if (mode == SImode && ARITHMETIC_P (src)) 6032 { 6033 op0 = XEXP (src, 0); 6034 op1 = XEXP (src, 1); 6035 6036 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1)) 6037 { 6038 op1 = frv_ifcvt_load_value (op1, insn); 6039 if (op1) 6040 COND_EXEC_CODE (pattern) 6041 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src), 6042 GET_MODE (src), 6043 op0, op1)); 6044 else 6045 goto fail; 6046 } 6047 } 6048 6049 /* For multiply by a constant, we need to handle the sign extending 6050 correctly. Add a USE of the value after the multiply to prevent flow 6051 from cratering because only one register out of the two were used. */ 6052 else if (mode == DImode && GET_CODE (src) == MULT) 6053 { 6054 op0 = XEXP (src, 0); 6055 op1 = XEXP (src, 1); 6056 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT) 6057 { 6058 op1 = frv_ifcvt_load_value (op1, insn); 6059 if (op1) 6060 { 6061 op1 = gen_rtx_SIGN_EXTEND (DImode, op1); 6062 COND_EXEC_CODE (pattern) 6063 = gen_rtx_SET (VOIDmode, dest, 6064 gen_rtx_MULT (DImode, op0, op1)); 6065 } 6066 else 6067 goto fail; 6068 } 6069 6070 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE); 6071 } 6072 6073 /* If we are just loading a constant created for a nested conditional 6074 execution statement, just load the constant without any conditional 6075 execution, since we know that the constant will not interfere with any 6076 other registers. */ 6077 else if (frv_ifcvt.scratch_insns_bitmap 6078 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap, 6079 INSN_UID (insn)) 6080 && REG_P (SET_DEST (set)) 6081 /* We must not unconditionally set a scratch reg chosen 6082 for a nested if-converted block if its incoming 6083 value from the TEST block (or the result of the THEN 6084 branch) could/should propagate to the JOIN block. 6085 It suffices to test whether the register is live at 6086 the JOIN point: if it's live there, we can infer 6087 that we set it in the former JOIN block of the 6088 nested if-converted block (otherwise it wouldn't 6089 have been available as a scratch register), and it 6090 is either propagated through or set in the other 6091 conditional block. It's probably not worth trying 6092 to catch the latter case, and it could actually 6093 limit scheduling of the combined block quite 6094 severely. */ 6095 && ce_info->join_bb 6096 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb), 6097 REGNO (SET_DEST (set)))) 6098 /* Similarly, we must not unconditionally set a reg 6099 used as scratch in the THEN branch if the same reg 6100 is live in the ELSE branch. */ 6101 && (! ce_info->else_bb 6102 || BLOCK_FOR_INSN (insn) == ce_info->else_bb 6103 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb), 6104 REGNO (SET_DEST (set)))))) 6105 pattern = set; 6106 6107 else if (mode == QImode || mode == HImode || mode == SImode 6108 || mode == SFmode) 6109 { 6110 int changed_p = FALSE; 6111 6112 /* Check for just loading up a constant */ 6113 if (CONSTANT_P (src) && integer_register_operand (dest, mode)) 6114 { 6115 src = frv_ifcvt_load_value (src, insn); 6116 if (!src) 6117 goto fail; 6118 6119 changed_p = TRUE; 6120 } 6121 6122 /* See if we need to fix up stores */ 6123 if (GET_CODE (dest) == MEM) 6124 { 6125 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn); 6126 6127 if (!new_mem) 6128 goto fail; 6129 6130 else if (new_mem != dest) 6131 { 6132 changed_p = TRUE; 6133 dest = new_mem; 6134 } 6135 } 6136 6137 /* See if we need to fix up loads */ 6138 if (GET_CODE (src) == MEM) 6139 { 6140 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn); 6141 6142 if (!new_mem) 6143 goto fail; 6144 6145 else if (new_mem != src) 6146 { 6147 changed_p = TRUE; 6148 src = new_mem; 6149 } 6150 } 6151 6152 /* If either src or destination changed, redo SET. */ 6153 if (changed_p) 6154 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src); 6155 } 6156 6157 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with 6158 rewriting the CC register to be the same as the paired CC/CR register 6159 for nested ifs. */ 6160 else if (mode == CC_CCRmode && COMPARISON_P (src)) 6161 { 6162 int regno = REGNO (XEXP (src, 0)); 6163 rtx if_else; 6164 6165 if (ce_info->pass > 1 6166 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg) 6167 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno)) 6168 { 6169 src = gen_rtx_fmt_ee (GET_CODE (src), 6170 CC_CCRmode, 6171 frv_ifcvt.nested_cc_reg, 6172 XEXP (src, 1)); 6173 } 6174 6175 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx); 6176 pattern = gen_rtx_SET (VOIDmode, dest, if_else); 6177 } 6178 6179 /* Remap a nested compare instruction to use the paired CC/CR reg. */ 6180 else if (ce_info->pass > 1 6181 && GET_CODE (dest) == REG 6182 && CC_P (REGNO (dest)) 6183 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg) 6184 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, 6185 REGNO (dest)) 6186 && GET_CODE (src) == COMPARE) 6187 { 6188 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest)); 6189 COND_EXEC_CODE (pattern) 6190 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src)); 6191 } 6192 } 6193 6194 if (TARGET_DEBUG_COND_EXEC) 6195 { 6196 rtx orig_pattern = PATTERN (insn); 6197 6198 PATTERN (insn) = pattern; 6199 fprintf (stderr, 6200 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n", 6201 ce_info->pass); 6202 6203 debug_rtx (insn); 6204 PATTERN (insn) = orig_pattern; 6205 } 6206 6207 return pattern; 6208 6209 fail: 6210 if (TARGET_DEBUG_COND_EXEC) 6211 { 6212 rtx orig_pattern = PATTERN (insn); 6213 6214 PATTERN (insn) = orig_ce_pattern; 6215 fprintf (stderr, 6216 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n", 6217 ce_info->pass); 6218 6219 debug_rtx (insn); 6220 PATTERN (insn) = orig_pattern; 6221 } 6222 6223 return NULL_RTX; 6224} 6225 6226 6227/* A C expression to perform any final machine dependent modifications in 6228 converting code to conditional execution in the code described by the 6229 conditional if information CE_INFO. */ 6230 6231void 6232frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) 6233{ 6234 rtx existing_insn; 6235 rtx check_insn; 6236 rtx p = frv_ifcvt.added_insns_list; 6237 int i; 6238 6239 /* Loop inserting the check insns. The last check insn is the first test, 6240 and is the appropriate place to insert constants. */ 6241 gcc_assert (p); 6242 6243 do 6244 { 6245 rtx check_and_insert_insns = XEXP (p, 0); 6246 rtx old_p = p; 6247 6248 check_insn = XEXP (check_and_insert_insns, 0); 6249 existing_insn = XEXP (check_and_insert_insns, 1); 6250 p = XEXP (p, 1); 6251 6252 /* The jump bit is used to say that the new insn is to be inserted BEFORE 6253 the existing insn, otherwise it is to be inserted AFTER. */ 6254 if (check_and_insert_insns->jump) 6255 { 6256 emit_insn_before (check_insn, existing_insn); 6257 check_and_insert_insns->jump = 0; 6258 } 6259 else 6260 emit_insn_after (check_insn, existing_insn); 6261 6262 free_EXPR_LIST_node (check_and_insert_insns); 6263 free_EXPR_LIST_node (old_p); 6264 } 6265 while (p != NULL_RTX); 6266 6267 /* Load up any constants needed into temp gprs */ 6268 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++) 6269 { 6270 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn); 6271 if (! frv_ifcvt.scratch_insns_bitmap) 6272 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL); 6273 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn)); 6274 frv_ifcvt.scratch_regs[i] = NULL_RTX; 6275 } 6276 6277 frv_ifcvt.added_insns_list = NULL_RTX; 6278 frv_ifcvt.cur_scratch_regs = 0; 6279} 6280 6281 6282/* A C expression to cancel any machine dependent modifications in converting 6283 code to conditional execution in the code described by the conditional if 6284 information CE_INFO. */ 6285 6286void 6287frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) 6288{ 6289 int i; 6290 rtx p = frv_ifcvt.added_insns_list; 6291 6292 /* Loop freeing up the EXPR_LIST's allocated. */ 6293 while (p != NULL_RTX) 6294 { 6295 rtx check_and_jump = XEXP (p, 0); 6296 rtx old_p = p; 6297 6298 p = XEXP (p, 1); 6299 free_EXPR_LIST_node (check_and_jump); 6300 free_EXPR_LIST_node (old_p); 6301 } 6302 6303 /* Release any temporary gprs allocated. */ 6304 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++) 6305 frv_ifcvt.scratch_regs[i] = NULL_RTX; 6306 6307 frv_ifcvt.added_insns_list = NULL_RTX; 6308 frv_ifcvt.cur_scratch_regs = 0; 6309 return; 6310} 6311 6312/* A C expression for the size in bytes of the trampoline, as an integer. 6313 The template is: 6314 6315 setlo #0, <jmp_reg> 6316 setlo #0, <static_chain> 6317 sethi #0, <jmp_reg> 6318 sethi #0, <static_chain> 6319 jmpl @(gr0,<jmp_reg>) */ 6320 6321int 6322frv_trampoline_size (void) 6323{ 6324 if (TARGET_FDPIC) 6325 /* Allocate room for the function descriptor and the lddi 6326 instruction. */ 6327 return 8 + 6 * 4; 6328 return 5 /* instructions */ * 4 /* instruction size. */; 6329} 6330 6331 6332/* A C statement to initialize the variable parts of a trampoline. ADDR is an 6333 RTX for the address of the trampoline; FNADDR is an RTX for the address of 6334 the nested function; STATIC_CHAIN is an RTX for the static chain value that 6335 should be passed to the function when it is called. 6336 6337 The template is: 6338 6339 setlo #0, <jmp_reg> 6340 setlo #0, <static_chain> 6341 sethi #0, <jmp_reg> 6342 sethi #0, <static_chain> 6343 jmpl @(gr0,<jmp_reg>) */ 6344 6345static void 6346frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain) 6347{ 6348 rtx addr = XEXP (m_tramp, 0); 6349 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); 6350 rtx sc_reg = force_reg (Pmode, static_chain); 6351 6352 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), 6353 FALSE, VOIDmode, 4, 6354 addr, Pmode, 6355 GEN_INT (frv_trampoline_size ()), SImode, 6356 fnaddr, Pmode, 6357 sc_reg, Pmode); 6358} 6359 6360 6361/* Many machines have some registers that cannot be copied directly to or from 6362 memory or even from other types of registers. An example is the `MQ' 6363 register, which on most machines, can only be copied to or from general 6364 registers, but not memory. Some machines allow copying all registers to and 6365 from memory, but require a scratch register for stores to some memory 6366 locations (e.g., those with symbolic address on the RT, and those with 6367 certain symbolic address on the SPARC when compiling PIC). In some cases, 6368 both an intermediate and a scratch register are required. 6369 6370 You should define these macros to indicate to the reload phase that it may 6371 need to allocate at least one register for a reload in addition to the 6372 register to contain the data. Specifically, if copying X to a register 6373 RCLASS in MODE requires an intermediate register, you should define 6374 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of 6375 whose registers can be used as intermediate registers or scratch registers. 6376 6377 If copying a register RCLASS in MODE to X requires an intermediate or scratch 6378 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the 6379 largest register class required. If the requirements for input and output 6380 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used 6381 instead of defining both macros identically. 6382 6383 The values returned by these macros are often `GENERAL_REGS'. Return 6384 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied 6385 to or from a register of RCLASS in MODE without requiring a scratch register. 6386 Do not define this macro if it would always return `NO_REGS'. 6387 6388 If a scratch register is required (either with or without an intermediate 6389 register), you should define patterns for `reload_inM' or `reload_outM', as 6390 required.. These patterns, which will normally be implemented with a 6391 `define_expand', should be similar to the `movM' patterns, except that 6392 operand 2 is the scratch register. 6393 6394 Define constraints for the reload register and scratch register that contain 6395 a single register class. If the original reload register (whose class is 6396 RCLASS) can meet the constraint given in the pattern, the value returned by 6397 these macros is used for the class of the scratch register. Otherwise, two 6398 additional reload registers are required. Their classes are obtained from 6399 the constraints in the insn pattern. 6400 6401 X might be a pseudo-register or a `subreg' of a pseudo-register, which could 6402 either be in a hard register or in memory. Use `true_regnum' to find out; 6403 it will return -1 if the pseudo is in memory and the hard register number if 6404 it is in a register. 6405 6406 These macros should not be used in the case where a particular class of 6407 registers can only be copied to memory and not to another class of 6408 registers. In that case, secondary reload registers are not needed and 6409 would not be helpful. Instead, a stack location must be used to perform the 6410 copy and the `movM' pattern should use memory as an intermediate storage. 6411 This case often occurs between floating-point and general registers. */ 6412 6413enum reg_class 6414frv_secondary_reload_class (enum reg_class rclass, 6415 enum machine_mode mode ATTRIBUTE_UNUSED, 6416 rtx x) 6417{ 6418 enum reg_class ret; 6419 6420 switch (rclass) 6421 { 6422 default: 6423 ret = NO_REGS; 6424 break; 6425 6426 /* Accumulators/Accumulator guard registers need to go through floating 6427 point registers. */ 6428 case QUAD_REGS: 6429 case EVEN_REGS: 6430 case GPR_REGS: 6431 ret = NO_REGS; 6432 if (x && GET_CODE (x) == REG) 6433 { 6434 int regno = REGNO (x); 6435 6436 if (ACC_P (regno) || ACCG_P (regno)) 6437 ret = FPR_REGS; 6438 } 6439 break; 6440 6441 /* Nonzero constants should be loaded into an FPR through a GPR. */ 6442 case QUAD_FPR_REGS: 6443 case FEVEN_REGS: 6444 case FPR_REGS: 6445 if (x && CONSTANT_P (x) && !ZERO_P (x)) 6446 ret = GPR_REGS; 6447 else 6448 ret = NO_REGS; 6449 break; 6450 6451 /* All of these types need gpr registers. */ 6452 case ICC_REGS: 6453 case FCC_REGS: 6454 case CC_REGS: 6455 case ICR_REGS: 6456 case FCR_REGS: 6457 case CR_REGS: 6458 case LCR_REG: 6459 case LR_REG: 6460 ret = GPR_REGS; 6461 break; 6462 6463 /* The accumulators need fpr registers. */ 6464 case ACC_REGS: 6465 case EVEN_ACC_REGS: 6466 case QUAD_ACC_REGS: 6467 case ACCG_REGS: 6468 ret = FPR_REGS; 6469 break; 6470 } 6471 6472 return ret; 6473} 6474 6475/* This hook exists to catch the case where secondary_reload_class() is 6476 called from init_reg_autoinc() in regclass.c - before the reload optabs 6477 have been initialised. */ 6478 6479static bool 6480frv_secondary_reload (bool in_p, rtx x, enum reg_class reload_class, 6481 enum machine_mode reload_mode, 6482 secondary_reload_info * sri) 6483{ 6484 enum reg_class rclass = NO_REGS; 6485 6486 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing) 6487 { 6488 sri->icode = sri->prev_sri->t_icode; 6489 return NO_REGS; 6490 } 6491 6492 rclass = frv_secondary_reload_class (reload_class, reload_mode, x); 6493 6494 if (rclass != NO_REGS) 6495 { 6496 enum insn_code icode = (in_p ? reload_in_optab[(int) reload_mode] 6497 : reload_out_optab[(int) reload_mode]); 6498 if (icode == 0) 6499 { 6500 /* This happens when then the reload_[in|out]_optabs have 6501 not been initialised. */ 6502 sri->t_icode = CODE_FOR_nothing; 6503 return rclass; 6504 } 6505 } 6506 6507 /* Fall back to the default secondary reload handler. */ 6508 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri); 6509 6510} 6511 6512/* A C expression whose value is nonzero if pseudos that have been assigned to 6513 registers of class RCLASS would likely be spilled because registers of RCLASS 6514 are needed for spill registers. 6515 6516 The default value of this macro returns 1 if RCLASS has exactly one register 6517 and zero otherwise. On most machines, this default should be used. Only 6518 define this macro to some other expression if pseudo allocated by 6519 `local-alloc.c' end up in memory because their hard registers were needed 6520 for spill registers. If this macro returns nonzero for those classes, those 6521 pseudos will only be allocated by `global.c', which knows how to reallocate 6522 the pseudo to another register. If there would not be another register 6523 available for reallocation, you should not change the definition of this 6524 macro since the only effect of such a definition would be to slow down 6525 register allocation. */ 6526 6527int 6528frv_class_likely_spilled_p (enum reg_class rclass) 6529{ 6530 switch (rclass) 6531 { 6532 default: 6533 break; 6534 6535 case GR8_REGS: 6536 case GR9_REGS: 6537 case GR89_REGS: 6538 case FDPIC_FPTR_REGS: 6539 case FDPIC_REGS: 6540 case ICC_REGS: 6541 case FCC_REGS: 6542 case CC_REGS: 6543 case ICR_REGS: 6544 case FCR_REGS: 6545 case CR_REGS: 6546 case LCR_REG: 6547 case LR_REG: 6548 case SPR_REGS: 6549 case QUAD_ACC_REGS: 6550 case EVEN_ACC_REGS: 6551 case ACC_REGS: 6552 case ACCG_REGS: 6553 return TRUE; 6554 } 6555 6556 return FALSE; 6557} 6558 6559 6560/* An expression for the alignment of a structure field FIELD if the 6561 alignment computed in the usual way is COMPUTED. GCC uses this 6562 value instead of the value in `BIGGEST_ALIGNMENT' or 6563 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */ 6564 6565/* The definition type of the bit field data is either char, short, long or 6566 long long. The maximum bit size is the number of bits of its own type. 6567 6568 The bit field data is assigned to a storage unit that has an adequate size 6569 for bit field data retention and is located at the smallest address. 6570 6571 Consecutive bit field data are packed at consecutive bits having the same 6572 storage unit, with regard to the type, beginning with the MSB and continuing 6573 toward the LSB. 6574 6575 If a field to be assigned lies over a bit field type boundary, its 6576 assignment is completed by aligning it with a boundary suitable for the 6577 type. 6578 6579 When a bit field having a bit length of 0 is declared, it is forcibly 6580 assigned to the next storage unit. 6581 6582 e.g) 6583 struct { 6584 int a:2; 6585 int b:6; 6586 char c:4; 6587 int d:10; 6588 int :0; 6589 int f:2; 6590 } x; 6591 6592 +0 +1 +2 +3 6593 &x 00000000 00000000 00000000 00000000 6594 MLM----L 6595 a b 6596 &x+4 00000000 00000000 00000000 00000000 6597 M--L 6598 c 6599 &x+8 00000000 00000000 00000000 00000000 6600 M----------L 6601 d 6602 &x+12 00000000 00000000 00000000 00000000 6603 ML 6604 f 6605*/ 6606 6607int 6608frv_adjust_field_align (tree field, int computed) 6609{ 6610 /* Make sure that the bitfield is not wider than the type. */ 6611 if (DECL_BIT_FIELD (field) 6612 && !DECL_ARTIFICIAL (field)) 6613 { 6614 tree parent = DECL_CONTEXT (field); 6615 tree prev = NULL_TREE; 6616 tree cur; 6617 6618 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur)) 6619 { 6620 if (TREE_CODE (cur) != FIELD_DECL) 6621 continue; 6622 6623 prev = cur; 6624 } 6625 6626 gcc_assert (cur); 6627 6628 /* If this isn't a :0 field and if the previous element is a bitfield 6629 also, see if the type is different, if so, we will need to align the 6630 bit-field to the next boundary. */ 6631 if (prev 6632 && ! DECL_PACKED (field) 6633 && ! integer_zerop (DECL_SIZE (field)) 6634 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev)) 6635 { 6636 int prev_align = TYPE_ALIGN (TREE_TYPE (prev)); 6637 int cur_align = TYPE_ALIGN (TREE_TYPE (field)); 6638 computed = (prev_align > cur_align) ? prev_align : cur_align; 6639 } 6640 } 6641 6642 return computed; 6643} 6644 6645 6646/* A C expression that is nonzero if it is permissible to store a value of mode 6647 MODE in hard register number REGNO (or in several registers starting with 6648 that one). For a machine where all registers are equivalent, a suitable 6649 definition is 6650 6651 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1 6652 6653 It is not necessary for this macro to check for the numbers of fixed 6654 registers, because the allocation mechanism considers them to be always 6655 occupied. 6656 6657 On some machines, double-precision values must be kept in even/odd register 6658 pairs. The way to implement that is to define this macro to reject odd 6659 register numbers for such modes. 6660 6661 The minimum requirement for a mode to be OK in a register is that the 6662 `movMODE' instruction pattern support moves between the register and any 6663 other hard register for which the mode is OK; and that moving a value into 6664 the register and back out not alter it. 6665 6666 Since the same instruction used to move `SImode' will work for all narrower 6667 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK' 6668 to distinguish between these modes, provided you define patterns `movhi', 6669 etc., to take advantage of this. This is useful because of the interaction 6670 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for 6671 all integer modes to be tieable. 6672 6673 Many machines have special registers for floating point arithmetic. Often 6674 people assume that floating point machine modes are allowed only in floating 6675 point registers. This is not true. Any registers that can hold integers 6676 can safely *hold* a floating point machine mode, whether or not floating 6677 arithmetic can be done on it in those registers. Integer move instructions 6678 can be used to move the values. 6679 6680 On some machines, though, the converse is true: fixed-point machine modes 6681 may not go in floating registers. This is true if the floating registers 6682 normalize any value stored in them, because storing a non-floating value 6683 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject 6684 fixed-point machine modes in floating registers. But if the floating 6685 registers do not automatically normalize, if you can store any bit pattern 6686 in one and retrieve it unchanged without a trap, then any machine mode may 6687 go in a floating register, so you can define this macro to say so. 6688 6689 The primary significance of special floating registers is rather that they 6690 are the registers acceptable in floating point arithmetic instructions. 6691 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by 6692 writing the proper constraints for those instructions. 6693 6694 On some machines, the floating registers are especially slow to access, so 6695 that it is better to store a value in a stack frame than in such a register 6696 if floating point arithmetic is not being done. As long as the floating 6697 registers are not in class `GENERAL_REGS', they will not be used unless some 6698 pattern's constraint asks for one. */ 6699 6700int 6701frv_hard_regno_mode_ok (int regno, enum machine_mode mode) 6702{ 6703 int base; 6704 int mask; 6705 6706 switch (mode) 6707 { 6708 case CCmode: 6709 case CC_UNSmode: 6710 case CC_NZmode: 6711 return ICC_P (regno) || GPR_P (regno); 6712 6713 case CC_CCRmode: 6714 return CR_P (regno) || GPR_P (regno); 6715 6716 case CC_FPmode: 6717 return FCC_P (regno) || GPR_P (regno); 6718 6719 default: 6720 break; 6721 } 6722 6723 /* Set BASE to the first register in REGNO's class. Set MASK to the 6724 bits that must be clear in (REGNO - BASE) for the register to be 6725 well-aligned. */ 6726 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)) 6727 { 6728 if (ACCG_P (regno)) 6729 { 6730 /* ACCGs store one byte. Two-byte quantities must start in 6731 even-numbered registers, four-byte ones in registers whose 6732 numbers are divisible by four, and so on. */ 6733 base = ACCG_FIRST; 6734 mask = GET_MODE_SIZE (mode) - 1; 6735 } 6736 else 6737 { 6738 /* The other registers store one word. */ 6739 if (GPR_P (regno) || regno == AP_FIRST) 6740 base = GPR_FIRST; 6741 6742 else if (FPR_P (regno)) 6743 base = FPR_FIRST; 6744 6745 else if (ACC_P (regno)) 6746 base = ACC_FIRST; 6747 6748 else if (SPR_P (regno)) 6749 return mode == SImode; 6750 6751 /* Fill in the table. */ 6752 else 6753 return 0; 6754 6755 /* Anything smaller than an SI is OK in any word-sized register. */ 6756 if (GET_MODE_SIZE (mode) < 4) 6757 return 1; 6758 6759 mask = (GET_MODE_SIZE (mode) / 4) - 1; 6760 } 6761 return (((regno - base) & mask) == 0); 6762 } 6763 6764 return 0; 6765} 6766 6767 6768/* A C expression for the number of consecutive hard registers, starting at 6769 register number REGNO, required to hold a value of mode MODE. 6770 6771 On a machine where all registers are exactly one word, a suitable definition 6772 of this macro is 6773 6774 #define HARD_REGNO_NREGS(REGNO, MODE) \ 6775 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \ 6776 / UNITS_PER_WORD)) */ 6777 6778/* On the FRV, make the CC_FP mode take 3 words in the integer registers, so 6779 that we can build the appropriate instructions to properly reload the 6780 values. Also, make the byte-sized accumulator guards use one guard 6781 for each byte. */ 6782 6783int 6784frv_hard_regno_nregs (int regno, enum machine_mode mode) 6785{ 6786 if (ACCG_P (regno)) 6787 return GET_MODE_SIZE (mode); 6788 else 6789 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 6790} 6791 6792 6793/* A C expression for the maximum number of consecutive registers of 6794 class RCLASS needed to hold a value of mode MODE. 6795 6796 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value 6797 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of 6798 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS. 6799 6800 This macro helps control the handling of multiple-word values in 6801 the reload pass. 6802 6803 This declaration is required. */ 6804 6805int 6806frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode) 6807{ 6808 if (rclass == ACCG_REGS) 6809 /* An N-byte value requires N accumulator guards. */ 6810 return GET_MODE_SIZE (mode); 6811 else 6812 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 6813} 6814 6815 6816/* A C expression that is nonzero if X is a legitimate constant for an 6817 immediate operand on the target machine. You can assume that X satisfies 6818 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable 6819 definition for this macro on machines where anything `CONSTANT_P' is valid. */ 6820 6821int 6822frv_legitimate_constant_p (rtx x) 6823{ 6824 enum machine_mode mode = GET_MODE (x); 6825 6826 /* frv_cannot_force_const_mem always returns true for FDPIC. This 6827 means that the move expanders will be expected to deal with most 6828 kinds of constant, regardless of what we return here. 6829 6830 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether 6831 a constant can be entered into reg_equiv_constant[]. If we return true, 6832 reload can create new instances of the constant whenever it likes. 6833 6834 The idea is therefore to accept as many constants as possible (to give 6835 reload more freedom) while rejecting constants that can only be created 6836 at certain times. In particular, anything with a symbolic component will 6837 require use of the pseudo FDPIC register, which is only available before 6838 reload. */ 6839 if (TARGET_FDPIC) 6840 return LEGITIMATE_PIC_OPERAND_P (x); 6841 6842 /* All of the integer constants are ok. */ 6843 if (GET_CODE (x) != CONST_DOUBLE) 6844 return TRUE; 6845 6846 /* double integer constants are ok. */ 6847 if (mode == VOIDmode || mode == DImode) 6848 return TRUE; 6849 6850 /* 0 is always ok. */ 6851 if (x == CONST0_RTX (mode)) 6852 return TRUE; 6853 6854 /* If floating point is just emulated, allow any constant, since it will be 6855 constructed in the GPRs. */ 6856 if (!TARGET_HAS_FPRS) 6857 return TRUE; 6858 6859 if (mode == DFmode && !TARGET_DOUBLE) 6860 return TRUE; 6861 6862 /* Otherwise store the constant away and do a load. */ 6863 return FALSE; 6864} 6865 6866/* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons, 6867 CC_NZ for comparisons against zero in which a single Z or N flag test 6868 is enough, CC_UNS for other unsigned comparisons, and CC for other 6869 signed comparisons. */ 6870 6871enum machine_mode 6872frv_select_cc_mode (enum rtx_code code, rtx x, rtx y) 6873{ 6874 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 6875 return CC_FPmode; 6876 6877 switch (code) 6878 { 6879 case EQ: 6880 case NE: 6881 case LT: 6882 case GE: 6883 return y == const0_rtx ? CC_NZmode : CCmode; 6884 6885 case GTU: 6886 case GEU: 6887 case LTU: 6888 case LEU: 6889 return y == const0_rtx ? CC_NZmode : CC_UNSmode; 6890 6891 default: 6892 return CCmode; 6893 } 6894} 6895 6896/* A C expression for the cost of moving data from a register in class FROM to 6897 one in class TO. The classes are expressed using the enumeration values 6898 such as `GENERAL_REGS'. A value of 4 is the default; other values are 6899 interpreted relative to that. 6900 6901 It is not required that the cost always equal 2 when FROM is the same as TO; 6902 on some machines it is expensive to move between registers if they are not 6903 general registers. 6904 6905 If reload sees an insn consisting of a single `set' between two hard 6906 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a 6907 value of 2, reload does not check to ensure that the constraints of the insn 6908 are met. Setting a cost of other than 2 will allow reload to verify that 6909 the constraints are met. You should do this if the `movM' pattern's 6910 constraints do not allow such copying. */ 6911 6912#define HIGH_COST 40 6913#define MEDIUM_COST 3 6914#define LOW_COST 1 6915 6916int 6917frv_register_move_cost (enum reg_class from, enum reg_class to) 6918{ 6919 switch (from) 6920 { 6921 default: 6922 break; 6923 6924 case QUAD_REGS: 6925 case EVEN_REGS: 6926 case GPR_REGS: 6927 switch (to) 6928 { 6929 default: 6930 break; 6931 6932 case QUAD_REGS: 6933 case EVEN_REGS: 6934 case GPR_REGS: 6935 return LOW_COST; 6936 6937 case FEVEN_REGS: 6938 case FPR_REGS: 6939 return LOW_COST; 6940 6941 case LCR_REG: 6942 case LR_REG: 6943 case SPR_REGS: 6944 return LOW_COST; 6945 } 6946 6947 case FEVEN_REGS: 6948 case FPR_REGS: 6949 switch (to) 6950 { 6951 default: 6952 break; 6953 6954 case QUAD_REGS: 6955 case EVEN_REGS: 6956 case GPR_REGS: 6957 case ACC_REGS: 6958 case EVEN_ACC_REGS: 6959 case QUAD_ACC_REGS: 6960 case ACCG_REGS: 6961 return MEDIUM_COST; 6962 6963 case FEVEN_REGS: 6964 case FPR_REGS: 6965 return LOW_COST; 6966 } 6967 6968 case LCR_REG: 6969 case LR_REG: 6970 case SPR_REGS: 6971 switch (to) 6972 { 6973 default: 6974 break; 6975 6976 case QUAD_REGS: 6977 case EVEN_REGS: 6978 case GPR_REGS: 6979 return MEDIUM_COST; 6980 } 6981 6982 case ACC_REGS: 6983 case EVEN_ACC_REGS: 6984 case QUAD_ACC_REGS: 6985 case ACCG_REGS: 6986 switch (to) 6987 { 6988 default: 6989 break; 6990 6991 case FEVEN_REGS: 6992 case FPR_REGS: 6993 return MEDIUM_COST; 6994 6995 } 6996 } 6997 6998 return HIGH_COST; 6999} 7000 7001/* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to 7002 use ".picptr" to generate safe relocations for PIC code. We also 7003 need a fixup entry for aligned (non-debugging) code. */ 7004 7005static bool 7006frv_assemble_integer (rtx value, unsigned int size, int aligned_p) 7007{ 7008 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD) 7009 { 7010 if (GET_CODE (value) == CONST 7011 || GET_CODE (value) == SYMBOL_REF 7012 || GET_CODE (value) == LABEL_REF) 7013 { 7014 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF 7015 && SYMBOL_REF_FUNCTION_P (value)) 7016 { 7017 fputs ("\t.picptr\tfuncdesc(", asm_out_file); 7018 output_addr_const (asm_out_file, value); 7019 fputs (")\n", asm_out_file); 7020 return true; 7021 } 7022 else if (TARGET_FDPIC && GET_CODE (value) == CONST 7023 && frv_function_symbol_referenced_p (value)) 7024 return false; 7025 if (aligned_p && !TARGET_FDPIC) 7026 { 7027 static int label_num = 0; 7028 char buf[256]; 7029 const char *p; 7030 7031 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++); 7032 p = (* targetm.strip_name_encoding) (buf); 7033 7034 fprintf (asm_out_file, "%s:\n", p); 7035 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP); 7036 fprintf (asm_out_file, "\t.picptr\t%s\n", p); 7037 fprintf (asm_out_file, "\t.previous\n"); 7038 } 7039 assemble_integer_with_op ("\t.picptr\t", value); 7040 return true; 7041 } 7042 if (!aligned_p) 7043 { 7044 /* We've set the unaligned SI op to NULL, so we always have to 7045 handle the unaligned case here. */ 7046 assemble_integer_with_op ("\t.4byte\t", value); 7047 return true; 7048 } 7049 } 7050 return default_assemble_integer (value, size, aligned_p); 7051} 7052 7053/* Function to set up the backend function structure. */ 7054 7055static struct machine_function * 7056frv_init_machine_status (void) 7057{ 7058 return GGC_CNEW (struct machine_function); 7059} 7060 7061/* Implement TARGET_SCHED_ISSUE_RATE. */ 7062 7063int 7064frv_issue_rate (void) 7065{ 7066 if (!TARGET_PACK) 7067 return 1; 7068 7069 switch (frv_cpu_type) 7070 { 7071 default: 7072 case FRV_CPU_FR300: 7073 case FRV_CPU_SIMPLE: 7074 return 1; 7075 7076 case FRV_CPU_FR400: 7077 case FRV_CPU_FR405: 7078 case FRV_CPU_FR450: 7079 return 2; 7080 7081 case FRV_CPU_GENERIC: 7082 case FRV_CPU_FR500: 7083 case FRV_CPU_TOMCAT: 7084 return 4; 7085 7086 case FRV_CPU_FR550: 7087 return 8; 7088 } 7089} 7090 7091/* A for_each_rtx callback. If X refers to an accumulator, return 7092 ACC_GROUP_ODD if the bit 2 of the register number is set and 7093 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE) 7094 otherwise. */ 7095 7096static int 7097frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED) 7098{ 7099 if (REG_P (*x)) 7100 { 7101 if (ACC_P (REGNO (*x))) 7102 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN; 7103 if (ACCG_P (REGNO (*x))) 7104 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN; 7105 } 7106 return 0; 7107} 7108 7109/* Return the value of INSN's acc_group attribute. */ 7110 7111int 7112frv_acc_group (rtx insn) 7113{ 7114 /* This distinction only applies to the FR550 packing constraints. */ 7115 if (frv_cpu_type != FRV_CPU_FR550) 7116 return ACC_GROUP_NONE; 7117 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0); 7118} 7119 7120/* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction 7121 INSN will try to claim first. Since this value depends only on the 7122 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */ 7123 7124static unsigned int 7125frv_insn_unit (rtx insn) 7126{ 7127 enum attr_type type; 7128 7129 type = get_attr_type (insn); 7130 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes)) 7131 { 7132 /* We haven't seen this type of instruction before. */ 7133 state_t state; 7134 unsigned int unit; 7135 7136 /* Issue the instruction on its own to see which unit it prefers. */ 7137 state = alloca (state_size ()); 7138 state_reset (state); 7139 state_transition (state, insn); 7140 7141 /* Find out which unit was taken. */ 7142 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++) 7143 if (cpu_unit_reservation_p (state, frv_unit_codes[unit])) 7144 break; 7145 7146 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes)); 7147 7148 frv_type_to_unit[type] = unit; 7149 } 7150 return frv_type_to_unit[type]; 7151} 7152 7153/* Return true if INSN issues to a branch unit. */ 7154 7155static bool 7156frv_issues_to_branch_unit_p (rtx insn) 7157{ 7158 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B; 7159} 7160 7161/* The current state of the packing pass, implemented by frv_pack_insns. */ 7162static struct { 7163 /* The state of the pipeline DFA. */ 7164 state_t dfa_state; 7165 7166 /* Which hardware registers are set within the current packet, 7167 and the conditions under which they are set. */ 7168 regstate_t regstate[FIRST_PSEUDO_REGISTER]; 7169 7170 /* The memory locations that have been modified so far in this 7171 packet. MEM is the memref and COND is the regstate_t condition 7172 under which it is set. */ 7173 struct { 7174 rtx mem; 7175 regstate_t cond; 7176 } mems[2]; 7177 7178 /* The number of valid entries in MEMS. The value is larger than 7179 ARRAY_SIZE (mems) if there were too many mems to record. */ 7180 unsigned int num_mems; 7181 7182 /* The maximum number of instructions that can be packed together. */ 7183 unsigned int issue_rate; 7184 7185 /* The instructions in the packet, partitioned into groups. */ 7186 struct frv_packet_group { 7187 /* How many instructions in the packet belong to this group. */ 7188 unsigned int num_insns; 7189 7190 /* A list of the instructions that belong to this group, in the order 7191 they appear in the rtl stream. */ 7192 rtx insns[ARRAY_SIZE (frv_unit_codes)]; 7193 7194 /* The contents of INSNS after they have been sorted into the correct 7195 assembly-language order. Element X issues to unit X. The list may 7196 contain extra nops. */ 7197 rtx sorted[ARRAY_SIZE (frv_unit_codes)]; 7198 7199 /* The member of frv_nops[] to use in sorted[]. */ 7200 rtx nop; 7201 } groups[NUM_GROUPS]; 7202 7203 /* The instructions that make up the current packet. */ 7204 rtx insns[ARRAY_SIZE (frv_unit_codes)]; 7205 unsigned int num_insns; 7206} frv_packet; 7207 7208/* Return the regstate_t flags for the given COND_EXEC condition. 7209 Abort if the condition isn't in the right form. */ 7210 7211static int 7212frv_cond_flags (rtx cond) 7213{ 7214 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE) 7215 && GET_CODE (XEXP (cond, 0)) == REG 7216 && CR_P (REGNO (XEXP (cond, 0))) 7217 && XEXP (cond, 1) == const0_rtx); 7218 return ((REGNO (XEXP (cond, 0)) - CR_FIRST) 7219 | (GET_CODE (cond) == NE 7220 ? REGSTATE_IF_TRUE 7221 : REGSTATE_IF_FALSE)); 7222} 7223 7224 7225/* Return true if something accessed under condition COND2 can 7226 conflict with something written under condition COND1. */ 7227 7228static bool 7229frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2) 7230{ 7231 /* If either reference was unconditional, we have a conflict. */ 7232 if ((cond1 & REGSTATE_IF_EITHER) == 0 7233 || (cond2 & REGSTATE_IF_EITHER) == 0) 7234 return true; 7235 7236 /* The references might conflict if they were controlled by 7237 different CRs. */ 7238 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK)) 7239 return true; 7240 7241 /* They definitely conflict if they are controlled by the 7242 same condition. */ 7243 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0) 7244 return true; 7245 7246 return false; 7247} 7248 7249 7250/* A for_each_rtx callback. Return 1 if *X depends on an instruction in 7251 the current packet. DATA points to a regstate_t that describes the 7252 condition under which *X might be set or used. */ 7253 7254static int 7255frv_registers_conflict_p_1 (rtx *x, void *data) 7256{ 7257 unsigned int regno, i; 7258 regstate_t cond; 7259 7260 cond = *(regstate_t *) data; 7261 7262 if (GET_CODE (*x) == REG) 7263 FOR_EACH_REGNO (regno, *x) 7264 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0) 7265 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond)) 7266 return 1; 7267 7268 if (GET_CODE (*x) == MEM) 7269 { 7270 /* If we ran out of memory slots, assume a conflict. */ 7271 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems)) 7272 return 1; 7273 7274 /* Check for output or true dependencies with earlier MEMs. */ 7275 for (i = 0; i < frv_packet.num_mems; i++) 7276 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond)) 7277 { 7278 if (true_dependence (frv_packet.mems[i].mem, VOIDmode, 7279 *x, rtx_varies_p)) 7280 return 1; 7281 7282 if (output_dependence (frv_packet.mems[i].mem, *x)) 7283 return 1; 7284 } 7285 } 7286 7287 /* The return values of calls aren't significant: they describe 7288 the effect of the call as a whole, not of the insn itself. */ 7289 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL) 7290 { 7291 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data)) 7292 return 1; 7293 return -1; 7294 } 7295 7296 /* Check subexpressions. */ 7297 return 0; 7298} 7299 7300 7301/* Return true if something in X might depend on an instruction 7302 in the current packet. */ 7303 7304static bool 7305frv_registers_conflict_p (rtx x) 7306{ 7307 regstate_t flags; 7308 7309 flags = 0; 7310 if (GET_CODE (x) == COND_EXEC) 7311 { 7312 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags)) 7313 return true; 7314 7315 flags |= frv_cond_flags (XEXP (x, 0)); 7316 x = XEXP (x, 1); 7317 } 7318 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags); 7319} 7320 7321 7322/* A note_stores callback. DATA points to the regstate_t condition 7323 under which X is modified. Update FRV_PACKET accordingly. */ 7324 7325static void 7326frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) 7327{ 7328 unsigned int regno; 7329 7330 if (GET_CODE (x) == REG) 7331 FOR_EACH_REGNO (regno, x) 7332 frv_packet.regstate[regno] |= *(regstate_t *) data; 7333 7334 if (GET_CODE (x) == MEM) 7335 { 7336 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems)) 7337 { 7338 frv_packet.mems[frv_packet.num_mems].mem = x; 7339 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data; 7340 } 7341 frv_packet.num_mems++; 7342 } 7343} 7344 7345 7346/* Update the register state information for an instruction whose 7347 body is X. */ 7348 7349static void 7350frv_registers_update (rtx x) 7351{ 7352 regstate_t flags; 7353 7354 flags = REGSTATE_MODIFIED; 7355 if (GET_CODE (x) == COND_EXEC) 7356 { 7357 flags |= frv_cond_flags (XEXP (x, 0)); 7358 x = XEXP (x, 1); 7359 } 7360 note_stores (x, frv_registers_update_1, &flags); 7361} 7362 7363 7364/* Initialize frv_packet for the start of a new packet. */ 7365 7366static void 7367frv_start_packet (void) 7368{ 7369 enum frv_insn_group group; 7370 7371 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate)); 7372 frv_packet.num_mems = 0; 7373 frv_packet.num_insns = 0; 7374 for (group = 0; group < NUM_GROUPS; group++) 7375 frv_packet.groups[group].num_insns = 0; 7376} 7377 7378 7379/* Likewise for the start of a new basic block. */ 7380 7381static void 7382frv_start_packet_block (void) 7383{ 7384 state_reset (frv_packet.dfa_state); 7385 frv_start_packet (); 7386} 7387 7388 7389/* Finish the current packet, if any, and start a new one. Call 7390 HANDLE_PACKET with FRV_PACKET describing the completed packet. */ 7391 7392static void 7393frv_finish_packet (void (*handle_packet) (void)) 7394{ 7395 if (frv_packet.num_insns > 0) 7396 { 7397 handle_packet (); 7398 state_transition (frv_packet.dfa_state, 0); 7399 frv_start_packet (); 7400 } 7401} 7402 7403 7404/* Return true if INSN can be added to the current packet. Update 7405 the DFA state on success. */ 7406 7407static bool 7408frv_pack_insn_p (rtx insn) 7409{ 7410 /* See if the packet is already as long as it can be. */ 7411 if (frv_packet.num_insns == frv_packet.issue_rate) 7412 return false; 7413 7414 /* If the scheduler thought that an instruction should start a packet, 7415 it's usually a good idea to believe it. It knows much more about 7416 the latencies than we do. 7417 7418 There are some exceptions though: 7419 7420 - Conditional instructions are scheduled on the assumption that 7421 they will be executed. This is usually a good thing, since it 7422 tends to avoid unnecessary stalls in the conditional code. 7423 But we want to pack conditional instructions as tightly as 7424 possible, in order to optimize the case where they aren't 7425 executed. 7426 7427 - The scheduler will always put branches on their own, even 7428 if there's no real dependency. 7429 7430 - There's no point putting a call in its own packet unless 7431 we have to. */ 7432 if (frv_packet.num_insns > 0 7433 && GET_CODE (insn) == INSN 7434 && GET_MODE (insn) == TImode 7435 && GET_CODE (PATTERN (insn)) != COND_EXEC) 7436 return false; 7437 7438 /* Check for register conflicts. Don't do this for setlo since any 7439 conflict will be with the partnering sethi, with which it can 7440 be packed. */ 7441 if (get_attr_type (insn) != TYPE_SETLO) 7442 if (frv_registers_conflict_p (PATTERN (insn))) 7443 return false; 7444 7445 return state_transition (frv_packet.dfa_state, insn) < 0; 7446} 7447 7448 7449/* Add instruction INSN to the current packet. */ 7450 7451static void 7452frv_add_insn_to_packet (rtx insn) 7453{ 7454 struct frv_packet_group *packet_group; 7455 7456 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]]; 7457 packet_group->insns[packet_group->num_insns++] = insn; 7458 frv_packet.insns[frv_packet.num_insns++] = insn; 7459 7460 frv_registers_update (PATTERN (insn)); 7461} 7462 7463 7464/* Insert INSN (a member of frv_nops[]) into the current packet. If the 7465 packet ends in a branch or call, insert the nop before it, otherwise 7466 add to the end. */ 7467 7468static void 7469frv_insert_nop_in_packet (rtx insn) 7470{ 7471 struct frv_packet_group *packet_group; 7472 rtx last; 7473 7474 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]]; 7475 last = frv_packet.insns[frv_packet.num_insns - 1]; 7476 if (GET_CODE (last) != INSN) 7477 { 7478 insn = emit_insn_before (PATTERN (insn), last); 7479 frv_packet.insns[frv_packet.num_insns - 1] = insn; 7480 frv_packet.insns[frv_packet.num_insns++] = last; 7481 } 7482 else 7483 { 7484 insn = emit_insn_after (PATTERN (insn), last); 7485 frv_packet.insns[frv_packet.num_insns++] = insn; 7486 } 7487 packet_group->insns[packet_group->num_insns++] = insn; 7488} 7489 7490 7491/* If packing is enabled, divide the instructions into packets and 7492 return true. Call HANDLE_PACKET for each complete packet. */ 7493 7494static bool 7495frv_for_each_packet (void (*handle_packet) (void)) 7496{ 7497 rtx insn, next_insn; 7498 7499 frv_packet.issue_rate = frv_issue_rate (); 7500 7501 /* Early exit if we don't want to pack insns. */ 7502 if (!optimize 7503 || !flag_schedule_insns_after_reload 7504 || !TARGET_VLIW_BRANCH 7505 || frv_packet.issue_rate == 1) 7506 return false; 7507 7508 /* Set up the initial packing state. */ 7509 dfa_start (); 7510 frv_packet.dfa_state = alloca (state_size ()); 7511 7512 frv_start_packet_block (); 7513 for (insn = get_insns (); insn != 0; insn = next_insn) 7514 { 7515 enum rtx_code code; 7516 bool eh_insn_p; 7517 7518 code = GET_CODE (insn); 7519 next_insn = NEXT_INSN (insn); 7520 7521 if (code == CODE_LABEL) 7522 { 7523 frv_finish_packet (handle_packet); 7524 frv_start_packet_block (); 7525 } 7526 7527 if (INSN_P (insn)) 7528 switch (GET_CODE (PATTERN (insn))) 7529 { 7530 case USE: 7531 case CLOBBER: 7532 case ADDR_VEC: 7533 case ADDR_DIFF_VEC: 7534 break; 7535 7536 default: 7537 /* Calls mustn't be packed on a TOMCAT. */ 7538 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT) 7539 frv_finish_packet (handle_packet); 7540 7541 /* Since the last instruction in a packet determines the EH 7542 region, any exception-throwing instruction must come at 7543 the end of reordered packet. Insns that issue to a 7544 branch unit are bound to come last; for others it's 7545 too hard to predict. */ 7546 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL); 7547 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn)) 7548 frv_finish_packet (handle_packet); 7549 7550 /* Finish the current packet if we can't add INSN to it. 7551 Simulate cycles until INSN is ready to issue. */ 7552 if (!frv_pack_insn_p (insn)) 7553 { 7554 frv_finish_packet (handle_packet); 7555 while (!frv_pack_insn_p (insn)) 7556 state_transition (frv_packet.dfa_state, 0); 7557 } 7558 7559 /* Add the instruction to the packet. */ 7560 frv_add_insn_to_packet (insn); 7561 7562 /* Calls and jumps end a packet, as do insns that throw 7563 an exception. */ 7564 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p) 7565 frv_finish_packet (handle_packet); 7566 break; 7567 } 7568 } 7569 frv_finish_packet (handle_packet); 7570 dfa_finish (); 7571 return true; 7572} 7573 7574/* Subroutine of frv_sort_insn_group. We are trying to sort 7575 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly 7576 language order. We have already picked a new position for 7577 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set. 7578 These instructions will occupy elements [0, LOWER_SLOT) and 7579 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is 7580 the DFA state after issuing these instructions. 7581 7582 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation 7583 of the unused instructions. Return true if one such permutation gives 7584 a valid ordering, leaving the successful permutation in sorted[]. 7585 Do not modify sorted[] until a valid permutation is found. */ 7586 7587static bool 7588frv_sort_insn_group_1 (enum frv_insn_group group, 7589 unsigned int lower_slot, unsigned int upper_slot, 7590 unsigned int issued, unsigned int num_insns, 7591 state_t state) 7592{ 7593 struct frv_packet_group *packet_group; 7594 unsigned int i; 7595 state_t test_state; 7596 size_t dfa_size; 7597 rtx insn; 7598 7599 /* Early success if we've filled all the slots. */ 7600 if (lower_slot == upper_slot) 7601 return true; 7602 7603 packet_group = &frv_packet.groups[group]; 7604 dfa_size = state_size (); 7605 test_state = alloca (dfa_size); 7606 7607 /* Try issuing each unused instruction. */ 7608 for (i = num_insns - 1; i + 1 != 0; i--) 7609 if (~issued & (1 << i)) 7610 { 7611 insn = packet_group->sorted[i]; 7612 memcpy (test_state, state, dfa_size); 7613 if (state_transition (test_state, insn) < 0 7614 && cpu_unit_reservation_p (test_state, 7615 NTH_UNIT (group, upper_slot - 1)) 7616 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1, 7617 issued | (1 << i), num_insns, 7618 test_state)) 7619 { 7620 packet_group->sorted[upper_slot - 1] = insn; 7621 return true; 7622 } 7623 } 7624 7625 return false; 7626} 7627 7628/* Compare two instructions by their frv_insn_unit. */ 7629 7630static int 7631frv_compare_insns (const void *first, const void *second) 7632{ 7633 const rtx *const insn1 = (rtx const *) first, 7634 *const insn2 = (rtx const *) second; 7635 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2); 7636} 7637 7638/* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[] 7639 and sort it into assembly language order. See frv.md for a description of 7640 the algorithm. */ 7641 7642static void 7643frv_sort_insn_group (enum frv_insn_group group) 7644{ 7645 struct frv_packet_group *packet_group; 7646 unsigned int first, i, nop, max_unit, num_slots; 7647 state_t state, test_state; 7648 size_t dfa_size; 7649 7650 packet_group = &frv_packet.groups[group]; 7651 7652 /* Assume no nop is needed. */ 7653 packet_group->nop = 0; 7654 7655 if (packet_group->num_insns == 0) 7656 return; 7657 7658 /* Copy insns[] to sorted[]. */ 7659 memcpy (packet_group->sorted, packet_group->insns, 7660 sizeof (rtx) * packet_group->num_insns); 7661 7662 /* Sort sorted[] by the unit that each insn tries to take first. */ 7663 if (packet_group->num_insns > 1) 7664 qsort (packet_group->sorted, packet_group->num_insns, 7665 sizeof (rtx), frv_compare_insns); 7666 7667 /* That's always enough for branch and control insns. */ 7668 if (group == GROUP_B || group == GROUP_C) 7669 return; 7670 7671 dfa_size = state_size (); 7672 state = alloca (dfa_size); 7673 test_state = alloca (dfa_size); 7674 7675 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue 7676 consecutively and such that the DFA takes unit X when sorted[X] 7677 is added. Set STATE to the new DFA state. */ 7678 state_reset (test_state); 7679 for (first = 0; first < packet_group->num_insns; first++) 7680 { 7681 memcpy (state, test_state, dfa_size); 7682 if (state_transition (test_state, packet_group->sorted[first]) >= 0 7683 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first))) 7684 break; 7685 } 7686 7687 /* If all the instructions issued in ascending order, we're done. */ 7688 if (first == packet_group->num_insns) 7689 return; 7690 7691 /* Add nops to the end of sorted[] and try each permutation until 7692 we find one that works. */ 7693 for (nop = 0; nop < frv_num_nops; nop++) 7694 { 7695 max_unit = frv_insn_unit (frv_nops[nop]); 7696 if (frv_unit_groups[max_unit] == group) 7697 { 7698 packet_group->nop = frv_nops[nop]; 7699 num_slots = UNIT_NUMBER (max_unit) + 1; 7700 for (i = packet_group->num_insns; i < num_slots; i++) 7701 packet_group->sorted[i] = frv_nops[nop]; 7702 if (frv_sort_insn_group_1 (group, first, num_slots, 7703 (1 << first) - 1, num_slots, state)) 7704 return; 7705 } 7706 } 7707 gcc_unreachable (); 7708} 7709 7710/* Sort the current packet into assembly-language order. Set packing 7711 flags as appropriate. */ 7712 7713static void 7714frv_reorder_packet (void) 7715{ 7716 unsigned int cursor[NUM_GROUPS]; 7717 rtx insns[ARRAY_SIZE (frv_unit_groups)]; 7718 unsigned int unit, to, from; 7719 enum frv_insn_group group; 7720 struct frv_packet_group *packet_group; 7721 7722 /* First sort each group individually. */ 7723 for (group = 0; group < NUM_GROUPS; group++) 7724 { 7725 cursor[group] = 0; 7726 frv_sort_insn_group (group); 7727 } 7728 7729 /* Go through the unit template and try add an instruction from 7730 that unit's group. */ 7731 to = 0; 7732 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++) 7733 { 7734 group = frv_unit_groups[unit]; 7735 packet_group = &frv_packet.groups[group]; 7736 if (cursor[group] < packet_group->num_insns) 7737 { 7738 /* frv_reorg should have added nops for us. */ 7739 gcc_assert (packet_group->sorted[cursor[group]] 7740 != packet_group->nop); 7741 insns[to++] = packet_group->sorted[cursor[group]++]; 7742 } 7743 } 7744 7745 gcc_assert (to == frv_packet.num_insns); 7746 7747 /* Clear the last instruction's packing flag, thus marking the end of 7748 a packet. Reorder the other instructions relative to it. */ 7749 CLEAR_PACKING_FLAG (insns[to - 1]); 7750 for (from = 0; from < to - 1; from++) 7751 { 7752 remove_insn (insns[from]); 7753 add_insn_before (insns[from], insns[to - 1], NULL); 7754 SET_PACKING_FLAG (insns[from]); 7755 } 7756} 7757 7758 7759/* Divide instructions into packets. Reorder the contents of each 7760 packet so that they are in the correct assembly-language order. 7761 7762 Since this pass can change the raw meaning of the rtl stream, it must 7763 only be called at the last minute, just before the instructions are 7764 written out. */ 7765 7766static void 7767frv_pack_insns (void) 7768{ 7769 if (frv_for_each_packet (frv_reorder_packet)) 7770 frv_insn_packing_flag = 0; 7771 else 7772 frv_insn_packing_flag = -1; 7773} 7774 7775/* See whether we need to add nops to group GROUP in order to 7776 make a valid packet. */ 7777 7778static void 7779frv_fill_unused_units (enum frv_insn_group group) 7780{ 7781 unsigned int non_nops, nops, i; 7782 struct frv_packet_group *packet_group; 7783 7784 packet_group = &frv_packet.groups[group]; 7785 7786 /* Sort the instructions into assembly-language order. 7787 Use nops to fill slots that are otherwise unused. */ 7788 frv_sort_insn_group (group); 7789 7790 /* See how many nops are needed before the final useful instruction. */ 7791 i = nops = 0; 7792 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++) 7793 while (packet_group->sorted[i++] == packet_group->nop) 7794 nops++; 7795 7796 /* Insert that many nops into the instruction stream. */ 7797 while (nops-- > 0) 7798 frv_insert_nop_in_packet (packet_group->nop); 7799} 7800 7801/* Return true if accesses IO1 and IO2 refer to the same doubleword. */ 7802 7803static bool 7804frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2) 7805{ 7806 if (io1->const_address != 0 && io2->const_address != 0) 7807 return io1->const_address == io2->const_address; 7808 7809 if (io1->var_address != 0 && io2->var_address != 0) 7810 return rtx_equal_p (io1->var_address, io2->var_address); 7811 7812 return false; 7813} 7814 7815/* Return true if operations IO1 and IO2 are guaranteed to complete 7816 in order. */ 7817 7818static bool 7819frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2) 7820{ 7821 /* The order of writes is always preserved. */ 7822 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE) 7823 return true; 7824 7825 /* The order of reads isn't preserved. */ 7826 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE) 7827 return false; 7828 7829 /* One operation is a write and the other is (or could be) a read. 7830 The order is only guaranteed if the accesses are to the same 7831 doubleword. */ 7832 return frv_same_doubleword_p (io1, io2); 7833} 7834 7835/* Generalize I/O operation X so that it covers both X and Y. */ 7836 7837static void 7838frv_io_union (struct frv_io *x, const struct frv_io *y) 7839{ 7840 if (x->type != y->type) 7841 x->type = FRV_IO_UNKNOWN; 7842 if (!frv_same_doubleword_p (x, y)) 7843 { 7844 x->const_address = 0; 7845 x->var_address = 0; 7846 } 7847} 7848 7849/* Fill IO with information about the load or store associated with 7850 membar instruction INSN. */ 7851 7852static void 7853frv_extract_membar (struct frv_io *io, rtx insn) 7854{ 7855 extract_insn (insn); 7856 io->type = INTVAL (recog_data.operand[2]); 7857 io->const_address = INTVAL (recog_data.operand[1]); 7858 io->var_address = XEXP (recog_data.operand[0], 0); 7859} 7860 7861/* A note_stores callback for which DATA points to an rtx. Nullify *DATA 7862 if X is a register and *DATA depends on X. */ 7863 7864static void 7865frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) 7866{ 7867 rtx *other = (rtx *) data; 7868 7869 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other)) 7870 *other = 0; 7871} 7872 7873/* A note_stores callback for which DATA points to a HARD_REG_SET. 7874 Remove every modified register from the set. */ 7875 7876static void 7877frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) 7878{ 7879 HARD_REG_SET *set = (HARD_REG_SET *) data; 7880 unsigned int regno; 7881 7882 if (REG_P (x)) 7883 FOR_EACH_REGNO (regno, x) 7884 CLEAR_HARD_REG_BIT (*set, regno); 7885} 7886 7887/* A for_each_rtx callback for which DATA points to a HARD_REG_SET. 7888 Add every register in *X to the set. */ 7889 7890static int 7891frv_io_handle_use_1 (rtx *x, void *data) 7892{ 7893 HARD_REG_SET *set = (HARD_REG_SET *) data; 7894 unsigned int regno; 7895 7896 if (REG_P (*x)) 7897 FOR_EACH_REGNO (regno, *x) 7898 SET_HARD_REG_BIT (*set, regno); 7899 7900 return 0; 7901} 7902 7903/* A note_stores callback that applies frv_io_handle_use_1 to an 7904 entire rhs value. */ 7905 7906static void 7907frv_io_handle_use (rtx *x, void *data) 7908{ 7909 for_each_rtx (x, frv_io_handle_use_1, data); 7910} 7911 7912/* Go through block BB looking for membars to remove. There are two 7913 cases where intra-block analysis is enough: 7914 7915 - a membar is redundant if it occurs between two consecutive I/O 7916 operations and if those operations are guaranteed to complete 7917 in order. 7918 7919 - a membar for a __builtin_read is redundant if the result is 7920 used before the next I/O operation is issued. 7921 7922 If the last membar in the block could not be removed, and there 7923 are guaranteed to be no I/O operations between that membar and 7924 the end of the block, store the membar in *LAST_MEMBAR, otherwise 7925 store null. 7926 7927 Describe the block's first I/O operation in *NEXT_IO. Describe 7928 an unknown operation if the block doesn't do any I/O. */ 7929 7930static void 7931frv_optimize_membar_local (basic_block bb, struct frv_io *next_io, 7932 rtx *last_membar) 7933{ 7934 HARD_REG_SET used_regs; 7935 rtx next_membar, set, insn; 7936 bool next_is_end_p; 7937 7938 /* NEXT_IO is the next I/O operation to be performed after the current 7939 instruction. It starts off as being an unknown operation. */ 7940 memset (next_io, 0, sizeof (*next_io)); 7941 7942 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */ 7943 next_is_end_p = true; 7944 7945 /* If the current instruction is a __builtin_read or __builtin_write, 7946 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR 7947 is null if the membar has already been deleted. 7948 7949 Note that the initialization here should only be needed to 7950 suppress warnings. */ 7951 next_membar = 0; 7952 7953 /* USED_REGS is the set of registers that are used before the 7954 next I/O instruction. */ 7955 CLEAR_HARD_REG_SET (used_regs); 7956 7957 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn)) 7958 if (GET_CODE (insn) == CALL_INSN) 7959 { 7960 /* We can't predict what a call will do to volatile memory. */ 7961 memset (next_io, 0, sizeof (struct frv_io)); 7962 next_is_end_p = false; 7963 CLEAR_HARD_REG_SET (used_regs); 7964 } 7965 else if (INSN_P (insn)) 7966 switch (recog_memoized (insn)) 7967 { 7968 case CODE_FOR_optional_membar_qi: 7969 case CODE_FOR_optional_membar_hi: 7970 case CODE_FOR_optional_membar_si: 7971 case CODE_FOR_optional_membar_di: 7972 next_membar = insn; 7973 if (next_is_end_p) 7974 { 7975 /* Local information isn't enough to decide whether this 7976 membar is needed. Stash it away for later. */ 7977 *last_membar = insn; 7978 frv_extract_membar (next_io, insn); 7979 next_is_end_p = false; 7980 } 7981 else 7982 { 7983 /* Check whether the I/O operation before INSN could be 7984 reordered with one described by NEXT_IO. If it can't, 7985 INSN will not be needed. */ 7986 struct frv_io prev_io; 7987 7988 frv_extract_membar (&prev_io, insn); 7989 if (frv_io_fixed_order_p (&prev_io, next_io)) 7990 { 7991 if (dump_file) 7992 fprintf (dump_file, 7993 ";; [Local] Removing membar %d since order" 7994 " of accesses is guaranteed\n", 7995 INSN_UID (next_membar)); 7996 7997 insn = NEXT_INSN (insn); 7998 delete_insn (next_membar); 7999 next_membar = 0; 8000 } 8001 *next_io = prev_io; 8002 } 8003 break; 8004 8005 default: 8006 /* Invalidate NEXT_IO's address if it depends on something that 8007 is clobbered by INSN. */ 8008 if (next_io->var_address) 8009 note_stores (PATTERN (insn), frv_io_check_address, 8010 &next_io->var_address); 8011 8012 /* If the next membar is associated with a __builtin_read, 8013 see if INSN reads from that address. If it does, and if 8014 the destination register is used before the next I/O access, 8015 there is no need for the membar. */ 8016 set = PATTERN (insn); 8017 if (next_io->type == FRV_IO_READ 8018 && next_io->var_address != 0 8019 && next_membar != 0 8020 && GET_CODE (set) == SET 8021 && GET_CODE (SET_DEST (set)) == REG 8022 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set)))) 8023 { 8024 rtx src; 8025 8026 src = SET_SRC (set); 8027 if (GET_CODE (src) == ZERO_EXTEND) 8028 src = XEXP (src, 0); 8029 8030 if (GET_CODE (src) == MEM 8031 && rtx_equal_p (XEXP (src, 0), next_io->var_address)) 8032 { 8033 if (dump_file) 8034 fprintf (dump_file, 8035 ";; [Local] Removing membar %d since the target" 8036 " of %d is used before the I/O operation\n", 8037 INSN_UID (next_membar), INSN_UID (insn)); 8038 8039 if (next_membar == *last_membar) 8040 *last_membar = 0; 8041 8042 delete_insn (next_membar); 8043 next_membar = 0; 8044 } 8045 } 8046 8047 /* If INSN has volatile references, forget about any registers 8048 that are used after it. Otherwise forget about uses that 8049 are (or might be) defined by INSN. */ 8050 if (volatile_refs_p (PATTERN (insn))) 8051 CLEAR_HARD_REG_SET (used_regs); 8052 else 8053 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs); 8054 8055 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs); 8056 break; 8057 } 8058} 8059 8060/* See if MEMBAR, the last membar instruction in BB, can be removed. 8061 FIRST_IO[X] describes the first operation performed by basic block X. */ 8062 8063static void 8064frv_optimize_membar_global (basic_block bb, struct frv_io *first_io, 8065 rtx membar) 8066{ 8067 struct frv_io this_io, next_io; 8068 edge succ; 8069 edge_iterator ei; 8070 8071 /* We need to keep the membar if there is an edge to the exit block. */ 8072 FOR_EACH_EDGE (succ, ei, bb->succs) 8073 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */ 8074 if (succ->dest == EXIT_BLOCK_PTR) 8075 return; 8076 8077 /* Work out the union of all successor blocks. */ 8078 ei = ei_start (bb->succs); 8079 ei_cond (ei, &succ); 8080 /* next_io = first_io[bb->succ->dest->index]; */ 8081 next_io = first_io[succ->dest->index]; 8082 ei = ei_start (bb->succs); 8083 if (ei_cond (ei, &succ)) 8084 { 8085 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei)) 8086 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/ 8087 frv_io_union (&next_io, &first_io[succ->dest->index]); 8088 } 8089 else 8090 gcc_unreachable (); 8091 8092 frv_extract_membar (&this_io, membar); 8093 if (frv_io_fixed_order_p (&this_io, &next_io)) 8094 { 8095 if (dump_file) 8096 fprintf (dump_file, 8097 ";; [Global] Removing membar %d since order of accesses" 8098 " is guaranteed\n", INSN_UID (membar)); 8099 8100 delete_insn (membar); 8101 } 8102} 8103 8104/* Remove redundant membars from the current function. */ 8105 8106static void 8107frv_optimize_membar (void) 8108{ 8109 basic_block bb; 8110 struct frv_io *first_io; 8111 rtx *last_membar; 8112 8113 compute_bb_for_insn (); 8114 first_io = XCNEWVEC (struct frv_io, last_basic_block); 8115 last_membar = XCNEWVEC (rtx, last_basic_block); 8116 8117 FOR_EACH_BB (bb) 8118 frv_optimize_membar_local (bb, &first_io[bb->index], 8119 &last_membar[bb->index]); 8120 8121 FOR_EACH_BB (bb) 8122 if (last_membar[bb->index] != 0) 8123 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]); 8124 8125 free (first_io); 8126 free (last_membar); 8127} 8128 8129/* Used by frv_reorg to keep track of the current packet's address. */ 8130static unsigned int frv_packet_address; 8131 8132/* If the current packet falls through to a label, try to pad the packet 8133 with nops in order to fit the label's alignment requirements. */ 8134 8135static void 8136frv_align_label (void) 8137{ 8138 unsigned int alignment, target, nop; 8139 rtx x, last, barrier, label; 8140 8141 /* Walk forward to the start of the next packet. Set ALIGNMENT to the 8142 maximum alignment of that packet, LABEL to the last label between 8143 the packets, and BARRIER to the last barrier. */ 8144 last = frv_packet.insns[frv_packet.num_insns - 1]; 8145 label = barrier = 0; 8146 alignment = 4; 8147 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x)) 8148 { 8149 if (LABEL_P (x)) 8150 { 8151 unsigned int subalign = 1 << label_to_alignment (x); 8152 alignment = MAX (alignment, subalign); 8153 label = x; 8154 } 8155 if (BARRIER_P (x)) 8156 barrier = x; 8157 } 8158 8159 /* If -malign-labels, and the packet falls through to an unaligned 8160 label, try introducing a nop to align that label to 8 bytes. */ 8161 if (TARGET_ALIGN_LABELS 8162 && label != 0 8163 && barrier == 0 8164 && frv_packet.num_insns < frv_packet.issue_rate) 8165 alignment = MAX (alignment, 8); 8166 8167 /* Advance the address to the end of the current packet. */ 8168 frv_packet_address += frv_packet.num_insns * 4; 8169 8170 /* Work out the target address, after alignment. */ 8171 target = (frv_packet_address + alignment - 1) & -alignment; 8172 8173 /* If the packet falls through to the label, try to find an efficient 8174 padding sequence. */ 8175 if (barrier == 0) 8176 { 8177 /* First try adding nops to the current packet. */ 8178 for (nop = 0; nop < frv_num_nops; nop++) 8179 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop])) 8180 { 8181 frv_insert_nop_in_packet (frv_nops[nop]); 8182 frv_packet_address += 4; 8183 } 8184 8185 /* If we still haven't reached the target, add some new packets that 8186 contain only nops. If there are two types of nop, insert an 8187 alternating sequence of frv_nops[0] and frv_nops[1], which will 8188 lead to packets like: 8189 8190 nop.p 8191 mnop.p/fnop.p 8192 nop.p 8193 mnop/fnop 8194 8195 etc. Just emit frv_nops[0] if that's the only nop we have. */ 8196 last = frv_packet.insns[frv_packet.num_insns - 1]; 8197 nop = 0; 8198 while (frv_packet_address < target) 8199 { 8200 last = emit_insn_after (PATTERN (frv_nops[nop]), last); 8201 frv_packet_address += 4; 8202 if (frv_num_nops > 1) 8203 nop ^= 1; 8204 } 8205 } 8206 8207 frv_packet_address = target; 8208} 8209 8210/* Subroutine of frv_reorg, called after each packet has been constructed 8211 in frv_packet. */ 8212 8213static void 8214frv_reorg_packet (void) 8215{ 8216 frv_fill_unused_units (GROUP_I); 8217 frv_fill_unused_units (GROUP_FM); 8218 frv_align_label (); 8219} 8220 8221/* Add an instruction with pattern NOP to frv_nops[]. */ 8222 8223static void 8224frv_register_nop (rtx nop) 8225{ 8226 nop = make_insn_raw (nop); 8227 NEXT_INSN (nop) = 0; 8228 PREV_INSN (nop) = 0; 8229 frv_nops[frv_num_nops++] = nop; 8230} 8231 8232/* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions 8233 into packets and check whether we need to insert nops in order to 8234 fulfill the processor's issue requirements. Also, if the user has 8235 requested a certain alignment for a label, try to meet that alignment 8236 by inserting nops in the previous packet. */ 8237 8238static void 8239frv_reorg (void) 8240{ 8241 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p) 8242 frv_optimize_membar (); 8243 8244 frv_num_nops = 0; 8245 frv_register_nop (gen_nop ()); 8246 if (TARGET_MEDIA) 8247 frv_register_nop (gen_mnop ()); 8248 if (TARGET_HARD_FLOAT) 8249 frv_register_nop (gen_fnop ()); 8250 8251 /* Estimate the length of each branch. Although this may change after 8252 we've inserted nops, it will only do so in big functions. */ 8253 shorten_branches (get_insns ()); 8254 8255 frv_packet_address = 0; 8256 frv_for_each_packet (frv_reorg_packet); 8257} 8258 8259#define def_builtin(name, type, code) \ 8260 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL) 8261 8262struct builtin_description 8263{ 8264 enum insn_code icode; 8265 const char *name; 8266 enum frv_builtins code; 8267 enum rtx_code comparison; 8268 unsigned int flag; 8269}; 8270 8271/* Media intrinsics that take a single, constant argument. */ 8272 8273static struct builtin_description bdesc_set[] = 8274{ 8275 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 } 8276}; 8277 8278/* Media intrinsics that take just one argument. */ 8279 8280static struct builtin_description bdesc_1arg[] = 8281{ 8282 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 }, 8283 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 }, 8284 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 }, 8285 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 }, 8286 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 }, 8287 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 } 8288}; 8289 8290/* Media intrinsics that take two arguments. */ 8291 8292static struct builtin_description bdesc_2arg[] = 8293{ 8294 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 }, 8295 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 }, 8296 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 }, 8297 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 }, 8298 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 }, 8299 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 }, 8300 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 }, 8301 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 }, 8302 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 }, 8303 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 }, 8304 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 }, 8305 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 }, 8306 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 }, 8307 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 }, 8308 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 }, 8309 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 }, 8310 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 }, 8311 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 }, 8312 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 }, 8313 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 }, 8314 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 }, 8315 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 }, 8316 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 }, 8317 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 }, 8318 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 }, 8319 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 }, 8320 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 } 8321}; 8322 8323/* Integer intrinsics that take two arguments and have no return value. */ 8324 8325static struct builtin_description bdesc_int_void2arg[] = 8326{ 8327 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 }, 8328 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 }, 8329 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 } 8330}; 8331 8332static struct builtin_description bdesc_prefetches[] = 8333{ 8334 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 }, 8335 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 } 8336}; 8337 8338/* Media intrinsics that take two arguments, the first being an ACC number. */ 8339 8340static struct builtin_description bdesc_cut[] = 8341{ 8342 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 }, 8343 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 }, 8344 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 } 8345}; 8346 8347/* Two-argument media intrinsics with an immediate second argument. */ 8348 8349static struct builtin_description bdesc_2argimm[] = 8350{ 8351 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 }, 8352 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 }, 8353 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 }, 8354 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 }, 8355 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 }, 8356 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 }, 8357 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 }, 8358 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 }, 8359 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 }, 8360 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 }, 8361 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 }, 8362 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 }, 8363 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 }, 8364 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 }, 8365 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 }, 8366 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 }, 8367 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 } 8368}; 8369 8370/* Media intrinsics that take two arguments and return void, the first argument 8371 being a pointer to 4 words in memory. */ 8372 8373static struct builtin_description bdesc_void2arg[] = 8374{ 8375 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 }, 8376 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 }, 8377}; 8378 8379/* Media intrinsics that take three arguments, the first being a const_int that 8380 denotes an accumulator, and that return void. */ 8381 8382static struct builtin_description bdesc_void3arg[] = 8383{ 8384 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 }, 8385 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 }, 8386 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 }, 8387 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 }, 8388 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 }, 8389 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 }, 8390 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 }, 8391 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 }, 8392 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 }, 8393 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 }, 8394 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 }, 8395 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 }, 8396 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 }, 8397 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 }, 8398 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 }, 8399 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 }, 8400 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 }, 8401 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 }, 8402 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 }, 8403 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 }, 8404 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 }, 8405 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 }, 8406 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 }, 8407 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 }, 8408 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 } 8409}; 8410 8411/* Media intrinsics that take two accumulator numbers as argument and 8412 return void. */ 8413 8414static struct builtin_description bdesc_voidacc[] = 8415{ 8416 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 }, 8417 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 }, 8418 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 }, 8419 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 }, 8420 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 }, 8421 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 } 8422}; 8423 8424/* Intrinsics that load a value and then issue a MEMBAR. The load is 8425 a normal move and the ICODE is for the membar. */ 8426 8427static struct builtin_description bdesc_loads[] = 8428{ 8429 { CODE_FOR_optional_membar_qi, "__builtin_read8", 8430 FRV_BUILTIN_READ8, 0, 0 }, 8431 { CODE_FOR_optional_membar_hi, "__builtin_read16", 8432 FRV_BUILTIN_READ16, 0, 0 }, 8433 { CODE_FOR_optional_membar_si, "__builtin_read32", 8434 FRV_BUILTIN_READ32, 0, 0 }, 8435 { CODE_FOR_optional_membar_di, "__builtin_read64", 8436 FRV_BUILTIN_READ64, 0, 0 } 8437}; 8438 8439/* Likewise stores. */ 8440 8441static struct builtin_description bdesc_stores[] = 8442{ 8443 { CODE_FOR_optional_membar_qi, "__builtin_write8", 8444 FRV_BUILTIN_WRITE8, 0, 0 }, 8445 { CODE_FOR_optional_membar_hi, "__builtin_write16", 8446 FRV_BUILTIN_WRITE16, 0, 0 }, 8447 { CODE_FOR_optional_membar_si, "__builtin_write32", 8448 FRV_BUILTIN_WRITE32, 0, 0 }, 8449 { CODE_FOR_optional_membar_di, "__builtin_write64", 8450 FRV_BUILTIN_WRITE64, 0, 0 }, 8451}; 8452 8453/* Initialize media builtins. */ 8454 8455static void 8456frv_init_builtins (void) 8457{ 8458 tree endlink = void_list_node; 8459 tree accumulator = integer_type_node; 8460 tree integer = integer_type_node; 8461 tree voidt = void_type_node; 8462 tree uhalf = short_unsigned_type_node; 8463 tree sword1 = long_integer_type_node; 8464 tree uword1 = long_unsigned_type_node; 8465 tree sword2 = long_long_integer_type_node; 8466 tree uword2 = long_long_unsigned_type_node; 8467 tree uword4 = build_pointer_type (uword1); 8468 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1)); 8469 tree ubyte = unsigned_char_type_node; 8470 tree iacc = integer_type_node; 8471 8472#define UNARY(RET, T1) \ 8473 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink)) 8474 8475#define BINARY(RET, T1, T2) \ 8476 build_function_type (RET, tree_cons (NULL_TREE, T1, \ 8477 tree_cons (NULL_TREE, T2, endlink))) 8478 8479#define TRINARY(RET, T1, T2, T3) \ 8480 build_function_type (RET, tree_cons (NULL_TREE, T1, \ 8481 tree_cons (NULL_TREE, T2, \ 8482 tree_cons (NULL_TREE, T3, endlink)))) 8483 8484#define QUAD(RET, T1, T2, T3, T4) \ 8485 build_function_type (RET, tree_cons (NULL_TREE, T1, \ 8486 tree_cons (NULL_TREE, T2, \ 8487 tree_cons (NULL_TREE, T3, \ 8488 tree_cons (NULL_TREE, T4, endlink))))) 8489 8490 tree void_ftype_void = build_function_type (voidt, endlink); 8491 8492 tree void_ftype_acc = UNARY (voidt, accumulator); 8493 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1); 8494 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2); 8495 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1); 8496 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator); 8497 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1); 8498 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1); 8499 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2); 8500 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2); 8501 8502 tree uw1_ftype_uw1 = UNARY (uword1, uword1); 8503 tree uw1_ftype_sw1 = UNARY (uword1, sword1); 8504 tree uw1_ftype_uw2 = UNARY (uword1, uword2); 8505 tree uw1_ftype_acc = UNARY (uword1, accumulator); 8506 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf); 8507 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1); 8508 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer); 8509 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1); 8510 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1); 8511 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1); 8512 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer); 8513 8514 tree sw1_ftype_int = UNARY (sword1, integer); 8515 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1); 8516 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer); 8517 8518 tree uw2_ftype_uw1 = UNARY (uword2, uword1); 8519 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer); 8520 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2); 8521 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer); 8522 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer); 8523 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf); 8524 8525 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2); 8526 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer); 8527 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1); 8528 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1); 8529 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1); 8530 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2); 8531 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1); 8532 tree sw1_ftype_sw1 = UNARY (sword1, sword1); 8533 tree sw2_ftype_iacc = UNARY (sword2, iacc); 8534 tree sw1_ftype_iacc = UNARY (sword1, iacc); 8535 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node); 8536 tree uw1_ftype_vptr = UNARY (uword1, vptr); 8537 tree uw2_ftype_vptr = UNARY (uword2, vptr); 8538 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte); 8539 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf); 8540 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1); 8541 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2); 8542 8543 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND); 8544 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR); 8545 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR); 8546 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT); 8547 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI); 8548 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI); 8549 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT); 8550 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH); 8551 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI); 8552 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI); 8553 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI); 8554 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS); 8555 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU); 8556 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS); 8557 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS); 8558 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS); 8559 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS); 8560 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS); 8561 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU); 8562 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS); 8563 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU); 8564 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS); 8565 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU); 8566 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS); 8567 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU); 8568 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS); 8569 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS); 8570 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS); 8571 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS); 8572 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS); 8573 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU); 8574 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS); 8575 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU); 8576 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS); 8577 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU); 8578 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS); 8579 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU); 8580 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS); 8581 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU); 8582 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS); 8583 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU); 8584 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS); 8585 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU); 8586 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT); 8587 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS); 8588 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW); 8589 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD); 8590 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH); 8591 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH); 8592 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH); 8593 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH); 8594 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH); 8595 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB); 8596 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE); 8597 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC); 8598 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA); 8599 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC); 8600 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG); 8601 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC); 8602 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG); 8603 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1); 8604 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2); 8605 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP); 8606 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS); 8607 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS); 8608 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS); 8609 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS); 8610 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS); 8611 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS); 8612 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS); 8613 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS); 8614 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS); 8615 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS); 8616 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI); 8617 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI); 8618 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI); 8619 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI); 8620 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS); 8621 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS); 8622 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS); 8623 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS); 8624 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH); 8625 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH); 8626 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH); 8627 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS); 8628 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS); 8629 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI); 8630 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI); 8631 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL); 8632 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL); 8633 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS); 8634 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS); 8635 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU); 8636 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS); 8637 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS); 8638 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS); 8639 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN); 8640 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS); 8641 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll); 8642 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl); 8643 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll); 8644 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl); 8645 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0); 8646 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH); 8647 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8); 8648 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16); 8649 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32); 8650 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64); 8651 8652 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8); 8653 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16); 8654 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32); 8655 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64); 8656 8657#undef UNARY 8658#undef BINARY 8659#undef TRINARY 8660#undef QUAD 8661} 8662 8663/* Set the names for various arithmetic operations according to the 8664 FRV ABI. */ 8665static void 8666frv_init_libfuncs (void) 8667{ 8668 set_optab_libfunc (smod_optab, SImode, "__modi"); 8669 set_optab_libfunc (umod_optab, SImode, "__umodi"); 8670 8671 set_optab_libfunc (add_optab, DImode, "__addll"); 8672 set_optab_libfunc (sub_optab, DImode, "__subll"); 8673 set_optab_libfunc (smul_optab, DImode, "__mulll"); 8674 set_optab_libfunc (sdiv_optab, DImode, "__divll"); 8675 set_optab_libfunc (smod_optab, DImode, "__modll"); 8676 set_optab_libfunc (umod_optab, DImode, "__umodll"); 8677 set_optab_libfunc (and_optab, DImode, "__andll"); 8678 set_optab_libfunc (ior_optab, DImode, "__orll"); 8679 set_optab_libfunc (xor_optab, DImode, "__xorll"); 8680 set_optab_libfunc (one_cmpl_optab, DImode, "__notll"); 8681 8682 set_optab_libfunc (add_optab, SFmode, "__addf"); 8683 set_optab_libfunc (sub_optab, SFmode, "__subf"); 8684 set_optab_libfunc (smul_optab, SFmode, "__mulf"); 8685 set_optab_libfunc (sdiv_optab, SFmode, "__divf"); 8686 8687 set_optab_libfunc (add_optab, DFmode, "__addd"); 8688 set_optab_libfunc (sub_optab, DFmode, "__subd"); 8689 set_optab_libfunc (smul_optab, DFmode, "__muld"); 8690 set_optab_libfunc (sdiv_optab, DFmode, "__divd"); 8691 8692 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod"); 8693 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof"); 8694 8695 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi"); 8696 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll"); 8697 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi"); 8698 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll"); 8699 8700 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui"); 8701 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull"); 8702 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui"); 8703 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull"); 8704 8705 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof"); 8706 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof"); 8707 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod"); 8708 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod"); 8709} 8710 8711/* Convert an integer constant to an accumulator register. ICODE is the 8712 code of the target instruction, OPNUM is the number of the 8713 accumulator operand and OPVAL is the constant integer. Try both 8714 ACC and ACCG registers; only report an error if neither fit the 8715 instruction. */ 8716 8717static rtx 8718frv_int_to_acc (enum insn_code icode, int opnum, rtx opval) 8719{ 8720 rtx reg; 8721 int i; 8722 8723 /* ACCs and ACCGs are implicit global registers if media intrinsics 8724 are being used. We set up this lazily to avoid creating lots of 8725 unnecessary call_insn rtl in non-media code. */ 8726 for (i = 0; i <= ACC_MASK; i++) 8727 if ((i & ACC_MASK) == i) 8728 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1; 8729 8730 if (GET_CODE (opval) != CONST_INT) 8731 { 8732 error ("accumulator is not a constant integer"); 8733 return NULL_RTX; 8734 } 8735 if ((INTVAL (opval) & ~ACC_MASK) != 0) 8736 { 8737 error ("accumulator number is out of bounds"); 8738 return NULL_RTX; 8739 } 8740 8741 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode, 8742 ACC_FIRST + INTVAL (opval)); 8743 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode)) 8744 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval)); 8745 8746 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode)) 8747 { 8748 error ("inappropriate accumulator for %qs", insn_data[icode].name); 8749 return NULL_RTX; 8750 } 8751 return reg; 8752} 8753 8754/* If an ACC rtx has mode MODE, return the mode that the matching ACCG 8755 should have. */ 8756 8757static enum machine_mode 8758frv_matching_accg_mode (enum machine_mode mode) 8759{ 8760 switch (mode) 8761 { 8762 case V4SImode: 8763 return V4QImode; 8764 8765 case DImode: 8766 return HImode; 8767 8768 case SImode: 8769 return QImode; 8770 8771 default: 8772 gcc_unreachable (); 8773 } 8774} 8775 8776/* Given that a __builtin_read or __builtin_write function is accessing 8777 address ADDRESS, return the value that should be used as operand 1 8778 of the membar. */ 8779 8780static rtx 8781frv_io_address_cookie (rtx address) 8782{ 8783 return (GET_CODE (address) == CONST_INT 8784 ? GEN_INT (INTVAL (address) / 8 * 8) 8785 : const0_rtx); 8786} 8787 8788/* Return the accumulator guard that should be paired with accumulator 8789 register ACC. The mode of the returned register is in the same 8790 class as ACC, but is four times smaller. */ 8791 8792rtx 8793frv_matching_accg_for_acc (rtx acc) 8794{ 8795 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)), 8796 REGNO (acc) - ACC_FIRST + ACCG_FIRST); 8797} 8798 8799/* Read the requested argument from the call EXP given by INDEX. 8800 Return the value as an rtx. */ 8801 8802static rtx 8803frv_read_argument (tree exp, unsigned int index) 8804{ 8805 return expand_expr (CALL_EXPR_ARG (exp, index), 8806 NULL_RTX, VOIDmode, 0); 8807} 8808 8809/* Like frv_read_argument, but interpret the argument as the number 8810 of an IACC register and return a (reg:MODE ...) rtx for it. */ 8811 8812static rtx 8813frv_read_iacc_argument (enum machine_mode mode, tree call, 8814 unsigned int index) 8815{ 8816 int i, regno; 8817 rtx op; 8818 8819 op = frv_read_argument (call, index); 8820 if (GET_CODE (op) != CONST_INT 8821 || INTVAL (op) < 0 8822 || INTVAL (op) > IACC_LAST - IACC_FIRST 8823 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0) 8824 { 8825 error ("invalid IACC argument"); 8826 op = const0_rtx; 8827 } 8828 8829 /* IACCs are implicit global registers. We set up this lazily to 8830 avoid creating lots of unnecessary call_insn rtl when IACCs aren't 8831 being used. */ 8832 regno = INTVAL (op) + IACC_FIRST; 8833 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++) 8834 global_regs[regno + i] = 1; 8835 8836 return gen_rtx_REG (mode, regno); 8837} 8838 8839/* Return true if OPVAL can be used for operand OPNUM of instruction ICODE. 8840 The instruction should require a constant operand of some sort. The 8841 function prints an error if OPVAL is not valid. */ 8842 8843static int 8844frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval) 8845{ 8846 if (GET_CODE (opval) != CONST_INT) 8847 { 8848 error ("%qs expects a constant argument", insn_data[icode].name); 8849 return FALSE; 8850 } 8851 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode)) 8852 { 8853 error ("constant argument out of range for %qs", insn_data[icode].name); 8854 return FALSE; 8855 } 8856 return TRUE; 8857} 8858 8859/* Return a legitimate rtx for instruction ICODE's return value. Use TARGET 8860 if it's not null, has the right mode, and satisfies operand 0's 8861 predicate. */ 8862 8863static rtx 8864frv_legitimize_target (enum insn_code icode, rtx target) 8865{ 8866 enum machine_mode mode = insn_data[icode].operand[0].mode; 8867 8868 if (! target 8869 || GET_MODE (target) != mode 8870 || ! (*insn_data[icode].operand[0].predicate) (target, mode)) 8871 return gen_reg_rtx (mode); 8872 else 8873 return target; 8874} 8875 8876/* Given that ARG is being passed as operand OPNUM to instruction ICODE, 8877 check whether ARG satisfies the operand's constraints. If it doesn't, 8878 copy ARG to a temporary register and return that. Otherwise return ARG 8879 itself. */ 8880 8881static rtx 8882frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg) 8883{ 8884 enum machine_mode mode = insn_data[icode].operand[opnum].mode; 8885 8886 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode)) 8887 return arg; 8888 else 8889 return copy_to_mode_reg (mode, arg); 8890} 8891 8892/* Return a volatile memory reference of mode MODE whose address is ARG. */ 8893 8894static rtx 8895frv_volatile_memref (enum machine_mode mode, rtx arg) 8896{ 8897 rtx mem; 8898 8899 mem = gen_rtx_MEM (mode, memory_address (mode, arg)); 8900 MEM_VOLATILE_P (mem) = 1; 8901 return mem; 8902} 8903 8904/* Expand builtins that take a single, constant argument. At the moment, 8905 only MHDSETS falls into this category. */ 8906 8907static rtx 8908frv_expand_set_builtin (enum insn_code icode, tree call, rtx target) 8909{ 8910 rtx pat; 8911 rtx op0 = frv_read_argument (call, 0); 8912 8913 if (! frv_check_constant_argument (icode, 1, op0)) 8914 return NULL_RTX; 8915 8916 target = frv_legitimize_target (icode, target); 8917 pat = GEN_FCN (icode) (target, op0); 8918 if (! pat) 8919 return NULL_RTX; 8920 8921 emit_insn (pat); 8922 return target; 8923} 8924 8925/* Expand builtins that take one operand. */ 8926 8927static rtx 8928frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target) 8929{ 8930 rtx pat; 8931 rtx op0 = frv_read_argument (call, 0); 8932 8933 target = frv_legitimize_target (icode, target); 8934 op0 = frv_legitimize_argument (icode, 1, op0); 8935 pat = GEN_FCN (icode) (target, op0); 8936 if (! pat) 8937 return NULL_RTX; 8938 8939 emit_insn (pat); 8940 return target; 8941} 8942 8943/* Expand builtins that take two operands. */ 8944 8945static rtx 8946frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target) 8947{ 8948 rtx pat; 8949 rtx op0 = frv_read_argument (call, 0); 8950 rtx op1 = frv_read_argument (call, 1); 8951 8952 target = frv_legitimize_target (icode, target); 8953 op0 = frv_legitimize_argument (icode, 1, op0); 8954 op1 = frv_legitimize_argument (icode, 2, op1); 8955 pat = GEN_FCN (icode) (target, op0, op1); 8956 if (! pat) 8957 return NULL_RTX; 8958 8959 emit_insn (pat); 8960 return target; 8961} 8962 8963/* Expand cut-style builtins, which take two operands and an implicit ACCG 8964 one. */ 8965 8966static rtx 8967frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target) 8968{ 8969 rtx pat; 8970 rtx op0 = frv_read_argument (call, 0); 8971 rtx op1 = frv_read_argument (call, 1); 8972 rtx op2; 8973 8974 target = frv_legitimize_target (icode, target); 8975 op0 = frv_int_to_acc (icode, 1, op0); 8976 if (! op0) 8977 return NULL_RTX; 8978 8979 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT) 8980 { 8981 if (! frv_check_constant_argument (icode, 2, op1)) 8982 return NULL_RTX; 8983 } 8984 else 8985 op1 = frv_legitimize_argument (icode, 2, op1); 8986 8987 op2 = frv_matching_accg_for_acc (op0); 8988 pat = GEN_FCN (icode) (target, op0, op1, op2); 8989 if (! pat) 8990 return NULL_RTX; 8991 8992 emit_insn (pat); 8993 return target; 8994} 8995 8996/* Expand builtins that take two operands and the second is immediate. */ 8997 8998static rtx 8999frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target) 9000{ 9001 rtx pat; 9002 rtx op0 = frv_read_argument (call, 0); 9003 rtx op1 = frv_read_argument (call, 1); 9004 9005 if (! frv_check_constant_argument (icode, 2, op1)) 9006 return NULL_RTX; 9007 9008 target = frv_legitimize_target (icode, target); 9009 op0 = frv_legitimize_argument (icode, 1, op0); 9010 pat = GEN_FCN (icode) (target, op0, op1); 9011 if (! pat) 9012 return NULL_RTX; 9013 9014 emit_insn (pat); 9015 return target; 9016} 9017 9018/* Expand builtins that take two operands, the first operand being a pointer to 9019 ints and return void. */ 9020 9021static rtx 9022frv_expand_voidbinop_builtin (enum insn_code icode, tree call) 9023{ 9024 rtx pat; 9025 rtx op0 = frv_read_argument (call, 0); 9026 rtx op1 = frv_read_argument (call, 1); 9027 enum machine_mode mode0 = insn_data[icode].operand[0].mode; 9028 rtx addr; 9029 9030 if (GET_CODE (op0) != MEM) 9031 { 9032 rtx reg = op0; 9033 9034 if (! offsettable_address_p (0, mode0, op0)) 9035 { 9036 reg = gen_reg_rtx (Pmode); 9037 emit_insn (gen_rtx_SET (VOIDmode, reg, op0)); 9038 } 9039 9040 op0 = gen_rtx_MEM (SImode, reg); 9041 } 9042 9043 addr = XEXP (op0, 0); 9044 if (! offsettable_address_p (0, mode0, addr)) 9045 addr = copy_to_mode_reg (Pmode, op0); 9046 9047 op0 = change_address (op0, V4SImode, addr); 9048 op1 = frv_legitimize_argument (icode, 1, op1); 9049 pat = GEN_FCN (icode) (op0, op1); 9050 if (! pat) 9051 return 0; 9052 9053 emit_insn (pat); 9054 return 0; 9055} 9056 9057/* Expand builtins that take two long operands and return void. */ 9058 9059static rtx 9060frv_expand_int_void2arg (enum insn_code icode, tree call) 9061{ 9062 rtx pat; 9063 rtx op0 = frv_read_argument (call, 0); 9064 rtx op1 = frv_read_argument (call, 1); 9065 9066 op0 = frv_legitimize_argument (icode, 1, op0); 9067 op1 = frv_legitimize_argument (icode, 1, op1); 9068 pat = GEN_FCN (icode) (op0, op1); 9069 if (! pat) 9070 return NULL_RTX; 9071 9072 emit_insn (pat); 9073 return NULL_RTX; 9074} 9075 9076/* Expand prefetch builtins. These take a single address as argument. */ 9077 9078static rtx 9079frv_expand_prefetches (enum insn_code icode, tree call) 9080{ 9081 rtx pat; 9082 rtx op0 = frv_read_argument (call, 0); 9083 9084 pat = GEN_FCN (icode) (force_reg (Pmode, op0)); 9085 if (! pat) 9086 return 0; 9087 9088 emit_insn (pat); 9089 return 0; 9090} 9091 9092/* Expand builtins that take three operands and return void. The first 9093 argument must be a constant that describes a pair or quad accumulators. A 9094 fourth argument is created that is the accumulator guard register that 9095 corresponds to the accumulator. */ 9096 9097static rtx 9098frv_expand_voidtriop_builtin (enum insn_code icode, tree call) 9099{ 9100 rtx pat; 9101 rtx op0 = frv_read_argument (call, 0); 9102 rtx op1 = frv_read_argument (call, 1); 9103 rtx op2 = frv_read_argument (call, 2); 9104 rtx op3; 9105 9106 op0 = frv_int_to_acc (icode, 0, op0); 9107 if (! op0) 9108 return NULL_RTX; 9109 9110 op1 = frv_legitimize_argument (icode, 1, op1); 9111 op2 = frv_legitimize_argument (icode, 2, op2); 9112 op3 = frv_matching_accg_for_acc (op0); 9113 pat = GEN_FCN (icode) (op0, op1, op2, op3); 9114 if (! pat) 9115 return NULL_RTX; 9116 9117 emit_insn (pat); 9118 return NULL_RTX; 9119} 9120 9121/* Expand builtins that perform accumulator-to-accumulator operations. 9122 These builtins take two accumulator numbers as argument and return 9123 void. */ 9124 9125static rtx 9126frv_expand_voidaccop_builtin (enum insn_code icode, tree call) 9127{ 9128 rtx pat; 9129 rtx op0 = frv_read_argument (call, 0); 9130 rtx op1 = frv_read_argument (call, 1); 9131 rtx op2; 9132 rtx op3; 9133 9134 op0 = frv_int_to_acc (icode, 0, op0); 9135 if (! op0) 9136 return NULL_RTX; 9137 9138 op1 = frv_int_to_acc (icode, 1, op1); 9139 if (! op1) 9140 return NULL_RTX; 9141 9142 op2 = frv_matching_accg_for_acc (op0); 9143 op3 = frv_matching_accg_for_acc (op1); 9144 pat = GEN_FCN (icode) (op0, op1, op2, op3); 9145 if (! pat) 9146 return NULL_RTX; 9147 9148 emit_insn (pat); 9149 return NULL_RTX; 9150} 9151 9152/* Expand a __builtin_read* function. ICODE is the instruction code for the 9153 membar and TARGET_MODE is the mode that the loaded value should have. */ 9154 9155static rtx 9156frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode, 9157 tree call, rtx target) 9158{ 9159 rtx op0 = frv_read_argument (call, 0); 9160 rtx cookie = frv_io_address_cookie (op0); 9161 9162 if (target == 0 || !REG_P (target)) 9163 target = gen_reg_rtx (target_mode); 9164 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0); 9165 convert_move (target, op0, 1); 9166 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ))); 9167 cfun->machine->has_membar_p = 1; 9168 return target; 9169} 9170 9171/* Likewise __builtin_write* functions. */ 9172 9173static rtx 9174frv_expand_store_builtin (enum insn_code icode, tree call) 9175{ 9176 rtx op0 = frv_read_argument (call, 0); 9177 rtx op1 = frv_read_argument (call, 1); 9178 rtx cookie = frv_io_address_cookie (op0); 9179 9180 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0); 9181 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1); 9182 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE))); 9183 cfun->machine->has_membar_p = 1; 9184 return NULL_RTX; 9185} 9186 9187/* Expand the MDPACKH builtin. It takes four unsigned short arguments and 9188 each argument forms one word of the two double-word input registers. 9189 CALL is the tree for the call and TARGET, if nonnull, suggests a good place 9190 to put the return value. */ 9191 9192static rtx 9193frv_expand_mdpackh_builtin (tree call, rtx target) 9194{ 9195 enum insn_code icode = CODE_FOR_mdpackh; 9196 rtx pat, op0, op1; 9197 rtx arg1 = frv_read_argument (call, 0); 9198 rtx arg2 = frv_read_argument (call, 1); 9199 rtx arg3 = frv_read_argument (call, 2); 9200 rtx arg4 = frv_read_argument (call, 3); 9201 9202 target = frv_legitimize_target (icode, target); 9203 op0 = gen_reg_rtx (DImode); 9204 op1 = gen_reg_rtx (DImode); 9205 9206 /* The high half of each word is not explicitly initialized, so indicate 9207 that the input operands are not live before this point. */ 9208 emit_clobber (op0); 9209 emit_clobber (op1); 9210 9211 /* Move each argument into the low half of its associated input word. */ 9212 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1); 9213 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2); 9214 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3); 9215 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4); 9216 9217 pat = GEN_FCN (icode) (target, op0, op1); 9218 if (! pat) 9219 return NULL_RTX; 9220 9221 emit_insn (pat); 9222 return target; 9223} 9224 9225/* Expand the MCLRACC builtin. This builtin takes a single accumulator 9226 number as argument. */ 9227 9228static rtx 9229frv_expand_mclracc_builtin (tree call) 9230{ 9231 enum insn_code icode = CODE_FOR_mclracc; 9232 rtx pat; 9233 rtx op0 = frv_read_argument (call, 0); 9234 9235 op0 = frv_int_to_acc (icode, 0, op0); 9236 if (! op0) 9237 return NULL_RTX; 9238 9239 pat = GEN_FCN (icode) (op0); 9240 if (pat) 9241 emit_insn (pat); 9242 9243 return NULL_RTX; 9244} 9245 9246/* Expand builtins that take no arguments. */ 9247 9248static rtx 9249frv_expand_noargs_builtin (enum insn_code icode) 9250{ 9251 rtx pat = GEN_FCN (icode) (const0_rtx); 9252 if (pat) 9253 emit_insn (pat); 9254 9255 return NULL_RTX; 9256} 9257 9258/* Expand MRDACC and MRDACCG. These builtins take a single accumulator 9259 number or accumulator guard number as argument and return an SI integer. */ 9260 9261static rtx 9262frv_expand_mrdacc_builtin (enum insn_code icode, tree call) 9263{ 9264 rtx pat; 9265 rtx target = gen_reg_rtx (SImode); 9266 rtx op0 = frv_read_argument (call, 0); 9267 9268 op0 = frv_int_to_acc (icode, 1, op0); 9269 if (! op0) 9270 return NULL_RTX; 9271 9272 pat = GEN_FCN (icode) (target, op0); 9273 if (! pat) 9274 return NULL_RTX; 9275 9276 emit_insn (pat); 9277 return target; 9278} 9279 9280/* Expand MWTACC and MWTACCG. These builtins take an accumulator or 9281 accumulator guard as their first argument and an SImode value as their 9282 second. */ 9283 9284static rtx 9285frv_expand_mwtacc_builtin (enum insn_code icode, tree call) 9286{ 9287 rtx pat; 9288 rtx op0 = frv_read_argument (call, 0); 9289 rtx op1 = frv_read_argument (call, 1); 9290 9291 op0 = frv_int_to_acc (icode, 0, op0); 9292 if (! op0) 9293 return NULL_RTX; 9294 9295 op1 = frv_legitimize_argument (icode, 1, op1); 9296 pat = GEN_FCN (icode) (op0, op1); 9297 if (pat) 9298 emit_insn (pat); 9299 9300 return NULL_RTX; 9301} 9302 9303/* Emit a move from SRC to DEST in SImode chunks. This can be used 9304 to move DImode values into and out of IACC0. */ 9305 9306static void 9307frv_split_iacc_move (rtx dest, rtx src) 9308{ 9309 enum machine_mode inner; 9310 int i; 9311 9312 inner = GET_MODE (dest); 9313 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode)) 9314 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i), 9315 simplify_gen_subreg (SImode, src, inner, i)); 9316} 9317 9318/* Expand builtins. */ 9319 9320static rtx 9321frv_expand_builtin (tree exp, 9322 rtx target, 9323 rtx subtarget ATTRIBUTE_UNUSED, 9324 enum machine_mode mode ATTRIBUTE_UNUSED, 9325 int ignore ATTRIBUTE_UNUSED) 9326{ 9327 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); 9328 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl); 9329 unsigned i; 9330 struct builtin_description *d; 9331 9332 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA) 9333 { 9334 error ("media functions are not available unless -mmedia is used"); 9335 return NULL_RTX; 9336 } 9337 9338 switch (fcode) 9339 { 9340 case FRV_BUILTIN_MCOP1: 9341 case FRV_BUILTIN_MCOP2: 9342 case FRV_BUILTIN_MDUNPACKH: 9343 case FRV_BUILTIN_MBTOHE: 9344 if (! TARGET_MEDIA_REV1) 9345 { 9346 error ("this media function is only available on the fr500"); 9347 return NULL_RTX; 9348 } 9349 break; 9350 9351 case FRV_BUILTIN_MQXMACHS: 9352 case FRV_BUILTIN_MQXMACXHS: 9353 case FRV_BUILTIN_MQMACXHS: 9354 case FRV_BUILTIN_MADDACCS: 9355 case FRV_BUILTIN_MSUBACCS: 9356 case FRV_BUILTIN_MASACCS: 9357 case FRV_BUILTIN_MDADDACCS: 9358 case FRV_BUILTIN_MDSUBACCS: 9359 case FRV_BUILTIN_MDASACCS: 9360 case FRV_BUILTIN_MABSHS: 9361 case FRV_BUILTIN_MDROTLI: 9362 case FRV_BUILTIN_MCPLHI: 9363 case FRV_BUILTIN_MCPLI: 9364 case FRV_BUILTIN_MDCUTSSI: 9365 case FRV_BUILTIN_MQSATHS: 9366 case FRV_BUILTIN_MHSETLOS: 9367 case FRV_BUILTIN_MHSETLOH: 9368 case FRV_BUILTIN_MHSETHIS: 9369 case FRV_BUILTIN_MHSETHIH: 9370 case FRV_BUILTIN_MHDSETS: 9371 case FRV_BUILTIN_MHDSETH: 9372 if (! TARGET_MEDIA_REV2) 9373 { 9374 error ("this media function is only available on the fr400" 9375 " and fr550"); 9376 return NULL_RTX; 9377 } 9378 break; 9379 9380 case FRV_BUILTIN_SMASS: 9381 case FRV_BUILTIN_SMSSS: 9382 case FRV_BUILTIN_SMU: 9383 case FRV_BUILTIN_ADDSS: 9384 case FRV_BUILTIN_SUBSS: 9385 case FRV_BUILTIN_SLASS: 9386 case FRV_BUILTIN_SCUTSS: 9387 case FRV_BUILTIN_IACCreadll: 9388 case FRV_BUILTIN_IACCreadl: 9389 case FRV_BUILTIN_IACCsetll: 9390 case FRV_BUILTIN_IACCsetl: 9391 if (!TARGET_FR405_BUILTINS) 9392 { 9393 error ("this builtin function is only available" 9394 " on the fr405 and fr450"); 9395 return NULL_RTX; 9396 } 9397 break; 9398 9399 case FRV_BUILTIN_PREFETCH: 9400 if (!TARGET_FR500_FR550_BUILTINS) 9401 { 9402 error ("this builtin function is only available on the fr500" 9403 " and fr550"); 9404 return NULL_RTX; 9405 } 9406 break; 9407 9408 case FRV_BUILTIN_MQLCLRHS: 9409 case FRV_BUILTIN_MQLMTHS: 9410 case FRV_BUILTIN_MQSLLHI: 9411 case FRV_BUILTIN_MQSRAHI: 9412 if (!TARGET_MEDIA_FR450) 9413 { 9414 error ("this builtin function is only available on the fr450"); 9415 return NULL_RTX; 9416 } 9417 break; 9418 9419 default: 9420 break; 9421 } 9422 9423 /* Expand unique builtins. */ 9424 9425 switch (fcode) 9426 { 9427 case FRV_BUILTIN_MTRAP: 9428 return frv_expand_noargs_builtin (CODE_FOR_mtrap); 9429 9430 case FRV_BUILTIN_MCLRACC: 9431 return frv_expand_mclracc_builtin (exp); 9432 9433 case FRV_BUILTIN_MCLRACCA: 9434 if (TARGET_ACC_8) 9435 return frv_expand_noargs_builtin (CODE_FOR_mclracca8); 9436 else 9437 return frv_expand_noargs_builtin (CODE_FOR_mclracca4); 9438 9439 case FRV_BUILTIN_MRDACC: 9440 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp); 9441 9442 case FRV_BUILTIN_MRDACCG: 9443 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp); 9444 9445 case FRV_BUILTIN_MWTACC: 9446 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp); 9447 9448 case FRV_BUILTIN_MWTACCG: 9449 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp); 9450 9451 case FRV_BUILTIN_MDPACKH: 9452 return frv_expand_mdpackh_builtin (exp, target); 9453 9454 case FRV_BUILTIN_IACCreadll: 9455 { 9456 rtx src = frv_read_iacc_argument (DImode, exp, 0); 9457 if (target == 0 || !REG_P (target)) 9458 target = gen_reg_rtx (DImode); 9459 frv_split_iacc_move (target, src); 9460 return target; 9461 } 9462 9463 case FRV_BUILTIN_IACCreadl: 9464 return frv_read_iacc_argument (SImode, exp, 0); 9465 9466 case FRV_BUILTIN_IACCsetll: 9467 { 9468 rtx dest = frv_read_iacc_argument (DImode, exp, 0); 9469 rtx src = frv_read_argument (exp, 1); 9470 frv_split_iacc_move (dest, force_reg (DImode, src)); 9471 return 0; 9472 } 9473 9474 case FRV_BUILTIN_IACCsetl: 9475 { 9476 rtx dest = frv_read_iacc_argument (SImode, exp, 0); 9477 rtx src = frv_read_argument (exp, 1); 9478 emit_move_insn (dest, force_reg (SImode, src)); 9479 return 0; 9480 } 9481 9482 default: 9483 break; 9484 } 9485 9486 /* Expand groups of builtins. */ 9487 9488 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++) 9489 if (d->code == fcode) 9490 return frv_expand_set_builtin (d->icode, exp, target); 9491 9492 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) 9493 if (d->code == fcode) 9494 return frv_expand_unop_builtin (d->icode, exp, target); 9495 9496 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) 9497 if (d->code == fcode) 9498 return frv_expand_binop_builtin (d->icode, exp, target); 9499 9500 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++) 9501 if (d->code == fcode) 9502 return frv_expand_cut_builtin (d->icode, exp, target); 9503 9504 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++) 9505 if (d->code == fcode) 9506 return frv_expand_binopimm_builtin (d->icode, exp, target); 9507 9508 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++) 9509 if (d->code == fcode) 9510 return frv_expand_voidbinop_builtin (d->icode, exp); 9511 9512 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++) 9513 if (d->code == fcode) 9514 return frv_expand_voidtriop_builtin (d->icode, exp); 9515 9516 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++) 9517 if (d->code == fcode) 9518 return frv_expand_voidaccop_builtin (d->icode, exp); 9519 9520 for (i = 0, d = bdesc_int_void2arg; 9521 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++) 9522 if (d->code == fcode) 9523 return frv_expand_int_void2arg (d->icode, exp); 9524 9525 for (i = 0, d = bdesc_prefetches; 9526 i < ARRAY_SIZE (bdesc_prefetches); i++, d++) 9527 if (d->code == fcode) 9528 return frv_expand_prefetches (d->icode, exp); 9529 9530 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++) 9531 if (d->code == fcode) 9532 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)), 9533 exp, target); 9534 9535 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++) 9536 if (d->code == fcode) 9537 return frv_expand_store_builtin (d->icode, exp); 9538 9539 return 0; 9540} 9541 9542static bool 9543frv_in_small_data_p (const_tree decl) 9544{ 9545 HOST_WIDE_INT size; 9546 const_tree section_name; 9547 9548 /* Don't apply the -G flag to internal compiler structures. We 9549 should leave such structures in the main data section, partly 9550 for efficiency and partly because the size of some of them 9551 (such as C++ typeinfos) is not known until later. */ 9552 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl)) 9553 return false; 9554 9555 /* If we already know which section the decl should be in, see if 9556 it's a small data section. */ 9557 section_name = DECL_SECTION_NAME (decl); 9558 if (section_name) 9559 { 9560 gcc_assert (TREE_CODE (section_name) == STRING_CST); 9561 if (frv_string_begins_with (section_name, ".sdata")) 9562 return true; 9563 if (frv_string_begins_with (section_name, ".sbss")) 9564 return true; 9565 return false; 9566 } 9567 9568 size = int_size_in_bytes (TREE_TYPE (decl)); 9569 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value) 9570 return true; 9571 9572 return false; 9573} 9574 9575static bool 9576frv_rtx_costs (rtx x, 9577 int code ATTRIBUTE_UNUSED, 9578 int outer_code ATTRIBUTE_UNUSED, 9579 int *total, 9580 bool speed ATTRIBUTE_UNUSED) 9581{ 9582 if (outer_code == MEM) 9583 { 9584 /* Don't differentiate between memory addresses. All the ones 9585 we accept have equal cost. */ 9586 *total = COSTS_N_INSNS (0); 9587 return true; 9588 } 9589 9590 switch (code) 9591 { 9592 case CONST_INT: 9593 /* Make 12-bit integers really cheap. */ 9594 if (IN_RANGE_P (INTVAL (x), -2048, 2047)) 9595 { 9596 *total = 0; 9597 return true; 9598 } 9599 /* Fall through. */ 9600 9601 case CONST: 9602 case LABEL_REF: 9603 case SYMBOL_REF: 9604 case CONST_DOUBLE: 9605 *total = COSTS_N_INSNS (2); 9606 return true; 9607 9608 case PLUS: 9609 case MINUS: 9610 case AND: 9611 case IOR: 9612 case XOR: 9613 case ASHIFT: 9614 case ASHIFTRT: 9615 case LSHIFTRT: 9616 case NOT: 9617 case NEG: 9618 case COMPARE: 9619 if (GET_MODE (x) == SImode) 9620 *total = COSTS_N_INSNS (1); 9621 else if (GET_MODE (x) == DImode) 9622 *total = COSTS_N_INSNS (2); 9623 else 9624 *total = COSTS_N_INSNS (3); 9625 return true; 9626 9627 case MULT: 9628 if (GET_MODE (x) == SImode) 9629 *total = COSTS_N_INSNS (2); 9630 else 9631 *total = COSTS_N_INSNS (6); /* guess */ 9632 return true; 9633 9634 case DIV: 9635 case UDIV: 9636 case MOD: 9637 case UMOD: 9638 *total = COSTS_N_INSNS (18); 9639 return true; 9640 9641 case MEM: 9642 *total = COSTS_N_INSNS (3); 9643 return true; 9644 9645 default: 9646 return false; 9647 } 9648} 9649 9650static void 9651frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED) 9652{ 9653 switch_to_section (ctors_section); 9654 assemble_align (POINTER_SIZE); 9655 if (TARGET_FDPIC) 9656 { 9657 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1); 9658 9659 gcc_assert (ok); 9660 return; 9661 } 9662 assemble_integer_with_op ("\t.picptr\t", symbol); 9663} 9664 9665static void 9666frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED) 9667{ 9668 switch_to_section (dtors_section); 9669 assemble_align (POINTER_SIZE); 9670 if (TARGET_FDPIC) 9671 { 9672 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1); 9673 9674 gcc_assert (ok); 9675 return; 9676 } 9677 assemble_integer_with_op ("\t.picptr\t", symbol); 9678} 9679 9680/* Worker function for TARGET_STRUCT_VALUE_RTX. */ 9681 9682static rtx 9683frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, 9684 int incoming ATTRIBUTE_UNUSED) 9685{ 9686 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM); 9687} 9688 9689#define TLS_BIAS (2048 - 16) 9690 9691/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. 9692 We need to emit DTP-relative relocations. */ 9693 9694static void 9695frv_output_dwarf_dtprel (FILE *file, int size, rtx x) 9696{ 9697 gcc_assert (size == 4); 9698 fputs ("\t.picptr\ttlsmoff(", file); 9699 /* We want the unbiased TLS offset, so add the bias to the 9700 expression, such that the implicit biasing cancels out. */ 9701 output_addr_const (file, plus_constant (x, TLS_BIAS)); 9702 fputs (")", file); 9703} 9704 9705#include "gt-frv.h" 9706