1/* tc-arm.c -- Assemble for the ARM 2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 3 2004, 2005, 2006, 2007, 2008, 2009, 2010 4 Free Software Foundation, Inc. 5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) 6 Modified by David Taylor (dtaylor@armltd.co.uk) 7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) 8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) 9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) 10 11 This file is part of GAS, the GNU Assembler. 12 13 GAS is free software; you can redistribute it and/or modify 14 it under the terms of the GNU General Public License as published by 15 the Free Software Foundation; either version 3, or (at your option) 16 any later version. 17 18 GAS is distributed in the hope that it will be useful, 19 but WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 GNU General Public License for more details. 22 23 You should have received a copy of the GNU General Public License 24 along with GAS; see the file COPYING. If not, write to the Free 25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 26 02110-1301, USA. */ 27 28#include "as.h" 29#include <limits.h> 30#include <stdarg.h> 31#define NO_RELOC 0 32#include "safe-ctype.h" 33#include "subsegs.h" 34#include "obstack.h" 35 36#include "opcode/arm.h" 37 38#ifdef OBJ_ELF 39#include "elf/arm.h" 40#include "dw2gencfi.h" 41#endif 42 43#include "dwarf2dbg.h" 44 45#ifdef OBJ_ELF 46/* Must be at least the size of the largest unwind opcode (currently two). */ 47#define ARM_OPCODE_CHUNK_SIZE 8 48 49/* This structure holds the unwinding state. */ 50 51static struct 52{ 53 symbolS * proc_start; 54 symbolS * table_entry; 55 symbolS * personality_routine; 56 int personality_index; 57 /* The segment containing the function. */ 58 segT saved_seg; 59 subsegT saved_subseg; 60 /* Opcodes generated from this function. */ 61 unsigned char * opcodes; 62 int opcode_count; 63 int opcode_alloc; 64 /* The number of bytes pushed to the stack. */ 65 offsetT frame_size; 66 /* We don't add stack adjustment opcodes immediately so that we can merge 67 multiple adjustments. We can also omit the final adjustment 68 when using a frame pointer. */ 69 offsetT pending_offset; 70 /* These two fields are set by both unwind_movsp and unwind_setfp. They 71 hold the reg+offset to use when restoring sp from a frame pointer. */ 72 offsetT fp_offset; 73 int fp_reg; 74 /* Nonzero if an unwind_setfp directive has been seen. */ 75 unsigned fp_used:1; 76 /* Nonzero if the last opcode restores sp from fp_reg. */ 77 unsigned sp_restored:1; 78} unwind; 79 80#endif /* OBJ_ELF */ 81 82/* Results from operand parsing worker functions. */ 83 84typedef enum 85{ 86 PARSE_OPERAND_SUCCESS, 87 PARSE_OPERAND_FAIL, 88 PARSE_OPERAND_FAIL_NO_BACKTRACK 89} parse_operand_result; 90 91enum arm_float_abi 92{ 93 ARM_FLOAT_ABI_HARD, 94 ARM_FLOAT_ABI_SOFTFP, 95 ARM_FLOAT_ABI_SOFT 96}; 97 98/* Types of processor to assemble for. */ 99#ifndef CPU_DEFAULT 100/* The code that was here used to select a default CPU depending on compiler 101 pre-defines which were only present when doing native builds, thus 102 changing gas' default behaviour depending upon the build host. 103 104 If you have a target that requires a default CPU option then the you 105 should define CPU_DEFAULT here. */ 106#endif 107 108#ifndef FPU_DEFAULT 109# ifdef TE_LINUX 110# define FPU_DEFAULT FPU_ARCH_FPA 111# elif defined (TE_NetBSD) 112# ifdef OBJ_ELF 113# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ 114# else 115 /* Legacy a.out format. */ 116# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ 117# endif 118# elif defined (TE_VXWORKS) 119# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ 120# else 121 /* For backwards compatibility, default to FPA. */ 122# define FPU_DEFAULT FPU_ARCH_FPA 123# endif 124#endif /* ifndef FPU_DEFAULT */ 125 126#define streq(a, b) (strcmp (a, b) == 0) 127 128static arm_feature_set cpu_variant; 129static arm_feature_set arm_arch_used; 130static arm_feature_set thumb_arch_used; 131 132/* Flags stored in private area of BFD structure. */ 133static int uses_apcs_26 = FALSE; 134static int atpcs = FALSE; 135static int support_interwork = FALSE; 136static int uses_apcs_float = FALSE; 137static int pic_code = FALSE; 138static int fix_v4bx = FALSE; 139/* Warn on using deprecated features. */ 140static int warn_on_deprecated = TRUE; 141 142 143/* Variables that we set while parsing command-line options. Once all 144 options have been read we re-process these values to set the real 145 assembly flags. */ 146static const arm_feature_set *legacy_cpu = NULL; 147static const arm_feature_set *legacy_fpu = NULL; 148 149static const arm_feature_set *mcpu_cpu_opt = NULL; 150static const arm_feature_set *mcpu_fpu_opt = NULL; 151static const arm_feature_set *march_cpu_opt = NULL; 152static const arm_feature_set *march_fpu_opt = NULL; 153static const arm_feature_set *mfpu_opt = NULL; 154static const arm_feature_set *object_arch = NULL; 155 156/* Constants for known architecture features. */ 157static const arm_feature_set fpu_default = FPU_DEFAULT; 158static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; 159static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; 160static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; 161static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; 162static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; 163static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; 164static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; 165static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; 166 167#ifdef CPU_DEFAULT 168static const arm_feature_set cpu_default = CPU_DEFAULT; 169#endif 170 171static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); 172static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); 173static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); 174static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); 175static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); 176static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); 177static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); 178static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); 179static const arm_feature_set arm_ext_v4t_5 = 180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); 181static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); 182static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); 183static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); 184static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); 185static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); 186static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); 187static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); 188static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0); 189static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); 190static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0); 191static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0); 192static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0); 193static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); 194static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); 195static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); 196static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); 197static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); 198static const arm_feature_set arm_ext_m = 199 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0); 200static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0); 201static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0); 202static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0); 203static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0); 204static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0); 205 206static const arm_feature_set arm_arch_any = ARM_ANY; 207static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); 208static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; 209static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; 210static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY; 211 212static const arm_feature_set arm_cext_iwmmxt2 = 213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2); 214static const arm_feature_set arm_cext_iwmmxt = 215 ARM_FEATURE (0, ARM_CEXT_IWMMXT); 216static const arm_feature_set arm_cext_xscale = 217 ARM_FEATURE (0, ARM_CEXT_XSCALE); 218static const arm_feature_set arm_cext_maverick = 219 ARM_FEATURE (0, ARM_CEXT_MAVERICK); 220static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); 221static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); 222static const arm_feature_set fpu_vfp_ext_v1xd = 223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD); 224static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); 225static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); 226static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD); 227static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); 228static const arm_feature_set fpu_vfp_ext_d32 = 229 ARM_FEATURE (0, FPU_VFP_EXT_D32); 230static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); 231static const arm_feature_set fpu_vfp_v3_or_neon_ext = 232 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); 233static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16); 234static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA); 235static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA); 236 237static int mfloat_abi_opt = -1; 238/* Record user cpu selection for object attributes. */ 239static arm_feature_set selected_cpu = ARM_ARCH_NONE; 240/* Must be long enough to hold any of the names in arm_cpus. */ 241static char selected_cpu_name[16]; 242#ifdef OBJ_ELF 243# ifdef EABI_DEFAULT 244static int meabi_flags = EABI_DEFAULT; 245# else 246static int meabi_flags = EF_ARM_EABI_UNKNOWN; 247# endif 248 249static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; 250 251bfd_boolean 252arm_is_eabi (void) 253{ 254 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); 255} 256#endif 257 258#ifdef OBJ_ELF 259/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ 260symbolS * GOT_symbol; 261#endif 262 263/* 0: assemble for ARM, 264 1: assemble for Thumb, 265 2: assemble for Thumb even though target CPU does not support thumb 266 instructions. */ 267static int thumb_mode = 0; 268/* A value distinct from the possible values for thumb_mode that we 269 can use to record whether thumb_mode has been copied into the 270 tc_frag_data field of a frag. */ 271#define MODE_RECORDED (1 << 4) 272 273/* Specifies the intrinsic IT insn behavior mode. */ 274enum implicit_it_mode 275{ 276 IMPLICIT_IT_MODE_NEVER = 0x00, 277 IMPLICIT_IT_MODE_ARM = 0x01, 278 IMPLICIT_IT_MODE_THUMB = 0x02, 279 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) 280}; 281static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; 282 283/* If unified_syntax is true, we are processing the new unified 284 ARM/Thumb syntax. Important differences from the old ARM mode: 285 286 - Immediate operands do not require a # prefix. 287 - Conditional affixes always appear at the end of the 288 instruction. (For backward compatibility, those instructions 289 that formerly had them in the middle, continue to accept them 290 there.) 291 - The IT instruction may appear, and if it does is validated 292 against subsequent conditional affixes. It does not generate 293 machine code. 294 295 Important differences from the old Thumb mode: 296 297 - Immediate operands do not require a # prefix. 298 - Most of the V6T2 instructions are only available in unified mode. 299 - The .N and .W suffixes are recognized and honored (it is an error 300 if they cannot be honored). 301 - All instructions set the flags if and only if they have an 's' affix. 302 - Conditional affixes may be used. They are validated against 303 preceding IT instructions. Unlike ARM mode, you cannot use a 304 conditional affix except in the scope of an IT instruction. */ 305 306static bfd_boolean unified_syntax = FALSE; 307 308enum neon_el_type 309{ 310 NT_invtype, 311 NT_untyped, 312 NT_integer, 313 NT_float, 314 NT_poly, 315 NT_signed, 316 NT_unsigned 317}; 318 319struct neon_type_el 320{ 321 enum neon_el_type type; 322 unsigned size; 323}; 324 325#define NEON_MAX_TYPE_ELS 4 326 327struct neon_type 328{ 329 struct neon_type_el el[NEON_MAX_TYPE_ELS]; 330 unsigned elems; 331}; 332 333enum it_instruction_type 334{ 335 OUTSIDE_IT_INSN, 336 INSIDE_IT_INSN, 337 INSIDE_IT_LAST_INSN, 338 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; 339 if inside, should be the last one. */ 340 NEUTRAL_IT_INSN, /* This could be either inside or outside, 341 i.e. BKPT and NOP. */ 342 IT_INSN /* The IT insn has been parsed. */ 343}; 344 345struct arm_it 346{ 347 const char * error; 348 unsigned long instruction; 349 int size; 350 int size_req; 351 int cond; 352 /* "uncond_value" is set to the value in place of the conditional field in 353 unconditional versions of the instruction, or -1 if nothing is 354 appropriate. */ 355 int uncond_value; 356 struct neon_type vectype; 357 /* This does not indicate an actual NEON instruction, only that 358 the mnemonic accepts neon-style type suffixes. */ 359 int is_neon; 360 /* Set to the opcode if the instruction needs relaxation. 361 Zero if the instruction is not relaxed. */ 362 unsigned long relax; 363 struct 364 { 365 bfd_reloc_code_real_type type; 366 expressionS exp; 367 int pc_rel; 368 } reloc; 369 370 enum it_instruction_type it_insn_type; 371 372 struct 373 { 374 unsigned reg; 375 signed int imm; 376 struct neon_type_el vectype; 377 unsigned present : 1; /* Operand present. */ 378 unsigned isreg : 1; /* Operand was a register. */ 379 unsigned immisreg : 1; /* .imm field is a second register. */ 380 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ 381 unsigned immisalign : 1; /* Immediate is an alignment specifier. */ 382 unsigned immisfloat : 1; /* Immediate was parsed as a float. */ 383 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV 384 instructions. This allows us to disambiguate ARM <-> vector insns. */ 385 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ 386 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ 387 unsigned isquad : 1; /* Operand is Neon quad-precision register. */ 388 unsigned issingle : 1; /* Operand is VFP single-precision register. */ 389 unsigned hasreloc : 1; /* Operand has relocation suffix. */ 390 unsigned writeback : 1; /* Operand has trailing ! */ 391 unsigned preind : 1; /* Preindexed address. */ 392 unsigned postind : 1; /* Postindexed address. */ 393 unsigned negative : 1; /* Index register was negated. */ 394 unsigned shifted : 1; /* Shift applied to operation. */ 395 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ 396 } operands[6]; 397}; 398 399static struct arm_it inst; 400 401#define NUM_FLOAT_VALS 8 402 403const char * fp_const[] = 404{ 405 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 406}; 407 408/* Number of littlenums required to hold an extended precision number. */ 409#define MAX_LITTLENUMS 6 410 411LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; 412 413#define FAIL (-1) 414#define SUCCESS (0) 415 416#define SUFF_S 1 417#define SUFF_D 2 418#define SUFF_E 3 419#define SUFF_P 4 420 421#define CP_T_X 0x00008000 422#define CP_T_Y 0x00400000 423 424#define CONDS_BIT 0x00100000 425#define LOAD_BIT 0x00100000 426 427#define DOUBLE_LOAD_FLAG 0x00000001 428 429struct asm_cond 430{ 431 const char * template_name; 432 unsigned long value; 433}; 434 435#define COND_ALWAYS 0xE 436 437struct asm_psr 438{ 439 const char * template_name; 440 unsigned long field; 441}; 442 443struct asm_barrier_opt 444{ 445 const char * template_name; 446 unsigned long value; 447}; 448 449/* The bit that distinguishes CPSR and SPSR. */ 450#define SPSR_BIT (1 << 22) 451 452/* The individual PSR flag bits. */ 453#define PSR_c (1 << 16) 454#define PSR_x (1 << 17) 455#define PSR_s (1 << 18) 456#define PSR_f (1 << 19) 457 458struct reloc_entry 459{ 460 char * name; 461 bfd_reloc_code_real_type reloc; 462}; 463 464enum vfp_reg_pos 465{ 466 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, 467 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn 468}; 469 470enum vfp_ldstm_type 471{ 472 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX 473}; 474 475/* Bits for DEFINED field in neon_typed_alias. */ 476#define NTA_HASTYPE 1 477#define NTA_HASINDEX 2 478 479struct neon_typed_alias 480{ 481 unsigned char defined; 482 unsigned char index; 483 struct neon_type_el eltype; 484}; 485 486/* ARM register categories. This includes coprocessor numbers and various 487 architecture extensions' registers. */ 488enum arm_reg_type 489{ 490 REG_TYPE_RN, 491 REG_TYPE_CP, 492 REG_TYPE_CN, 493 REG_TYPE_FN, 494 REG_TYPE_VFS, 495 REG_TYPE_VFD, 496 REG_TYPE_NQ, 497 REG_TYPE_VFSD, 498 REG_TYPE_NDQ, 499 REG_TYPE_NSDQ, 500 REG_TYPE_VFC, 501 REG_TYPE_MVF, 502 REG_TYPE_MVD, 503 REG_TYPE_MVFX, 504 REG_TYPE_MVDX, 505 REG_TYPE_MVAX, 506 REG_TYPE_DSPSC, 507 REG_TYPE_MMXWR, 508 REG_TYPE_MMXWC, 509 REG_TYPE_MMXWCG, 510 REG_TYPE_XSCALE, 511 REG_TYPE_RNB 512}; 513 514/* Structure for a hash table entry for a register. 515 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra 516 information which states whether a vector type or index is specified (for a 517 register alias created with .dn or .qn). Otherwise NEON should be NULL. */ 518struct reg_entry 519{ 520 const char * name; 521 unsigned int number; 522 unsigned char type; 523 unsigned char builtin; 524 struct neon_typed_alias * neon; 525}; 526 527/* Diagnostics used when we don't get a register of the expected type. */ 528const char * const reg_expected_msgs[] = 529{ 530 N_("ARM register expected"), 531 N_("bad or missing co-processor number"), 532 N_("co-processor register expected"), 533 N_("FPA register expected"), 534 N_("VFP single precision register expected"), 535 N_("VFP/Neon double precision register expected"), 536 N_("Neon quad precision register expected"), 537 N_("VFP single or double precision register expected"), 538 N_("Neon double or quad precision register expected"), 539 N_("VFP single, double or Neon quad precision register expected"), 540 N_("VFP system register expected"), 541 N_("Maverick MVF register expected"), 542 N_("Maverick MVD register expected"), 543 N_("Maverick MVFX register expected"), 544 N_("Maverick MVDX register expected"), 545 N_("Maverick MVAX register expected"), 546 N_("Maverick DSPSC register expected"), 547 N_("iWMMXt data register expected"), 548 N_("iWMMXt control register expected"), 549 N_("iWMMXt scalar register expected"), 550 N_("XScale accumulator register expected"), 551}; 552 553/* Some well known registers that we refer to directly elsewhere. */ 554#define REG_SP 13 555#define REG_LR 14 556#define REG_PC 15 557 558/* ARM instructions take 4bytes in the object file, Thumb instructions 559 take 2: */ 560#define INSN_SIZE 4 561 562struct asm_opcode 563{ 564 /* Basic string to match. */ 565 const char * template_name; 566 567 /* Parameters to instruction. */ 568 unsigned int operands[8]; 569 570 /* Conditional tag - see opcode_lookup. */ 571 unsigned int tag : 4; 572 573 /* Basic instruction code. */ 574 unsigned int avalue : 28; 575 576 /* Thumb-format instruction code. */ 577 unsigned int tvalue; 578 579 /* Which architecture variant provides this instruction. */ 580 const arm_feature_set * avariant; 581 const arm_feature_set * tvariant; 582 583 /* Function to call to encode instruction in ARM format. */ 584 void (* aencode) (void); 585 586 /* Function to call to encode instruction in Thumb format. */ 587 void (* tencode) (void); 588}; 589 590/* Defines for various bits that we will want to toggle. */ 591#define INST_IMMEDIATE 0x02000000 592#define OFFSET_REG 0x02000000 593#define HWOFFSET_IMM 0x00400000 594#define SHIFT_BY_REG 0x00000010 595#define PRE_INDEX 0x01000000 596#define INDEX_UP 0x00800000 597#define WRITE_BACK 0x00200000 598#define LDM_TYPE_2_OR_3 0x00400000 599#define CPSI_MMOD 0x00020000 600 601#define LITERAL_MASK 0xf000f000 602#define OPCODE_MASK 0xfe1fffff 603#define V4_STR_BIT 0x00000020 604 605#define T2_SUBS_PC_LR 0xf3de8f00 606 607#define DATA_OP_SHIFT 21 608 609#define T2_OPCODE_MASK 0xfe1fffff 610#define T2_DATA_OP_SHIFT 21 611 612/* Codes to distinguish the arithmetic instructions. */ 613#define OPCODE_AND 0 614#define OPCODE_EOR 1 615#define OPCODE_SUB 2 616#define OPCODE_RSB 3 617#define OPCODE_ADD 4 618#define OPCODE_ADC 5 619#define OPCODE_SBC 6 620#define OPCODE_RSC 7 621#define OPCODE_TST 8 622#define OPCODE_TEQ 9 623#define OPCODE_CMP 10 624#define OPCODE_CMN 11 625#define OPCODE_ORR 12 626#define OPCODE_MOV 13 627#define OPCODE_BIC 14 628#define OPCODE_MVN 15 629 630#define T2_OPCODE_AND 0 631#define T2_OPCODE_BIC 1 632#define T2_OPCODE_ORR 2 633#define T2_OPCODE_ORN 3 634#define T2_OPCODE_EOR 4 635#define T2_OPCODE_ADD 8 636#define T2_OPCODE_ADC 10 637#define T2_OPCODE_SBC 11 638#define T2_OPCODE_SUB 13 639#define T2_OPCODE_RSB 14 640 641#define T_OPCODE_MUL 0x4340 642#define T_OPCODE_TST 0x4200 643#define T_OPCODE_CMN 0x42c0 644#define T_OPCODE_NEG 0x4240 645#define T_OPCODE_MVN 0x43c0 646 647#define T_OPCODE_ADD_R3 0x1800 648#define T_OPCODE_SUB_R3 0x1a00 649#define T_OPCODE_ADD_HI 0x4400 650#define T_OPCODE_ADD_ST 0xb000 651#define T_OPCODE_SUB_ST 0xb080 652#define T_OPCODE_ADD_SP 0xa800 653#define T_OPCODE_ADD_PC 0xa000 654#define T_OPCODE_ADD_I8 0x3000 655#define T_OPCODE_SUB_I8 0x3800 656#define T_OPCODE_ADD_I3 0x1c00 657#define T_OPCODE_SUB_I3 0x1e00 658 659#define T_OPCODE_ASR_R 0x4100 660#define T_OPCODE_LSL_R 0x4080 661#define T_OPCODE_LSR_R 0x40c0 662#define T_OPCODE_ROR_R 0x41c0 663#define T_OPCODE_ASR_I 0x1000 664#define T_OPCODE_LSL_I 0x0000 665#define T_OPCODE_LSR_I 0x0800 666 667#define T_OPCODE_MOV_I8 0x2000 668#define T_OPCODE_CMP_I8 0x2800 669#define T_OPCODE_CMP_LR 0x4280 670#define T_OPCODE_MOV_HR 0x4600 671#define T_OPCODE_CMP_HR 0x4500 672 673#define T_OPCODE_LDR_PC 0x4800 674#define T_OPCODE_LDR_SP 0x9800 675#define T_OPCODE_STR_SP 0x9000 676#define T_OPCODE_LDR_IW 0x6800 677#define T_OPCODE_STR_IW 0x6000 678#define T_OPCODE_LDR_IH 0x8800 679#define T_OPCODE_STR_IH 0x8000 680#define T_OPCODE_LDR_IB 0x7800 681#define T_OPCODE_STR_IB 0x7000 682#define T_OPCODE_LDR_RW 0x5800 683#define T_OPCODE_STR_RW 0x5000 684#define T_OPCODE_LDR_RH 0x5a00 685#define T_OPCODE_STR_RH 0x5200 686#define T_OPCODE_LDR_RB 0x5c00 687#define T_OPCODE_STR_RB 0x5400 688 689#define T_OPCODE_PUSH 0xb400 690#define T_OPCODE_POP 0xbc00 691 692#define T_OPCODE_BRANCH 0xe000 693 694#define THUMB_SIZE 2 /* Size of thumb instruction. */ 695#define THUMB_PP_PC_LR 0x0100 696#define THUMB_LOAD_BIT 0x0800 697#define THUMB2_LOAD_BIT 0x00100000 698 699#define BAD_ARGS _("bad arguments to instruction") 700#define BAD_SP _("r13 not allowed here") 701#define BAD_PC _("r15 not allowed here") 702#define BAD_COND _("instruction cannot be conditional") 703#define BAD_OVERLAP _("registers may not be the same") 704#define BAD_HIREG _("lo register required") 705#define BAD_THUMB32 _("instruction not supported in Thumb16 mode") 706#define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); 707#define BAD_BRANCH _("branch must be last instruction in IT block") 708#define BAD_NOT_IT _("instruction not allowed in IT block") 709#define BAD_FPU _("selected FPU does not support instruction") 710#define BAD_OUT_IT _("thumb conditional instruction should be in IT block") 711#define BAD_IT_COND _("incorrect condition in IT block") 712#define BAD_IT_IT _("IT falling in the range of a previous IT block") 713#define MISSING_FNSTART _("missing .fnstart before unwinding directive") 714#define BAD_PC_ADDRESSING \ 715 _("cannot use register index with PC-relative addressing") 716#define BAD_PC_WRITEBACK \ 717 _("cannot use writeback with PC-relative addressing") 718 719static struct hash_control * arm_ops_hsh; 720static struct hash_control * arm_cond_hsh; 721static struct hash_control * arm_shift_hsh; 722static struct hash_control * arm_psr_hsh; 723static struct hash_control * arm_v7m_psr_hsh; 724static struct hash_control * arm_reg_hsh; 725static struct hash_control * arm_reloc_hsh; 726static struct hash_control * arm_barrier_opt_hsh; 727 728/* Stuff needed to resolve the label ambiguity 729 As: 730 ... 731 label: <insn> 732 may differ from: 733 ... 734 label: 735 <insn> */ 736 737symbolS * last_label_seen; 738static int label_is_thumb_function_name = FALSE; 739 740/* Literal pool structure. Held on a per-section 741 and per-sub-section basis. */ 742 743#define MAX_LITERAL_POOL_SIZE 1024 744typedef struct literal_pool 745{ 746 expressionS literals [MAX_LITERAL_POOL_SIZE]; 747 unsigned int next_free_entry; 748 unsigned int id; 749 symbolS * symbol; 750 segT section; 751 subsegT sub_section; 752 struct literal_pool * next; 753} literal_pool; 754 755/* Pointer to a linked list of literal pools. */ 756literal_pool * list_of_pools = NULL; 757 758#ifdef OBJ_ELF 759# define now_it seg_info (now_seg)->tc_segment_info_data.current_it 760#else 761static struct current_it now_it; 762#endif 763 764static inline int 765now_it_compatible (int cond) 766{ 767 return (cond & ~1) == (now_it.cc & ~1); 768} 769 770static inline int 771conditional_insn (void) 772{ 773 return inst.cond != COND_ALWAYS; 774} 775 776static int in_it_block (void); 777 778static int handle_it_state (void); 779 780static void force_automatic_it_block_close (void); 781 782static void it_fsm_post_encode (void); 783 784#define set_it_insn_type(type) \ 785 do \ 786 { \ 787 inst.it_insn_type = type; \ 788 if (handle_it_state () == FAIL) \ 789 return; \ 790 } \ 791 while (0) 792 793#define set_it_insn_type_nonvoid(type, failret) \ 794 do \ 795 { \ 796 inst.it_insn_type = type; \ 797 if (handle_it_state () == FAIL) \ 798 return failret; \ 799 } \ 800 while(0) 801 802#define set_it_insn_type_last() \ 803 do \ 804 { \ 805 if (inst.cond == COND_ALWAYS) \ 806 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \ 807 else \ 808 set_it_insn_type (INSIDE_IT_LAST_INSN); \ 809 } \ 810 while (0) 811 812/* Pure syntax. */ 813 814/* This array holds the chars that always start a comment. If the 815 pre-processor is disabled, these aren't very useful. */ 816const char comment_chars[] = "@"; 817 818/* This array holds the chars that only start a comment at the beginning of 819 a line. If the line seems to have the form '# 123 filename' 820 .line and .file directives will appear in the pre-processed output. */ 821/* Note that input_file.c hand checks for '#' at the beginning of the 822 first line of the input file. This is because the compiler outputs 823 #NO_APP at the beginning of its output. */ 824/* Also note that comments like this one will always work. */ 825const char line_comment_chars[] = "#"; 826 827const char line_separator_chars[] = ";"; 828 829/* Chars that can be used to separate mant 830 from exp in floating point numbers. */ 831const char EXP_CHARS[] = "eE"; 832 833/* Chars that mean this number is a floating point constant. */ 834/* As in 0f12.456 */ 835/* or 0d1.2345e12 */ 836 837const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; 838 839/* Prefix characters that indicate the start of an immediate 840 value. */ 841#define is_immediate_prefix(C) ((C) == '#' || (C) == '$') 842 843/* Separator character handling. */ 844 845#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) 846 847static inline int 848skip_past_char (char ** str, char c) 849{ 850 if (**str == c) 851 { 852 (*str)++; 853 return SUCCESS; 854 } 855 else 856 return FAIL; 857} 858 859#define skip_past_comma(str) skip_past_char (str, ',') 860 861/* Arithmetic expressions (possibly involving symbols). */ 862 863/* Return TRUE if anything in the expression is a bignum. */ 864 865static int 866walk_no_bignums (symbolS * sp) 867{ 868 if (symbol_get_value_expression (sp)->X_op == O_big) 869 return 1; 870 871 if (symbol_get_value_expression (sp)->X_add_symbol) 872 { 873 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) 874 || (symbol_get_value_expression (sp)->X_op_symbol 875 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); 876 } 877 878 return 0; 879} 880 881static int in_my_get_expression = 0; 882 883/* Third argument to my_get_expression. */ 884#define GE_NO_PREFIX 0 885#define GE_IMM_PREFIX 1 886#define GE_OPT_PREFIX 2 887/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) 888 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ 889#define GE_OPT_PREFIX_BIG 3 890 891static int 892my_get_expression (expressionS * ep, char ** str, int prefix_mode) 893{ 894 char * save_in; 895 segT seg; 896 897 /* In unified syntax, all prefixes are optional. */ 898 if (unified_syntax) 899 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode 900 : GE_OPT_PREFIX; 901 902 switch (prefix_mode) 903 { 904 case GE_NO_PREFIX: break; 905 case GE_IMM_PREFIX: 906 if (!is_immediate_prefix (**str)) 907 { 908 inst.error = _("immediate expression requires a # prefix"); 909 return FAIL; 910 } 911 (*str)++; 912 break; 913 case GE_OPT_PREFIX: 914 case GE_OPT_PREFIX_BIG: 915 if (is_immediate_prefix (**str)) 916 (*str)++; 917 break; 918 default: abort (); 919 } 920 921 memset (ep, 0, sizeof (expressionS)); 922 923 save_in = input_line_pointer; 924 input_line_pointer = *str; 925 in_my_get_expression = 1; 926 seg = expression (ep); 927 in_my_get_expression = 0; 928 929 if (ep->X_op == O_illegal || ep->X_op == O_absent) 930 { 931 /* We found a bad or missing expression in md_operand(). */ 932 *str = input_line_pointer; 933 input_line_pointer = save_in; 934 if (inst.error == NULL) 935 inst.error = (ep->X_op == O_absent 936 ? _("missing expression") :_("bad expression")); 937 return 1; 938 } 939 940#ifdef OBJ_AOUT 941 if (seg != absolute_section 942 && seg != text_section 943 && seg != data_section 944 && seg != bss_section 945 && seg != undefined_section) 946 { 947 inst.error = _("bad segment"); 948 *str = input_line_pointer; 949 input_line_pointer = save_in; 950 return 1; 951 } 952#else 953 (void) seg; 954#endif 955 956 /* Get rid of any bignums now, so that we don't generate an error for which 957 we can't establish a line number later on. Big numbers are never valid 958 in instructions, which is where this routine is always called. */ 959 if (prefix_mode != GE_OPT_PREFIX_BIG 960 && (ep->X_op == O_big 961 || (ep->X_add_symbol 962 && (walk_no_bignums (ep->X_add_symbol) 963 || (ep->X_op_symbol 964 && walk_no_bignums (ep->X_op_symbol)))))) 965 { 966 inst.error = _("invalid constant"); 967 *str = input_line_pointer; 968 input_line_pointer = save_in; 969 return 1; 970 } 971 972 *str = input_line_pointer; 973 input_line_pointer = save_in; 974 return 0; 975} 976 977/* Turn a string in input_line_pointer into a floating point constant 978 of type TYPE, and store the appropriate bytes in *LITP. The number 979 of LITTLENUMS emitted is stored in *SIZEP. An error message is 980 returned, or NULL on OK. 981 982 Note that fp constants aren't represent in the normal way on the ARM. 983 In big endian mode, things are as expected. However, in little endian 984 mode fp constants are big-endian word-wise, and little-endian byte-wise 985 within the words. For example, (double) 1.1 in big endian mode is 986 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is 987 the byte sequence 99 99 f1 3f 9a 99 99 99. 988 989 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ 990 991char * 992md_atof (int type, char * litP, int * sizeP) 993{ 994 int prec; 995 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 996 char *t; 997 int i; 998 999 switch (type) 1000 { 1001 case 'f': 1002 case 'F': 1003 case 's': 1004 case 'S': 1005 prec = 2; 1006 break; 1007 1008 case 'd': 1009 case 'D': 1010 case 'r': 1011 case 'R': 1012 prec = 4; 1013 break; 1014 1015 case 'x': 1016 case 'X': 1017 prec = 5; 1018 break; 1019 1020 case 'p': 1021 case 'P': 1022 prec = 5; 1023 break; 1024 1025 default: 1026 *sizeP = 0; 1027 return _("Unrecognized or unsupported floating point constant"); 1028 } 1029 1030 t = atof_ieee (input_line_pointer, type, words); 1031 if (t) 1032 input_line_pointer = t; 1033 *sizeP = prec * sizeof (LITTLENUM_TYPE); 1034 1035 if (target_big_endian) 1036 { 1037 for (i = 0; i < prec; i++) 1038 { 1039 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); 1040 litP += sizeof (LITTLENUM_TYPE); 1041 } 1042 } 1043 else 1044 { 1045 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) 1046 for (i = prec - 1; i >= 0; i--) 1047 { 1048 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); 1049 litP += sizeof (LITTLENUM_TYPE); 1050 } 1051 else 1052 /* For a 4 byte float the order of elements in `words' is 1 0. 1053 For an 8 byte float the order is 1 0 3 2. */ 1054 for (i = 0; i < prec; i += 2) 1055 { 1056 md_number_to_chars (litP, (valueT) words[i + 1], 1057 sizeof (LITTLENUM_TYPE)); 1058 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), 1059 (valueT) words[i], sizeof (LITTLENUM_TYPE)); 1060 litP += 2 * sizeof (LITTLENUM_TYPE); 1061 } 1062 } 1063 1064 return NULL; 1065} 1066 1067/* We handle all bad expressions here, so that we can report the faulty 1068 instruction in the error message. */ 1069void 1070md_operand (expressionS * exp) 1071{ 1072 if (in_my_get_expression) 1073 exp->X_op = O_illegal; 1074} 1075 1076/* Immediate values. */ 1077 1078/* Generic immediate-value read function for use in directives. 1079 Accepts anything that 'expression' can fold to a constant. 1080 *val receives the number. */ 1081#ifdef OBJ_ELF 1082static int 1083immediate_for_directive (int *val) 1084{ 1085 expressionS exp; 1086 exp.X_op = O_illegal; 1087 1088 if (is_immediate_prefix (*input_line_pointer)) 1089 { 1090 input_line_pointer++; 1091 expression (&exp); 1092 } 1093 1094 if (exp.X_op != O_constant) 1095 { 1096 as_bad (_("expected #constant")); 1097 ignore_rest_of_line (); 1098 return FAIL; 1099 } 1100 *val = exp.X_add_number; 1101 return SUCCESS; 1102} 1103#endif 1104 1105/* Register parsing. */ 1106 1107/* Generic register parser. CCP points to what should be the 1108 beginning of a register name. If it is indeed a valid register 1109 name, advance CCP over it and return the reg_entry structure; 1110 otherwise return NULL. Does not issue diagnostics. */ 1111 1112static struct reg_entry * 1113arm_reg_parse_multi (char **ccp) 1114{ 1115 char *start = *ccp; 1116 char *p; 1117 struct reg_entry *reg; 1118 1119#ifdef REGISTER_PREFIX 1120 if (*start != REGISTER_PREFIX) 1121 return NULL; 1122 start++; 1123#endif 1124#ifdef OPTIONAL_REGISTER_PREFIX 1125 if (*start == OPTIONAL_REGISTER_PREFIX) 1126 start++; 1127#endif 1128 1129 p = start; 1130 if (!ISALPHA (*p) || !is_name_beginner (*p)) 1131 return NULL; 1132 1133 do 1134 p++; 1135 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); 1136 1137 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); 1138 1139 if (!reg) 1140 return NULL; 1141 1142 *ccp = p; 1143 return reg; 1144} 1145 1146static int 1147arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, 1148 enum arm_reg_type type) 1149{ 1150 /* Alternative syntaxes are accepted for a few register classes. */ 1151 switch (type) 1152 { 1153 case REG_TYPE_MVF: 1154 case REG_TYPE_MVD: 1155 case REG_TYPE_MVFX: 1156 case REG_TYPE_MVDX: 1157 /* Generic coprocessor register names are allowed for these. */ 1158 if (reg && reg->type == REG_TYPE_CN) 1159 return reg->number; 1160 break; 1161 1162 case REG_TYPE_CP: 1163 /* For backward compatibility, a bare number is valid here. */ 1164 { 1165 unsigned long processor = strtoul (start, ccp, 10); 1166 if (*ccp != start && processor <= 15) 1167 return processor; 1168 } 1169 1170 case REG_TYPE_MMXWC: 1171 /* WC includes WCG. ??? I'm not sure this is true for all 1172 instructions that take WC registers. */ 1173 if (reg && reg->type == REG_TYPE_MMXWCG) 1174 return reg->number; 1175 break; 1176 1177 default: 1178 break; 1179 } 1180 1181 return FAIL; 1182} 1183 1184/* As arm_reg_parse_multi, but the register must be of type TYPE, and the 1185 return value is the register number or FAIL. */ 1186 1187static int 1188arm_reg_parse (char **ccp, enum arm_reg_type type) 1189{ 1190 char *start = *ccp; 1191 struct reg_entry *reg = arm_reg_parse_multi (ccp); 1192 int ret; 1193 1194 /* Do not allow a scalar (reg+index) to parse as a register. */ 1195 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) 1196 return FAIL; 1197 1198 if (reg && reg->type == type) 1199 return reg->number; 1200 1201 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) 1202 return ret; 1203 1204 *ccp = start; 1205 return FAIL; 1206} 1207 1208/* Parse a Neon type specifier. *STR should point at the leading '.' 1209 character. Does no verification at this stage that the type fits the opcode 1210 properly. E.g., 1211 1212 .i32.i32.s16 1213 .s32.f32 1214 .u16 1215 1216 Can all be legally parsed by this function. 1217 1218 Fills in neon_type struct pointer with parsed information, and updates STR 1219 to point after the parsed type specifier. Returns SUCCESS if this was a legal 1220 type, FAIL if not. */ 1221 1222static int 1223parse_neon_type (struct neon_type *type, char **str) 1224{ 1225 char *ptr = *str; 1226 1227 if (type) 1228 type->elems = 0; 1229 1230 while (type->elems < NEON_MAX_TYPE_ELS) 1231 { 1232 enum neon_el_type thistype = NT_untyped; 1233 unsigned thissize = -1u; 1234 1235 if (*ptr != '.') 1236 break; 1237 1238 ptr++; 1239 1240 /* Just a size without an explicit type. */ 1241 if (ISDIGIT (*ptr)) 1242 goto parsesize; 1243 1244 switch (TOLOWER (*ptr)) 1245 { 1246 case 'i': thistype = NT_integer; break; 1247 case 'f': thistype = NT_float; break; 1248 case 'p': thistype = NT_poly; break; 1249 case 's': thistype = NT_signed; break; 1250 case 'u': thistype = NT_unsigned; break; 1251 case 'd': 1252 thistype = NT_float; 1253 thissize = 64; 1254 ptr++; 1255 goto done; 1256 default: 1257 as_bad (_("unexpected character `%c' in type specifier"), *ptr); 1258 return FAIL; 1259 } 1260 1261 ptr++; 1262 1263 /* .f is an abbreviation for .f32. */ 1264 if (thistype == NT_float && !ISDIGIT (*ptr)) 1265 thissize = 32; 1266 else 1267 { 1268 parsesize: 1269 thissize = strtoul (ptr, &ptr, 10); 1270 1271 if (thissize != 8 && thissize != 16 && thissize != 32 1272 && thissize != 64) 1273 { 1274 as_bad (_("bad size %d in type specifier"), thissize); 1275 return FAIL; 1276 } 1277 } 1278 1279 done: 1280 if (type) 1281 { 1282 type->el[type->elems].type = thistype; 1283 type->el[type->elems].size = thissize; 1284 type->elems++; 1285 } 1286 } 1287 1288 /* Empty/missing type is not a successful parse. */ 1289 if (type->elems == 0) 1290 return FAIL; 1291 1292 *str = ptr; 1293 1294 return SUCCESS; 1295} 1296 1297/* Errors may be set multiple times during parsing or bit encoding 1298 (particularly in the Neon bits), but usually the earliest error which is set 1299 will be the most meaningful. Avoid overwriting it with later (cascading) 1300 errors by calling this function. */ 1301 1302static void 1303first_error (const char *err) 1304{ 1305 if (!inst.error) 1306 inst.error = err; 1307} 1308 1309/* Parse a single type, e.g. ".s32", leading period included. */ 1310static int 1311parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) 1312{ 1313 char *str = *ccp; 1314 struct neon_type optype; 1315 1316 if (*str == '.') 1317 { 1318 if (parse_neon_type (&optype, &str) == SUCCESS) 1319 { 1320 if (optype.elems == 1) 1321 *vectype = optype.el[0]; 1322 else 1323 { 1324 first_error (_("only one type should be specified for operand")); 1325 return FAIL; 1326 } 1327 } 1328 else 1329 { 1330 first_error (_("vector type expected")); 1331 return FAIL; 1332 } 1333 } 1334 else 1335 return FAIL; 1336 1337 *ccp = str; 1338 1339 return SUCCESS; 1340} 1341 1342/* Special meanings for indices (which have a range of 0-7), which will fit into 1343 a 4-bit integer. */ 1344 1345#define NEON_ALL_LANES 15 1346#define NEON_INTERLEAVE_LANES 14 1347 1348/* Parse either a register or a scalar, with an optional type. Return the 1349 register number, and optionally fill in the actual type of the register 1350 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and 1351 type/index information in *TYPEINFO. */ 1352 1353static int 1354parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, 1355 enum arm_reg_type *rtype, 1356 struct neon_typed_alias *typeinfo) 1357{ 1358 char *str = *ccp; 1359 struct reg_entry *reg = arm_reg_parse_multi (&str); 1360 struct neon_typed_alias atype; 1361 struct neon_type_el parsetype; 1362 1363 atype.defined = 0; 1364 atype.index = -1; 1365 atype.eltype.type = NT_invtype; 1366 atype.eltype.size = -1; 1367 1368 /* Try alternate syntax for some types of register. Note these are mutually 1369 exclusive with the Neon syntax extensions. */ 1370 if (reg == NULL) 1371 { 1372 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); 1373 if (altreg != FAIL) 1374 *ccp = str; 1375 if (typeinfo) 1376 *typeinfo = atype; 1377 return altreg; 1378 } 1379 1380 /* Undo polymorphism when a set of register types may be accepted. */ 1381 if ((type == REG_TYPE_NDQ 1382 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) 1383 || (type == REG_TYPE_VFSD 1384 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) 1385 || (type == REG_TYPE_NSDQ 1386 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD 1387 || reg->type == REG_TYPE_NQ)) 1388 || (type == REG_TYPE_MMXWC 1389 && (reg->type == REG_TYPE_MMXWCG))) 1390 type = (enum arm_reg_type) reg->type; 1391 1392 if (type != reg->type) 1393 return FAIL; 1394 1395 if (reg->neon) 1396 atype = *reg->neon; 1397 1398 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) 1399 { 1400 if ((atype.defined & NTA_HASTYPE) != 0) 1401 { 1402 first_error (_("can't redefine type for operand")); 1403 return FAIL; 1404 } 1405 atype.defined |= NTA_HASTYPE; 1406 atype.eltype = parsetype; 1407 } 1408 1409 if (skip_past_char (&str, '[') == SUCCESS) 1410 { 1411 if (type != REG_TYPE_VFD) 1412 { 1413 first_error (_("only D registers may be indexed")); 1414 return FAIL; 1415 } 1416 1417 if ((atype.defined & NTA_HASINDEX) != 0) 1418 { 1419 first_error (_("can't change index for operand")); 1420 return FAIL; 1421 } 1422 1423 atype.defined |= NTA_HASINDEX; 1424 1425 if (skip_past_char (&str, ']') == SUCCESS) 1426 atype.index = NEON_ALL_LANES; 1427 else 1428 { 1429 expressionS exp; 1430 1431 my_get_expression (&exp, &str, GE_NO_PREFIX); 1432 1433 if (exp.X_op != O_constant) 1434 { 1435 first_error (_("constant expression required")); 1436 return FAIL; 1437 } 1438 1439 if (skip_past_char (&str, ']') == FAIL) 1440 return FAIL; 1441 1442 atype.index = exp.X_add_number; 1443 } 1444 } 1445 1446 if (typeinfo) 1447 *typeinfo = atype; 1448 1449 if (rtype) 1450 *rtype = type; 1451 1452 *ccp = str; 1453 1454 return reg->number; 1455} 1456 1457/* Like arm_reg_parse, but allow allow the following extra features: 1458 - If RTYPE is non-zero, return the (possibly restricted) type of the 1459 register (e.g. Neon double or quad reg when either has been requested). 1460 - If this is a Neon vector type with additional type information, fill 1461 in the struct pointed to by VECTYPE (if non-NULL). 1462 This function will fault on encountering a scalar. */ 1463 1464static int 1465arm_typed_reg_parse (char **ccp, enum arm_reg_type type, 1466 enum arm_reg_type *rtype, struct neon_type_el *vectype) 1467{ 1468 struct neon_typed_alias atype; 1469 char *str = *ccp; 1470 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); 1471 1472 if (reg == FAIL) 1473 return FAIL; 1474 1475 /* Do not allow a scalar (reg+index) to parse as a register. */ 1476 if ((atype.defined & NTA_HASINDEX) != 0) 1477 { 1478 first_error (_("register operand expected, but got scalar")); 1479 return FAIL; 1480 } 1481 1482 if (vectype) 1483 *vectype = atype.eltype; 1484 1485 *ccp = str; 1486 1487 return reg; 1488} 1489 1490#define NEON_SCALAR_REG(X) ((X) >> 4) 1491#define NEON_SCALAR_INDEX(X) ((X) & 15) 1492 1493/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't 1494 have enough information to be able to do a good job bounds-checking. So, we 1495 just do easy checks here, and do further checks later. */ 1496 1497static int 1498parse_scalar (char **ccp, int elsize, struct neon_type_el *type) 1499{ 1500 int reg; 1501 char *str = *ccp; 1502 struct neon_typed_alias atype; 1503 1504 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); 1505 1506 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) 1507 return FAIL; 1508 1509 if (atype.index == NEON_ALL_LANES) 1510 { 1511 first_error (_("scalar must have an index")); 1512 return FAIL; 1513 } 1514 else if (atype.index >= 64 / elsize) 1515 { 1516 first_error (_("scalar index out of range")); 1517 return FAIL; 1518 } 1519 1520 if (type) 1521 *type = atype.eltype; 1522 1523 *ccp = str; 1524 1525 return reg * 16 + atype.index; 1526} 1527 1528/* Parse an ARM register list. Returns the bitmask, or FAIL. */ 1529 1530static long 1531parse_reg_list (char ** strp) 1532{ 1533 char * str = * strp; 1534 long range = 0; 1535 int another_range; 1536 1537 /* We come back here if we get ranges concatenated by '+' or '|'. */ 1538 do 1539 { 1540 another_range = 0; 1541 1542 if (*str == '{') 1543 { 1544 int in_range = 0; 1545 int cur_reg = -1; 1546 1547 str++; 1548 do 1549 { 1550 int reg; 1551 1552 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) 1553 { 1554 first_error (_(reg_expected_msgs[REG_TYPE_RN])); 1555 return FAIL; 1556 } 1557 1558 if (in_range) 1559 { 1560 int i; 1561 1562 if (reg <= cur_reg) 1563 { 1564 first_error (_("bad range in register list")); 1565 return FAIL; 1566 } 1567 1568 for (i = cur_reg + 1; i < reg; i++) 1569 { 1570 if (range & (1 << i)) 1571 as_tsktsk 1572 (_("Warning: duplicated register (r%d) in register list"), 1573 i); 1574 else 1575 range |= 1 << i; 1576 } 1577 in_range = 0; 1578 } 1579 1580 if (range & (1 << reg)) 1581 as_tsktsk (_("Warning: duplicated register (r%d) in register list"), 1582 reg); 1583 else if (reg <= cur_reg) 1584 as_tsktsk (_("Warning: register range not in ascending order")); 1585 1586 range |= 1 << reg; 1587 cur_reg = reg; 1588 } 1589 while (skip_past_comma (&str) != FAIL 1590 || (in_range = 1, *str++ == '-')); 1591 str--; 1592 1593 if (*str++ != '}') 1594 { 1595 first_error (_("missing `}'")); 1596 return FAIL; 1597 } 1598 } 1599 else 1600 { 1601 expressionS exp; 1602 1603 if (my_get_expression (&exp, &str, GE_NO_PREFIX)) 1604 return FAIL; 1605 1606 if (exp.X_op == O_constant) 1607 { 1608 if (exp.X_add_number 1609 != (exp.X_add_number & 0x0000ffff)) 1610 { 1611 inst.error = _("invalid register mask"); 1612 return FAIL; 1613 } 1614 1615 if ((range & exp.X_add_number) != 0) 1616 { 1617 int regno = range & exp.X_add_number; 1618 1619 regno &= -regno; 1620 regno = (1 << regno) - 1; 1621 as_tsktsk 1622 (_("Warning: duplicated register (r%d) in register list"), 1623 regno); 1624 } 1625 1626 range |= exp.X_add_number; 1627 } 1628 else 1629 { 1630 if (inst.reloc.type != 0) 1631 { 1632 inst.error = _("expression too complex"); 1633 return FAIL; 1634 } 1635 1636 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS)); 1637 inst.reloc.type = BFD_RELOC_ARM_MULTI; 1638 inst.reloc.pc_rel = 0; 1639 } 1640 } 1641 1642 if (*str == '|' || *str == '+') 1643 { 1644 str++; 1645 another_range = 1; 1646 } 1647 } 1648 while (another_range); 1649 1650 *strp = str; 1651 return range; 1652} 1653 1654/* Types of registers in a list. */ 1655 1656enum reg_list_els 1657{ 1658 REGLIST_VFP_S, 1659 REGLIST_VFP_D, 1660 REGLIST_NEON_D 1661}; 1662 1663/* Parse a VFP register list. If the string is invalid return FAIL. 1664 Otherwise return the number of registers, and set PBASE to the first 1665 register. Parses registers of type ETYPE. 1666 If REGLIST_NEON_D is used, several syntax enhancements are enabled: 1667 - Q registers can be used to specify pairs of D registers 1668 - { } can be omitted from around a singleton register list 1669 FIXME: This is not implemented, as it would require backtracking in 1670 some cases, e.g.: 1671 vtbl.8 d3,d4,d5 1672 This could be done (the meaning isn't really ambiguous), but doesn't 1673 fit in well with the current parsing framework. 1674 - 32 D registers may be used (also true for VFPv3). 1675 FIXME: Types are ignored in these register lists, which is probably a 1676 bug. */ 1677 1678static int 1679parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) 1680{ 1681 char *str = *ccp; 1682 int base_reg; 1683 int new_base; 1684 enum arm_reg_type regtype = (enum arm_reg_type) 0; 1685 int max_regs = 0; 1686 int count = 0; 1687 int warned = 0; 1688 unsigned long mask = 0; 1689 int i; 1690 1691 if (*str != '{') 1692 { 1693 inst.error = _("expecting {"); 1694 return FAIL; 1695 } 1696 1697 str++; 1698 1699 switch (etype) 1700 { 1701 case REGLIST_VFP_S: 1702 regtype = REG_TYPE_VFS; 1703 max_regs = 32; 1704 break; 1705 1706 case REGLIST_VFP_D: 1707 regtype = REG_TYPE_VFD; 1708 break; 1709 1710 case REGLIST_NEON_D: 1711 regtype = REG_TYPE_NDQ; 1712 break; 1713 } 1714 1715 if (etype != REGLIST_VFP_S) 1716 { 1717 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ 1718 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) 1719 { 1720 max_regs = 32; 1721 if (thumb_mode) 1722 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 1723 fpu_vfp_ext_d32); 1724 else 1725 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 1726 fpu_vfp_ext_d32); 1727 } 1728 else 1729 max_regs = 16; 1730 } 1731 1732 base_reg = max_regs; 1733 1734 do 1735 { 1736 int setmask = 1, addregs = 1; 1737 1738 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); 1739 1740 if (new_base == FAIL) 1741 { 1742 first_error (_(reg_expected_msgs[regtype])); 1743 return FAIL; 1744 } 1745 1746 if (new_base >= max_regs) 1747 { 1748 first_error (_("register out of range in list")); 1749 return FAIL; 1750 } 1751 1752 /* Note: a value of 2 * n is returned for the register Q<n>. */ 1753 if (regtype == REG_TYPE_NQ) 1754 { 1755 setmask = 3; 1756 addregs = 2; 1757 } 1758 1759 if (new_base < base_reg) 1760 base_reg = new_base; 1761 1762 if (mask & (setmask << new_base)) 1763 { 1764 first_error (_("invalid register list")); 1765 return FAIL; 1766 } 1767 1768 if ((mask >> new_base) != 0 && ! warned) 1769 { 1770 as_tsktsk (_("register list not in ascending order")); 1771 warned = 1; 1772 } 1773 1774 mask |= setmask << new_base; 1775 count += addregs; 1776 1777 if (*str == '-') /* We have the start of a range expression */ 1778 { 1779 int high_range; 1780 1781 str++; 1782 1783 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) 1784 == FAIL) 1785 { 1786 inst.error = gettext (reg_expected_msgs[regtype]); 1787 return FAIL; 1788 } 1789 1790 if (high_range >= max_regs) 1791 { 1792 first_error (_("register out of range in list")); 1793 return FAIL; 1794 } 1795 1796 if (regtype == REG_TYPE_NQ) 1797 high_range = high_range + 1; 1798 1799 if (high_range <= new_base) 1800 { 1801 inst.error = _("register range not in ascending order"); 1802 return FAIL; 1803 } 1804 1805 for (new_base += addregs; new_base <= high_range; new_base += addregs) 1806 { 1807 if (mask & (setmask << new_base)) 1808 { 1809 inst.error = _("invalid register list"); 1810 return FAIL; 1811 } 1812 1813 mask |= setmask << new_base; 1814 count += addregs; 1815 } 1816 } 1817 } 1818 while (skip_past_comma (&str) != FAIL); 1819 1820 str++; 1821 1822 /* Sanity check -- should have raised a parse error above. */ 1823 if (count == 0 || count > max_regs) 1824 abort (); 1825 1826 *pbase = base_reg; 1827 1828 /* Final test -- the registers must be consecutive. */ 1829 mask >>= base_reg; 1830 for (i = 0; i < count; i++) 1831 { 1832 if ((mask & (1u << i)) == 0) 1833 { 1834 inst.error = _("non-contiguous register range"); 1835 return FAIL; 1836 } 1837 } 1838 1839 *ccp = str; 1840 1841 return count; 1842} 1843 1844/* True if two alias types are the same. */ 1845 1846static bfd_boolean 1847neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) 1848{ 1849 if (!a && !b) 1850 return TRUE; 1851 1852 if (!a || !b) 1853 return FALSE; 1854 1855 if (a->defined != b->defined) 1856 return FALSE; 1857 1858 if ((a->defined & NTA_HASTYPE) != 0 1859 && (a->eltype.type != b->eltype.type 1860 || a->eltype.size != b->eltype.size)) 1861 return FALSE; 1862 1863 if ((a->defined & NTA_HASINDEX) != 0 1864 && (a->index != b->index)) 1865 return FALSE; 1866 1867 return TRUE; 1868} 1869 1870/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. 1871 The base register is put in *PBASE. 1872 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of 1873 the return value. 1874 The register stride (minus one) is put in bit 4 of the return value. 1875 Bits [6:5] encode the list length (minus one). 1876 The type of the list elements is put in *ELTYPE, if non-NULL. */ 1877 1878#define NEON_LANE(X) ((X) & 0xf) 1879#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) 1880#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) 1881 1882static int 1883parse_neon_el_struct_list (char **str, unsigned *pbase, 1884 struct neon_type_el *eltype) 1885{ 1886 char *ptr = *str; 1887 int base_reg = -1; 1888 int reg_incr = -1; 1889 int count = 0; 1890 int lane = -1; 1891 int leading_brace = 0; 1892 enum arm_reg_type rtype = REG_TYPE_NDQ; 1893 const char *const incr_error = _("register stride must be 1 or 2"); 1894 const char *const type_error = _("mismatched element/structure types in list"); 1895 struct neon_typed_alias firsttype; 1896 1897 if (skip_past_char (&ptr, '{') == SUCCESS) 1898 leading_brace = 1; 1899 1900 do 1901 { 1902 struct neon_typed_alias atype; 1903 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); 1904 1905 if (getreg == FAIL) 1906 { 1907 first_error (_(reg_expected_msgs[rtype])); 1908 return FAIL; 1909 } 1910 1911 if (base_reg == -1) 1912 { 1913 base_reg = getreg; 1914 if (rtype == REG_TYPE_NQ) 1915 { 1916 reg_incr = 1; 1917 } 1918 firsttype = atype; 1919 } 1920 else if (reg_incr == -1) 1921 { 1922 reg_incr = getreg - base_reg; 1923 if (reg_incr < 1 || reg_incr > 2) 1924 { 1925 first_error (_(incr_error)); 1926 return FAIL; 1927 } 1928 } 1929 else if (getreg != base_reg + reg_incr * count) 1930 { 1931 first_error (_(incr_error)); 1932 return FAIL; 1933 } 1934 1935 if (! neon_alias_types_same (&atype, &firsttype)) 1936 { 1937 first_error (_(type_error)); 1938 return FAIL; 1939 } 1940 1941 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list 1942 modes. */ 1943 if (ptr[0] == '-') 1944 { 1945 struct neon_typed_alias htype; 1946 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; 1947 if (lane == -1) 1948 lane = NEON_INTERLEAVE_LANES; 1949 else if (lane != NEON_INTERLEAVE_LANES) 1950 { 1951 first_error (_(type_error)); 1952 return FAIL; 1953 } 1954 if (reg_incr == -1) 1955 reg_incr = 1; 1956 else if (reg_incr != 1) 1957 { 1958 first_error (_("don't use Rn-Rm syntax with non-unit stride")); 1959 return FAIL; 1960 } 1961 ptr++; 1962 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); 1963 if (hireg == FAIL) 1964 { 1965 first_error (_(reg_expected_msgs[rtype])); 1966 return FAIL; 1967 } 1968 if (! neon_alias_types_same (&htype, &firsttype)) 1969 { 1970 first_error (_(type_error)); 1971 return FAIL; 1972 } 1973 count += hireg + dregs - getreg; 1974 continue; 1975 } 1976 1977 /* If we're using Q registers, we can't use [] or [n] syntax. */ 1978 if (rtype == REG_TYPE_NQ) 1979 { 1980 count += 2; 1981 continue; 1982 } 1983 1984 if ((atype.defined & NTA_HASINDEX) != 0) 1985 { 1986 if (lane == -1) 1987 lane = atype.index; 1988 else if (lane != atype.index) 1989 { 1990 first_error (_(type_error)); 1991 return FAIL; 1992 } 1993 } 1994 else if (lane == -1) 1995 lane = NEON_INTERLEAVE_LANES; 1996 else if (lane != NEON_INTERLEAVE_LANES) 1997 { 1998 first_error (_(type_error)); 1999 return FAIL; 2000 } 2001 count++; 2002 } 2003 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); 2004 2005 /* No lane set by [x]. We must be interleaving structures. */ 2006 if (lane == -1) 2007 lane = NEON_INTERLEAVE_LANES; 2008 2009 /* Sanity check. */ 2010 if (lane == -1 || base_reg == -1 || count < 1 || count > 4 2011 || (count > 1 && reg_incr == -1)) 2012 { 2013 first_error (_("error parsing element/structure list")); 2014 return FAIL; 2015 } 2016 2017 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) 2018 { 2019 first_error (_("expected }")); 2020 return FAIL; 2021 } 2022 2023 if (reg_incr == -1) 2024 reg_incr = 1; 2025 2026 if (eltype) 2027 *eltype = firsttype.eltype; 2028 2029 *pbase = base_reg; 2030 *str = ptr; 2031 2032 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); 2033} 2034 2035/* Parse an explicit relocation suffix on an expression. This is 2036 either nothing, or a word in parentheses. Note that if !OBJ_ELF, 2037 arm_reloc_hsh contains no entries, so this function can only 2038 succeed if there is no () after the word. Returns -1 on error, 2039 BFD_RELOC_UNUSED if there wasn't any suffix. */ 2040static int 2041parse_reloc (char **str) 2042{ 2043 struct reloc_entry *r; 2044 char *p, *q; 2045 2046 if (**str != '(') 2047 return BFD_RELOC_UNUSED; 2048 2049 p = *str + 1; 2050 q = p; 2051 2052 while (*q && *q != ')' && *q != ',') 2053 q++; 2054 if (*q != ')') 2055 return -1; 2056 2057 if ((r = (struct reloc_entry *) 2058 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) 2059 return -1; 2060 2061 *str = q + 1; 2062 return r->reloc; 2063} 2064 2065/* Directives: register aliases. */ 2066 2067static struct reg_entry * 2068insert_reg_alias (char *str, unsigned number, int type) 2069{ 2070 struct reg_entry *new_reg; 2071 const char *name; 2072 2073 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) 2074 { 2075 if (new_reg->builtin) 2076 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); 2077 2078 /* Only warn about a redefinition if it's not defined as the 2079 same register. */ 2080 else if (new_reg->number != number || new_reg->type != type) 2081 as_warn (_("ignoring redefinition of register alias '%s'"), str); 2082 2083 return NULL; 2084 } 2085 2086 name = xstrdup (str); 2087 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry)); 2088 2089 new_reg->name = name; 2090 new_reg->number = number; 2091 new_reg->type = type; 2092 new_reg->builtin = FALSE; 2093 new_reg->neon = NULL; 2094 2095 if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) 2096 abort (); 2097 2098 return new_reg; 2099} 2100 2101static void 2102insert_neon_reg_alias (char *str, int number, int type, 2103 struct neon_typed_alias *atype) 2104{ 2105 struct reg_entry *reg = insert_reg_alias (str, number, type); 2106 2107 if (!reg) 2108 { 2109 first_error (_("attempt to redefine typed alias")); 2110 return; 2111 } 2112 2113 if (atype) 2114 { 2115 reg->neon = (struct neon_typed_alias *) 2116 xmalloc (sizeof (struct neon_typed_alias)); 2117 *reg->neon = *atype; 2118 } 2119} 2120 2121/* Look for the .req directive. This is of the form: 2122 2123 new_register_name .req existing_register_name 2124 2125 If we find one, or if it looks sufficiently like one that we want to 2126 handle any error here, return TRUE. Otherwise return FALSE. */ 2127 2128static bfd_boolean 2129create_register_alias (char * newname, char *p) 2130{ 2131 struct reg_entry *old; 2132 char *oldname, *nbuf; 2133 size_t nlen; 2134 2135 /* The input scrubber ensures that whitespace after the mnemonic is 2136 collapsed to single spaces. */ 2137 oldname = p; 2138 if (strncmp (oldname, " .req ", 6) != 0) 2139 return FALSE; 2140 2141 oldname += 6; 2142 if (*oldname == '\0') 2143 return FALSE; 2144 2145 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); 2146 if (!old) 2147 { 2148 as_warn (_("unknown register '%s' -- .req ignored"), oldname); 2149 return TRUE; 2150 } 2151 2152 /* If TC_CASE_SENSITIVE is defined, then newname already points to 2153 the desired alias name, and p points to its end. If not, then 2154 the desired alias name is in the global original_case_string. */ 2155#ifdef TC_CASE_SENSITIVE 2156 nlen = p - newname; 2157#else 2158 newname = original_case_string; 2159 nlen = strlen (newname); 2160#endif 2161 2162 nbuf = (char *) alloca (nlen + 1); 2163 memcpy (nbuf, newname, nlen); 2164 nbuf[nlen] = '\0'; 2165 2166 /* Create aliases under the new name as stated; an all-lowercase 2167 version of the new name; and an all-uppercase version of the new 2168 name. */ 2169 if (insert_reg_alias (nbuf, old->number, old->type) != NULL) 2170 { 2171 for (p = nbuf; *p; p++) 2172 *p = TOUPPER (*p); 2173 2174 if (strncmp (nbuf, newname, nlen)) 2175 { 2176 /* If this attempt to create an additional alias fails, do not bother 2177 trying to create the all-lower case alias. We will fail and issue 2178 a second, duplicate error message. This situation arises when the 2179 programmer does something like: 2180 foo .req r0 2181 Foo .req r1 2182 The second .req creates the "Foo" alias but then fails to create 2183 the artificial FOO alias because it has already been created by the 2184 first .req. */ 2185 if (insert_reg_alias (nbuf, old->number, old->type) == NULL) 2186 return TRUE; 2187 } 2188 2189 for (p = nbuf; *p; p++) 2190 *p = TOLOWER (*p); 2191 2192 if (strncmp (nbuf, newname, nlen)) 2193 insert_reg_alias (nbuf, old->number, old->type); 2194 } 2195 2196 return TRUE; 2197} 2198 2199/* Create a Neon typed/indexed register alias using directives, e.g.: 2200 X .dn d5.s32[1] 2201 Y .qn 6.s16 2202 Z .dn d7 2203 T .dn Z[0] 2204 These typed registers can be used instead of the types specified after the 2205 Neon mnemonic, so long as all operands given have types. Types can also be 2206 specified directly, e.g.: 2207 vadd d0.s32, d1.s32, d2.s32 */ 2208 2209static bfd_boolean 2210create_neon_reg_alias (char *newname, char *p) 2211{ 2212 enum arm_reg_type basetype; 2213 struct reg_entry *basereg; 2214 struct reg_entry mybasereg; 2215 struct neon_type ntype; 2216 struct neon_typed_alias typeinfo; 2217 char *namebuf, *nameend ATTRIBUTE_UNUSED; 2218 int namelen; 2219 2220 typeinfo.defined = 0; 2221 typeinfo.eltype.type = NT_invtype; 2222 typeinfo.eltype.size = -1; 2223 typeinfo.index = -1; 2224 2225 nameend = p; 2226 2227 if (strncmp (p, " .dn ", 5) == 0) 2228 basetype = REG_TYPE_VFD; 2229 else if (strncmp (p, " .qn ", 5) == 0) 2230 basetype = REG_TYPE_NQ; 2231 else 2232 return FALSE; 2233 2234 p += 5; 2235 2236 if (*p == '\0') 2237 return FALSE; 2238 2239 basereg = arm_reg_parse_multi (&p); 2240 2241 if (basereg && basereg->type != basetype) 2242 { 2243 as_bad (_("bad type for register")); 2244 return FALSE; 2245 } 2246 2247 if (basereg == NULL) 2248 { 2249 expressionS exp; 2250 /* Try parsing as an integer. */ 2251 my_get_expression (&exp, &p, GE_NO_PREFIX); 2252 if (exp.X_op != O_constant) 2253 { 2254 as_bad (_("expression must be constant")); 2255 return FALSE; 2256 } 2257 basereg = &mybasereg; 2258 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 2259 : exp.X_add_number; 2260 basereg->neon = 0; 2261 } 2262 2263 if (basereg->neon) 2264 typeinfo = *basereg->neon; 2265 2266 if (parse_neon_type (&ntype, &p) == SUCCESS) 2267 { 2268 /* We got a type. */ 2269 if (typeinfo.defined & NTA_HASTYPE) 2270 { 2271 as_bad (_("can't redefine the type of a register alias")); 2272 return FALSE; 2273 } 2274 2275 typeinfo.defined |= NTA_HASTYPE; 2276 if (ntype.elems != 1) 2277 { 2278 as_bad (_("you must specify a single type only")); 2279 return FALSE; 2280 } 2281 typeinfo.eltype = ntype.el[0]; 2282 } 2283 2284 if (skip_past_char (&p, '[') == SUCCESS) 2285 { 2286 expressionS exp; 2287 /* We got a scalar index. */ 2288 2289 if (typeinfo.defined & NTA_HASINDEX) 2290 { 2291 as_bad (_("can't redefine the index of a scalar alias")); 2292 return FALSE; 2293 } 2294 2295 my_get_expression (&exp, &p, GE_NO_PREFIX); 2296 2297 if (exp.X_op != O_constant) 2298 { 2299 as_bad (_("scalar index must be constant")); 2300 return FALSE; 2301 } 2302 2303 typeinfo.defined |= NTA_HASINDEX; 2304 typeinfo.index = exp.X_add_number; 2305 2306 if (skip_past_char (&p, ']') == FAIL) 2307 { 2308 as_bad (_("expecting ]")); 2309 return FALSE; 2310 } 2311 } 2312 2313 /* If TC_CASE_SENSITIVE is defined, then newname already points to 2314 the desired alias name, and p points to its end. If not, then 2315 the desired alias name is in the global original_case_string. */ 2316#ifdef TC_CASE_SENSITIVE 2317 namelen = nameend - newname; 2318#else 2319 newname = original_case_string; 2320 namelen = strlen (newname); 2321#endif 2322 2323 namebuf = (char *) alloca (namelen + 1); 2324 strncpy (namebuf, newname, namelen); 2325 namebuf[namelen] = '\0'; 2326 2327 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2328 typeinfo.defined != 0 ? &typeinfo : NULL); 2329 2330 /* Insert name in all uppercase. */ 2331 for (p = namebuf; *p; p++) 2332 *p = TOUPPER (*p); 2333 2334 if (strncmp (namebuf, newname, namelen)) 2335 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2336 typeinfo.defined != 0 ? &typeinfo : NULL); 2337 2338 /* Insert name in all lowercase. */ 2339 for (p = namebuf; *p; p++) 2340 *p = TOLOWER (*p); 2341 2342 if (strncmp (namebuf, newname, namelen)) 2343 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2344 typeinfo.defined != 0 ? &typeinfo : NULL); 2345 2346 return TRUE; 2347} 2348 2349/* Should never be called, as .req goes between the alias and the 2350 register name, not at the beginning of the line. */ 2351 2352static void 2353s_req (int a ATTRIBUTE_UNUSED) 2354{ 2355 as_bad (_("invalid syntax for .req directive")); 2356} 2357 2358static void 2359s_dn (int a ATTRIBUTE_UNUSED) 2360{ 2361 as_bad (_("invalid syntax for .dn directive")); 2362} 2363 2364static void 2365s_qn (int a ATTRIBUTE_UNUSED) 2366{ 2367 as_bad (_("invalid syntax for .qn directive")); 2368} 2369 2370/* The .unreq directive deletes an alias which was previously defined 2371 by .req. For example: 2372 2373 my_alias .req r11 2374 .unreq my_alias */ 2375 2376static void 2377s_unreq (int a ATTRIBUTE_UNUSED) 2378{ 2379 char * name; 2380 char saved_char; 2381 2382 name = input_line_pointer; 2383 2384 while (*input_line_pointer != 0 2385 && *input_line_pointer != ' ' 2386 && *input_line_pointer != '\n') 2387 ++input_line_pointer; 2388 2389 saved_char = *input_line_pointer; 2390 *input_line_pointer = 0; 2391 2392 if (!*name) 2393 as_bad (_("invalid syntax for .unreq directive")); 2394 else 2395 { 2396 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, 2397 name); 2398 2399 if (!reg) 2400 as_bad (_("unknown register alias '%s'"), name); 2401 else if (reg->builtin) 2402 as_warn (_("ignoring attempt to undefine built-in register '%s'"), 2403 name); 2404 else 2405 { 2406 char * p; 2407 char * nbuf; 2408 2409 hash_delete (arm_reg_hsh, name, FALSE); 2410 free ((char *) reg->name); 2411 if (reg->neon) 2412 free (reg->neon); 2413 free (reg); 2414 2415 /* Also locate the all upper case and all lower case versions. 2416 Do not complain if we cannot find one or the other as it 2417 was probably deleted above. */ 2418 2419 nbuf = strdup (name); 2420 for (p = nbuf; *p; p++) 2421 *p = TOUPPER (*p); 2422 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); 2423 if (reg) 2424 { 2425 hash_delete (arm_reg_hsh, nbuf, FALSE); 2426 free ((char *) reg->name); 2427 if (reg->neon) 2428 free (reg->neon); 2429 free (reg); 2430 } 2431 2432 for (p = nbuf; *p; p++) 2433 *p = TOLOWER (*p); 2434 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); 2435 if (reg) 2436 { 2437 hash_delete (arm_reg_hsh, nbuf, FALSE); 2438 free ((char *) reg->name); 2439 if (reg->neon) 2440 free (reg->neon); 2441 free (reg); 2442 } 2443 2444 free (nbuf); 2445 } 2446 } 2447 2448 *input_line_pointer = saved_char; 2449 demand_empty_rest_of_line (); 2450} 2451 2452/* Directives: Instruction set selection. */ 2453 2454#ifdef OBJ_ELF 2455/* This code is to handle mapping symbols as defined in the ARM ELF spec. 2456 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). 2457 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), 2458 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ 2459 2460/* Create a new mapping symbol for the transition to STATE. */ 2461 2462static void 2463make_mapping_symbol (enum mstate state, valueT value, fragS *frag) 2464{ 2465 symbolS * symbolP; 2466 const char * symname; 2467 int type; 2468 2469 switch (state) 2470 { 2471 case MAP_DATA: 2472 symname = "$d"; 2473 type = BSF_NO_FLAGS; 2474 break; 2475 case MAP_ARM: 2476 symname = "$a"; 2477 type = BSF_NO_FLAGS; 2478 break; 2479 case MAP_THUMB: 2480 symname = "$t"; 2481 type = BSF_NO_FLAGS; 2482 break; 2483 default: 2484 abort (); 2485 } 2486 2487 symbolP = symbol_new (symname, now_seg, value, frag); 2488 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; 2489 2490 switch (state) 2491 { 2492 case MAP_ARM: 2493 THUMB_SET_FUNC (symbolP, 0); 2494 ARM_SET_THUMB (symbolP, 0); 2495 ARM_SET_INTERWORK (symbolP, support_interwork); 2496 break; 2497 2498 case MAP_THUMB: 2499 THUMB_SET_FUNC (symbolP, 1); 2500 ARM_SET_THUMB (symbolP, 1); 2501 ARM_SET_INTERWORK (symbolP, support_interwork); 2502 break; 2503 2504 case MAP_DATA: 2505 default: 2506 break; 2507 } 2508 2509 /* Save the mapping symbols for future reference. Also check that 2510 we do not place two mapping symbols at the same offset within a 2511 frag. We'll handle overlap between frags in 2512 check_mapping_symbols. 2513 2514 If .fill or other data filling directive generates zero sized data, 2515 the mapping symbol for the following code will have the same value 2516 as the one generated for the data filling directive. In this case, 2517 we replace the old symbol with the new one at the same address. */ 2518 if (value == 0) 2519 { 2520 if (frag->tc_frag_data.first_map != NULL) 2521 { 2522 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); 2523 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); 2524 } 2525 frag->tc_frag_data.first_map = symbolP; 2526 } 2527 if (frag->tc_frag_data.last_map != NULL) 2528 { 2529 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); 2530 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) 2531 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); 2532 } 2533 frag->tc_frag_data.last_map = symbolP; 2534} 2535 2536/* We must sometimes convert a region marked as code to data during 2537 code alignment, if an odd number of bytes have to be padded. The 2538 code mapping symbol is pushed to an aligned address. */ 2539 2540static void 2541insert_data_mapping_symbol (enum mstate state, 2542 valueT value, fragS *frag, offsetT bytes) 2543{ 2544 /* If there was already a mapping symbol, remove it. */ 2545 if (frag->tc_frag_data.last_map != NULL 2546 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) 2547 { 2548 symbolS *symp = frag->tc_frag_data.last_map; 2549 2550 if (value == 0) 2551 { 2552 know (frag->tc_frag_data.first_map == symp); 2553 frag->tc_frag_data.first_map = NULL; 2554 } 2555 frag->tc_frag_data.last_map = NULL; 2556 symbol_remove (symp, &symbol_rootP, &symbol_lastP); 2557 } 2558 2559 make_mapping_symbol (MAP_DATA, value, frag); 2560 make_mapping_symbol (state, value + bytes, frag); 2561} 2562 2563static void mapping_state_2 (enum mstate state, int max_chars); 2564 2565/* Set the mapping state to STATE. Only call this when about to 2566 emit some STATE bytes to the file. */ 2567 2568void 2569mapping_state (enum mstate state) 2570{ 2571 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; 2572 2573#define TRANSITION(from, to) (mapstate == (from) && state == (to)) 2574 2575 if (mapstate == state) 2576 /* The mapping symbol has already been emitted. 2577 There is nothing else to do. */ 2578 return; 2579 else if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) 2580 /* This case will be evaluated later in the next else. */ 2581 return; 2582 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM) 2583 || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) 2584 { 2585 /* Only add the symbol if the offset is > 0: 2586 if we're at the first frag, check it's size > 0; 2587 if we're not at the first frag, then for sure 2588 the offset is > 0. */ 2589 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; 2590 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); 2591 2592 if (add_symbol) 2593 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); 2594 } 2595 2596 mapping_state_2 (state, 0); 2597#undef TRANSITION 2598} 2599 2600/* Same as mapping_state, but MAX_CHARS bytes have already been 2601 allocated. Put the mapping symbol that far back. */ 2602 2603static void 2604mapping_state_2 (enum mstate state, int max_chars) 2605{ 2606 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; 2607 2608 if (!SEG_NORMAL (now_seg)) 2609 return; 2610 2611 if (mapstate == state) 2612 /* The mapping symbol has already been emitted. 2613 There is nothing else to do. */ 2614 return; 2615 2616 seg_info (now_seg)->tc_segment_info_data.mapstate = state; 2617 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); 2618} 2619#else 2620#define mapping_state(x) ((void)0) 2621#define mapping_state_2(x, y) ((void)0) 2622#endif 2623 2624/* Find the real, Thumb encoded start of a Thumb function. */ 2625 2626#ifdef OBJ_COFF 2627static symbolS * 2628find_real_start (symbolS * symbolP) 2629{ 2630 char * real_start; 2631 const char * name = S_GET_NAME (symbolP); 2632 symbolS * new_target; 2633 2634 /* This definition must agree with the one in gcc/config/arm/thumb.c. */ 2635#define STUB_NAME ".real_start_of" 2636 2637 if (name == NULL) 2638 abort (); 2639 2640 /* The compiler may generate BL instructions to local labels because 2641 it needs to perform a branch to a far away location. These labels 2642 do not have a corresponding ".real_start_of" label. We check 2643 both for S_IS_LOCAL and for a leading dot, to give a way to bypass 2644 the ".real_start_of" convention for nonlocal branches. */ 2645 if (S_IS_LOCAL (symbolP) || name[0] == '.') 2646 return symbolP; 2647 2648 real_start = ACONCAT ((STUB_NAME, name, NULL)); 2649 new_target = symbol_find (real_start); 2650 2651 if (new_target == NULL) 2652 { 2653 as_warn (_("Failed to find real start of function: %s\n"), name); 2654 new_target = symbolP; 2655 } 2656 2657 return new_target; 2658} 2659#endif 2660 2661static void 2662opcode_select (int width) 2663{ 2664 switch (width) 2665 { 2666 case 16: 2667 if (! thumb_mode) 2668 { 2669 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 2670 as_bad (_("selected processor does not support THUMB opcodes")); 2671 2672 thumb_mode = 1; 2673 /* No need to force the alignment, since we will have been 2674 coming from ARM mode, which is word-aligned. */ 2675 record_alignment (now_seg, 1); 2676 } 2677 break; 2678 2679 case 32: 2680 if (thumb_mode) 2681 { 2682 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 2683 as_bad (_("selected processor does not support ARM opcodes")); 2684 2685 thumb_mode = 0; 2686 2687 if (!need_pass_2) 2688 frag_align (2, 0, 0); 2689 2690 record_alignment (now_seg, 1); 2691 } 2692 break; 2693 2694 default: 2695 as_bad (_("invalid instruction size selected (%d)"), width); 2696 } 2697} 2698 2699static void 2700s_arm (int ignore ATTRIBUTE_UNUSED) 2701{ 2702 opcode_select (32); 2703 demand_empty_rest_of_line (); 2704} 2705 2706static void 2707s_thumb (int ignore ATTRIBUTE_UNUSED) 2708{ 2709 opcode_select (16); 2710 demand_empty_rest_of_line (); 2711} 2712 2713static void 2714s_code (int unused ATTRIBUTE_UNUSED) 2715{ 2716 int temp; 2717 2718 temp = get_absolute_expression (); 2719 switch (temp) 2720 { 2721 case 16: 2722 case 32: 2723 opcode_select (temp); 2724 break; 2725 2726 default: 2727 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); 2728 } 2729} 2730 2731static void 2732s_force_thumb (int ignore ATTRIBUTE_UNUSED) 2733{ 2734 /* If we are not already in thumb mode go into it, EVEN if 2735 the target processor does not support thumb instructions. 2736 This is used by gcc/config/arm/lib1funcs.asm for example 2737 to compile interworking support functions even if the 2738 target processor should not support interworking. */ 2739 if (! thumb_mode) 2740 { 2741 thumb_mode = 2; 2742 record_alignment (now_seg, 1); 2743 } 2744 2745 demand_empty_rest_of_line (); 2746} 2747 2748static void 2749s_thumb_func (int ignore ATTRIBUTE_UNUSED) 2750{ 2751 s_thumb (0); 2752 2753 /* The following label is the name/address of the start of a Thumb function. 2754 We need to know this for the interworking support. */ 2755 label_is_thumb_function_name = TRUE; 2756} 2757 2758/* Perform a .set directive, but also mark the alias as 2759 being a thumb function. */ 2760 2761static void 2762s_thumb_set (int equiv) 2763{ 2764 /* XXX the following is a duplicate of the code for s_set() in read.c 2765 We cannot just call that code as we need to get at the symbol that 2766 is created. */ 2767 char * name; 2768 char delim; 2769 char * end_name; 2770 symbolS * symbolP; 2771 2772 /* Especial apologies for the random logic: 2773 This just grew, and could be parsed much more simply! 2774 Dean - in haste. */ 2775 name = input_line_pointer; 2776 delim = get_symbol_end (); 2777 end_name = input_line_pointer; 2778 *end_name = delim; 2779 2780 if (*input_line_pointer != ',') 2781 { 2782 *end_name = 0; 2783 as_bad (_("expected comma after name \"%s\""), name); 2784 *end_name = delim; 2785 ignore_rest_of_line (); 2786 return; 2787 } 2788 2789 input_line_pointer++; 2790 *end_name = 0; 2791 2792 if (name[0] == '.' && name[1] == '\0') 2793 { 2794 /* XXX - this should not happen to .thumb_set. */ 2795 abort (); 2796 } 2797 2798 if ((symbolP = symbol_find (name)) == NULL 2799 && (symbolP = md_undefined_symbol (name)) == NULL) 2800 { 2801#ifndef NO_LISTING 2802 /* When doing symbol listings, play games with dummy fragments living 2803 outside the normal fragment chain to record the file and line info 2804 for this symbol. */ 2805 if (listing & LISTING_SYMBOLS) 2806 { 2807 extern struct list_info_struct * listing_tail; 2808 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); 2809 2810 memset (dummy_frag, 0, sizeof (fragS)); 2811 dummy_frag->fr_type = rs_fill; 2812 dummy_frag->line = listing_tail; 2813 symbolP = symbol_new (name, undefined_section, 0, dummy_frag); 2814 dummy_frag->fr_symbol = symbolP; 2815 } 2816 else 2817#endif 2818 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); 2819 2820#ifdef OBJ_COFF 2821 /* "set" symbols are local unless otherwise specified. */ 2822 SF_SET_LOCAL (symbolP); 2823#endif /* OBJ_COFF */ 2824 } /* Make a new symbol. */ 2825 2826 symbol_table_insert (symbolP); 2827 2828 * end_name = delim; 2829 2830 if (equiv 2831 && S_IS_DEFINED (symbolP) 2832 && S_GET_SEGMENT (symbolP) != reg_section) 2833 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); 2834 2835 pseudo_set (symbolP); 2836 2837 demand_empty_rest_of_line (); 2838 2839 /* XXX Now we come to the Thumb specific bit of code. */ 2840 2841 THUMB_SET_FUNC (symbolP, 1); 2842 ARM_SET_THUMB (symbolP, 1); 2843#if defined OBJ_ELF || defined OBJ_COFF 2844 ARM_SET_INTERWORK (symbolP, support_interwork); 2845#endif 2846} 2847 2848/* Directives: Mode selection. */ 2849 2850/* .syntax [unified|divided] - choose the new unified syntax 2851 (same for Arm and Thumb encoding, modulo slight differences in what 2852 can be represented) or the old divergent syntax for each mode. */ 2853static void 2854s_syntax (int unused ATTRIBUTE_UNUSED) 2855{ 2856 char *name, delim; 2857 2858 name = input_line_pointer; 2859 delim = get_symbol_end (); 2860 2861 if (!strcasecmp (name, "unified")) 2862 unified_syntax = TRUE; 2863 else if (!strcasecmp (name, "divided")) 2864 unified_syntax = FALSE; 2865 else 2866 { 2867 as_bad (_("unrecognized syntax mode \"%s\""), name); 2868 return; 2869 } 2870 *input_line_pointer = delim; 2871 demand_empty_rest_of_line (); 2872} 2873 2874/* Directives: sectioning and alignment. */ 2875 2876/* Same as s_align_ptwo but align 0 => align 2. */ 2877 2878static void 2879s_align (int unused ATTRIBUTE_UNUSED) 2880{ 2881 int temp; 2882 bfd_boolean fill_p; 2883 long temp_fill; 2884 long max_alignment = 15; 2885 2886 temp = get_absolute_expression (); 2887 if (temp > max_alignment) 2888 as_bad (_("alignment too large: %d assumed"), temp = max_alignment); 2889 else if (temp < 0) 2890 { 2891 as_bad (_("alignment negative. 0 assumed.")); 2892 temp = 0; 2893 } 2894 2895 if (*input_line_pointer == ',') 2896 { 2897 input_line_pointer++; 2898 temp_fill = get_absolute_expression (); 2899 fill_p = TRUE; 2900 } 2901 else 2902 { 2903 fill_p = FALSE; 2904 temp_fill = 0; 2905 } 2906 2907 if (!temp) 2908 temp = 2; 2909 2910 /* Only make a frag if we HAVE to. */ 2911 if (temp && !need_pass_2) 2912 { 2913 if (!fill_p && subseg_text_p (now_seg)) 2914 frag_align_code (temp, 0); 2915 else 2916 frag_align (temp, (int) temp_fill, 0); 2917 } 2918 demand_empty_rest_of_line (); 2919 2920 record_alignment (now_seg, temp); 2921} 2922 2923static void 2924s_bss (int ignore ATTRIBUTE_UNUSED) 2925{ 2926 /* We don't support putting frags in the BSS segment, we fake it by 2927 marking in_bss, then looking at s_skip for clues. */ 2928 subseg_set (bss_section, 0); 2929 demand_empty_rest_of_line (); 2930 2931#ifdef md_elf_section_change_hook 2932 md_elf_section_change_hook (); 2933#endif 2934} 2935 2936static void 2937s_even (int ignore ATTRIBUTE_UNUSED) 2938{ 2939 /* Never make frag if expect extra pass. */ 2940 if (!need_pass_2) 2941 frag_align (1, 0, 0); 2942 2943 record_alignment (now_seg, 1); 2944 2945 demand_empty_rest_of_line (); 2946} 2947 2948/* Directives: Literal pools. */ 2949 2950static literal_pool * 2951find_literal_pool (void) 2952{ 2953 literal_pool * pool; 2954 2955 for (pool = list_of_pools; pool != NULL; pool = pool->next) 2956 { 2957 if (pool->section == now_seg 2958 && pool->sub_section == now_subseg) 2959 break; 2960 } 2961 2962 return pool; 2963} 2964 2965static literal_pool * 2966find_or_make_literal_pool (void) 2967{ 2968 /* Next literal pool ID number. */ 2969 static unsigned int latest_pool_num = 1; 2970 literal_pool * pool; 2971 2972 pool = find_literal_pool (); 2973 2974 if (pool == NULL) 2975 { 2976 /* Create a new pool. */ 2977 pool = (literal_pool *) xmalloc (sizeof (* pool)); 2978 if (! pool) 2979 return NULL; 2980 2981 pool->next_free_entry = 0; 2982 pool->section = now_seg; 2983 pool->sub_section = now_subseg; 2984 pool->next = list_of_pools; 2985 pool->symbol = NULL; 2986 2987 /* Add it to the list. */ 2988 list_of_pools = pool; 2989 } 2990 2991 /* New pools, and emptied pools, will have a NULL symbol. */ 2992 if (pool->symbol == NULL) 2993 { 2994 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, 2995 (valueT) 0, &zero_address_frag); 2996 pool->id = latest_pool_num ++; 2997 } 2998 2999 /* Done. */ 3000 return pool; 3001} 3002 3003/* Add the literal in the global 'inst' 3004 structure to the relevant literal pool. */ 3005 3006static int 3007add_to_lit_pool (void) 3008{ 3009 literal_pool * pool; 3010 unsigned int entry; 3011 3012 pool = find_or_make_literal_pool (); 3013 3014 /* Check if this literal value is already in the pool. */ 3015 for (entry = 0; entry < pool->next_free_entry; entry ++) 3016 { 3017 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) 3018 && (inst.reloc.exp.X_op == O_constant) 3019 && (pool->literals[entry].X_add_number 3020 == inst.reloc.exp.X_add_number) 3021 && (pool->literals[entry].X_unsigned 3022 == inst.reloc.exp.X_unsigned)) 3023 break; 3024 3025 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) 3026 && (inst.reloc.exp.X_op == O_symbol) 3027 && (pool->literals[entry].X_add_number 3028 == inst.reloc.exp.X_add_number) 3029 && (pool->literals[entry].X_add_symbol 3030 == inst.reloc.exp.X_add_symbol) 3031 && (pool->literals[entry].X_op_symbol 3032 == inst.reloc.exp.X_op_symbol)) 3033 break; 3034 } 3035 3036 /* Do we need to create a new entry? */ 3037 if (entry == pool->next_free_entry) 3038 { 3039 if (entry >= MAX_LITERAL_POOL_SIZE) 3040 { 3041 inst.error = _("literal pool overflow"); 3042 return FAIL; 3043 } 3044 3045 pool->literals[entry] = inst.reloc.exp; 3046 pool->next_free_entry += 1; 3047 } 3048 3049 inst.reloc.exp.X_op = O_symbol; 3050 inst.reloc.exp.X_add_number = ((int) entry) * 4; 3051 inst.reloc.exp.X_add_symbol = pool->symbol; 3052 3053 return SUCCESS; 3054} 3055 3056/* Can't use symbol_new here, so have to create a symbol and then at 3057 a later date assign it a value. Thats what these functions do. */ 3058 3059static void 3060symbol_locate (symbolS * symbolP, 3061 const char * name, /* It is copied, the caller can modify. */ 3062 segT segment, /* Segment identifier (SEG_<something>). */ 3063 valueT valu, /* Symbol value. */ 3064 fragS * frag) /* Associated fragment. */ 3065{ 3066 unsigned int name_length; 3067 char * preserved_copy_of_name; 3068 3069 name_length = strlen (name) + 1; /* +1 for \0. */ 3070 obstack_grow (¬es, name, name_length); 3071 preserved_copy_of_name = (char *) obstack_finish (¬es); 3072 3073#ifdef tc_canonicalize_symbol_name 3074 preserved_copy_of_name = 3075 tc_canonicalize_symbol_name (preserved_copy_of_name); 3076#endif 3077 3078 S_SET_NAME (symbolP, preserved_copy_of_name); 3079 3080 S_SET_SEGMENT (symbolP, segment); 3081 S_SET_VALUE (symbolP, valu); 3082 symbol_clear_list_pointers (symbolP); 3083 3084 symbol_set_frag (symbolP, frag); 3085 3086 /* Link to end of symbol chain. */ 3087 { 3088 extern int symbol_table_frozen; 3089 3090 if (symbol_table_frozen) 3091 abort (); 3092 } 3093 3094 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); 3095 3096 obj_symbol_new_hook (symbolP); 3097 3098#ifdef tc_symbol_new_hook 3099 tc_symbol_new_hook (symbolP); 3100#endif 3101 3102#ifdef DEBUG_SYMS 3103 verify_symbol_chain (symbol_rootP, symbol_lastP); 3104#endif /* DEBUG_SYMS */ 3105} 3106 3107 3108static void 3109s_ltorg (int ignored ATTRIBUTE_UNUSED) 3110{ 3111 unsigned int entry; 3112 literal_pool * pool; 3113 char sym_name[20]; 3114 3115 pool = find_literal_pool (); 3116 if (pool == NULL 3117 || pool->symbol == NULL 3118 || pool->next_free_entry == 0) 3119 return; 3120 3121 mapping_state (MAP_DATA); 3122 3123 /* Align pool as you have word accesses. 3124 Only make a frag if we have to. */ 3125 if (!need_pass_2) 3126 frag_align (2, 0, 0); 3127 3128 record_alignment (now_seg, 2); 3129 3130 sprintf (sym_name, "$$lit_\002%x", pool->id); 3131 3132 symbol_locate (pool->symbol, sym_name, now_seg, 3133 (valueT) frag_now_fix (), frag_now); 3134 symbol_table_insert (pool->symbol); 3135 3136 ARM_SET_THUMB (pool->symbol, thumb_mode); 3137 3138#if defined OBJ_COFF || defined OBJ_ELF 3139 ARM_SET_INTERWORK (pool->symbol, support_interwork); 3140#endif 3141 3142 for (entry = 0; entry < pool->next_free_entry; entry ++) 3143 /* First output the expression in the instruction to the pool. */ 3144 emit_expr (&(pool->literals[entry]), 4); /* .word */ 3145 3146 /* Mark the pool as empty. */ 3147 pool->next_free_entry = 0; 3148 pool->symbol = NULL; 3149} 3150 3151#ifdef OBJ_ELF 3152/* Forward declarations for functions below, in the MD interface 3153 section. */ 3154static void fix_new_arm (fragS *, int, short, expressionS *, int, int); 3155static valueT create_unwind_entry (int); 3156static void start_unwind_section (const segT, int); 3157static void add_unwind_opcode (valueT, int); 3158static void flush_pending_unwind (void); 3159 3160/* Directives: Data. */ 3161 3162static void 3163s_arm_elf_cons (int nbytes) 3164{ 3165 expressionS exp; 3166 3167#ifdef md_flush_pending_output 3168 md_flush_pending_output (); 3169#endif 3170 3171 if (is_it_end_of_statement ()) 3172 { 3173 demand_empty_rest_of_line (); 3174 return; 3175 } 3176 3177#ifdef md_cons_align 3178 md_cons_align (nbytes); 3179#endif 3180 3181 mapping_state (MAP_DATA); 3182 do 3183 { 3184 int reloc; 3185 char *base = input_line_pointer; 3186 3187 expression (& exp); 3188 3189 if (exp.X_op != O_symbol) 3190 emit_expr (&exp, (unsigned int) nbytes); 3191 else 3192 { 3193 char *before_reloc = input_line_pointer; 3194 reloc = parse_reloc (&input_line_pointer); 3195 if (reloc == -1) 3196 { 3197 as_bad (_("unrecognized relocation suffix")); 3198 ignore_rest_of_line (); 3199 return; 3200 } 3201 else if (reloc == BFD_RELOC_UNUSED) 3202 emit_expr (&exp, (unsigned int) nbytes); 3203 else 3204 { 3205 reloc_howto_type *howto = (reloc_howto_type *) 3206 bfd_reloc_type_lookup (stdoutput, 3207 (bfd_reloc_code_real_type) reloc); 3208 int size = bfd_get_reloc_size (howto); 3209 3210 if (reloc == BFD_RELOC_ARM_PLT32) 3211 { 3212 as_bad (_("(plt) is only valid on branch targets")); 3213 reloc = BFD_RELOC_UNUSED; 3214 size = 0; 3215 } 3216 3217 if (size > nbytes) 3218 as_bad (_("%s relocations do not fit in %d bytes"), 3219 howto->name, nbytes); 3220 else 3221 { 3222 /* We've parsed an expression stopping at O_symbol. 3223 But there may be more expression left now that we 3224 have parsed the relocation marker. Parse it again. 3225 XXX Surely there is a cleaner way to do this. */ 3226 char *p = input_line_pointer; 3227 int offset; 3228 char *save_buf = (char *) alloca (input_line_pointer - base); 3229 memcpy (save_buf, base, input_line_pointer - base); 3230 memmove (base + (input_line_pointer - before_reloc), 3231 base, before_reloc - base); 3232 3233 input_line_pointer = base + (input_line_pointer-before_reloc); 3234 expression (&exp); 3235 memcpy (base, save_buf, p - base); 3236 3237 offset = nbytes - size; 3238 p = frag_more ((int) nbytes); 3239 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, 3240 size, &exp, 0, (enum bfd_reloc_code_real) reloc); 3241 } 3242 } 3243 } 3244 } 3245 while (*input_line_pointer++ == ','); 3246 3247 /* Put terminator back into stream. */ 3248 input_line_pointer --; 3249 demand_empty_rest_of_line (); 3250} 3251 3252/* Emit an expression containing a 32-bit thumb instruction. 3253 Implementation based on put_thumb32_insn. */ 3254 3255static void 3256emit_thumb32_expr (expressionS * exp) 3257{ 3258 expressionS exp_high = *exp; 3259 3260 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; 3261 emit_expr (& exp_high, (unsigned int) THUMB_SIZE); 3262 exp->X_add_number &= 0xffff; 3263 emit_expr (exp, (unsigned int) THUMB_SIZE); 3264} 3265 3266/* Guess the instruction size based on the opcode. */ 3267 3268static int 3269thumb_insn_size (int opcode) 3270{ 3271 if ((unsigned int) opcode < 0xe800u) 3272 return 2; 3273 else if ((unsigned int) opcode >= 0xe8000000u) 3274 return 4; 3275 else 3276 return 0; 3277} 3278 3279static bfd_boolean 3280emit_insn (expressionS *exp, int nbytes) 3281{ 3282 int size = 0; 3283 3284 if (exp->X_op == O_constant) 3285 { 3286 size = nbytes; 3287 3288 if (size == 0) 3289 size = thumb_insn_size (exp->X_add_number); 3290 3291 if (size != 0) 3292 { 3293 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) 3294 { 3295 as_bad (_(".inst.n operand too big. "\ 3296 "Use .inst.w instead")); 3297 size = 0; 3298 } 3299 else 3300 { 3301 if (now_it.state == AUTOMATIC_IT_BLOCK) 3302 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0); 3303 else 3304 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); 3305 3306 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) 3307 emit_thumb32_expr (exp); 3308 else 3309 emit_expr (exp, (unsigned int) size); 3310 3311 it_fsm_post_encode (); 3312 } 3313 } 3314 else 3315 as_bad (_("cannot determine Thumb instruction size. " \ 3316 "Use .inst.n/.inst.w instead")); 3317 } 3318 else 3319 as_bad (_("constant expression required")); 3320 3321 return (size != 0); 3322} 3323 3324/* Like s_arm_elf_cons but do not use md_cons_align and 3325 set the mapping state to MAP_ARM/MAP_THUMB. */ 3326 3327static void 3328s_arm_elf_inst (int nbytes) 3329{ 3330 if (is_it_end_of_statement ()) 3331 { 3332 demand_empty_rest_of_line (); 3333 return; 3334 } 3335 3336 /* Calling mapping_state () here will not change ARM/THUMB, 3337 but will ensure not to be in DATA state. */ 3338 3339 if (thumb_mode) 3340 mapping_state (MAP_THUMB); 3341 else 3342 { 3343 if (nbytes != 0) 3344 { 3345 as_bad (_("width suffixes are invalid in ARM mode")); 3346 ignore_rest_of_line (); 3347 return; 3348 } 3349 3350 nbytes = 4; 3351 3352 mapping_state (MAP_ARM); 3353 } 3354 3355 do 3356 { 3357 expressionS exp; 3358 3359 expression (& exp); 3360 3361 if (! emit_insn (& exp, nbytes)) 3362 { 3363 ignore_rest_of_line (); 3364 return; 3365 } 3366 } 3367 while (*input_line_pointer++ == ','); 3368 3369 /* Put terminator back into stream. */ 3370 input_line_pointer --; 3371 demand_empty_rest_of_line (); 3372} 3373 3374/* Parse a .rel31 directive. */ 3375 3376static void 3377s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) 3378{ 3379 expressionS exp; 3380 char *p; 3381 valueT highbit; 3382 3383 highbit = 0; 3384 if (*input_line_pointer == '1') 3385 highbit = 0x80000000; 3386 else if (*input_line_pointer != '0') 3387 as_bad (_("expected 0 or 1")); 3388 3389 input_line_pointer++; 3390 if (*input_line_pointer != ',') 3391 as_bad (_("missing comma")); 3392 input_line_pointer++; 3393 3394#ifdef md_flush_pending_output 3395 md_flush_pending_output (); 3396#endif 3397 3398#ifdef md_cons_align 3399 md_cons_align (4); 3400#endif 3401 3402 mapping_state (MAP_DATA); 3403 3404 expression (&exp); 3405 3406 p = frag_more (4); 3407 md_number_to_chars (p, highbit, 4); 3408 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, 3409 BFD_RELOC_ARM_PREL31); 3410 3411 demand_empty_rest_of_line (); 3412} 3413 3414/* Directives: AEABI stack-unwind tables. */ 3415 3416/* Parse an unwind_fnstart directive. Simply records the current location. */ 3417 3418static void 3419s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) 3420{ 3421 demand_empty_rest_of_line (); 3422 if (unwind.proc_start) 3423 { 3424 as_bad (_("duplicate .fnstart directive")); 3425 return; 3426 } 3427 3428 /* Mark the start of the function. */ 3429 unwind.proc_start = expr_build_dot (); 3430 3431 /* Reset the rest of the unwind info. */ 3432 unwind.opcode_count = 0; 3433 unwind.table_entry = NULL; 3434 unwind.personality_routine = NULL; 3435 unwind.personality_index = -1; 3436 unwind.frame_size = 0; 3437 unwind.fp_offset = 0; 3438 unwind.fp_reg = REG_SP; 3439 unwind.fp_used = 0; 3440 unwind.sp_restored = 0; 3441} 3442 3443 3444/* Parse a handlerdata directive. Creates the exception handling table entry 3445 for the function. */ 3446 3447static void 3448s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) 3449{ 3450 demand_empty_rest_of_line (); 3451 if (!unwind.proc_start) 3452 as_bad (MISSING_FNSTART); 3453 3454 if (unwind.table_entry) 3455 as_bad (_("duplicate .handlerdata directive")); 3456 3457 create_unwind_entry (1); 3458} 3459 3460/* Parse an unwind_fnend directive. Generates the index table entry. */ 3461 3462static void 3463s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) 3464{ 3465 long where; 3466 char *ptr; 3467 valueT val; 3468 unsigned int marked_pr_dependency; 3469 3470 demand_empty_rest_of_line (); 3471 3472 if (!unwind.proc_start) 3473 { 3474 as_bad (_(".fnend directive without .fnstart")); 3475 return; 3476 } 3477 3478 /* Add eh table entry. */ 3479 if (unwind.table_entry == NULL) 3480 val = create_unwind_entry (0); 3481 else 3482 val = 0; 3483 3484 /* Add index table entry. This is two words. */ 3485 start_unwind_section (unwind.saved_seg, 1); 3486 frag_align (2, 0, 0); 3487 record_alignment (now_seg, 2); 3488 3489 ptr = frag_more (8); 3490 where = frag_now_fix () - 8; 3491 3492 /* Self relative offset of the function start. */ 3493 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, 3494 BFD_RELOC_ARM_PREL31); 3495 3496 /* Indicate dependency on EHABI-defined personality routines to the 3497 linker, if it hasn't been done already. */ 3498 marked_pr_dependency 3499 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; 3500 if (unwind.personality_index >= 0 && unwind.personality_index < 3 3501 && !(marked_pr_dependency & (1 << unwind.personality_index))) 3502 { 3503 static const char *const name[] = 3504 { 3505 "__aeabi_unwind_cpp_pr0", 3506 "__aeabi_unwind_cpp_pr1", 3507 "__aeabi_unwind_cpp_pr2" 3508 }; 3509 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); 3510 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); 3511 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency 3512 |= 1 << unwind.personality_index; 3513 } 3514 3515 if (val) 3516 /* Inline exception table entry. */ 3517 md_number_to_chars (ptr + 4, val, 4); 3518 else 3519 /* Self relative offset of the table entry. */ 3520 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, 3521 BFD_RELOC_ARM_PREL31); 3522 3523 /* Restore the original section. */ 3524 subseg_set (unwind.saved_seg, unwind.saved_subseg); 3525 3526 unwind.proc_start = NULL; 3527} 3528 3529 3530/* Parse an unwind_cantunwind directive. */ 3531 3532static void 3533s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) 3534{ 3535 demand_empty_rest_of_line (); 3536 if (!unwind.proc_start) 3537 as_bad (MISSING_FNSTART); 3538 3539 if (unwind.personality_routine || unwind.personality_index != -1) 3540 as_bad (_("personality routine specified for cantunwind frame")); 3541 3542 unwind.personality_index = -2; 3543} 3544 3545 3546/* Parse a personalityindex directive. */ 3547 3548static void 3549s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) 3550{ 3551 expressionS exp; 3552 3553 if (!unwind.proc_start) 3554 as_bad (MISSING_FNSTART); 3555 3556 if (unwind.personality_routine || unwind.personality_index != -1) 3557 as_bad (_("duplicate .personalityindex directive")); 3558 3559 expression (&exp); 3560 3561 if (exp.X_op != O_constant 3562 || exp.X_add_number < 0 || exp.X_add_number > 15) 3563 { 3564 as_bad (_("bad personality routine number")); 3565 ignore_rest_of_line (); 3566 return; 3567 } 3568 3569 unwind.personality_index = exp.X_add_number; 3570 3571 demand_empty_rest_of_line (); 3572} 3573 3574 3575/* Parse a personality directive. */ 3576 3577static void 3578s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) 3579{ 3580 char *name, *p, c; 3581 3582 if (!unwind.proc_start) 3583 as_bad (MISSING_FNSTART); 3584 3585 if (unwind.personality_routine || unwind.personality_index != -1) 3586 as_bad (_("duplicate .personality directive")); 3587 3588 name = input_line_pointer; 3589 c = get_symbol_end (); 3590 p = input_line_pointer; 3591 unwind.personality_routine = symbol_find_or_make (name); 3592 *p = c; 3593 demand_empty_rest_of_line (); 3594} 3595 3596 3597/* Parse a directive saving core registers. */ 3598 3599static void 3600s_arm_unwind_save_core (void) 3601{ 3602 valueT op; 3603 long range; 3604 int n; 3605 3606 range = parse_reg_list (&input_line_pointer); 3607 if (range == FAIL) 3608 { 3609 as_bad (_("expected register list")); 3610 ignore_rest_of_line (); 3611 return; 3612 } 3613 3614 demand_empty_rest_of_line (); 3615 3616 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} 3617 into .unwind_save {..., sp...}. We aren't bothered about the value of 3618 ip because it is clobbered by calls. */ 3619 if (unwind.sp_restored && unwind.fp_reg == 12 3620 && (range & 0x3000) == 0x1000) 3621 { 3622 unwind.opcode_count--; 3623 unwind.sp_restored = 0; 3624 range = (range | 0x2000) & ~0x1000; 3625 unwind.pending_offset = 0; 3626 } 3627 3628 /* Pop r4-r15. */ 3629 if (range & 0xfff0) 3630 { 3631 /* See if we can use the short opcodes. These pop a block of up to 8 3632 registers starting with r4, plus maybe r14. */ 3633 for (n = 0; n < 8; n++) 3634 { 3635 /* Break at the first non-saved register. */ 3636 if ((range & (1 << (n + 4))) == 0) 3637 break; 3638 } 3639 /* See if there are any other bits set. */ 3640 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) 3641 { 3642 /* Use the long form. */ 3643 op = 0x8000 | ((range >> 4) & 0xfff); 3644 add_unwind_opcode (op, 2); 3645 } 3646 else 3647 { 3648 /* Use the short form. */ 3649 if (range & 0x4000) 3650 op = 0xa8; /* Pop r14. */ 3651 else 3652 op = 0xa0; /* Do not pop r14. */ 3653 op |= (n - 1); 3654 add_unwind_opcode (op, 1); 3655 } 3656 } 3657 3658 /* Pop r0-r3. */ 3659 if (range & 0xf) 3660 { 3661 op = 0xb100 | (range & 0xf); 3662 add_unwind_opcode (op, 2); 3663 } 3664 3665 /* Record the number of bytes pushed. */ 3666 for (n = 0; n < 16; n++) 3667 { 3668 if (range & (1 << n)) 3669 unwind.frame_size += 4; 3670 } 3671} 3672 3673 3674/* Parse a directive saving FPA registers. */ 3675 3676static void 3677s_arm_unwind_save_fpa (int reg) 3678{ 3679 expressionS exp; 3680 int num_regs; 3681 valueT op; 3682 3683 /* Get Number of registers to transfer. */ 3684 if (skip_past_comma (&input_line_pointer) != FAIL) 3685 expression (&exp); 3686 else 3687 exp.X_op = O_illegal; 3688 3689 if (exp.X_op != O_constant) 3690 { 3691 as_bad (_("expected , <constant>")); 3692 ignore_rest_of_line (); 3693 return; 3694 } 3695 3696 num_regs = exp.X_add_number; 3697 3698 if (num_regs < 1 || num_regs > 4) 3699 { 3700 as_bad (_("number of registers must be in the range [1:4]")); 3701 ignore_rest_of_line (); 3702 return; 3703 } 3704 3705 demand_empty_rest_of_line (); 3706 3707 if (reg == 4) 3708 { 3709 /* Short form. */ 3710 op = 0xb4 | (num_regs - 1); 3711 add_unwind_opcode (op, 1); 3712 } 3713 else 3714 { 3715 /* Long form. */ 3716 op = 0xc800 | (reg << 4) | (num_regs - 1); 3717 add_unwind_opcode (op, 2); 3718 } 3719 unwind.frame_size += num_regs * 12; 3720} 3721 3722 3723/* Parse a directive saving VFP registers for ARMv6 and above. */ 3724 3725static void 3726s_arm_unwind_save_vfp_armv6 (void) 3727{ 3728 int count; 3729 unsigned int start; 3730 valueT op; 3731 int num_vfpv3_regs = 0; 3732 int num_regs_below_16; 3733 3734 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); 3735 if (count == FAIL) 3736 { 3737 as_bad (_("expected register list")); 3738 ignore_rest_of_line (); 3739 return; 3740 } 3741 3742 demand_empty_rest_of_line (); 3743 3744 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather 3745 than FSTMX/FLDMX-style ones). */ 3746 3747 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ 3748 if (start >= 16) 3749 num_vfpv3_regs = count; 3750 else if (start + count > 16) 3751 num_vfpv3_regs = start + count - 16; 3752 3753 if (num_vfpv3_regs > 0) 3754 { 3755 int start_offset = start > 16 ? start - 16 : 0; 3756 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); 3757 add_unwind_opcode (op, 2); 3758 } 3759 3760 /* Generate opcode for registers numbered in the range 0 .. 15. */ 3761 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; 3762 gas_assert (num_regs_below_16 + num_vfpv3_regs == count); 3763 if (num_regs_below_16 > 0) 3764 { 3765 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); 3766 add_unwind_opcode (op, 2); 3767 } 3768 3769 unwind.frame_size += count * 8; 3770} 3771 3772 3773/* Parse a directive saving VFP registers for pre-ARMv6. */ 3774 3775static void 3776s_arm_unwind_save_vfp (void) 3777{ 3778 int count; 3779 unsigned int reg; 3780 valueT op; 3781 3782 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); 3783 if (count == FAIL) 3784 { 3785 as_bad (_("expected register list")); 3786 ignore_rest_of_line (); 3787 return; 3788 } 3789 3790 demand_empty_rest_of_line (); 3791 3792 if (reg == 8) 3793 { 3794 /* Short form. */ 3795 op = 0xb8 | (count - 1); 3796 add_unwind_opcode (op, 1); 3797 } 3798 else 3799 { 3800 /* Long form. */ 3801 op = 0xb300 | (reg << 4) | (count - 1); 3802 add_unwind_opcode (op, 2); 3803 } 3804 unwind.frame_size += count * 8 + 4; 3805} 3806 3807 3808/* Parse a directive saving iWMMXt data registers. */ 3809 3810static void 3811s_arm_unwind_save_mmxwr (void) 3812{ 3813 int reg; 3814 int hi_reg; 3815 int i; 3816 unsigned mask = 0; 3817 valueT op; 3818 3819 if (*input_line_pointer == '{') 3820 input_line_pointer++; 3821 3822 do 3823 { 3824 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); 3825 3826 if (reg == FAIL) 3827 { 3828 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); 3829 goto error; 3830 } 3831 3832 if (mask >> reg) 3833 as_tsktsk (_("register list not in ascending order")); 3834 mask |= 1 << reg; 3835 3836 if (*input_line_pointer == '-') 3837 { 3838 input_line_pointer++; 3839 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); 3840 if (hi_reg == FAIL) 3841 { 3842 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); 3843 goto error; 3844 } 3845 else if (reg >= hi_reg) 3846 { 3847 as_bad (_("bad register range")); 3848 goto error; 3849 } 3850 for (; reg < hi_reg; reg++) 3851 mask |= 1 << reg; 3852 } 3853 } 3854 while (skip_past_comma (&input_line_pointer) != FAIL); 3855 3856 if (*input_line_pointer == '}') 3857 input_line_pointer++; 3858 3859 demand_empty_rest_of_line (); 3860 3861 /* Generate any deferred opcodes because we're going to be looking at 3862 the list. */ 3863 flush_pending_unwind (); 3864 3865 for (i = 0; i < 16; i++) 3866 { 3867 if (mask & (1 << i)) 3868 unwind.frame_size += 8; 3869 } 3870 3871 /* Attempt to combine with a previous opcode. We do this because gcc 3872 likes to output separate unwind directives for a single block of 3873 registers. */ 3874 if (unwind.opcode_count > 0) 3875 { 3876 i = unwind.opcodes[unwind.opcode_count - 1]; 3877 if ((i & 0xf8) == 0xc0) 3878 { 3879 i &= 7; 3880 /* Only merge if the blocks are contiguous. */ 3881 if (i < 6) 3882 { 3883 if ((mask & 0xfe00) == (1 << 9)) 3884 { 3885 mask |= ((1 << (i + 11)) - 1) & 0xfc00; 3886 unwind.opcode_count--; 3887 } 3888 } 3889 else if (i == 6 && unwind.opcode_count >= 2) 3890 { 3891 i = unwind.opcodes[unwind.opcode_count - 2]; 3892 reg = i >> 4; 3893 i &= 0xf; 3894 3895 op = 0xffff << (reg - 1); 3896 if (reg > 0 3897 && ((mask & op) == (1u << (reg - 1)))) 3898 { 3899 op = (1 << (reg + i + 1)) - 1; 3900 op &= ~((1 << reg) - 1); 3901 mask |= op; 3902 unwind.opcode_count -= 2; 3903 } 3904 } 3905 } 3906 } 3907 3908 hi_reg = 15; 3909 /* We want to generate opcodes in the order the registers have been 3910 saved, ie. descending order. */ 3911 for (reg = 15; reg >= -1; reg--) 3912 { 3913 /* Save registers in blocks. */ 3914 if (reg < 0 3915 || !(mask & (1 << reg))) 3916 { 3917 /* We found an unsaved reg. Generate opcodes to save the 3918 preceding block. */ 3919 if (reg != hi_reg) 3920 { 3921 if (reg == 9) 3922 { 3923 /* Short form. */ 3924 op = 0xc0 | (hi_reg - 10); 3925 add_unwind_opcode (op, 1); 3926 } 3927 else 3928 { 3929 /* Long form. */ 3930 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); 3931 add_unwind_opcode (op, 2); 3932 } 3933 } 3934 hi_reg = reg - 1; 3935 } 3936 } 3937 3938 return; 3939error: 3940 ignore_rest_of_line (); 3941} 3942 3943static void 3944s_arm_unwind_save_mmxwcg (void) 3945{ 3946 int reg; 3947 int hi_reg; 3948 unsigned mask = 0; 3949 valueT op; 3950 3951 if (*input_line_pointer == '{') 3952 input_line_pointer++; 3953 3954 do 3955 { 3956 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); 3957 3958 if (reg == FAIL) 3959 { 3960 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); 3961 goto error; 3962 } 3963 3964 reg -= 8; 3965 if (mask >> reg) 3966 as_tsktsk (_("register list not in ascending order")); 3967 mask |= 1 << reg; 3968 3969 if (*input_line_pointer == '-') 3970 { 3971 input_line_pointer++; 3972 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); 3973 if (hi_reg == FAIL) 3974 { 3975 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); 3976 goto error; 3977 } 3978 else if (reg >= hi_reg) 3979 { 3980 as_bad (_("bad register range")); 3981 goto error; 3982 } 3983 for (; reg < hi_reg; reg++) 3984 mask |= 1 << reg; 3985 } 3986 } 3987 while (skip_past_comma (&input_line_pointer) != FAIL); 3988 3989 if (*input_line_pointer == '}') 3990 input_line_pointer++; 3991 3992 demand_empty_rest_of_line (); 3993 3994 /* Generate any deferred opcodes because we're going to be looking at 3995 the list. */ 3996 flush_pending_unwind (); 3997 3998 for (reg = 0; reg < 16; reg++) 3999 { 4000 if (mask & (1 << reg)) 4001 unwind.frame_size += 4; 4002 } 4003 op = 0xc700 | mask; 4004 add_unwind_opcode (op, 2); 4005 return; 4006error: 4007 ignore_rest_of_line (); 4008} 4009 4010 4011/* Parse an unwind_save directive. 4012 If the argument is non-zero, this is a .vsave directive. */ 4013 4014static void 4015s_arm_unwind_save (int arch_v6) 4016{ 4017 char *peek; 4018 struct reg_entry *reg; 4019 bfd_boolean had_brace = FALSE; 4020 4021 if (!unwind.proc_start) 4022 as_bad (MISSING_FNSTART); 4023 4024 /* Figure out what sort of save we have. */ 4025 peek = input_line_pointer; 4026 4027 if (*peek == '{') 4028 { 4029 had_brace = TRUE; 4030 peek++; 4031 } 4032 4033 reg = arm_reg_parse_multi (&peek); 4034 4035 if (!reg) 4036 { 4037 as_bad (_("register expected")); 4038 ignore_rest_of_line (); 4039 return; 4040 } 4041 4042 switch (reg->type) 4043 { 4044 case REG_TYPE_FN: 4045 if (had_brace) 4046 { 4047 as_bad (_("FPA .unwind_save does not take a register list")); 4048 ignore_rest_of_line (); 4049 return; 4050 } 4051 input_line_pointer = peek; 4052 s_arm_unwind_save_fpa (reg->number); 4053 return; 4054 4055 case REG_TYPE_RN: s_arm_unwind_save_core (); return; 4056 case REG_TYPE_VFD: 4057 if (arch_v6) 4058 s_arm_unwind_save_vfp_armv6 (); 4059 else 4060 s_arm_unwind_save_vfp (); 4061 return; 4062 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; 4063 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; 4064 4065 default: 4066 as_bad (_(".unwind_save does not support this kind of register")); 4067 ignore_rest_of_line (); 4068 } 4069} 4070 4071 4072/* Parse an unwind_movsp directive. */ 4073 4074static void 4075s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) 4076{ 4077 int reg; 4078 valueT op; 4079 int offset; 4080 4081 if (!unwind.proc_start) 4082 as_bad (MISSING_FNSTART); 4083 4084 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 4085 if (reg == FAIL) 4086 { 4087 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); 4088 ignore_rest_of_line (); 4089 return; 4090 } 4091 4092 /* Optional constant. */ 4093 if (skip_past_comma (&input_line_pointer) != FAIL) 4094 { 4095 if (immediate_for_directive (&offset) == FAIL) 4096 return; 4097 } 4098 else 4099 offset = 0; 4100 4101 demand_empty_rest_of_line (); 4102 4103 if (reg == REG_SP || reg == REG_PC) 4104 { 4105 as_bad (_("SP and PC not permitted in .unwind_movsp directive")); 4106 return; 4107 } 4108 4109 if (unwind.fp_reg != REG_SP) 4110 as_bad (_("unexpected .unwind_movsp directive")); 4111 4112 /* Generate opcode to restore the value. */ 4113 op = 0x90 | reg; 4114 add_unwind_opcode (op, 1); 4115 4116 /* Record the information for later. */ 4117 unwind.fp_reg = reg; 4118 unwind.fp_offset = unwind.frame_size - offset; 4119 unwind.sp_restored = 1; 4120} 4121 4122/* Parse an unwind_pad directive. */ 4123 4124static void 4125s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) 4126{ 4127 int offset; 4128 4129 if (!unwind.proc_start) 4130 as_bad (MISSING_FNSTART); 4131 4132 if (immediate_for_directive (&offset) == FAIL) 4133 return; 4134 4135 if (offset & 3) 4136 { 4137 as_bad (_("stack increment must be multiple of 4")); 4138 ignore_rest_of_line (); 4139 return; 4140 } 4141 4142 /* Don't generate any opcodes, just record the details for later. */ 4143 unwind.frame_size += offset; 4144 unwind.pending_offset += offset; 4145 4146 demand_empty_rest_of_line (); 4147} 4148 4149/* Parse an unwind_setfp directive. */ 4150 4151static void 4152s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) 4153{ 4154 int sp_reg; 4155 int fp_reg; 4156 int offset; 4157 4158 if (!unwind.proc_start) 4159 as_bad (MISSING_FNSTART); 4160 4161 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 4162 if (skip_past_comma (&input_line_pointer) == FAIL) 4163 sp_reg = FAIL; 4164 else 4165 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 4166 4167 if (fp_reg == FAIL || sp_reg == FAIL) 4168 { 4169 as_bad (_("expected <reg>, <reg>")); 4170 ignore_rest_of_line (); 4171 return; 4172 } 4173 4174 /* Optional constant. */ 4175 if (skip_past_comma (&input_line_pointer) != FAIL) 4176 { 4177 if (immediate_for_directive (&offset) == FAIL) 4178 return; 4179 } 4180 else 4181 offset = 0; 4182 4183 demand_empty_rest_of_line (); 4184 4185 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) 4186 { 4187 as_bad (_("register must be either sp or set by a previous" 4188 "unwind_movsp directive")); 4189 return; 4190 } 4191 4192 /* Don't generate any opcodes, just record the information for later. */ 4193 unwind.fp_reg = fp_reg; 4194 unwind.fp_used = 1; 4195 if (sp_reg == REG_SP) 4196 unwind.fp_offset = unwind.frame_size - offset; 4197 else 4198 unwind.fp_offset -= offset; 4199} 4200 4201/* Parse an unwind_raw directive. */ 4202 4203static void 4204s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) 4205{ 4206 expressionS exp; 4207 /* This is an arbitrary limit. */ 4208 unsigned char op[16]; 4209 int count; 4210 4211 if (!unwind.proc_start) 4212 as_bad (MISSING_FNSTART); 4213 4214 expression (&exp); 4215 if (exp.X_op == O_constant 4216 && skip_past_comma (&input_line_pointer) != FAIL) 4217 { 4218 unwind.frame_size += exp.X_add_number; 4219 expression (&exp); 4220 } 4221 else 4222 exp.X_op = O_illegal; 4223 4224 if (exp.X_op != O_constant) 4225 { 4226 as_bad (_("expected <offset>, <opcode>")); 4227 ignore_rest_of_line (); 4228 return; 4229 } 4230 4231 count = 0; 4232 4233 /* Parse the opcode. */ 4234 for (;;) 4235 { 4236 if (count >= 16) 4237 { 4238 as_bad (_("unwind opcode too long")); 4239 ignore_rest_of_line (); 4240 } 4241 if (exp.X_op != O_constant || exp.X_add_number & ~0xff) 4242 { 4243 as_bad (_("invalid unwind opcode")); 4244 ignore_rest_of_line (); 4245 return; 4246 } 4247 op[count++] = exp.X_add_number; 4248 4249 /* Parse the next byte. */ 4250 if (skip_past_comma (&input_line_pointer) == FAIL) 4251 break; 4252 4253 expression (&exp); 4254 } 4255 4256 /* Add the opcode bytes in reverse order. */ 4257 while (count--) 4258 add_unwind_opcode (op[count], 1); 4259 4260 demand_empty_rest_of_line (); 4261} 4262 4263 4264/* Parse a .eabi_attribute directive. */ 4265 4266static void 4267s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) 4268{ 4269 int tag = s_vendor_attribute (OBJ_ATTR_PROC); 4270 4271 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) 4272 attributes_set_explicitly[tag] = 1; 4273} 4274#endif /* OBJ_ELF */ 4275 4276static void s_arm_arch (int); 4277static void s_arm_object_arch (int); 4278static void s_arm_cpu (int); 4279static void s_arm_fpu (int); 4280static void s_arm_arch_extension (int); 4281 4282#ifdef TE_PE 4283 4284static void 4285pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) 4286{ 4287 expressionS exp; 4288 4289 do 4290 { 4291 expression (&exp); 4292 if (exp.X_op == O_symbol) 4293 exp.X_op = O_secrel; 4294 4295 emit_expr (&exp, 4); 4296 } 4297 while (*input_line_pointer++ == ','); 4298 4299 input_line_pointer--; 4300 demand_empty_rest_of_line (); 4301} 4302#endif /* TE_PE */ 4303 4304/* This table describes all the machine specific pseudo-ops the assembler 4305 has to support. The fields are: 4306 pseudo-op name without dot 4307 function to call to execute this pseudo-op 4308 Integer arg to pass to the function. */ 4309 4310const pseudo_typeS md_pseudo_table[] = 4311{ 4312 /* Never called because '.req' does not start a line. */ 4313 { "req", s_req, 0 }, 4314 /* Following two are likewise never called. */ 4315 { "dn", s_dn, 0 }, 4316 { "qn", s_qn, 0 }, 4317 { "unreq", s_unreq, 0 }, 4318 { "bss", s_bss, 0 }, 4319 { "align", s_align, 0 }, 4320 { "arm", s_arm, 0 }, 4321 { "thumb", s_thumb, 0 }, 4322 { "code", s_code, 0 }, 4323 { "force_thumb", s_force_thumb, 0 }, 4324 { "thumb_func", s_thumb_func, 0 }, 4325 { "thumb_set", s_thumb_set, 0 }, 4326 { "even", s_even, 0 }, 4327 { "ltorg", s_ltorg, 0 }, 4328 { "pool", s_ltorg, 0 }, 4329 { "syntax", s_syntax, 0 }, 4330 { "cpu", s_arm_cpu, 0 }, 4331 { "arch", s_arm_arch, 0 }, 4332 { "object_arch", s_arm_object_arch, 0 }, 4333 { "fpu", s_arm_fpu, 0 }, 4334 { "arch_extension", s_arm_arch_extension, 0 }, 4335#ifdef OBJ_ELF 4336 { "word", s_arm_elf_cons, 4 }, 4337 { "long", s_arm_elf_cons, 4 }, 4338 { "inst.n", s_arm_elf_inst, 2 }, 4339 { "inst.w", s_arm_elf_inst, 4 }, 4340 { "inst", s_arm_elf_inst, 0 }, 4341 { "rel31", s_arm_rel31, 0 }, 4342 { "fnstart", s_arm_unwind_fnstart, 0 }, 4343 { "fnend", s_arm_unwind_fnend, 0 }, 4344 { "cantunwind", s_arm_unwind_cantunwind, 0 }, 4345 { "personality", s_arm_unwind_personality, 0 }, 4346 { "personalityindex", s_arm_unwind_personalityindex, 0 }, 4347 { "handlerdata", s_arm_unwind_handlerdata, 0 }, 4348 { "save", s_arm_unwind_save, 0 }, 4349 { "vsave", s_arm_unwind_save, 1 }, 4350 { "movsp", s_arm_unwind_movsp, 0 }, 4351 { "pad", s_arm_unwind_pad, 0 }, 4352 { "setfp", s_arm_unwind_setfp, 0 }, 4353 { "unwind_raw", s_arm_unwind_raw, 0 }, 4354 { "eabi_attribute", s_arm_eabi_attribute, 0 }, 4355#else 4356 { "word", cons, 4}, 4357 4358 /* These are used for dwarf. */ 4359 {"2byte", cons, 2}, 4360 {"4byte", cons, 4}, 4361 {"8byte", cons, 8}, 4362 /* These are used for dwarf2. */ 4363 { "file", (void (*) (int)) dwarf2_directive_file, 0 }, 4364 { "loc", dwarf2_directive_loc, 0 }, 4365 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, 4366#endif 4367 { "extend", float_cons, 'x' }, 4368 { "ldouble", float_cons, 'x' }, 4369 { "packed", float_cons, 'p' }, 4370#ifdef TE_PE 4371 {"secrel32", pe_directive_secrel, 0}, 4372#endif 4373 { 0, 0, 0 } 4374}; 4375 4376/* Parser functions used exclusively in instruction operands. */ 4377 4378/* Generic immediate-value read function for use in insn parsing. 4379 STR points to the beginning of the immediate (the leading #); 4380 VAL receives the value; if the value is outside [MIN, MAX] 4381 issue an error. PREFIX_OPT is true if the immediate prefix is 4382 optional. */ 4383 4384static int 4385parse_immediate (char **str, int *val, int min, int max, 4386 bfd_boolean prefix_opt) 4387{ 4388 expressionS exp; 4389 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); 4390 if (exp.X_op != O_constant) 4391 { 4392 inst.error = _("constant expression required"); 4393 return FAIL; 4394 } 4395 4396 if (exp.X_add_number < min || exp.X_add_number > max) 4397 { 4398 inst.error = _("immediate value out of range"); 4399 return FAIL; 4400 } 4401 4402 *val = exp.X_add_number; 4403 return SUCCESS; 4404} 4405 4406/* Less-generic immediate-value read function with the possibility of loading a 4407 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate 4408 instructions. Puts the result directly in inst.operands[i]. */ 4409 4410static int 4411parse_big_immediate (char **str, int i) 4412{ 4413 expressionS exp; 4414 char *ptr = *str; 4415 4416 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); 4417 4418 if (exp.X_op == O_constant) 4419 { 4420 inst.operands[i].imm = exp.X_add_number & 0xffffffff; 4421 /* If we're on a 64-bit host, then a 64-bit number can be returned using 4422 O_constant. We have to be careful not to break compilation for 4423 32-bit X_add_number, though. */ 4424 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0) 4425 { 4426 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ 4427 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; 4428 inst.operands[i].regisimm = 1; 4429 } 4430 } 4431 else if (exp.X_op == O_big 4432 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32) 4433 { 4434 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; 4435 4436 /* Bignums have their least significant bits in 4437 generic_bignum[0]. Make sure we put 32 bits in imm and 4438 32 bits in reg, in a (hopefully) portable way. */ 4439 gas_assert (parts != 0); 4440 4441 /* Make sure that the number is not too big. 4442 PR 11972: Bignums can now be sign-extended to the 4443 size of a .octa so check that the out of range bits 4444 are all zero or all one. */ 4445 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64) 4446 { 4447 LITTLENUM_TYPE m = -1; 4448 4449 if (generic_bignum[parts * 2] != 0 4450 && generic_bignum[parts * 2] != m) 4451 return FAIL; 4452 4453 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++) 4454 if (generic_bignum[j] != generic_bignum[j-1]) 4455 return FAIL; 4456 } 4457 4458 inst.operands[i].imm = 0; 4459 for (j = 0; j < parts; j++, idx++) 4460 inst.operands[i].imm |= generic_bignum[idx] 4461 << (LITTLENUM_NUMBER_OF_BITS * j); 4462 inst.operands[i].reg = 0; 4463 for (j = 0; j < parts; j++, idx++) 4464 inst.operands[i].reg |= generic_bignum[idx] 4465 << (LITTLENUM_NUMBER_OF_BITS * j); 4466 inst.operands[i].regisimm = 1; 4467 } 4468 else 4469 return FAIL; 4470 4471 *str = ptr; 4472 4473 return SUCCESS; 4474} 4475 4476/* Returns the pseudo-register number of an FPA immediate constant, 4477 or FAIL if there isn't a valid constant here. */ 4478 4479static int 4480parse_fpa_immediate (char ** str) 4481{ 4482 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 4483 char * save_in; 4484 expressionS exp; 4485 int i; 4486 int j; 4487 4488 /* First try and match exact strings, this is to guarantee 4489 that some formats will work even for cross assembly. */ 4490 4491 for (i = 0; fp_const[i]; i++) 4492 { 4493 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) 4494 { 4495 char *start = *str; 4496 4497 *str += strlen (fp_const[i]); 4498 if (is_end_of_line[(unsigned char) **str]) 4499 return i + 8; 4500 *str = start; 4501 } 4502 } 4503 4504 /* Just because we didn't get a match doesn't mean that the constant 4505 isn't valid, just that it is in a format that we don't 4506 automatically recognize. Try parsing it with the standard 4507 expression routines. */ 4508 4509 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); 4510 4511 /* Look for a raw floating point number. */ 4512 if ((save_in = atof_ieee (*str, 'x', words)) != NULL 4513 && is_end_of_line[(unsigned char) *save_in]) 4514 { 4515 for (i = 0; i < NUM_FLOAT_VALS; i++) 4516 { 4517 for (j = 0; j < MAX_LITTLENUMS; j++) 4518 { 4519 if (words[j] != fp_values[i][j]) 4520 break; 4521 } 4522 4523 if (j == MAX_LITTLENUMS) 4524 { 4525 *str = save_in; 4526 return i + 8; 4527 } 4528 } 4529 } 4530 4531 /* Try and parse a more complex expression, this will probably fail 4532 unless the code uses a floating point prefix (eg "0f"). */ 4533 save_in = input_line_pointer; 4534 input_line_pointer = *str; 4535 if (expression (&exp) == absolute_section 4536 && exp.X_op == O_big 4537 && exp.X_add_number < 0) 4538 { 4539 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. 4540 Ditto for 15. */ 4541 if (gen_to_words (words, 5, (long) 15) == 0) 4542 { 4543 for (i = 0; i < NUM_FLOAT_VALS; i++) 4544 { 4545 for (j = 0; j < MAX_LITTLENUMS; j++) 4546 { 4547 if (words[j] != fp_values[i][j]) 4548 break; 4549 } 4550 4551 if (j == MAX_LITTLENUMS) 4552 { 4553 *str = input_line_pointer; 4554 input_line_pointer = save_in; 4555 return i + 8; 4556 } 4557 } 4558 } 4559 } 4560 4561 *str = input_line_pointer; 4562 input_line_pointer = save_in; 4563 inst.error = _("invalid FPA immediate expression"); 4564 return FAIL; 4565} 4566 4567/* Returns 1 if a number has "quarter-precision" float format 4568 0baBbbbbbc defgh000 00000000 00000000. */ 4569 4570static int 4571is_quarter_float (unsigned imm) 4572{ 4573 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; 4574 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; 4575} 4576 4577/* Parse an 8-bit "quarter-precision" floating point number of the form: 4578 0baBbbbbbc defgh000 00000000 00000000. 4579 The zero and minus-zero cases need special handling, since they can't be 4580 encoded in the "quarter-precision" float format, but can nonetheless be 4581 loaded as integer constants. */ 4582 4583static unsigned 4584parse_qfloat_immediate (char **ccp, int *immed) 4585{ 4586 char *str = *ccp; 4587 char *fpnum; 4588 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 4589 int found_fpchar = 0; 4590 4591 skip_past_char (&str, '#'); 4592 4593 /* We must not accidentally parse an integer as a floating-point number. Make 4594 sure that the value we parse is not an integer by checking for special 4595 characters '.' or 'e'. 4596 FIXME: This is a horrible hack, but doing better is tricky because type 4597 information isn't in a very usable state at parse time. */ 4598 fpnum = str; 4599 skip_whitespace (fpnum); 4600 4601 if (strncmp (fpnum, "0x", 2) == 0) 4602 return FAIL; 4603 else 4604 { 4605 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) 4606 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') 4607 { 4608 found_fpchar = 1; 4609 break; 4610 } 4611 4612 if (!found_fpchar) 4613 return FAIL; 4614 } 4615 4616 if ((str = atof_ieee (str, 's', words)) != NULL) 4617 { 4618 unsigned fpword = 0; 4619 int i; 4620 4621 /* Our FP word must be 32 bits (single-precision FP). */ 4622 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) 4623 { 4624 fpword <<= LITTLENUM_NUMBER_OF_BITS; 4625 fpword |= words[i]; 4626 } 4627 4628 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) 4629 *immed = fpword; 4630 else 4631 return FAIL; 4632 4633 *ccp = str; 4634 4635 return SUCCESS; 4636 } 4637 4638 return FAIL; 4639} 4640 4641/* Shift operands. */ 4642enum shift_kind 4643{ 4644 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX 4645}; 4646 4647struct asm_shift_name 4648{ 4649 const char *name; 4650 enum shift_kind kind; 4651}; 4652 4653/* Third argument to parse_shift. */ 4654enum parse_shift_mode 4655{ 4656 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ 4657 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ 4658 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ 4659 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ 4660 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ 4661}; 4662 4663/* Parse a <shift> specifier on an ARM data processing instruction. 4664 This has three forms: 4665 4666 (LSL|LSR|ASL|ASR|ROR) Rs 4667 (LSL|LSR|ASL|ASR|ROR) #imm 4668 RRX 4669 4670 Note that ASL is assimilated to LSL in the instruction encoding, and 4671 RRX to ROR #0 (which cannot be written as such). */ 4672 4673static int 4674parse_shift (char **str, int i, enum parse_shift_mode mode) 4675{ 4676 const struct asm_shift_name *shift_name; 4677 enum shift_kind shift; 4678 char *s = *str; 4679 char *p = s; 4680 int reg; 4681 4682 for (p = *str; ISALPHA (*p); p++) 4683 ; 4684 4685 if (p == *str) 4686 { 4687 inst.error = _("shift expression expected"); 4688 return FAIL; 4689 } 4690 4691 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, 4692 p - *str); 4693 4694 if (shift_name == NULL) 4695 { 4696 inst.error = _("shift expression expected"); 4697 return FAIL; 4698 } 4699 4700 shift = shift_name->kind; 4701 4702 switch (mode) 4703 { 4704 case NO_SHIFT_RESTRICT: 4705 case SHIFT_IMMEDIATE: break; 4706 4707 case SHIFT_LSL_OR_ASR_IMMEDIATE: 4708 if (shift != SHIFT_LSL && shift != SHIFT_ASR) 4709 { 4710 inst.error = _("'LSL' or 'ASR' required"); 4711 return FAIL; 4712 } 4713 break; 4714 4715 case SHIFT_LSL_IMMEDIATE: 4716 if (shift != SHIFT_LSL) 4717 { 4718 inst.error = _("'LSL' required"); 4719 return FAIL; 4720 } 4721 break; 4722 4723 case SHIFT_ASR_IMMEDIATE: 4724 if (shift != SHIFT_ASR) 4725 { 4726 inst.error = _("'ASR' required"); 4727 return FAIL; 4728 } 4729 break; 4730 4731 default: abort (); 4732 } 4733 4734 if (shift != SHIFT_RRX) 4735 { 4736 /* Whitespace can appear here if the next thing is a bare digit. */ 4737 skip_whitespace (p); 4738 4739 if (mode == NO_SHIFT_RESTRICT 4740 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4741 { 4742 inst.operands[i].imm = reg; 4743 inst.operands[i].immisreg = 1; 4744 } 4745 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4746 return FAIL; 4747 } 4748 inst.operands[i].shift_kind = shift; 4749 inst.operands[i].shifted = 1; 4750 *str = p; 4751 return SUCCESS; 4752} 4753 4754/* Parse a <shifter_operand> for an ARM data processing instruction: 4755 4756 #<immediate> 4757 #<immediate>, <rotate> 4758 <Rm> 4759 <Rm>, <shift> 4760 4761 where <shift> is defined by parse_shift above, and <rotate> is a 4762 multiple of 2 between 0 and 30. Validation of immediate operands 4763 is deferred to md_apply_fix. */ 4764 4765static int 4766parse_shifter_operand (char **str, int i) 4767{ 4768 int value; 4769 expressionS exp; 4770 4771 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) 4772 { 4773 inst.operands[i].reg = value; 4774 inst.operands[i].isreg = 1; 4775 4776 /* parse_shift will override this if appropriate */ 4777 inst.reloc.exp.X_op = O_constant; 4778 inst.reloc.exp.X_add_number = 0; 4779 4780 if (skip_past_comma (str) == FAIL) 4781 return SUCCESS; 4782 4783 /* Shift operation on register. */ 4784 return parse_shift (str, i, NO_SHIFT_RESTRICT); 4785 } 4786 4787 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) 4788 return FAIL; 4789 4790 if (skip_past_comma (str) == SUCCESS) 4791 { 4792 /* #x, y -- ie explicit rotation by Y. */ 4793 if (my_get_expression (&exp, str, GE_NO_PREFIX)) 4794 return FAIL; 4795 4796 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant) 4797 { 4798 inst.error = _("constant expression expected"); 4799 return FAIL; 4800 } 4801 4802 value = exp.X_add_number; 4803 if (value < 0 || value > 30 || value % 2 != 0) 4804 { 4805 inst.error = _("invalid rotation"); 4806 return FAIL; 4807 } 4808 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) 4809 { 4810 inst.error = _("invalid constant"); 4811 return FAIL; 4812 } 4813 4814 /* Convert to decoded value. md_apply_fix will put it back. */ 4815 inst.reloc.exp.X_add_number 4816 = (((inst.reloc.exp.X_add_number << (32 - value)) 4817 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); 4818 } 4819 4820 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 4821 inst.reloc.pc_rel = 0; 4822 return SUCCESS; 4823} 4824 4825/* Group relocation information. Each entry in the table contains the 4826 textual name of the relocation as may appear in assembler source 4827 and must end with a colon. 4828 Along with this textual name are the relocation codes to be used if 4829 the corresponding instruction is an ALU instruction (ADD or SUB only), 4830 an LDR, an LDRS, or an LDC. */ 4831 4832struct group_reloc_table_entry 4833{ 4834 const char *name; 4835 int alu_code; 4836 int ldr_code; 4837 int ldrs_code; 4838 int ldc_code; 4839}; 4840 4841typedef enum 4842{ 4843 /* Varieties of non-ALU group relocation. */ 4844 4845 GROUP_LDR, 4846 GROUP_LDRS, 4847 GROUP_LDC 4848} group_reloc_type; 4849 4850static struct group_reloc_table_entry group_reloc_table[] = 4851 { /* Program counter relative: */ 4852 { "pc_g0_nc", 4853 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ 4854 0, /* LDR */ 4855 0, /* LDRS */ 4856 0 }, /* LDC */ 4857 { "pc_g0", 4858 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ 4859 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ 4860 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ 4861 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ 4862 { "pc_g1_nc", 4863 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ 4864 0, /* LDR */ 4865 0, /* LDRS */ 4866 0 }, /* LDC */ 4867 { "pc_g1", 4868 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ 4869 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ 4870 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ 4871 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ 4872 { "pc_g2", 4873 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ 4874 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ 4875 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ 4876 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ 4877 /* Section base relative */ 4878 { "sb_g0_nc", 4879 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ 4880 0, /* LDR */ 4881 0, /* LDRS */ 4882 0 }, /* LDC */ 4883 { "sb_g0", 4884 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ 4885 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ 4886 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ 4887 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ 4888 { "sb_g1_nc", 4889 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ 4890 0, /* LDR */ 4891 0, /* LDRS */ 4892 0 }, /* LDC */ 4893 { "sb_g1", 4894 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ 4895 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ 4896 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ 4897 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ 4898 { "sb_g2", 4899 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ 4900 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ 4901 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ 4902 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ 4903 4904/* Given the address of a pointer pointing to the textual name of a group 4905 relocation as may appear in assembler source, attempt to find its details 4906 in group_reloc_table. The pointer will be updated to the character after 4907 the trailing colon. On failure, FAIL will be returned; SUCCESS 4908 otherwise. On success, *entry will be updated to point at the relevant 4909 group_reloc_table entry. */ 4910 4911static int 4912find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) 4913{ 4914 unsigned int i; 4915 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) 4916 { 4917 int length = strlen (group_reloc_table[i].name); 4918 4919 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 4920 && (*str)[length] == ':') 4921 { 4922 *out = &group_reloc_table[i]; 4923 *str += (length + 1); 4924 return SUCCESS; 4925 } 4926 } 4927 4928 return FAIL; 4929} 4930 4931/* Parse a <shifter_operand> for an ARM data processing instruction 4932 (as for parse_shifter_operand) where group relocations are allowed: 4933 4934 #<immediate> 4935 #<immediate>, <rotate> 4936 #:<group_reloc>:<expression> 4937 <Rm> 4938 <Rm>, <shift> 4939 4940 where <group_reloc> is one of the strings defined in group_reloc_table. 4941 The hashes are optional. 4942 4943 Everything else is as for parse_shifter_operand. */ 4944 4945static parse_operand_result 4946parse_shifter_operand_group_reloc (char **str, int i) 4947{ 4948 /* Determine if we have the sequence of characters #: or just : 4949 coming next. If we do, then we check for a group relocation. 4950 If we don't, punt the whole lot to parse_shifter_operand. */ 4951 4952 if (((*str)[0] == '#' && (*str)[1] == ':') 4953 || (*str)[0] == ':') 4954 { 4955 struct group_reloc_table_entry *entry; 4956 4957 if ((*str)[0] == '#') 4958 (*str) += 2; 4959 else 4960 (*str)++; 4961 4962 /* Try to parse a group relocation. Anything else is an error. */ 4963 if (find_group_reloc_table_entry (str, &entry) == FAIL) 4964 { 4965 inst.error = _("unknown group relocation"); 4966 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4967 } 4968 4969 /* We now have the group relocation table entry corresponding to 4970 the name in the assembler source. Next, we parse the expression. */ 4971 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) 4972 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4973 4974 /* Record the relocation type (always the ALU variant here). */ 4975 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code; 4976 gas_assert (inst.reloc.type != 0); 4977 4978 return PARSE_OPERAND_SUCCESS; 4979 } 4980 else 4981 return parse_shifter_operand (str, i) == SUCCESS 4982 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; 4983 4984 /* Never reached. */ 4985} 4986 4987/* Parse a Neon alignment expression. Information is written to 4988 inst.operands[i]. We assume the initial ':' has been skipped. 4989 4990 align .imm = align << 8, .immisalign=1, .preind=0 */ 4991static parse_operand_result 4992parse_neon_alignment (char **str, int i) 4993{ 4994 char *p = *str; 4995 expressionS exp; 4996 4997 my_get_expression (&exp, &p, GE_NO_PREFIX); 4998 4999 if (exp.X_op != O_constant) 5000 { 5001 inst.error = _("alignment must be constant"); 5002 return PARSE_OPERAND_FAIL; 5003 } 5004 5005 inst.operands[i].imm = exp.X_add_number << 8; 5006 inst.operands[i].immisalign = 1; 5007 /* Alignments are not pre-indexes. */ 5008 inst.operands[i].preind = 0; 5009 5010 *str = p; 5011 return PARSE_OPERAND_SUCCESS; 5012} 5013 5014/* Parse all forms of an ARM address expression. Information is written 5015 to inst.operands[i] and/or inst.reloc. 5016 5017 Preindexed addressing (.preind=1): 5018 5019 [Rn, #offset] .reg=Rn .reloc.exp=offset 5020 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 5021 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 5022 .shift_kind=shift .reloc.exp=shift_imm 5023 5024 These three may have a trailing ! which causes .writeback to be set also. 5025 5026 Postindexed addressing (.postind=1, .writeback=1): 5027 5028 [Rn], #offset .reg=Rn .reloc.exp=offset 5029 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 5030 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 5031 .shift_kind=shift .reloc.exp=shift_imm 5032 5033 Unindexed addressing (.preind=0, .postind=0): 5034 5035 [Rn], {option} .reg=Rn .imm=option .immisreg=0 5036 5037 Other: 5038 5039 [Rn]{!} shorthand for [Rn,#0]{!} 5040 =immediate .isreg=0 .reloc.exp=immediate 5041 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label 5042 5043 It is the caller's responsibility to check for addressing modes not 5044 supported by the instruction, and to set inst.reloc.type. */ 5045 5046static parse_operand_result 5047parse_address_main (char **str, int i, int group_relocations, 5048 group_reloc_type group_type) 5049{ 5050 char *p = *str; 5051 int reg; 5052 5053 if (skip_past_char (&p, '[') == FAIL) 5054 { 5055 if (skip_past_char (&p, '=') == FAIL) 5056 { 5057 /* Bare address - translate to PC-relative offset. */ 5058 inst.reloc.pc_rel = 1; 5059 inst.operands[i].reg = REG_PC; 5060 inst.operands[i].isreg = 1; 5061 inst.operands[i].preind = 1; 5062 } 5063 /* Otherwise a load-constant pseudo op, no special treatment needed here. */ 5064 5065 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 5066 return PARSE_OPERAND_FAIL; 5067 5068 *str = p; 5069 return PARSE_OPERAND_SUCCESS; 5070 } 5071 5072 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 5073 { 5074 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 5075 return PARSE_OPERAND_FAIL; 5076 } 5077 inst.operands[i].reg = reg; 5078 inst.operands[i].isreg = 1; 5079 5080 if (skip_past_comma (&p) == SUCCESS) 5081 { 5082 inst.operands[i].preind = 1; 5083 5084 if (*p == '+') p++; 5085 else if (*p == '-') p++, inst.operands[i].negative = 1; 5086 5087 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 5088 { 5089 inst.operands[i].imm = reg; 5090 inst.operands[i].immisreg = 1; 5091 5092 if (skip_past_comma (&p) == SUCCESS) 5093 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) 5094 return PARSE_OPERAND_FAIL; 5095 } 5096 else if (skip_past_char (&p, ':') == SUCCESS) 5097 { 5098 /* FIXME: '@' should be used here, but it's filtered out by generic 5099 code before we get to see it here. This may be subject to 5100 change. */ 5101 parse_operand_result result = parse_neon_alignment (&p, i); 5102 5103 if (result != PARSE_OPERAND_SUCCESS) 5104 return result; 5105 } 5106 else 5107 { 5108 if (inst.operands[i].negative) 5109 { 5110 inst.operands[i].negative = 0; 5111 p--; 5112 } 5113 5114 if (group_relocations 5115 && ((*p == '#' && *(p + 1) == ':') || *p == ':')) 5116 { 5117 struct group_reloc_table_entry *entry; 5118 5119 /* Skip over the #: or : sequence. */ 5120 if (*p == '#') 5121 p += 2; 5122 else 5123 p++; 5124 5125 /* Try to parse a group relocation. Anything else is an 5126 error. */ 5127 if (find_group_reloc_table_entry (&p, &entry) == FAIL) 5128 { 5129 inst.error = _("unknown group relocation"); 5130 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 5131 } 5132 5133 /* We now have the group relocation table entry corresponding to 5134 the name in the assembler source. Next, we parse the 5135 expression. */ 5136 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 5137 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 5138 5139 /* Record the relocation type. */ 5140 switch (group_type) 5141 { 5142 case GROUP_LDR: 5143 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code; 5144 break; 5145 5146 case GROUP_LDRS: 5147 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code; 5148 break; 5149 5150 case GROUP_LDC: 5151 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code; 5152 break; 5153 5154 default: 5155 gas_assert (0); 5156 } 5157 5158 if (inst.reloc.type == 0) 5159 { 5160 inst.error = _("this group relocation is not allowed on this instruction"); 5161 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 5162 } 5163 } 5164 else 5165 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 5166 return PARSE_OPERAND_FAIL; 5167 } 5168 } 5169 else if (skip_past_char (&p, ':') == SUCCESS) 5170 { 5171 /* FIXME: '@' should be used here, but it's filtered out by generic code 5172 before we get to see it here. This may be subject to change. */ 5173 parse_operand_result result = parse_neon_alignment (&p, i); 5174 5175 if (result != PARSE_OPERAND_SUCCESS) 5176 return result; 5177 } 5178 5179 if (skip_past_char (&p, ']') == FAIL) 5180 { 5181 inst.error = _("']' expected"); 5182 return PARSE_OPERAND_FAIL; 5183 } 5184 5185 if (skip_past_char (&p, '!') == SUCCESS) 5186 inst.operands[i].writeback = 1; 5187 5188 else if (skip_past_comma (&p) == SUCCESS) 5189 { 5190 if (skip_past_char (&p, '{') == SUCCESS) 5191 { 5192 /* [Rn], {expr} - unindexed, with option */ 5193 if (parse_immediate (&p, &inst.operands[i].imm, 5194 0, 255, TRUE) == FAIL) 5195 return PARSE_OPERAND_FAIL; 5196 5197 if (skip_past_char (&p, '}') == FAIL) 5198 { 5199 inst.error = _("'}' expected at end of 'option' field"); 5200 return PARSE_OPERAND_FAIL; 5201 } 5202 if (inst.operands[i].preind) 5203 { 5204 inst.error = _("cannot combine index with option"); 5205 return PARSE_OPERAND_FAIL; 5206 } 5207 *str = p; 5208 return PARSE_OPERAND_SUCCESS; 5209 } 5210 else 5211 { 5212 inst.operands[i].postind = 1; 5213 inst.operands[i].writeback = 1; 5214 5215 if (inst.operands[i].preind) 5216 { 5217 inst.error = _("cannot combine pre- and post-indexing"); 5218 return PARSE_OPERAND_FAIL; 5219 } 5220 5221 if (*p == '+') p++; 5222 else if (*p == '-') p++, inst.operands[i].negative = 1; 5223 5224 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 5225 { 5226 /* We might be using the immediate for alignment already. If we 5227 are, OR the register number into the low-order bits. */ 5228 if (inst.operands[i].immisalign) 5229 inst.operands[i].imm |= reg; 5230 else 5231 inst.operands[i].imm = reg; 5232 inst.operands[i].immisreg = 1; 5233 5234 if (skip_past_comma (&p) == SUCCESS) 5235 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) 5236 return PARSE_OPERAND_FAIL; 5237 } 5238 else 5239 { 5240 if (inst.operands[i].negative) 5241 { 5242 inst.operands[i].negative = 0; 5243 p--; 5244 } 5245 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 5246 return PARSE_OPERAND_FAIL; 5247 } 5248 } 5249 } 5250 5251 /* If at this point neither .preind nor .postind is set, we have a 5252 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ 5253 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) 5254 { 5255 inst.operands[i].preind = 1; 5256 inst.reloc.exp.X_op = O_constant; 5257 inst.reloc.exp.X_add_number = 0; 5258 } 5259 *str = p; 5260 return PARSE_OPERAND_SUCCESS; 5261} 5262 5263static int 5264parse_address (char **str, int i) 5265{ 5266 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS 5267 ? SUCCESS : FAIL; 5268} 5269 5270static parse_operand_result 5271parse_address_group_reloc (char **str, int i, group_reloc_type type) 5272{ 5273 return parse_address_main (str, i, 1, type); 5274} 5275 5276/* Parse an operand for a MOVW or MOVT instruction. */ 5277static int 5278parse_half (char **str) 5279{ 5280 char * p; 5281 5282 p = *str; 5283 skip_past_char (&p, '#'); 5284 if (strncasecmp (p, ":lower16:", 9) == 0) 5285 inst.reloc.type = BFD_RELOC_ARM_MOVW; 5286 else if (strncasecmp (p, ":upper16:", 9) == 0) 5287 inst.reloc.type = BFD_RELOC_ARM_MOVT; 5288 5289 if (inst.reloc.type != BFD_RELOC_UNUSED) 5290 { 5291 p += 9; 5292 skip_whitespace (p); 5293 } 5294 5295 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 5296 return FAIL; 5297 5298 if (inst.reloc.type == BFD_RELOC_UNUSED) 5299 { 5300 if (inst.reloc.exp.X_op != O_constant) 5301 { 5302 inst.error = _("constant expression expected"); 5303 return FAIL; 5304 } 5305 if (inst.reloc.exp.X_add_number < 0 5306 || inst.reloc.exp.X_add_number > 0xffff) 5307 { 5308 inst.error = _("immediate value out of range"); 5309 return FAIL; 5310 } 5311 } 5312 *str = p; 5313 return SUCCESS; 5314} 5315 5316/* Miscellaneous. */ 5317 5318/* Parse a PSR flag operand. The value returned is FAIL on syntax error, 5319 or a bitmask suitable to be or-ed into the ARM msr instruction. */ 5320static int 5321parse_psr (char **str) 5322{ 5323 char *p; 5324 unsigned long psr_field; 5325 const struct asm_psr *psr; 5326 char *start; 5327 5328 /* CPSR's and SPSR's can now be lowercase. This is just a convenience 5329 feature for ease of use and backwards compatibility. */ 5330 p = *str; 5331 if (strncasecmp (p, "SPSR", 4) == 0) 5332 psr_field = SPSR_BIT; 5333 else if (strncasecmp (p, "CPSR", 4) == 0 5334 || (strncasecmp (p, "APSR", 4) == 0 5335 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))) 5336 psr_field = 0; 5337 else 5338 { 5339 start = p; 5340 do 5341 p++; 5342 while (ISALNUM (*p) || *p == '_'); 5343 5344 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, 5345 p - start); 5346 if (!psr) 5347 return FAIL; 5348 5349 *str = p; 5350 return psr->field; 5351 } 5352 5353 p += 4; 5354 if (*p == '_') 5355 { 5356 /* A suffix follows. */ 5357 p++; 5358 start = p; 5359 5360 do 5361 p++; 5362 while (ISALNUM (*p) || *p == '_'); 5363 5364 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, 5365 p - start); 5366 if (!psr) 5367 goto error; 5368 5369 psr_field |= psr->field; 5370 } 5371 else 5372 { 5373 if (ISALNUM (*p)) 5374 goto error; /* Garbage after "[CS]PSR". */ 5375 5376 psr_field |= (PSR_c | PSR_f); 5377 } 5378 *str = p; 5379 return psr_field; 5380 5381 error: 5382 inst.error = _("flag for {c}psr instruction expected"); 5383 return FAIL; 5384} 5385 5386/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a 5387 value suitable for splatting into the AIF field of the instruction. */ 5388 5389static int 5390parse_cps_flags (char **str) 5391{ 5392 int val = 0; 5393 int saw_a_flag = 0; 5394 char *s = *str; 5395 5396 for (;;) 5397 switch (*s++) 5398 { 5399 case '\0': case ',': 5400 goto done; 5401 5402 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; 5403 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; 5404 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; 5405 5406 default: 5407 inst.error = _("unrecognized CPS flag"); 5408 return FAIL; 5409 } 5410 5411 done: 5412 if (saw_a_flag == 0) 5413 { 5414 inst.error = _("missing CPS flags"); 5415 return FAIL; 5416 } 5417 5418 *str = s - 1; 5419 return val; 5420} 5421 5422/* Parse an endian specifier ("BE" or "LE", case insensitive); 5423 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ 5424 5425static int 5426parse_endian_specifier (char **str) 5427{ 5428 int little_endian; 5429 char *s = *str; 5430 5431 if (strncasecmp (s, "BE", 2)) 5432 little_endian = 0; 5433 else if (strncasecmp (s, "LE", 2)) 5434 little_endian = 1; 5435 else 5436 { 5437 inst.error = _("valid endian specifiers are be or le"); 5438 return FAIL; 5439 } 5440 5441 if (ISALNUM (s[2]) || s[2] == '_') 5442 { 5443 inst.error = _("valid endian specifiers are be or le"); 5444 return FAIL; 5445 } 5446 5447 *str = s + 2; 5448 return little_endian; 5449} 5450 5451/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a 5452 value suitable for poking into the rotate field of an sxt or sxta 5453 instruction, or FAIL on error. */ 5454 5455static int 5456parse_ror (char **str) 5457{ 5458 int rot; 5459 char *s = *str; 5460 5461 if (strncasecmp (s, "ROR", 3) == 0) 5462 s += 3; 5463 else 5464 { 5465 inst.error = _("missing rotation field after comma"); 5466 return FAIL; 5467 } 5468 5469 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) 5470 return FAIL; 5471 5472 switch (rot) 5473 { 5474 case 0: *str = s; return 0x0; 5475 case 8: *str = s; return 0x1; 5476 case 16: *str = s; return 0x2; 5477 case 24: *str = s; return 0x3; 5478 5479 default: 5480 inst.error = _("rotation can only be 0, 8, 16, or 24"); 5481 return FAIL; 5482 } 5483} 5484 5485/* Parse a conditional code (from conds[] below). The value returned is in the 5486 range 0 .. 14, or FAIL. */ 5487static int 5488parse_cond (char **str) 5489{ 5490 char *q; 5491 const struct asm_cond *c; 5492 int n; 5493 /* Condition codes are always 2 characters, so matching up to 5494 3 characters is sufficient. */ 5495 char cond[3]; 5496 5497 q = *str; 5498 n = 0; 5499 while (ISALPHA (*q) && n < 3) 5500 { 5501 cond[n] = TOLOWER (*q); 5502 q++; 5503 n++; 5504 } 5505 5506 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); 5507 if (!c) 5508 { 5509 inst.error = _("condition required"); 5510 return FAIL; 5511 } 5512 5513 *str = q; 5514 return c->value; 5515} 5516 5517/* Parse an option for a barrier instruction. Returns the encoding for the 5518 option, or FAIL. */ 5519static int 5520parse_barrier (char **str) 5521{ 5522 char *p, *q; 5523 const struct asm_barrier_opt *o; 5524 5525 p = q = *str; 5526 while (ISALPHA (*q)) 5527 q++; 5528 5529 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, 5530 q - p); 5531 if (!o) 5532 return FAIL; 5533 5534 *str = q; 5535 return o->value; 5536} 5537 5538/* Parse the operands of a table branch instruction. Similar to a memory 5539 operand. */ 5540static int 5541parse_tb (char **str) 5542{ 5543 char * p = *str; 5544 int reg; 5545 5546 if (skip_past_char (&p, '[') == FAIL) 5547 { 5548 inst.error = _("'[' expected"); 5549 return FAIL; 5550 } 5551 5552 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 5553 { 5554 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 5555 return FAIL; 5556 } 5557 inst.operands[0].reg = reg; 5558 5559 if (skip_past_comma (&p) == FAIL) 5560 { 5561 inst.error = _("',' expected"); 5562 return FAIL; 5563 } 5564 5565 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 5566 { 5567 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 5568 return FAIL; 5569 } 5570 inst.operands[0].imm = reg; 5571 5572 if (skip_past_comma (&p) == SUCCESS) 5573 { 5574 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) 5575 return FAIL; 5576 if (inst.reloc.exp.X_add_number != 1) 5577 { 5578 inst.error = _("invalid shift"); 5579 return FAIL; 5580 } 5581 inst.operands[0].shifted = 1; 5582 } 5583 5584 if (skip_past_char (&p, ']') == FAIL) 5585 { 5586 inst.error = _("']' expected"); 5587 return FAIL; 5588 } 5589 *str = p; 5590 return SUCCESS; 5591} 5592 5593/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more 5594 information on the types the operands can take and how they are encoded. 5595 Up to four operands may be read; this function handles setting the 5596 ".present" field for each read operand itself. 5597 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, 5598 else returns FAIL. */ 5599 5600static int 5601parse_neon_mov (char **str, int *which_operand) 5602{ 5603 int i = *which_operand, val; 5604 enum arm_reg_type rtype; 5605 char *ptr = *str; 5606 struct neon_type_el optype; 5607 5608 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) 5609 { 5610 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ 5611 inst.operands[i].reg = val; 5612 inst.operands[i].isscalar = 1; 5613 inst.operands[i].vectype = optype; 5614 inst.operands[i++].present = 1; 5615 5616 if (skip_past_comma (&ptr) == FAIL) 5617 goto wanted_comma; 5618 5619 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5620 goto wanted_arm; 5621 5622 inst.operands[i].reg = val; 5623 inst.operands[i].isreg = 1; 5624 inst.operands[i].present = 1; 5625 } 5626 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) 5627 != FAIL) 5628 { 5629 /* Cases 0, 1, 2, 3, 5 (D only). */ 5630 if (skip_past_comma (&ptr) == FAIL) 5631 goto wanted_comma; 5632 5633 inst.operands[i].reg = val; 5634 inst.operands[i].isreg = 1; 5635 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); 5636 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5637 inst.operands[i].isvec = 1; 5638 inst.operands[i].vectype = optype; 5639 inst.operands[i++].present = 1; 5640 5641 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5642 { 5643 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. 5644 Case 13: VMOV <Sd>, <Rm> */ 5645 inst.operands[i].reg = val; 5646 inst.operands[i].isreg = 1; 5647 inst.operands[i].present = 1; 5648 5649 if (rtype == REG_TYPE_NQ) 5650 { 5651 first_error (_("can't use Neon quad register here")); 5652 return FAIL; 5653 } 5654 else if (rtype != REG_TYPE_VFS) 5655 { 5656 i++; 5657 if (skip_past_comma (&ptr) == FAIL) 5658 goto wanted_comma; 5659 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5660 goto wanted_arm; 5661 inst.operands[i].reg = val; 5662 inst.operands[i].isreg = 1; 5663 inst.operands[i].present = 1; 5664 } 5665 } 5666 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, 5667 &optype)) != FAIL) 5668 { 5669 /* Case 0: VMOV<c><q> <Qd>, <Qm> 5670 Case 1: VMOV<c><q> <Dd>, <Dm> 5671 Case 8: VMOV.F32 <Sd>, <Sm> 5672 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ 5673 5674 inst.operands[i].reg = val; 5675 inst.operands[i].isreg = 1; 5676 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); 5677 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5678 inst.operands[i].isvec = 1; 5679 inst.operands[i].vectype = optype; 5680 inst.operands[i].present = 1; 5681 5682 if (skip_past_comma (&ptr) == SUCCESS) 5683 { 5684 /* Case 15. */ 5685 i++; 5686 5687 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5688 goto wanted_arm; 5689 5690 inst.operands[i].reg = val; 5691 inst.operands[i].isreg = 1; 5692 inst.operands[i++].present = 1; 5693 5694 if (skip_past_comma (&ptr) == FAIL) 5695 goto wanted_comma; 5696 5697 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5698 goto wanted_arm; 5699 5700 inst.operands[i].reg = val; 5701 inst.operands[i].isreg = 1; 5702 inst.operands[i++].present = 1; 5703 } 5704 } 5705 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) 5706 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> 5707 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> 5708 Case 10: VMOV.F32 <Sd>, #<imm> 5709 Case 11: VMOV.F64 <Dd>, #<imm> */ 5710 inst.operands[i].immisfloat = 1; 5711 else if (parse_big_immediate (&ptr, i) == SUCCESS) 5712 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> 5713 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ 5714 ; 5715 else 5716 { 5717 first_error (_("expected <Rm> or <Dm> or <Qm> operand")); 5718 return FAIL; 5719 } 5720 } 5721 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5722 { 5723 /* Cases 6, 7. */ 5724 inst.operands[i].reg = val; 5725 inst.operands[i].isreg = 1; 5726 inst.operands[i++].present = 1; 5727 5728 if (skip_past_comma (&ptr) == FAIL) 5729 goto wanted_comma; 5730 5731 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) 5732 { 5733 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ 5734 inst.operands[i].reg = val; 5735 inst.operands[i].isscalar = 1; 5736 inst.operands[i].present = 1; 5737 inst.operands[i].vectype = optype; 5738 } 5739 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5740 { 5741 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ 5742 inst.operands[i].reg = val; 5743 inst.operands[i].isreg = 1; 5744 inst.operands[i++].present = 1; 5745 5746 if (skip_past_comma (&ptr) == FAIL) 5747 goto wanted_comma; 5748 5749 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) 5750 == FAIL) 5751 { 5752 first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); 5753 return FAIL; 5754 } 5755 5756 inst.operands[i].reg = val; 5757 inst.operands[i].isreg = 1; 5758 inst.operands[i].isvec = 1; 5759 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5760 inst.operands[i].vectype = optype; 5761 inst.operands[i].present = 1; 5762 5763 if (rtype == REG_TYPE_VFS) 5764 { 5765 /* Case 14. */ 5766 i++; 5767 if (skip_past_comma (&ptr) == FAIL) 5768 goto wanted_comma; 5769 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, 5770 &optype)) == FAIL) 5771 { 5772 first_error (_(reg_expected_msgs[REG_TYPE_VFS])); 5773 return FAIL; 5774 } 5775 inst.operands[i].reg = val; 5776 inst.operands[i].isreg = 1; 5777 inst.operands[i].isvec = 1; 5778 inst.operands[i].issingle = 1; 5779 inst.operands[i].vectype = optype; 5780 inst.operands[i].present = 1; 5781 } 5782 } 5783 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) 5784 != FAIL) 5785 { 5786 /* Case 13. */ 5787 inst.operands[i].reg = val; 5788 inst.operands[i].isreg = 1; 5789 inst.operands[i].isvec = 1; 5790 inst.operands[i].issingle = 1; 5791 inst.operands[i].vectype = optype; 5792 inst.operands[i++].present = 1; 5793 } 5794 } 5795 else 5796 { 5797 first_error (_("parse error")); 5798 return FAIL; 5799 } 5800 5801 /* Successfully parsed the operands. Update args. */ 5802 *which_operand = i; 5803 *str = ptr; 5804 return SUCCESS; 5805 5806 wanted_comma: 5807 first_error (_("expected comma")); 5808 return FAIL; 5809 5810 wanted_arm: 5811 first_error (_(reg_expected_msgs[REG_TYPE_RN])); 5812 return FAIL; 5813} 5814 5815/* Use this macro when the operand constraints are different 5816 for ARM and THUMB (e.g. ldrd). */ 5817#define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ 5818 ((arm_operand) | ((thumb_operand) << 16)) 5819 5820/* Matcher codes for parse_operands. */ 5821enum operand_parse_code 5822{ 5823 OP_stop, /* end of line */ 5824 5825 OP_RR, /* ARM register */ 5826 OP_RRnpc, /* ARM register, not r15 */ 5827 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ 5828 OP_RRnpcb, /* ARM register, not r15, in square brackets */ 5829 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback, 5830 optional trailing ! */ 5831 OP_RRw, /* ARM register, not r15, optional trailing ! */ 5832 OP_RCP, /* Coprocessor number */ 5833 OP_RCN, /* Coprocessor register */ 5834 OP_RF, /* FPA register */ 5835 OP_RVS, /* VFP single precision register */ 5836 OP_RVD, /* VFP double precision register (0..15) */ 5837 OP_RND, /* Neon double precision register (0..31) */ 5838 OP_RNQ, /* Neon quad precision register */ 5839 OP_RVSD, /* VFP single or double precision register */ 5840 OP_RNDQ, /* Neon double or quad precision register */ 5841 OP_RNSDQ, /* Neon single, double or quad precision register */ 5842 OP_RNSC, /* Neon scalar D[X] */ 5843 OP_RVC, /* VFP control register */ 5844 OP_RMF, /* Maverick F register */ 5845 OP_RMD, /* Maverick D register */ 5846 OP_RMFX, /* Maverick FX register */ 5847 OP_RMDX, /* Maverick DX register */ 5848 OP_RMAX, /* Maverick AX register */ 5849 OP_RMDS, /* Maverick DSPSC register */ 5850 OP_RIWR, /* iWMMXt wR register */ 5851 OP_RIWC, /* iWMMXt wC register */ 5852 OP_RIWG, /* iWMMXt wCG register */ 5853 OP_RXA, /* XScale accumulator register */ 5854 5855 OP_REGLST, /* ARM register list */ 5856 OP_VRSLST, /* VFP single-precision register list */ 5857 OP_VRDLST, /* VFP double-precision register list */ 5858 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ 5859 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ 5860 OP_NSTRLST, /* Neon element/structure list */ 5861 5862 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ 5863 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ 5864 OP_RR_RNSC, /* ARM reg or Neon scalar. */ 5865 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ 5866 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ 5867 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ 5868 OP_VMOV, /* Neon VMOV operands. */ 5869 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ 5870 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ 5871 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ 5872 5873 OP_I0, /* immediate zero */ 5874 OP_I7, /* immediate value 0 .. 7 */ 5875 OP_I15, /* 0 .. 15 */ 5876 OP_I16, /* 1 .. 16 */ 5877 OP_I16z, /* 0 .. 16 */ 5878 OP_I31, /* 0 .. 31 */ 5879 OP_I31w, /* 0 .. 31, optional trailing ! */ 5880 OP_I32, /* 1 .. 32 */ 5881 OP_I32z, /* 0 .. 32 */ 5882 OP_I63, /* 0 .. 63 */ 5883 OP_I63s, /* -64 .. 63 */ 5884 OP_I64, /* 1 .. 64 */ 5885 OP_I64z, /* 0 .. 64 */ 5886 OP_I255, /* 0 .. 255 */ 5887 5888 OP_I4b, /* immediate, prefix optional, 1 .. 4 */ 5889 OP_I7b, /* 0 .. 7 */ 5890 OP_I15b, /* 0 .. 15 */ 5891 OP_I31b, /* 0 .. 31 */ 5892 5893 OP_SH, /* shifter operand */ 5894 OP_SHG, /* shifter operand with possible group relocation */ 5895 OP_ADDR, /* Memory address expression (any mode) */ 5896 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ 5897 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ 5898 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ 5899 OP_EXP, /* arbitrary expression */ 5900 OP_EXPi, /* same, with optional immediate prefix */ 5901 OP_EXPr, /* same, with optional relocation suffix */ 5902 OP_HALF, /* 0 .. 65535 or low/high reloc. */ 5903 5904 OP_CPSF, /* CPS flags */ 5905 OP_ENDI, /* Endianness specifier */ 5906 OP_PSR, /* CPSR/SPSR mask for msr */ 5907 OP_COND, /* conditional code */ 5908 OP_TB, /* Table branch. */ 5909 5910 OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */ 5911 OP_APSR_RR, /* ARM register or "APSR_nzcv". */ 5912 5913 OP_RRnpc_I0, /* ARM register or literal 0 */ 5914 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ 5915 OP_RR_EXi, /* ARM register or expression with imm prefix */ 5916 OP_RF_IF, /* FPA register or immediate */ 5917 OP_RIWR_RIWC, /* iWMMXt R or C reg */ 5918 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ 5919 5920 /* Optional operands. */ 5921 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ 5922 OP_oI31b, /* 0 .. 31 */ 5923 OP_oI32b, /* 1 .. 32 */ 5924 OP_oIffffb, /* 0 .. 65535 */ 5925 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ 5926 5927 OP_oRR, /* ARM register */ 5928 OP_oRRnpc, /* ARM register, not the PC */ 5929 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ 5930 OP_oRRw, /* ARM register, not r15, optional trailing ! */ 5931 OP_oRND, /* Optional Neon double precision register */ 5932 OP_oRNQ, /* Optional Neon quad precision register */ 5933 OP_oRNDQ, /* Optional Neon double or quad precision register */ 5934 OP_oRNSDQ, /* Optional single, double or quad precision vector register */ 5935 OP_oSHll, /* LSL immediate */ 5936 OP_oSHar, /* ASR immediate */ 5937 OP_oSHllar, /* LSL or ASR immediate */ 5938 OP_oROR, /* ROR 0/8/16/24 */ 5939 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */ 5940 5941 /* Some pre-defined mixed (ARM/THUMB) operands. */ 5942 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), 5943 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), 5944 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), 5945 5946 OP_FIRST_OPTIONAL = OP_oI7b 5947}; 5948 5949/* Generic instruction operand parser. This does no encoding and no 5950 semantic validation; it merely squirrels values away in the inst 5951 structure. Returns SUCCESS or FAIL depending on whether the 5952 specified grammar matched. */ 5953static int 5954parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) 5955{ 5956 unsigned const int *upat = pattern; 5957 char *backtrack_pos = 0; 5958 const char *backtrack_error = 0; 5959 int i, val, backtrack_index = 0; 5960 enum arm_reg_type rtype; 5961 parse_operand_result result; 5962 unsigned int op_parse_code; 5963 5964#define po_char_or_fail(chr) \ 5965 do \ 5966 { \ 5967 if (skip_past_char (&str, chr) == FAIL) \ 5968 goto bad_args; \ 5969 } \ 5970 while (0) 5971 5972#define po_reg_or_fail(regtype) \ 5973 do \ 5974 { \ 5975 val = arm_typed_reg_parse (& str, regtype, & rtype, \ 5976 & inst.operands[i].vectype); \ 5977 if (val == FAIL) \ 5978 { \ 5979 first_error (_(reg_expected_msgs[regtype])); \ 5980 goto failure; \ 5981 } \ 5982 inst.operands[i].reg = val; \ 5983 inst.operands[i].isreg = 1; \ 5984 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ 5985 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ 5986 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ 5987 || rtype == REG_TYPE_VFD \ 5988 || rtype == REG_TYPE_NQ); \ 5989 } \ 5990 while (0) 5991 5992#define po_reg_or_goto(regtype, label) \ 5993 do \ 5994 { \ 5995 val = arm_typed_reg_parse (& str, regtype, & rtype, \ 5996 & inst.operands[i].vectype); \ 5997 if (val == FAIL) \ 5998 goto label; \ 5999 \ 6000 inst.operands[i].reg = val; \ 6001 inst.operands[i].isreg = 1; \ 6002 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ 6003 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ 6004 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ 6005 || rtype == REG_TYPE_VFD \ 6006 || rtype == REG_TYPE_NQ); \ 6007 } \ 6008 while (0) 6009 6010#define po_imm_or_fail(min, max, popt) \ 6011 do \ 6012 { \ 6013 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ 6014 goto failure; \ 6015 inst.operands[i].imm = val; \ 6016 } \ 6017 while (0) 6018 6019#define po_scalar_or_goto(elsz, label) \ 6020 do \ 6021 { \ 6022 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \ 6023 if (val == FAIL) \ 6024 goto label; \ 6025 inst.operands[i].reg = val; \ 6026 inst.operands[i].isscalar = 1; \ 6027 } \ 6028 while (0) 6029 6030#define po_misc_or_fail(expr) \ 6031 do \ 6032 { \ 6033 if (expr) \ 6034 goto failure; \ 6035 } \ 6036 while (0) 6037 6038#define po_misc_or_fail_no_backtrack(expr) \ 6039 do \ 6040 { \ 6041 result = expr; \ 6042 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ 6043 backtrack_pos = 0; \ 6044 if (result != PARSE_OPERAND_SUCCESS) \ 6045 goto failure; \ 6046 } \ 6047 while (0) 6048 6049#define po_barrier_or_imm(str) \ 6050 do \ 6051 { \ 6052 val = parse_barrier (&str); \ 6053 if (val == FAIL) \ 6054 { \ 6055 if (ISALPHA (*str)) \ 6056 goto failure; \ 6057 else \ 6058 goto immediate; \ 6059 } \ 6060 else \ 6061 { \ 6062 if ((inst.instruction & 0xf0) == 0x60 \ 6063 && val != 0xf) \ 6064 { \ 6065 /* ISB can only take SY as an option. */ \ 6066 inst.error = _("invalid barrier type"); \ 6067 goto failure; \ 6068 } \ 6069 } \ 6070 } \ 6071 while (0) 6072 6073 skip_whitespace (str); 6074 6075 for (i = 0; upat[i] != OP_stop; i++) 6076 { 6077 op_parse_code = upat[i]; 6078 if (op_parse_code >= 1<<16) 6079 op_parse_code = thumb ? (op_parse_code >> 16) 6080 : (op_parse_code & ((1<<16)-1)); 6081 6082 if (op_parse_code >= OP_FIRST_OPTIONAL) 6083 { 6084 /* Remember where we are in case we need to backtrack. */ 6085 gas_assert (!backtrack_pos); 6086 backtrack_pos = str; 6087 backtrack_error = inst.error; 6088 backtrack_index = i; 6089 } 6090 6091 if (i > 0 && (i > 1 || inst.operands[0].present)) 6092 po_char_or_fail (','); 6093 6094 switch (op_parse_code) 6095 { 6096 /* Registers */ 6097 case OP_oRRnpc: 6098 case OP_oRRnpcsp: 6099 case OP_RRnpc: 6100 case OP_RRnpcsp: 6101 case OP_oRR: 6102 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; 6103 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; 6104 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; 6105 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; 6106 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; 6107 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; 6108 case OP_oRND: 6109 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; 6110 case OP_RVC: 6111 po_reg_or_goto (REG_TYPE_VFC, coproc_reg); 6112 break; 6113 /* Also accept generic coprocessor regs for unknown registers. */ 6114 coproc_reg: 6115 po_reg_or_fail (REG_TYPE_CN); 6116 break; 6117 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; 6118 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; 6119 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; 6120 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; 6121 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; 6122 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; 6123 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; 6124 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; 6125 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; 6126 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; 6127 case OP_oRNQ: 6128 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; 6129 case OP_oRNDQ: 6130 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; 6131 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; 6132 case OP_oRNSDQ: 6133 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; 6134 6135 /* Neon scalar. Using an element size of 8 means that some invalid 6136 scalars are accepted here, so deal with those in later code. */ 6137 case OP_RNSC: po_scalar_or_goto (8, failure); break; 6138 6139 case OP_RNDQ_I0: 6140 { 6141 po_reg_or_goto (REG_TYPE_NDQ, try_imm0); 6142 break; 6143 try_imm0: 6144 po_imm_or_fail (0, 0, TRUE); 6145 } 6146 break; 6147 6148 case OP_RVSD_I0: 6149 po_reg_or_goto (REG_TYPE_VFSD, try_imm0); 6150 break; 6151 6152 case OP_RR_RNSC: 6153 { 6154 po_scalar_or_goto (8, try_rr); 6155 break; 6156 try_rr: 6157 po_reg_or_fail (REG_TYPE_RN); 6158 } 6159 break; 6160 6161 case OP_RNSDQ_RNSC: 6162 { 6163 po_scalar_or_goto (8, try_nsdq); 6164 break; 6165 try_nsdq: 6166 po_reg_or_fail (REG_TYPE_NSDQ); 6167 } 6168 break; 6169 6170 case OP_RNDQ_RNSC: 6171 { 6172 po_scalar_or_goto (8, try_ndq); 6173 break; 6174 try_ndq: 6175 po_reg_or_fail (REG_TYPE_NDQ); 6176 } 6177 break; 6178 6179 case OP_RND_RNSC: 6180 { 6181 po_scalar_or_goto (8, try_vfd); 6182 break; 6183 try_vfd: 6184 po_reg_or_fail (REG_TYPE_VFD); 6185 } 6186 break; 6187 6188 case OP_VMOV: 6189 /* WARNING: parse_neon_mov can move the operand counter, i. If we're 6190 not careful then bad things might happen. */ 6191 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); 6192 break; 6193 6194 case OP_RNDQ_Ibig: 6195 { 6196 po_reg_or_goto (REG_TYPE_NDQ, try_immbig); 6197 break; 6198 try_immbig: 6199 /* There's a possibility of getting a 64-bit immediate here, so 6200 we need special handling. */ 6201 if (parse_big_immediate (&str, i) == FAIL) 6202 { 6203 inst.error = _("immediate value is out of range"); 6204 goto failure; 6205 } 6206 } 6207 break; 6208 6209 case OP_RNDQ_I63b: 6210 { 6211 po_reg_or_goto (REG_TYPE_NDQ, try_shimm); 6212 break; 6213 try_shimm: 6214 po_imm_or_fail (0, 63, TRUE); 6215 } 6216 break; 6217 6218 case OP_RRnpcb: 6219 po_char_or_fail ('['); 6220 po_reg_or_fail (REG_TYPE_RN); 6221 po_char_or_fail (']'); 6222 break; 6223 6224 case OP_RRnpctw: 6225 case OP_RRw: 6226 case OP_oRRw: 6227 po_reg_or_fail (REG_TYPE_RN); 6228 if (skip_past_char (&str, '!') == SUCCESS) 6229 inst.operands[i].writeback = 1; 6230 break; 6231 6232 /* Immediates */ 6233 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; 6234 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; 6235 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; 6236 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; 6237 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; 6238 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; 6239 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; 6240 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; 6241 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; 6242 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; 6243 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; 6244 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; 6245 6246 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; 6247 case OP_oI7b: 6248 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; 6249 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; 6250 case OP_oI31b: 6251 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; 6252 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; 6253 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; 6254 6255 /* Immediate variants */ 6256 case OP_oI255c: 6257 po_char_or_fail ('{'); 6258 po_imm_or_fail (0, 255, TRUE); 6259 po_char_or_fail ('}'); 6260 break; 6261 6262 case OP_I31w: 6263 /* The expression parser chokes on a trailing !, so we have 6264 to find it first and zap it. */ 6265 { 6266 char *s = str; 6267 while (*s && *s != ',') 6268 s++; 6269 if (s[-1] == '!') 6270 { 6271 s[-1] = '\0'; 6272 inst.operands[i].writeback = 1; 6273 } 6274 po_imm_or_fail (0, 31, TRUE); 6275 if (str == s - 1) 6276 str = s; 6277 } 6278 break; 6279 6280 /* Expressions */ 6281 case OP_EXPi: EXPi: 6282 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 6283 GE_OPT_PREFIX)); 6284 break; 6285 6286 case OP_EXP: 6287 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 6288 GE_NO_PREFIX)); 6289 break; 6290 6291 case OP_EXPr: EXPr: 6292 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 6293 GE_NO_PREFIX)); 6294 if (inst.reloc.exp.X_op == O_symbol) 6295 { 6296 val = parse_reloc (&str); 6297 if (val == -1) 6298 { 6299 inst.error = _("unrecognized relocation suffix"); 6300 goto failure; 6301 } 6302 else if (val != BFD_RELOC_UNUSED) 6303 { 6304 inst.operands[i].imm = val; 6305 inst.operands[i].hasreloc = 1; 6306 } 6307 } 6308 break; 6309 6310 /* Operand for MOVW or MOVT. */ 6311 case OP_HALF: 6312 po_misc_or_fail (parse_half (&str)); 6313 break; 6314 6315 /* Register or expression. */ 6316 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; 6317 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; 6318 6319 /* Register or immediate. */ 6320 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; 6321 I0: po_imm_or_fail (0, 0, FALSE); break; 6322 6323 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; 6324 IF: 6325 if (!is_immediate_prefix (*str)) 6326 goto bad_args; 6327 str++; 6328 val = parse_fpa_immediate (&str); 6329 if (val == FAIL) 6330 goto failure; 6331 /* FPA immediates are encoded as registers 8-15. 6332 parse_fpa_immediate has already applied the offset. */ 6333 inst.operands[i].reg = val; 6334 inst.operands[i].isreg = 1; 6335 break; 6336 6337 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; 6338 I32z: po_imm_or_fail (0, 32, FALSE); break; 6339 6340 /* Two kinds of register. */ 6341 case OP_RIWR_RIWC: 6342 { 6343 struct reg_entry *rege = arm_reg_parse_multi (&str); 6344 if (!rege 6345 || (rege->type != REG_TYPE_MMXWR 6346 && rege->type != REG_TYPE_MMXWC 6347 && rege->type != REG_TYPE_MMXWCG)) 6348 { 6349 inst.error = _("iWMMXt data or control register expected"); 6350 goto failure; 6351 } 6352 inst.operands[i].reg = rege->number; 6353 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); 6354 } 6355 break; 6356 6357 case OP_RIWC_RIWG: 6358 { 6359 struct reg_entry *rege = arm_reg_parse_multi (&str); 6360 if (!rege 6361 || (rege->type != REG_TYPE_MMXWC 6362 && rege->type != REG_TYPE_MMXWCG)) 6363 { 6364 inst.error = _("iWMMXt control register expected"); 6365 goto failure; 6366 } 6367 inst.operands[i].reg = rege->number; 6368 inst.operands[i].isreg = 1; 6369 } 6370 break; 6371 6372 /* Misc */ 6373 case OP_CPSF: val = parse_cps_flags (&str); break; 6374 case OP_ENDI: val = parse_endian_specifier (&str); break; 6375 case OP_oROR: val = parse_ror (&str); break; 6376 case OP_PSR: val = parse_psr (&str); break; 6377 case OP_COND: val = parse_cond (&str); break; 6378 case OP_oBARRIER_I15: 6379 po_barrier_or_imm (str); break; 6380 immediate: 6381 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL) 6382 goto failure; 6383 break; 6384 6385 case OP_RVC_PSR: 6386 po_reg_or_goto (REG_TYPE_VFC, try_banked_reg); 6387 inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */ 6388 break; 6389 try_banked_reg: 6390 po_reg_or_goto (REG_TYPE_RNB, try_psr); 6391 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt)) 6392 { 6393 inst.error = _("Banked registers are not available with this " 6394 "architecture."); 6395 goto failure; 6396 } 6397 break; 6398 try_psr: 6399 val = parse_psr (&str); 6400 break; 6401 6402 case OP_APSR_RR: 6403 po_reg_or_goto (REG_TYPE_RN, try_apsr); 6404 break; 6405 try_apsr: 6406 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS 6407 instruction). */ 6408 if (strncasecmp (str, "APSR_", 5) == 0) 6409 { 6410 unsigned found = 0; 6411 str += 5; 6412 while (found < 15) 6413 switch (*str++) 6414 { 6415 case 'c': found = (found & 1) ? 16 : found | 1; break; 6416 case 'n': found = (found & 2) ? 16 : found | 2; break; 6417 case 'z': found = (found & 4) ? 16 : found | 4; break; 6418 case 'v': found = (found & 8) ? 16 : found | 8; break; 6419 default: found = 16; 6420 } 6421 if (found != 15) 6422 goto failure; 6423 inst.operands[i].isvec = 1; 6424 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ 6425 inst.operands[i].reg = REG_PC; 6426 } 6427 else 6428 goto failure; 6429 break; 6430 6431 case OP_TB: 6432 po_misc_or_fail (parse_tb (&str)); 6433 break; 6434 6435 /* Register lists. */ 6436 case OP_REGLST: 6437 val = parse_reg_list (&str); 6438 if (*str == '^') 6439 { 6440 inst.operands[1].writeback = 1; 6441 str++; 6442 } 6443 break; 6444 6445 case OP_VRSLST: 6446 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); 6447 break; 6448 6449 case OP_VRDLST: 6450 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); 6451 break; 6452 6453 case OP_VRSDLST: 6454 /* Allow Q registers too. */ 6455 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 6456 REGLIST_NEON_D); 6457 if (val == FAIL) 6458 { 6459 inst.error = NULL; 6460 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 6461 REGLIST_VFP_S); 6462 inst.operands[i].issingle = 1; 6463 } 6464 break; 6465 6466 case OP_NRDLST: 6467 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 6468 REGLIST_NEON_D); 6469 break; 6470 6471 case OP_NSTRLST: 6472 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, 6473 &inst.operands[i].vectype); 6474 break; 6475 6476 /* Addressing modes */ 6477 case OP_ADDR: 6478 po_misc_or_fail (parse_address (&str, i)); 6479 break; 6480 6481 case OP_ADDRGLDR: 6482 po_misc_or_fail_no_backtrack ( 6483 parse_address_group_reloc (&str, i, GROUP_LDR)); 6484 break; 6485 6486 case OP_ADDRGLDRS: 6487 po_misc_or_fail_no_backtrack ( 6488 parse_address_group_reloc (&str, i, GROUP_LDRS)); 6489 break; 6490 6491 case OP_ADDRGLDC: 6492 po_misc_or_fail_no_backtrack ( 6493 parse_address_group_reloc (&str, i, GROUP_LDC)); 6494 break; 6495 6496 case OP_SH: 6497 po_misc_or_fail (parse_shifter_operand (&str, i)); 6498 break; 6499 6500 case OP_SHG: 6501 po_misc_or_fail_no_backtrack ( 6502 parse_shifter_operand_group_reloc (&str, i)); 6503 break; 6504 6505 case OP_oSHll: 6506 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); 6507 break; 6508 6509 case OP_oSHar: 6510 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); 6511 break; 6512 6513 case OP_oSHllar: 6514 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); 6515 break; 6516 6517 default: 6518 as_fatal (_("unhandled operand code %d"), op_parse_code); 6519 } 6520 6521 /* Various value-based sanity checks and shared operations. We 6522 do not signal immediate failures for the register constraints; 6523 this allows a syntax error to take precedence. */ 6524 switch (op_parse_code) 6525 { 6526 case OP_oRRnpc: 6527 case OP_RRnpc: 6528 case OP_RRnpcb: 6529 case OP_RRw: 6530 case OP_oRRw: 6531 case OP_RRnpc_I0: 6532 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) 6533 inst.error = BAD_PC; 6534 break; 6535 6536 case OP_oRRnpcsp: 6537 case OP_RRnpcsp: 6538 if (inst.operands[i].isreg) 6539 { 6540 if (inst.operands[i].reg == REG_PC) 6541 inst.error = BAD_PC; 6542 else if (inst.operands[i].reg == REG_SP) 6543 inst.error = BAD_SP; 6544 } 6545 break; 6546 6547 case OP_RRnpctw: 6548 if (inst.operands[i].isreg 6549 && inst.operands[i].reg == REG_PC 6550 && (inst.operands[i].writeback || thumb)) 6551 inst.error = BAD_PC; 6552 break; 6553 6554 case OP_CPSF: 6555 case OP_ENDI: 6556 case OP_oROR: 6557 case OP_PSR: 6558 case OP_RVC_PSR: 6559 case OP_COND: 6560 case OP_oBARRIER_I15: 6561 case OP_REGLST: 6562 case OP_VRSLST: 6563 case OP_VRDLST: 6564 case OP_VRSDLST: 6565 case OP_NRDLST: 6566 case OP_NSTRLST: 6567 if (val == FAIL) 6568 goto failure; 6569 inst.operands[i].imm = val; 6570 break; 6571 6572 default: 6573 break; 6574 } 6575 6576 /* If we get here, this operand was successfully parsed. */ 6577 inst.operands[i].present = 1; 6578 continue; 6579 6580 bad_args: 6581 inst.error = BAD_ARGS; 6582 6583 failure: 6584 if (!backtrack_pos) 6585 { 6586 /* The parse routine should already have set inst.error, but set a 6587 default here just in case. */ 6588 if (!inst.error) 6589 inst.error = _("syntax error"); 6590 return FAIL; 6591 } 6592 6593 /* Do not backtrack over a trailing optional argument that 6594 absorbed some text. We will only fail again, with the 6595 'garbage following instruction' error message, which is 6596 probably less helpful than the current one. */ 6597 if (backtrack_index == i && backtrack_pos != str 6598 && upat[i+1] == OP_stop) 6599 { 6600 if (!inst.error) 6601 inst.error = _("syntax error"); 6602 return FAIL; 6603 } 6604 6605 /* Try again, skipping the optional argument at backtrack_pos. */ 6606 str = backtrack_pos; 6607 inst.error = backtrack_error; 6608 inst.operands[backtrack_index].present = 0; 6609 i = backtrack_index; 6610 backtrack_pos = 0; 6611 } 6612 6613 /* Check that we have parsed all the arguments. */ 6614 if (*str != '\0' && !inst.error) 6615 inst.error = _("garbage following instruction"); 6616 6617 return inst.error ? FAIL : SUCCESS; 6618} 6619 6620#undef po_char_or_fail 6621#undef po_reg_or_fail 6622#undef po_reg_or_goto 6623#undef po_imm_or_fail 6624#undef po_scalar_or_fail 6625#undef po_barrier_or_imm 6626 6627/* Shorthand macro for instruction encoding functions issuing errors. */ 6628#define constraint(expr, err) \ 6629 do \ 6630 { \ 6631 if (expr) \ 6632 { \ 6633 inst.error = err; \ 6634 return; \ 6635 } \ 6636 } \ 6637 while (0) 6638 6639/* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 6640 instructions are unpredictable if these registers are used. This 6641 is the BadReg predicate in ARM's Thumb-2 documentation. */ 6642#define reject_bad_reg(reg) \ 6643 do \ 6644 if (reg == REG_SP || reg == REG_PC) \ 6645 { \ 6646 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ 6647 return; \ 6648 } \ 6649 while (0) 6650 6651/* If REG is R13 (the stack pointer), warn that its use is 6652 deprecated. */ 6653#define warn_deprecated_sp(reg) \ 6654 do \ 6655 if (warn_on_deprecated && reg == REG_SP) \ 6656 as_warn (_("use of r13 is deprecated")); \ 6657 while (0) 6658 6659/* Functions for operand encoding. ARM, then Thumb. */ 6660 6661#define rotate_left(v, n) (v << n | v >> (32 - n)) 6662 6663/* If VAL can be encoded in the immediate field of an ARM instruction, 6664 return the encoded form. Otherwise, return FAIL. */ 6665 6666static unsigned int 6667encode_arm_immediate (unsigned int val) 6668{ 6669 unsigned int a, i; 6670 6671 for (i = 0; i < 32; i += 2) 6672 if ((a = rotate_left (val, i)) <= 0xff) 6673 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ 6674 6675 return FAIL; 6676} 6677 6678/* If VAL can be encoded in the immediate field of a Thumb32 instruction, 6679 return the encoded form. Otherwise, return FAIL. */ 6680static unsigned int 6681encode_thumb32_immediate (unsigned int val) 6682{ 6683 unsigned int a, i; 6684 6685 if (val <= 0xff) 6686 return val; 6687 6688 for (i = 1; i <= 24; i++) 6689 { 6690 a = val >> i; 6691 if ((val & ~(0xff << i)) == 0) 6692 return ((val >> i) & 0x7f) | ((32 - i) << 7); 6693 } 6694 6695 a = val & 0xff; 6696 if (val == ((a << 16) | a)) 6697 return 0x100 | a; 6698 if (val == ((a << 24) | (a << 16) | (a << 8) | a)) 6699 return 0x300 | a; 6700 6701 a = val & 0xff00; 6702 if (val == ((a << 16) | a)) 6703 return 0x200 | (a >> 8); 6704 6705 return FAIL; 6706} 6707/* Encode a VFP SP or DP register number into inst.instruction. */ 6708 6709static void 6710encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) 6711{ 6712 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) 6713 && reg > 15) 6714 { 6715 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) 6716 { 6717 if (thumb_mode) 6718 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 6719 fpu_vfp_ext_d32); 6720 else 6721 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 6722 fpu_vfp_ext_d32); 6723 } 6724 else 6725 { 6726 first_error (_("D register out of range for selected VFP version")); 6727 return; 6728 } 6729 } 6730 6731 switch (pos) 6732 { 6733 case VFP_REG_Sd: 6734 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); 6735 break; 6736 6737 case VFP_REG_Sn: 6738 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); 6739 break; 6740 6741 case VFP_REG_Sm: 6742 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); 6743 break; 6744 6745 case VFP_REG_Dd: 6746 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); 6747 break; 6748 6749 case VFP_REG_Dn: 6750 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); 6751 break; 6752 6753 case VFP_REG_Dm: 6754 inst.instruction |= (reg & 15) | ((reg >> 4) << 5); 6755 break; 6756 6757 default: 6758 abort (); 6759 } 6760} 6761 6762/* Encode a <shift> in an ARM-format instruction. The immediate, 6763 if any, is handled by md_apply_fix. */ 6764static void 6765encode_arm_shift (int i) 6766{ 6767 if (inst.operands[i].shift_kind == SHIFT_RRX) 6768 inst.instruction |= SHIFT_ROR << 5; 6769 else 6770 { 6771 inst.instruction |= inst.operands[i].shift_kind << 5; 6772 if (inst.operands[i].immisreg) 6773 { 6774 inst.instruction |= SHIFT_BY_REG; 6775 inst.instruction |= inst.operands[i].imm << 8; 6776 } 6777 else 6778 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 6779 } 6780} 6781 6782static void 6783encode_arm_shifter_operand (int i) 6784{ 6785 if (inst.operands[i].isreg) 6786 { 6787 inst.instruction |= inst.operands[i].reg; 6788 encode_arm_shift (i); 6789 } 6790 else 6791 inst.instruction |= INST_IMMEDIATE; 6792} 6793 6794/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ 6795static void 6796encode_arm_addr_mode_common (int i, bfd_boolean is_t) 6797{ 6798 gas_assert (inst.operands[i].isreg); 6799 inst.instruction |= inst.operands[i].reg << 16; 6800 6801 if (inst.operands[i].preind) 6802 { 6803 if (is_t) 6804 { 6805 inst.error = _("instruction does not accept preindexed addressing"); 6806 return; 6807 } 6808 inst.instruction |= PRE_INDEX; 6809 if (inst.operands[i].writeback) 6810 inst.instruction |= WRITE_BACK; 6811 6812 } 6813 else if (inst.operands[i].postind) 6814 { 6815 gas_assert (inst.operands[i].writeback); 6816 if (is_t) 6817 inst.instruction |= WRITE_BACK; 6818 } 6819 else /* unindexed - only for coprocessor */ 6820 { 6821 inst.error = _("instruction does not accept unindexed addressing"); 6822 return; 6823 } 6824 6825 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) 6826 && (((inst.instruction & 0x000f0000) >> 16) 6827 == ((inst.instruction & 0x0000f000) >> 12))) 6828 as_warn ((inst.instruction & LOAD_BIT) 6829 ? _("destination register same as write-back base") 6830 : _("source register same as write-back base")); 6831} 6832 6833/* inst.operands[i] was set up by parse_address. Encode it into an 6834 ARM-format mode 2 load or store instruction. If is_t is true, 6835 reject forms that cannot be used with a T instruction (i.e. not 6836 post-indexed). */ 6837static void 6838encode_arm_addr_mode_2 (int i, bfd_boolean is_t) 6839{ 6840 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); 6841 6842 encode_arm_addr_mode_common (i, is_t); 6843 6844 if (inst.operands[i].immisreg) 6845 { 6846 constraint ((inst.operands[i].imm == REG_PC 6847 || (is_pc && inst.operands[i].writeback)), 6848 BAD_PC_ADDRESSING); 6849 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ 6850 inst.instruction |= inst.operands[i].imm; 6851 if (!inst.operands[i].negative) 6852 inst.instruction |= INDEX_UP; 6853 if (inst.operands[i].shifted) 6854 { 6855 if (inst.operands[i].shift_kind == SHIFT_RRX) 6856 inst.instruction |= SHIFT_ROR << 5; 6857 else 6858 { 6859 inst.instruction |= inst.operands[i].shift_kind << 5; 6860 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 6861 } 6862 } 6863 } 6864 else /* immediate offset in inst.reloc */ 6865 { 6866 if (is_pc && !inst.reloc.pc_rel) 6867 { 6868 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); 6869 6870 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt 6871 cannot use PC in addressing. 6872 PC cannot be used in writeback addressing, either. */ 6873 constraint ((is_t || inst.operands[i].writeback), 6874 BAD_PC_ADDRESSING); 6875 6876 /* Use of PC in str is deprecated for ARMv7. */ 6877 if (warn_on_deprecated 6878 && !is_load 6879 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) 6880 as_warn (_("use of PC in this instruction is deprecated")); 6881 } 6882 6883 if (inst.reloc.type == BFD_RELOC_UNUSED) 6884 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; 6885 } 6886} 6887 6888/* inst.operands[i] was set up by parse_address. Encode it into an 6889 ARM-format mode 3 load or store instruction. Reject forms that 6890 cannot be used with such instructions. If is_t is true, reject 6891 forms that cannot be used with a T instruction (i.e. not 6892 post-indexed). */ 6893static void 6894encode_arm_addr_mode_3 (int i, bfd_boolean is_t) 6895{ 6896 if (inst.operands[i].immisreg && inst.operands[i].shifted) 6897 { 6898 inst.error = _("instruction does not accept scaled register index"); 6899 return; 6900 } 6901 6902 encode_arm_addr_mode_common (i, is_t); 6903 6904 if (inst.operands[i].immisreg) 6905 { 6906 constraint ((inst.operands[i].imm == REG_PC 6907 || inst.operands[i].reg == REG_PC), 6908 BAD_PC_ADDRESSING); 6909 inst.instruction |= inst.operands[i].imm; 6910 if (!inst.operands[i].negative) 6911 inst.instruction |= INDEX_UP; 6912 } 6913 else /* immediate offset in inst.reloc */ 6914 { 6915 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel 6916 && inst.operands[i].writeback), 6917 BAD_PC_WRITEBACK); 6918 inst.instruction |= HWOFFSET_IMM; 6919 if (inst.reloc.type == BFD_RELOC_UNUSED) 6920 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; 6921 } 6922} 6923 6924/* inst.operands[i] was set up by parse_address. Encode it into an 6925 ARM-format instruction. Reject all forms which cannot be encoded 6926 into a coprocessor load/store instruction. If wb_ok is false, 6927 reject use of writeback; if unind_ok is false, reject use of 6928 unindexed addressing. If reloc_override is not 0, use it instead 6929 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one 6930 (in which case it is preserved). */ 6931 6932static int 6933encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) 6934{ 6935 inst.instruction |= inst.operands[i].reg << 16; 6936 6937 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); 6938 6939 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ 6940 { 6941 gas_assert (!inst.operands[i].writeback); 6942 if (!unind_ok) 6943 { 6944 inst.error = _("instruction does not support unindexed addressing"); 6945 return FAIL; 6946 } 6947 inst.instruction |= inst.operands[i].imm; 6948 inst.instruction |= INDEX_UP; 6949 return SUCCESS; 6950 } 6951 6952 if (inst.operands[i].preind) 6953 inst.instruction |= PRE_INDEX; 6954 6955 if (inst.operands[i].writeback) 6956 { 6957 if (inst.operands[i].reg == REG_PC) 6958 { 6959 inst.error = _("pc may not be used with write-back"); 6960 return FAIL; 6961 } 6962 if (!wb_ok) 6963 { 6964 inst.error = _("instruction does not support writeback"); 6965 return FAIL; 6966 } 6967 inst.instruction |= WRITE_BACK; 6968 } 6969 6970 if (reloc_override) 6971 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override; 6972 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC 6973 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) 6974 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) 6975 { 6976 if (thumb_mode) 6977 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; 6978 else 6979 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; 6980 } 6981 6982 return SUCCESS; 6983} 6984 6985/* inst.reloc.exp describes an "=expr" load pseudo-operation. 6986 Determine whether it can be performed with a move instruction; if 6987 it can, convert inst.instruction to that move instruction and 6988 return TRUE; if it can't, convert inst.instruction to a literal-pool 6989 load and return FALSE. If this is not a valid thing to do in the 6990 current context, set inst.error and return TRUE. 6991 6992 inst.operands[i] describes the destination register. */ 6993 6994static bfd_boolean 6995move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) 6996{ 6997 unsigned long tbit; 6998 6999 if (thumb_p) 7000 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; 7001 else 7002 tbit = LOAD_BIT; 7003 7004 if ((inst.instruction & tbit) == 0) 7005 { 7006 inst.error = _("invalid pseudo operation"); 7007 return TRUE; 7008 } 7009 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) 7010 { 7011 inst.error = _("constant expression expected"); 7012 return TRUE; 7013 } 7014 if (inst.reloc.exp.X_op == O_constant) 7015 { 7016 if (thumb_p) 7017 { 7018 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) 7019 { 7020 /* This can be done with a mov(1) instruction. */ 7021 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); 7022 inst.instruction |= inst.reloc.exp.X_add_number; 7023 return TRUE; 7024 } 7025 } 7026 else 7027 { 7028 int value = encode_arm_immediate (inst.reloc.exp.X_add_number); 7029 if (value != FAIL) 7030 { 7031 /* This can be done with a mov instruction. */ 7032 inst.instruction &= LITERAL_MASK; 7033 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); 7034 inst.instruction |= value & 0xfff; 7035 return TRUE; 7036 } 7037 7038 value = encode_arm_immediate (~inst.reloc.exp.X_add_number); 7039 if (value != FAIL) 7040 { 7041 /* This can be done with a mvn instruction. */ 7042 inst.instruction &= LITERAL_MASK; 7043 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); 7044 inst.instruction |= value & 0xfff; 7045 return TRUE; 7046 } 7047 } 7048 } 7049 7050 if (add_to_lit_pool () == FAIL) 7051 { 7052 inst.error = _("literal pool insertion failed"); 7053 return TRUE; 7054 } 7055 inst.operands[1].reg = REG_PC; 7056 inst.operands[1].isreg = 1; 7057 inst.operands[1].preind = 1; 7058 inst.reloc.pc_rel = 1; 7059 inst.reloc.type = (thumb_p 7060 ? BFD_RELOC_ARM_THUMB_OFFSET 7061 : (mode_3 7062 ? BFD_RELOC_ARM_HWLITERAL 7063 : BFD_RELOC_ARM_LITERAL)); 7064 return FALSE; 7065} 7066 7067/* Functions for instruction encoding, sorted by sub-architecture. 7068 First some generics; their names are taken from the conventional 7069 bit positions for register arguments in ARM format instructions. */ 7070 7071static void 7072do_noargs (void) 7073{ 7074} 7075 7076static void 7077do_rd (void) 7078{ 7079 inst.instruction |= inst.operands[0].reg << 12; 7080} 7081 7082static void 7083do_rd_rm (void) 7084{ 7085 inst.instruction |= inst.operands[0].reg << 12; 7086 inst.instruction |= inst.operands[1].reg; 7087} 7088 7089static void 7090do_rd_rn (void) 7091{ 7092 inst.instruction |= inst.operands[0].reg << 12; 7093 inst.instruction |= inst.operands[1].reg << 16; 7094} 7095 7096static void 7097do_rn_rd (void) 7098{ 7099 inst.instruction |= inst.operands[0].reg << 16; 7100 inst.instruction |= inst.operands[1].reg << 12; 7101} 7102 7103static void 7104do_rd_rm_rn (void) 7105{ 7106 unsigned Rn = inst.operands[2].reg; 7107 /* Enforce restrictions on SWP instruction. */ 7108 if ((inst.instruction & 0x0fbfffff) == 0x01000090) 7109 { 7110 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, 7111 _("Rn must not overlap other operands")); 7112 7113 /* SWP{b} is deprecated for ARMv6* and ARMv7. */ 7114 if (warn_on_deprecated 7115 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) 7116 as_warn (_("swp{b} use is deprecated for this architecture")); 7117 7118 } 7119 inst.instruction |= inst.operands[0].reg << 12; 7120 inst.instruction |= inst.operands[1].reg; 7121 inst.instruction |= Rn << 16; 7122} 7123 7124static void 7125do_rd_rn_rm (void) 7126{ 7127 inst.instruction |= inst.operands[0].reg << 12; 7128 inst.instruction |= inst.operands[1].reg << 16; 7129 inst.instruction |= inst.operands[2].reg; 7130} 7131 7132static void 7133do_rm_rd_rn (void) 7134{ 7135 constraint ((inst.operands[2].reg == REG_PC), BAD_PC); 7136 constraint (((inst.reloc.exp.X_op != O_constant 7137 && inst.reloc.exp.X_op != O_illegal) 7138 || inst.reloc.exp.X_add_number != 0), 7139 BAD_ADDR_MODE); 7140 inst.instruction |= inst.operands[0].reg; 7141 inst.instruction |= inst.operands[1].reg << 12; 7142 inst.instruction |= inst.operands[2].reg << 16; 7143} 7144 7145static void 7146do_imm0 (void) 7147{ 7148 inst.instruction |= inst.operands[0].imm; 7149} 7150 7151static void 7152do_rd_cpaddr (void) 7153{ 7154 inst.instruction |= inst.operands[0].reg << 12; 7155 encode_arm_cp_address (1, TRUE, TRUE, 0); 7156} 7157 7158/* ARM instructions, in alphabetical order by function name (except 7159 that wrapper functions appear immediately after the function they 7160 wrap). */ 7161 7162/* This is a pseudo-op of the form "adr rd, label" to be converted 7163 into a relative address of the form "add rd, pc, #label-.-8". */ 7164 7165static void 7166do_adr (void) 7167{ 7168 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 7169 7170 /* Frag hacking will turn this into a sub instruction if the offset turns 7171 out to be negative. */ 7172 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 7173 inst.reloc.pc_rel = 1; 7174 inst.reloc.exp.X_add_number -= 8; 7175} 7176 7177/* This is a pseudo-op of the form "adrl rd, label" to be converted 7178 into a relative address of the form: 7179 add rd, pc, #low(label-.-8)" 7180 add rd, rd, #high(label-.-8)" */ 7181 7182static void 7183do_adrl (void) 7184{ 7185 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 7186 7187 /* Frag hacking will turn this into a sub instruction if the offset turns 7188 out to be negative. */ 7189 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; 7190 inst.reloc.pc_rel = 1; 7191 inst.size = INSN_SIZE * 2; 7192 inst.reloc.exp.X_add_number -= 8; 7193} 7194 7195static void 7196do_arit (void) 7197{ 7198 if (!inst.operands[1].present) 7199 inst.operands[1].reg = inst.operands[0].reg; 7200 inst.instruction |= inst.operands[0].reg << 12; 7201 inst.instruction |= inst.operands[1].reg << 16; 7202 encode_arm_shifter_operand (2); 7203} 7204 7205static void 7206do_barrier (void) 7207{ 7208 if (inst.operands[0].present) 7209 { 7210 constraint ((inst.instruction & 0xf0) != 0x40 7211 && inst.operands[0].imm > 0xf 7212 && inst.operands[0].imm < 0x0, 7213 _("bad barrier type")); 7214 inst.instruction |= inst.operands[0].imm; 7215 } 7216 else 7217 inst.instruction |= 0xf; 7218} 7219 7220static void 7221do_bfc (void) 7222{ 7223 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; 7224 constraint (msb > 32, _("bit-field extends past end of register")); 7225 /* The instruction encoding stores the LSB and MSB, 7226 not the LSB and width. */ 7227 inst.instruction |= inst.operands[0].reg << 12; 7228 inst.instruction |= inst.operands[1].imm << 7; 7229 inst.instruction |= (msb - 1) << 16; 7230} 7231 7232static void 7233do_bfi (void) 7234{ 7235 unsigned int msb; 7236 7237 /* #0 in second position is alternative syntax for bfc, which is 7238 the same instruction but with REG_PC in the Rm field. */ 7239 if (!inst.operands[1].isreg) 7240 inst.operands[1].reg = REG_PC; 7241 7242 msb = inst.operands[2].imm + inst.operands[3].imm; 7243 constraint (msb > 32, _("bit-field extends past end of register")); 7244 /* The instruction encoding stores the LSB and MSB, 7245 not the LSB and width. */ 7246 inst.instruction |= inst.operands[0].reg << 12; 7247 inst.instruction |= inst.operands[1].reg; 7248 inst.instruction |= inst.operands[2].imm << 7; 7249 inst.instruction |= (msb - 1) << 16; 7250} 7251 7252static void 7253do_bfx (void) 7254{ 7255 constraint (inst.operands[2].imm + inst.operands[3].imm > 32, 7256 _("bit-field extends past end of register")); 7257 inst.instruction |= inst.operands[0].reg << 12; 7258 inst.instruction |= inst.operands[1].reg; 7259 inst.instruction |= inst.operands[2].imm << 7; 7260 inst.instruction |= (inst.operands[3].imm - 1) << 16; 7261} 7262 7263/* ARM V5 breakpoint instruction (argument parse) 7264 BKPT <16 bit unsigned immediate> 7265 Instruction is not conditional. 7266 The bit pattern given in insns[] has the COND_ALWAYS condition, 7267 and it is an error if the caller tried to override that. */ 7268 7269static void 7270do_bkpt (void) 7271{ 7272 /* Top 12 of 16 bits to bits 19:8. */ 7273 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; 7274 7275 /* Bottom 4 of 16 bits to bits 3:0. */ 7276 inst.instruction |= inst.operands[0].imm & 0xf; 7277} 7278 7279static void 7280encode_branch (int default_reloc) 7281{ 7282 if (inst.operands[0].hasreloc) 7283 { 7284 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, 7285 _("the only suffix valid here is '(plt)'")); 7286 inst.reloc.type = BFD_RELOC_ARM_PLT32; 7287 } 7288 else 7289 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc; 7290 inst.reloc.pc_rel = 1; 7291} 7292 7293static void 7294do_branch (void) 7295{ 7296#ifdef OBJ_ELF 7297 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 7298 encode_branch (BFD_RELOC_ARM_PCREL_JUMP); 7299 else 7300#endif 7301 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); 7302} 7303 7304static void 7305do_bl (void) 7306{ 7307#ifdef OBJ_ELF 7308 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 7309 { 7310 if (inst.cond == COND_ALWAYS) 7311 encode_branch (BFD_RELOC_ARM_PCREL_CALL); 7312 else 7313 encode_branch (BFD_RELOC_ARM_PCREL_JUMP); 7314 } 7315 else 7316#endif 7317 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); 7318} 7319 7320/* ARM V5 branch-link-exchange instruction (argument parse) 7321 BLX <target_addr> ie BLX(1) 7322 BLX{<condition>} <Rm> ie BLX(2) 7323 Unfortunately, there are two different opcodes for this mnemonic. 7324 So, the insns[].value is not used, and the code here zaps values 7325 into inst.instruction. 7326 Also, the <target_addr> can be 25 bits, hence has its own reloc. */ 7327 7328static void 7329do_blx (void) 7330{ 7331 if (inst.operands[0].isreg) 7332 { 7333 /* Arg is a register; the opcode provided by insns[] is correct. 7334 It is not illegal to do "blx pc", just useless. */ 7335 if (inst.operands[0].reg == REG_PC) 7336 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); 7337 7338 inst.instruction |= inst.operands[0].reg; 7339 } 7340 else 7341 { 7342 /* Arg is an address; this instruction cannot be executed 7343 conditionally, and the opcode must be adjusted. 7344 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end 7345 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ 7346 constraint (inst.cond != COND_ALWAYS, BAD_COND); 7347 inst.instruction = 0xfa000000; 7348 encode_branch (BFD_RELOC_ARM_PCREL_BLX); 7349 } 7350} 7351 7352static void 7353do_bx (void) 7354{ 7355 bfd_boolean want_reloc; 7356 7357 if (inst.operands[0].reg == REG_PC) 7358 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); 7359 7360 inst.instruction |= inst.operands[0].reg; 7361 /* Output R_ARM_V4BX relocations if is an EABI object that looks like 7362 it is for ARMv4t or earlier. */ 7363 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); 7364 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5)) 7365 want_reloc = TRUE; 7366 7367#ifdef OBJ_ELF 7368 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) 7369#endif 7370 want_reloc = FALSE; 7371 7372 if (want_reloc) 7373 inst.reloc.type = BFD_RELOC_ARM_V4BX; 7374} 7375 7376 7377/* ARM v5TEJ. Jump to Jazelle code. */ 7378 7379static void 7380do_bxj (void) 7381{ 7382 if (inst.operands[0].reg == REG_PC) 7383 as_tsktsk (_("use of r15 in bxj is not really useful")); 7384 7385 inst.instruction |= inst.operands[0].reg; 7386} 7387 7388/* Co-processor data operation: 7389 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} 7390 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ 7391static void 7392do_cdp (void) 7393{ 7394 inst.instruction |= inst.operands[0].reg << 8; 7395 inst.instruction |= inst.operands[1].imm << 20; 7396 inst.instruction |= inst.operands[2].reg << 12; 7397 inst.instruction |= inst.operands[3].reg << 16; 7398 inst.instruction |= inst.operands[4].reg; 7399 inst.instruction |= inst.operands[5].imm << 5; 7400} 7401 7402static void 7403do_cmp (void) 7404{ 7405 inst.instruction |= inst.operands[0].reg << 16; 7406 encode_arm_shifter_operand (1); 7407} 7408 7409/* Transfer between coprocessor and ARM registers. 7410 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} 7411 MRC2 7412 MCR{cond} 7413 MCR2 7414 7415 No special properties. */ 7416 7417static void 7418do_co_reg (void) 7419{ 7420 unsigned Rd; 7421 7422 Rd = inst.operands[2].reg; 7423 if (thumb_mode) 7424 { 7425 if (inst.instruction == 0xee000010 7426 || inst.instruction == 0xfe000010) 7427 /* MCR, MCR2 */ 7428 reject_bad_reg (Rd); 7429 else 7430 /* MRC, MRC2 */ 7431 constraint (Rd == REG_SP, BAD_SP); 7432 } 7433 else 7434 { 7435 /* MCR */ 7436 if (inst.instruction == 0xe000010) 7437 constraint (Rd == REG_PC, BAD_PC); 7438 } 7439 7440 7441 inst.instruction |= inst.operands[0].reg << 8; 7442 inst.instruction |= inst.operands[1].imm << 21; 7443 inst.instruction |= Rd << 12; 7444 inst.instruction |= inst.operands[3].reg << 16; 7445 inst.instruction |= inst.operands[4].reg; 7446 inst.instruction |= inst.operands[5].imm << 5; 7447} 7448 7449/* Transfer between coprocessor register and pair of ARM registers. 7450 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. 7451 MCRR2 7452 MRRC{cond} 7453 MRRC2 7454 7455 Two XScale instructions are special cases of these: 7456 7457 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 7458 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 7459 7460 Result unpredictable if Rd or Rn is R15. */ 7461 7462static void 7463do_co_reg2c (void) 7464{ 7465 unsigned Rd, Rn; 7466 7467 Rd = inst.operands[2].reg; 7468 Rn = inst.operands[3].reg; 7469 7470 if (thumb_mode) 7471 { 7472 reject_bad_reg (Rd); 7473 reject_bad_reg (Rn); 7474 } 7475 else 7476 { 7477 constraint (Rd == REG_PC, BAD_PC); 7478 constraint (Rn == REG_PC, BAD_PC); 7479 } 7480 7481 inst.instruction |= inst.operands[0].reg << 8; 7482 inst.instruction |= inst.operands[1].imm << 4; 7483 inst.instruction |= Rd << 12; 7484 inst.instruction |= Rn << 16; 7485 inst.instruction |= inst.operands[4].reg; 7486} 7487 7488static void 7489do_cpsi (void) 7490{ 7491 inst.instruction |= inst.operands[0].imm << 6; 7492 if (inst.operands[1].present) 7493 { 7494 inst.instruction |= CPSI_MMOD; 7495 inst.instruction |= inst.operands[1].imm; 7496 } 7497} 7498 7499static void 7500do_dbg (void) 7501{ 7502 inst.instruction |= inst.operands[0].imm; 7503} 7504 7505static void 7506do_div (void) 7507{ 7508 unsigned Rd, Rn, Rm; 7509 7510 Rd = inst.operands[0].reg; 7511 Rn = (inst.operands[1].present 7512 ? inst.operands[1].reg : Rd); 7513 Rm = inst.operands[2].reg; 7514 7515 constraint ((Rd == REG_PC), BAD_PC); 7516 constraint ((Rn == REG_PC), BAD_PC); 7517 constraint ((Rm == REG_PC), BAD_PC); 7518 7519 inst.instruction |= Rd << 16; 7520 inst.instruction |= Rn << 0; 7521 inst.instruction |= Rm << 8; 7522} 7523 7524static void 7525do_it (void) 7526{ 7527 /* There is no IT instruction in ARM mode. We 7528 process it to do the validation as if in 7529 thumb mode, just in case the code gets 7530 assembled for thumb using the unified syntax. */ 7531 7532 inst.size = 0; 7533 if (unified_syntax) 7534 { 7535 set_it_insn_type (IT_INSN); 7536 now_it.mask = (inst.instruction & 0xf) | 0x10; 7537 now_it.cc = inst.operands[0].imm; 7538 } 7539} 7540 7541static void 7542do_ldmstm (void) 7543{ 7544 int base_reg = inst.operands[0].reg; 7545 int range = inst.operands[1].imm; 7546 7547 inst.instruction |= base_reg << 16; 7548 inst.instruction |= range; 7549 7550 if (inst.operands[1].writeback) 7551 inst.instruction |= LDM_TYPE_2_OR_3; 7552 7553 if (inst.operands[0].writeback) 7554 { 7555 inst.instruction |= WRITE_BACK; 7556 /* Check for unpredictable uses of writeback. */ 7557 if (inst.instruction & LOAD_BIT) 7558 { 7559 /* Not allowed in LDM type 2. */ 7560 if ((inst.instruction & LDM_TYPE_2_OR_3) 7561 && ((range & (1 << REG_PC)) == 0)) 7562 as_warn (_("writeback of base register is UNPREDICTABLE")); 7563 /* Only allowed if base reg not in list for other types. */ 7564 else if (range & (1 << base_reg)) 7565 as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); 7566 } 7567 else /* STM. */ 7568 { 7569 /* Not allowed for type 2. */ 7570 if (inst.instruction & LDM_TYPE_2_OR_3) 7571 as_warn (_("writeback of base register is UNPREDICTABLE")); 7572 /* Only allowed if base reg not in list, or first in list. */ 7573 else if ((range & (1 << base_reg)) 7574 && (range & ((1 << base_reg) - 1))) 7575 as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); 7576 } 7577 } 7578} 7579 7580/* ARMv5TE load-consecutive (argument parse) 7581 Mode is like LDRH. 7582 7583 LDRccD R, mode 7584 STRccD R, mode. */ 7585 7586static void 7587do_ldrd (void) 7588{ 7589 constraint (inst.operands[0].reg % 2 != 0, 7590 _("first destination register must be even")); 7591 constraint (inst.operands[1].present 7592 && inst.operands[1].reg != inst.operands[0].reg + 1, 7593 _("can only load two consecutive registers")); 7594 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); 7595 constraint (!inst.operands[2].isreg, _("'[' expected")); 7596 7597 if (!inst.operands[1].present) 7598 inst.operands[1].reg = inst.operands[0].reg + 1; 7599 7600 if (inst.instruction & LOAD_BIT) 7601 { 7602 /* encode_arm_addr_mode_3 will diagnose overlap between the base 7603 register and the first register written; we have to diagnose 7604 overlap between the base and the second register written here. */ 7605 7606 if (inst.operands[2].reg == inst.operands[1].reg 7607 && (inst.operands[2].writeback || inst.operands[2].postind)) 7608 as_warn (_("base register written back, and overlaps " 7609 "second destination register")); 7610 7611 /* For an index-register load, the index register must not overlap the 7612 destination (even if not write-back). */ 7613 else if (inst.operands[2].immisreg 7614 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg 7615 || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) 7616 as_warn (_("index register overlaps destination register")); 7617 } 7618 7619 inst.instruction |= inst.operands[0].reg << 12; 7620 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); 7621} 7622 7623static void 7624do_ldrex (void) 7625{ 7626 constraint (!inst.operands[1].isreg || !inst.operands[1].preind 7627 || inst.operands[1].postind || inst.operands[1].writeback 7628 || inst.operands[1].immisreg || inst.operands[1].shifted 7629 || inst.operands[1].negative 7630 /* This can arise if the programmer has written 7631 strex rN, rM, foo 7632 or if they have mistakenly used a register name as the last 7633 operand, eg: 7634 strex rN, rM, rX 7635 It is very difficult to distinguish between these two cases 7636 because "rX" might actually be a label. ie the register 7637 name has been occluded by a symbol of the same name. So we 7638 just generate a general 'bad addressing mode' type error 7639 message and leave it up to the programmer to discover the 7640 true cause and fix their mistake. */ 7641 || (inst.operands[1].reg == REG_PC), 7642 BAD_ADDR_MODE); 7643 7644 constraint (inst.reloc.exp.X_op != O_constant 7645 || inst.reloc.exp.X_add_number != 0, 7646 _("offset must be zero in ARM encoding")); 7647 7648 constraint ((inst.operands[1].reg == REG_PC), BAD_PC); 7649 7650 inst.instruction |= inst.operands[0].reg << 12; 7651 inst.instruction |= inst.operands[1].reg << 16; 7652 inst.reloc.type = BFD_RELOC_UNUSED; 7653} 7654 7655static void 7656do_ldrexd (void) 7657{ 7658 constraint (inst.operands[0].reg % 2 != 0, 7659 _("even register required")); 7660 constraint (inst.operands[1].present 7661 && inst.operands[1].reg != inst.operands[0].reg + 1, 7662 _("can only load two consecutive registers")); 7663 /* If op 1 were present and equal to PC, this function wouldn't 7664 have been called in the first place. */ 7665 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); 7666 7667 inst.instruction |= inst.operands[0].reg << 12; 7668 inst.instruction |= inst.operands[2].reg << 16; 7669} 7670 7671static void 7672do_ldst (void) 7673{ 7674 inst.instruction |= inst.operands[0].reg << 12; 7675 if (!inst.operands[1].isreg) 7676 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) 7677 return; 7678 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); 7679} 7680 7681static void 7682do_ldstt (void) 7683{ 7684 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and 7685 reject [Rn,...]. */ 7686 if (inst.operands[1].preind) 7687 { 7688 constraint (inst.reloc.exp.X_op != O_constant 7689 || inst.reloc.exp.X_add_number != 0, 7690 _("this instruction requires a post-indexed address")); 7691 7692 inst.operands[1].preind = 0; 7693 inst.operands[1].postind = 1; 7694 inst.operands[1].writeback = 1; 7695 } 7696 inst.instruction |= inst.operands[0].reg << 12; 7697 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); 7698} 7699 7700/* Halfword and signed-byte load/store operations. */ 7701 7702static void 7703do_ldstv4 (void) 7704{ 7705 constraint (inst.operands[0].reg == REG_PC, BAD_PC); 7706 inst.instruction |= inst.operands[0].reg << 12; 7707 if (!inst.operands[1].isreg) 7708 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) 7709 return; 7710 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); 7711} 7712 7713static void 7714do_ldsttv4 (void) 7715{ 7716 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and 7717 reject [Rn,...]. */ 7718 if (inst.operands[1].preind) 7719 { 7720 constraint (inst.reloc.exp.X_op != O_constant 7721 || inst.reloc.exp.X_add_number != 0, 7722 _("this instruction requires a post-indexed address")); 7723 7724 inst.operands[1].preind = 0; 7725 inst.operands[1].postind = 1; 7726 inst.operands[1].writeback = 1; 7727 } 7728 inst.instruction |= inst.operands[0].reg << 12; 7729 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); 7730} 7731 7732/* Co-processor register load/store. 7733 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ 7734static void 7735do_lstc (void) 7736{ 7737 inst.instruction |= inst.operands[0].reg << 8; 7738 inst.instruction |= inst.operands[1].reg << 12; 7739 encode_arm_cp_address (2, TRUE, TRUE, 0); 7740} 7741 7742static void 7743do_mlas (void) 7744{ 7745 /* This restriction does not apply to mls (nor to mla in v6 or later). */ 7746 if (inst.operands[0].reg == inst.operands[1].reg 7747 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) 7748 && !(inst.instruction & 0x00400000)) 7749 as_tsktsk (_("Rd and Rm should be different in mla")); 7750 7751 inst.instruction |= inst.operands[0].reg << 16; 7752 inst.instruction |= inst.operands[1].reg; 7753 inst.instruction |= inst.operands[2].reg << 8; 7754 inst.instruction |= inst.operands[3].reg << 12; 7755} 7756 7757static void 7758do_mov (void) 7759{ 7760 inst.instruction |= inst.operands[0].reg << 12; 7761 encode_arm_shifter_operand (1); 7762} 7763 7764/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ 7765static void 7766do_mov16 (void) 7767{ 7768 bfd_vma imm; 7769 bfd_boolean top; 7770 7771 top = (inst.instruction & 0x00400000) != 0; 7772 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, 7773 _(":lower16: not allowed this instruction")); 7774 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, 7775 _(":upper16: not allowed instruction")); 7776 inst.instruction |= inst.operands[0].reg << 12; 7777 if (inst.reloc.type == BFD_RELOC_UNUSED) 7778 { 7779 imm = inst.reloc.exp.X_add_number; 7780 /* The value is in two pieces: 0:11, 16:19. */ 7781 inst.instruction |= (imm & 0x00000fff); 7782 inst.instruction |= (imm & 0x0000f000) << 4; 7783 } 7784} 7785 7786static void do_vfp_nsyn_opcode (const char *); 7787 7788static int 7789do_vfp_nsyn_mrs (void) 7790{ 7791 if (inst.operands[0].isvec) 7792 { 7793 if (inst.operands[1].reg != 1) 7794 first_error (_("operand 1 must be FPSCR")); 7795 memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); 7796 memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); 7797 do_vfp_nsyn_opcode ("fmstat"); 7798 } 7799 else if (inst.operands[1].isvec) 7800 do_vfp_nsyn_opcode ("fmrx"); 7801 else 7802 return FAIL; 7803 7804 return SUCCESS; 7805} 7806 7807static int 7808do_vfp_nsyn_msr (void) 7809{ 7810 if (inst.operands[0].isvec) 7811 do_vfp_nsyn_opcode ("fmxr"); 7812 else 7813 return FAIL; 7814 7815 return SUCCESS; 7816} 7817 7818static void 7819do_vmrs (void) 7820{ 7821 unsigned Rt = inst.operands[0].reg; 7822 7823 if (thumb_mode && inst.operands[0].reg == REG_SP) 7824 { 7825 inst.error = BAD_SP; 7826 return; 7827 } 7828 7829 /* APSR_ sets isvec. All other refs to PC are illegal. */ 7830 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC) 7831 { 7832 inst.error = BAD_PC; 7833 return; 7834 } 7835 7836 if (inst.operands[1].reg != 1) 7837 first_error (_("operand 1 must be FPSCR")); 7838 7839 inst.instruction |= (Rt << 12); 7840} 7841 7842static void 7843do_vmsr (void) 7844{ 7845 unsigned Rt = inst.operands[1].reg; 7846 7847 if (thumb_mode) 7848 reject_bad_reg (Rt); 7849 else if (Rt == REG_PC) 7850 { 7851 inst.error = BAD_PC; 7852 return; 7853 } 7854 7855 if (inst.operands[0].reg != 1) 7856 first_error (_("operand 0 must be FPSCR")); 7857 7858 inst.instruction |= (Rt << 12); 7859} 7860 7861static void 7862do_mrs (void) 7863{ 7864 unsigned br; 7865 7866 if (do_vfp_nsyn_mrs () == SUCCESS) 7867 return; 7868 7869 constraint (inst.operands[0].reg == REG_PC, BAD_PC); 7870 inst.instruction |= inst.operands[0].reg << 12; 7871 7872 if (inst.operands[1].isreg) 7873 { 7874 br = inst.operands[1].reg; 7875 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000)) 7876 as_bad (_("bad register for mrs")); 7877 } 7878 else 7879 { 7880 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ 7881 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) 7882 != (PSR_c|PSR_f), 7883 _("'CPSR' or 'SPSR' expected")); 7884 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT); 7885 } 7886 7887 inst.instruction |= br; 7888} 7889 7890/* Two possible forms: 7891 "{C|S}PSR_<field>, Rm", 7892 "{C|S}PSR_f, #expression". */ 7893 7894static void 7895do_msr (void) 7896{ 7897 if (do_vfp_nsyn_msr () == SUCCESS) 7898 return; 7899 7900 inst.instruction |= inst.operands[0].imm; 7901 if (inst.operands[1].isreg) 7902 inst.instruction |= inst.operands[1].reg; 7903 else 7904 { 7905 inst.instruction |= INST_IMMEDIATE; 7906 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 7907 inst.reloc.pc_rel = 0; 7908 } 7909} 7910 7911static void 7912do_mul (void) 7913{ 7914 constraint (inst.operands[2].reg == REG_PC, BAD_PC); 7915 7916 if (!inst.operands[2].present) 7917 inst.operands[2].reg = inst.operands[0].reg; 7918 inst.instruction |= inst.operands[0].reg << 16; 7919 inst.instruction |= inst.operands[1].reg; 7920 inst.instruction |= inst.operands[2].reg << 8; 7921 7922 if (inst.operands[0].reg == inst.operands[1].reg 7923 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) 7924 as_tsktsk (_("Rd and Rm should be different in mul")); 7925} 7926 7927/* Long Multiply Parser 7928 UMULL RdLo, RdHi, Rm, Rs 7929 SMULL RdLo, RdHi, Rm, Rs 7930 UMLAL RdLo, RdHi, Rm, Rs 7931 SMLAL RdLo, RdHi, Rm, Rs. */ 7932 7933static void 7934do_mull (void) 7935{ 7936 inst.instruction |= inst.operands[0].reg << 12; 7937 inst.instruction |= inst.operands[1].reg << 16; 7938 inst.instruction |= inst.operands[2].reg; 7939 inst.instruction |= inst.operands[3].reg << 8; 7940 7941 /* rdhi and rdlo must be different. */ 7942 if (inst.operands[0].reg == inst.operands[1].reg) 7943 as_tsktsk (_("rdhi and rdlo must be different")); 7944 7945 /* rdhi, rdlo and rm must all be different before armv6. */ 7946 if ((inst.operands[0].reg == inst.operands[2].reg 7947 || inst.operands[1].reg == inst.operands[2].reg) 7948 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) 7949 as_tsktsk (_("rdhi, rdlo and rm must all be different")); 7950} 7951 7952static void 7953do_nop (void) 7954{ 7955 if (inst.operands[0].present 7956 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) 7957 { 7958 /* Architectural NOP hints are CPSR sets with no bits selected. */ 7959 inst.instruction &= 0xf0000000; 7960 inst.instruction |= 0x0320f000; 7961 if (inst.operands[0].present) 7962 inst.instruction |= inst.operands[0].imm; 7963 } 7964} 7965 7966/* ARM V6 Pack Halfword Bottom Top instruction (argument parse). 7967 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} 7968 Condition defaults to COND_ALWAYS. 7969 Error if Rd, Rn or Rm are R15. */ 7970 7971static void 7972do_pkhbt (void) 7973{ 7974 inst.instruction |= inst.operands[0].reg << 12; 7975 inst.instruction |= inst.operands[1].reg << 16; 7976 inst.instruction |= inst.operands[2].reg; 7977 if (inst.operands[3].present) 7978 encode_arm_shift (3); 7979} 7980 7981/* ARM V6 PKHTB (Argument Parse). */ 7982 7983static void 7984do_pkhtb (void) 7985{ 7986 if (!inst.operands[3].present) 7987 { 7988 /* If the shift specifier is omitted, turn the instruction 7989 into pkhbt rd, rm, rn. */ 7990 inst.instruction &= 0xfff00010; 7991 inst.instruction |= inst.operands[0].reg << 12; 7992 inst.instruction |= inst.operands[1].reg; 7993 inst.instruction |= inst.operands[2].reg << 16; 7994 } 7995 else 7996 { 7997 inst.instruction |= inst.operands[0].reg << 12; 7998 inst.instruction |= inst.operands[1].reg << 16; 7999 inst.instruction |= inst.operands[2].reg; 8000 encode_arm_shift (3); 8001 } 8002} 8003 8004/* ARMv5TE: Preload-Cache 8005 MP Extensions: Preload for write 8006 8007 PLD(W) <addr_mode> 8008 8009 Syntactically, like LDR with B=1, W=0, L=1. */ 8010 8011static void 8012do_pld (void) 8013{ 8014 constraint (!inst.operands[0].isreg, 8015 _("'[' expected after PLD mnemonic")); 8016 constraint (inst.operands[0].postind, 8017 _("post-indexed expression used in preload instruction")); 8018 constraint (inst.operands[0].writeback, 8019 _("writeback used in preload instruction")); 8020 constraint (!inst.operands[0].preind, 8021 _("unindexed addressing used in preload instruction")); 8022 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); 8023} 8024 8025/* ARMv7: PLI <addr_mode> */ 8026static void 8027do_pli (void) 8028{ 8029 constraint (!inst.operands[0].isreg, 8030 _("'[' expected after PLI mnemonic")); 8031 constraint (inst.operands[0].postind, 8032 _("post-indexed expression used in preload instruction")); 8033 constraint (inst.operands[0].writeback, 8034 _("writeback used in preload instruction")); 8035 constraint (!inst.operands[0].preind, 8036 _("unindexed addressing used in preload instruction")); 8037 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); 8038 inst.instruction &= ~PRE_INDEX; 8039} 8040 8041static void 8042do_push_pop (void) 8043{ 8044 inst.operands[1] = inst.operands[0]; 8045 memset (&inst.operands[0], 0, sizeof inst.operands[0]); 8046 inst.operands[0].isreg = 1; 8047 inst.operands[0].writeback = 1; 8048 inst.operands[0].reg = REG_SP; 8049 do_ldmstm (); 8050} 8051 8052/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the 8053 word at the specified address and the following word 8054 respectively. 8055 Unconditionally executed. 8056 Error if Rn is R15. */ 8057 8058static void 8059do_rfe (void) 8060{ 8061 inst.instruction |= inst.operands[0].reg << 16; 8062 if (inst.operands[0].writeback) 8063 inst.instruction |= WRITE_BACK; 8064} 8065 8066/* ARM V6 ssat (argument parse). */ 8067 8068static void 8069do_ssat (void) 8070{ 8071 inst.instruction |= inst.operands[0].reg << 12; 8072 inst.instruction |= (inst.operands[1].imm - 1) << 16; 8073 inst.instruction |= inst.operands[2].reg; 8074 8075 if (inst.operands[3].present) 8076 encode_arm_shift (3); 8077} 8078 8079/* ARM V6 usat (argument parse). */ 8080 8081static void 8082do_usat (void) 8083{ 8084 inst.instruction |= inst.operands[0].reg << 12; 8085 inst.instruction |= inst.operands[1].imm << 16; 8086 inst.instruction |= inst.operands[2].reg; 8087 8088 if (inst.operands[3].present) 8089 encode_arm_shift (3); 8090} 8091 8092/* ARM V6 ssat16 (argument parse). */ 8093 8094static void 8095do_ssat16 (void) 8096{ 8097 inst.instruction |= inst.operands[0].reg << 12; 8098 inst.instruction |= ((inst.operands[1].imm - 1) << 16); 8099 inst.instruction |= inst.operands[2].reg; 8100} 8101 8102static void 8103do_usat16 (void) 8104{ 8105 inst.instruction |= inst.operands[0].reg << 12; 8106 inst.instruction |= inst.operands[1].imm << 16; 8107 inst.instruction |= inst.operands[2].reg; 8108} 8109 8110/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while 8111 preserving the other bits. 8112 8113 setend <endian_specifier>, where <endian_specifier> is either 8114 BE or LE. */ 8115 8116static void 8117do_setend (void) 8118{ 8119 if (inst.operands[0].imm) 8120 inst.instruction |= 0x200; 8121} 8122 8123static void 8124do_shift (void) 8125{ 8126 unsigned int Rm = (inst.operands[1].present 8127 ? inst.operands[1].reg 8128 : inst.operands[0].reg); 8129 8130 inst.instruction |= inst.operands[0].reg << 12; 8131 inst.instruction |= Rm; 8132 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ 8133 { 8134 inst.instruction |= inst.operands[2].reg << 8; 8135 inst.instruction |= SHIFT_BY_REG; 8136 } 8137 else 8138 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 8139} 8140 8141static void 8142do_smc (void) 8143{ 8144 inst.reloc.type = BFD_RELOC_ARM_SMC; 8145 inst.reloc.pc_rel = 0; 8146} 8147 8148static void 8149do_hvc (void) 8150{ 8151 inst.reloc.type = BFD_RELOC_ARM_HVC; 8152 inst.reloc.pc_rel = 0; 8153} 8154 8155static void 8156do_swi (void) 8157{ 8158 inst.reloc.type = BFD_RELOC_ARM_SWI; 8159 inst.reloc.pc_rel = 0; 8160} 8161 8162/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) 8163 SMLAxy{cond} Rd,Rm,Rs,Rn 8164 SMLAWy{cond} Rd,Rm,Rs,Rn 8165 Error if any register is R15. */ 8166 8167static void 8168do_smla (void) 8169{ 8170 inst.instruction |= inst.operands[0].reg << 16; 8171 inst.instruction |= inst.operands[1].reg; 8172 inst.instruction |= inst.operands[2].reg << 8; 8173 inst.instruction |= inst.operands[3].reg << 12; 8174} 8175 8176/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) 8177 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs 8178 Error if any register is R15. 8179 Warning if Rdlo == Rdhi. */ 8180 8181static void 8182do_smlal (void) 8183{ 8184 inst.instruction |= inst.operands[0].reg << 12; 8185 inst.instruction |= inst.operands[1].reg << 16; 8186 inst.instruction |= inst.operands[2].reg; 8187 inst.instruction |= inst.operands[3].reg << 8; 8188 8189 if (inst.operands[0].reg == inst.operands[1].reg) 8190 as_tsktsk (_("rdhi and rdlo must be different")); 8191} 8192 8193/* ARM V5E (El Segundo) signed-multiply (argument parse) 8194 SMULxy{cond} Rd,Rm,Rs 8195 Error if any register is R15. */ 8196 8197static void 8198do_smul (void) 8199{ 8200 inst.instruction |= inst.operands[0].reg << 16; 8201 inst.instruction |= inst.operands[1].reg; 8202 inst.instruction |= inst.operands[2].reg << 8; 8203} 8204 8205/* ARM V6 srs (argument parse). The variable fields in the encoding are 8206 the same for both ARM and Thumb-2. */ 8207 8208static void 8209do_srs (void) 8210{ 8211 int reg; 8212 8213 if (inst.operands[0].present) 8214 { 8215 reg = inst.operands[0].reg; 8216 constraint (reg != REG_SP, _("SRS base register must be r13")); 8217 } 8218 else 8219 reg = REG_SP; 8220 8221 inst.instruction |= reg << 16; 8222 inst.instruction |= inst.operands[1].imm; 8223 if (inst.operands[0].writeback || inst.operands[1].writeback) 8224 inst.instruction |= WRITE_BACK; 8225} 8226 8227/* ARM V6 strex (argument parse). */ 8228 8229static void 8230do_strex (void) 8231{ 8232 constraint (!inst.operands[2].isreg || !inst.operands[2].preind 8233 || inst.operands[2].postind || inst.operands[2].writeback 8234 || inst.operands[2].immisreg || inst.operands[2].shifted 8235 || inst.operands[2].negative 8236 /* See comment in do_ldrex(). */ 8237 || (inst.operands[2].reg == REG_PC), 8238 BAD_ADDR_MODE); 8239 8240 constraint (inst.operands[0].reg == inst.operands[1].reg 8241 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); 8242 8243 constraint (inst.reloc.exp.X_op != O_constant 8244 || inst.reloc.exp.X_add_number != 0, 8245 _("offset must be zero in ARM encoding")); 8246 8247 inst.instruction |= inst.operands[0].reg << 12; 8248 inst.instruction |= inst.operands[1].reg; 8249 inst.instruction |= inst.operands[2].reg << 16; 8250 inst.reloc.type = BFD_RELOC_UNUSED; 8251} 8252 8253static void 8254do_strexd (void) 8255{ 8256 constraint (inst.operands[1].reg % 2 != 0, 8257 _("even register required")); 8258 constraint (inst.operands[2].present 8259 && inst.operands[2].reg != inst.operands[1].reg + 1, 8260 _("can only store two consecutive registers")); 8261 /* If op 2 were present and equal to PC, this function wouldn't 8262 have been called in the first place. */ 8263 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); 8264 8265 constraint (inst.operands[0].reg == inst.operands[1].reg 8266 || inst.operands[0].reg == inst.operands[1].reg + 1 8267 || inst.operands[0].reg == inst.operands[3].reg, 8268 BAD_OVERLAP); 8269 8270 inst.instruction |= inst.operands[0].reg << 12; 8271 inst.instruction |= inst.operands[1].reg; 8272 inst.instruction |= inst.operands[3].reg << 16; 8273} 8274 8275/* ARM V6 SXTAH extracts a 16-bit value from a register, sign 8276 extends it to 32-bits, and adds the result to a value in another 8277 register. You can specify a rotation by 0, 8, 16, or 24 bits 8278 before extracting the 16-bit value. 8279 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} 8280 Condition defaults to COND_ALWAYS. 8281 Error if any register uses R15. */ 8282 8283static void 8284do_sxtah (void) 8285{ 8286 inst.instruction |= inst.operands[0].reg << 12; 8287 inst.instruction |= inst.operands[1].reg << 16; 8288 inst.instruction |= inst.operands[2].reg; 8289 inst.instruction |= inst.operands[3].imm << 10; 8290} 8291 8292/* ARM V6 SXTH. 8293 8294 SXTH {<cond>} <Rd>, <Rm>{, <rotation>} 8295 Condition defaults to COND_ALWAYS. 8296 Error if any register uses R15. */ 8297 8298static void 8299do_sxth (void) 8300{ 8301 inst.instruction |= inst.operands[0].reg << 12; 8302 inst.instruction |= inst.operands[1].reg; 8303 inst.instruction |= inst.operands[2].imm << 10; 8304} 8305 8306/* VFP instructions. In a logical order: SP variant first, monad 8307 before dyad, arithmetic then move then load/store. */ 8308 8309static void 8310do_vfp_sp_monadic (void) 8311{ 8312 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 8313 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); 8314} 8315 8316static void 8317do_vfp_sp_dyadic (void) 8318{ 8319 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 8320 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); 8321 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); 8322} 8323 8324static void 8325do_vfp_sp_compare_z (void) 8326{ 8327 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 8328} 8329 8330static void 8331do_vfp_dp_sp_cvt (void) 8332{ 8333 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 8334 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); 8335} 8336 8337static void 8338do_vfp_sp_dp_cvt (void) 8339{ 8340 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 8341 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); 8342} 8343 8344static void 8345do_vfp_reg_from_sp (void) 8346{ 8347 inst.instruction |= inst.operands[0].reg << 12; 8348 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); 8349} 8350 8351static void 8352do_vfp_reg2_from_sp2 (void) 8353{ 8354 constraint (inst.operands[2].imm != 2, 8355 _("only two consecutive VFP SP registers allowed here")); 8356 inst.instruction |= inst.operands[0].reg << 12; 8357 inst.instruction |= inst.operands[1].reg << 16; 8358 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); 8359} 8360 8361static void 8362do_vfp_sp_from_reg (void) 8363{ 8364 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); 8365 inst.instruction |= inst.operands[1].reg << 12; 8366} 8367 8368static void 8369do_vfp_sp2_from_reg2 (void) 8370{ 8371 constraint (inst.operands[0].imm != 2, 8372 _("only two consecutive VFP SP registers allowed here")); 8373 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); 8374 inst.instruction |= inst.operands[1].reg << 12; 8375 inst.instruction |= inst.operands[2].reg << 16; 8376} 8377 8378static void 8379do_vfp_sp_ldst (void) 8380{ 8381 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 8382 encode_arm_cp_address (1, FALSE, TRUE, 0); 8383} 8384 8385static void 8386do_vfp_dp_ldst (void) 8387{ 8388 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 8389 encode_arm_cp_address (1, FALSE, TRUE, 0); 8390} 8391 8392 8393static void 8394vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) 8395{ 8396 if (inst.operands[0].writeback) 8397 inst.instruction |= WRITE_BACK; 8398 else 8399 constraint (ldstm_type != VFP_LDSTMIA, 8400 _("this addressing mode requires base-register writeback")); 8401 inst.instruction |= inst.operands[0].reg << 16; 8402 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); 8403 inst.instruction |= inst.operands[1].imm; 8404} 8405 8406static void 8407vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) 8408{ 8409 int count; 8410 8411 if (inst.operands[0].writeback) 8412 inst.instruction |= WRITE_BACK; 8413 else 8414 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, 8415 _("this addressing mode requires base-register writeback")); 8416 8417 inst.instruction |= inst.operands[0].reg << 16; 8418 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 8419 8420 count = inst.operands[1].imm << 1; 8421 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) 8422 count += 1; 8423 8424 inst.instruction |= count; 8425} 8426 8427static void 8428do_vfp_sp_ldstmia (void) 8429{ 8430 vfp_sp_ldstm (VFP_LDSTMIA); 8431} 8432 8433static void 8434do_vfp_sp_ldstmdb (void) 8435{ 8436 vfp_sp_ldstm (VFP_LDSTMDB); 8437} 8438 8439static void 8440do_vfp_dp_ldstmia (void) 8441{ 8442 vfp_dp_ldstm (VFP_LDSTMIA); 8443} 8444 8445static void 8446do_vfp_dp_ldstmdb (void) 8447{ 8448 vfp_dp_ldstm (VFP_LDSTMDB); 8449} 8450 8451static void 8452do_vfp_xp_ldstmia (void) 8453{ 8454 vfp_dp_ldstm (VFP_LDSTMIAX); 8455} 8456 8457static void 8458do_vfp_xp_ldstmdb (void) 8459{ 8460 vfp_dp_ldstm (VFP_LDSTMDBX); 8461} 8462 8463static void 8464do_vfp_dp_rd_rm (void) 8465{ 8466 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 8467 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); 8468} 8469 8470static void 8471do_vfp_dp_rn_rd (void) 8472{ 8473 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); 8474 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 8475} 8476 8477static void 8478do_vfp_dp_rd_rn (void) 8479{ 8480 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 8481 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); 8482} 8483 8484static void 8485do_vfp_dp_rd_rn_rm (void) 8486{ 8487 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 8488 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); 8489 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); 8490} 8491 8492static void 8493do_vfp_dp_rd (void) 8494{ 8495 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 8496} 8497 8498static void 8499do_vfp_dp_rm_rd_rn (void) 8500{ 8501 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); 8502 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 8503 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); 8504} 8505 8506/* VFPv3 instructions. */ 8507static void 8508do_vfp_sp_const (void) 8509{ 8510 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 8511 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; 8512 inst.instruction |= (inst.operands[1].imm & 0x0f); 8513} 8514 8515static void 8516do_vfp_dp_const (void) 8517{ 8518 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 8519 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; 8520 inst.instruction |= (inst.operands[1].imm & 0x0f); 8521} 8522 8523static void 8524vfp_conv (int srcsize) 8525{ 8526 unsigned immbits = srcsize - inst.operands[1].imm; 8527 inst.instruction |= (immbits & 1) << 5; 8528 inst.instruction |= (immbits >> 1); 8529} 8530 8531static void 8532do_vfp_sp_conv_16 (void) 8533{ 8534 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 8535 vfp_conv (16); 8536} 8537 8538static void 8539do_vfp_dp_conv_16 (void) 8540{ 8541 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 8542 vfp_conv (16); 8543} 8544 8545static void 8546do_vfp_sp_conv_32 (void) 8547{ 8548 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 8549 vfp_conv (32); 8550} 8551 8552static void 8553do_vfp_dp_conv_32 (void) 8554{ 8555 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 8556 vfp_conv (32); 8557} 8558 8559/* FPA instructions. Also in a logical order. */ 8560 8561static void 8562do_fpa_cmp (void) 8563{ 8564 inst.instruction |= inst.operands[0].reg << 16; 8565 inst.instruction |= inst.operands[1].reg; 8566} 8567 8568static void 8569do_fpa_ldmstm (void) 8570{ 8571 inst.instruction |= inst.operands[0].reg << 12; 8572 switch (inst.operands[1].imm) 8573 { 8574 case 1: inst.instruction |= CP_T_X; break; 8575 case 2: inst.instruction |= CP_T_Y; break; 8576 case 3: inst.instruction |= CP_T_Y | CP_T_X; break; 8577 case 4: break; 8578 default: abort (); 8579 } 8580 8581 if (inst.instruction & (PRE_INDEX | INDEX_UP)) 8582 { 8583 /* The instruction specified "ea" or "fd", so we can only accept 8584 [Rn]{!}. The instruction does not really support stacking or 8585 unstacking, so we have to emulate these by setting appropriate 8586 bits and offsets. */ 8587 constraint (inst.reloc.exp.X_op != O_constant 8588 || inst.reloc.exp.X_add_number != 0, 8589 _("this instruction does not support indexing")); 8590 8591 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) 8592 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; 8593 8594 if (!(inst.instruction & INDEX_UP)) 8595 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; 8596 8597 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) 8598 { 8599 inst.operands[2].preind = 0; 8600 inst.operands[2].postind = 1; 8601 } 8602 } 8603 8604 encode_arm_cp_address (2, TRUE, TRUE, 0); 8605} 8606 8607/* iWMMXt instructions: strictly in alphabetical order. */ 8608 8609static void 8610do_iwmmxt_tandorc (void) 8611{ 8612 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); 8613} 8614 8615static void 8616do_iwmmxt_textrc (void) 8617{ 8618 inst.instruction |= inst.operands[0].reg << 12; 8619 inst.instruction |= inst.operands[1].imm; 8620} 8621 8622static void 8623do_iwmmxt_textrm (void) 8624{ 8625 inst.instruction |= inst.operands[0].reg << 12; 8626 inst.instruction |= inst.operands[1].reg << 16; 8627 inst.instruction |= inst.operands[2].imm; 8628} 8629 8630static void 8631do_iwmmxt_tinsr (void) 8632{ 8633 inst.instruction |= inst.operands[0].reg << 16; 8634 inst.instruction |= inst.operands[1].reg << 12; 8635 inst.instruction |= inst.operands[2].imm; 8636} 8637 8638static void 8639do_iwmmxt_tmia (void) 8640{ 8641 inst.instruction |= inst.operands[0].reg << 5; 8642 inst.instruction |= inst.operands[1].reg; 8643 inst.instruction |= inst.operands[2].reg << 12; 8644} 8645 8646static void 8647do_iwmmxt_waligni (void) 8648{ 8649 inst.instruction |= inst.operands[0].reg << 12; 8650 inst.instruction |= inst.operands[1].reg << 16; 8651 inst.instruction |= inst.operands[2].reg; 8652 inst.instruction |= inst.operands[3].imm << 20; 8653} 8654 8655static void 8656do_iwmmxt_wmerge (void) 8657{ 8658 inst.instruction |= inst.operands[0].reg << 12; 8659 inst.instruction |= inst.operands[1].reg << 16; 8660 inst.instruction |= inst.operands[2].reg; 8661 inst.instruction |= inst.operands[3].imm << 21; 8662} 8663 8664static void 8665do_iwmmxt_wmov (void) 8666{ 8667 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ 8668 inst.instruction |= inst.operands[0].reg << 12; 8669 inst.instruction |= inst.operands[1].reg << 16; 8670 inst.instruction |= inst.operands[1].reg; 8671} 8672 8673static void 8674do_iwmmxt_wldstbh (void) 8675{ 8676 int reloc; 8677 inst.instruction |= inst.operands[0].reg << 12; 8678 if (thumb_mode) 8679 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; 8680 else 8681 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; 8682 encode_arm_cp_address (1, TRUE, FALSE, reloc); 8683} 8684 8685static void 8686do_iwmmxt_wldstw (void) 8687{ 8688 /* RIWR_RIWC clears .isreg for a control register. */ 8689 if (!inst.operands[0].isreg) 8690 { 8691 constraint (inst.cond != COND_ALWAYS, BAD_COND); 8692 inst.instruction |= 0xf0000000; 8693 } 8694 8695 inst.instruction |= inst.operands[0].reg << 12; 8696 encode_arm_cp_address (1, TRUE, TRUE, 0); 8697} 8698 8699static void 8700do_iwmmxt_wldstd (void) 8701{ 8702 inst.instruction |= inst.operands[0].reg << 12; 8703 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) 8704 && inst.operands[1].immisreg) 8705 { 8706 inst.instruction &= ~0x1a000ff; 8707 inst.instruction |= (0xf << 28); 8708 if (inst.operands[1].preind) 8709 inst.instruction |= PRE_INDEX; 8710 if (!inst.operands[1].negative) 8711 inst.instruction |= INDEX_UP; 8712 if (inst.operands[1].writeback) 8713 inst.instruction |= WRITE_BACK; 8714 inst.instruction |= inst.operands[1].reg << 16; 8715 inst.instruction |= inst.reloc.exp.X_add_number << 4; 8716 inst.instruction |= inst.operands[1].imm; 8717 } 8718 else 8719 encode_arm_cp_address (1, TRUE, FALSE, 0); 8720} 8721 8722static void 8723do_iwmmxt_wshufh (void) 8724{ 8725 inst.instruction |= inst.operands[0].reg << 12; 8726 inst.instruction |= inst.operands[1].reg << 16; 8727 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); 8728 inst.instruction |= (inst.operands[2].imm & 0x0f); 8729} 8730 8731static void 8732do_iwmmxt_wzero (void) 8733{ 8734 /* WZERO reg is an alias for WANDN reg, reg, reg. */ 8735 inst.instruction |= inst.operands[0].reg; 8736 inst.instruction |= inst.operands[0].reg << 12; 8737 inst.instruction |= inst.operands[0].reg << 16; 8738} 8739 8740static void 8741do_iwmmxt_wrwrwr_or_imm5 (void) 8742{ 8743 if (inst.operands[2].isreg) 8744 do_rd_rn_rm (); 8745 else { 8746 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), 8747 _("immediate operand requires iWMMXt2")); 8748 do_rd_rn (); 8749 if (inst.operands[2].imm == 0) 8750 { 8751 switch ((inst.instruction >> 20) & 0xf) 8752 { 8753 case 4: 8754 case 5: 8755 case 6: 8756 case 7: 8757 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ 8758 inst.operands[2].imm = 16; 8759 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); 8760 break; 8761 case 8: 8762 case 9: 8763 case 10: 8764 case 11: 8765 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ 8766 inst.operands[2].imm = 32; 8767 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); 8768 break; 8769 case 12: 8770 case 13: 8771 case 14: 8772 case 15: 8773 { 8774 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ 8775 unsigned long wrn; 8776 wrn = (inst.instruction >> 16) & 0xf; 8777 inst.instruction &= 0xff0fff0f; 8778 inst.instruction |= wrn; 8779 /* Bail out here; the instruction is now assembled. */ 8780 return; 8781 } 8782 } 8783 } 8784 /* Map 32 -> 0, etc. */ 8785 inst.operands[2].imm &= 0x1f; 8786 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); 8787 } 8788} 8789 8790/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register 8791 operations first, then control, shift, and load/store. */ 8792 8793/* Insns like "foo X,Y,Z". */ 8794 8795static void 8796do_mav_triple (void) 8797{ 8798 inst.instruction |= inst.operands[0].reg << 16; 8799 inst.instruction |= inst.operands[1].reg; 8800 inst.instruction |= inst.operands[2].reg << 12; 8801} 8802 8803/* Insns like "foo W,X,Y,Z". 8804 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ 8805 8806static void 8807do_mav_quad (void) 8808{ 8809 inst.instruction |= inst.operands[0].reg << 5; 8810 inst.instruction |= inst.operands[1].reg << 12; 8811 inst.instruction |= inst.operands[2].reg << 16; 8812 inst.instruction |= inst.operands[3].reg; 8813} 8814 8815/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ 8816static void 8817do_mav_dspsc (void) 8818{ 8819 inst.instruction |= inst.operands[1].reg << 12; 8820} 8821 8822/* Maverick shift immediate instructions. 8823 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. 8824 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ 8825 8826static void 8827do_mav_shift (void) 8828{ 8829 int imm = inst.operands[2].imm; 8830 8831 inst.instruction |= inst.operands[0].reg << 12; 8832 inst.instruction |= inst.operands[1].reg << 16; 8833 8834 /* Bits 0-3 of the insn should have bits 0-3 of the immediate. 8835 Bits 5-7 of the insn should have bits 4-6 of the immediate. 8836 Bit 4 should be 0. */ 8837 imm = (imm & 0xf) | ((imm & 0x70) << 1); 8838 8839 inst.instruction |= imm; 8840} 8841 8842/* XScale instructions. Also sorted arithmetic before move. */ 8843 8844/* Xscale multiply-accumulate (argument parse) 8845 MIAcc acc0,Rm,Rs 8846 MIAPHcc acc0,Rm,Rs 8847 MIAxycc acc0,Rm,Rs. */ 8848 8849static void 8850do_xsc_mia (void) 8851{ 8852 inst.instruction |= inst.operands[1].reg; 8853 inst.instruction |= inst.operands[2].reg << 12; 8854} 8855 8856/* Xscale move-accumulator-register (argument parse) 8857 8858 MARcc acc0,RdLo,RdHi. */ 8859 8860static void 8861do_xsc_mar (void) 8862{ 8863 inst.instruction |= inst.operands[1].reg << 12; 8864 inst.instruction |= inst.operands[2].reg << 16; 8865} 8866 8867/* Xscale move-register-accumulator (argument parse) 8868 8869 MRAcc RdLo,RdHi,acc0. */ 8870 8871static void 8872do_xsc_mra (void) 8873{ 8874 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); 8875 inst.instruction |= inst.operands[0].reg << 12; 8876 inst.instruction |= inst.operands[1].reg << 16; 8877} 8878 8879/* Encoding functions relevant only to Thumb. */ 8880 8881/* inst.operands[i] is a shifted-register operand; encode 8882 it into inst.instruction in the format used by Thumb32. */ 8883 8884static void 8885encode_thumb32_shifted_operand (int i) 8886{ 8887 unsigned int value = inst.reloc.exp.X_add_number; 8888 unsigned int shift = inst.operands[i].shift_kind; 8889 8890 constraint (inst.operands[i].immisreg, 8891 _("shift by register not allowed in thumb mode")); 8892 inst.instruction |= inst.operands[i].reg; 8893 if (shift == SHIFT_RRX) 8894 inst.instruction |= SHIFT_ROR << 4; 8895 else 8896 { 8897 constraint (inst.reloc.exp.X_op != O_constant, 8898 _("expression too complex")); 8899 8900 constraint (value > 32 8901 || (value == 32 && (shift == SHIFT_LSL 8902 || shift == SHIFT_ROR)), 8903 _("shift expression is too large")); 8904 8905 if (value == 0) 8906 shift = SHIFT_LSL; 8907 else if (value == 32) 8908 value = 0; 8909 8910 inst.instruction |= shift << 4; 8911 inst.instruction |= (value & 0x1c) << 10; 8912 inst.instruction |= (value & 0x03) << 6; 8913 } 8914} 8915 8916 8917/* inst.operands[i] was set up by parse_address. Encode it into a 8918 Thumb32 format load or store instruction. Reject forms that cannot 8919 be used with such instructions. If is_t is true, reject forms that 8920 cannot be used with a T instruction; if is_d is true, reject forms 8921 that cannot be used with a D instruction. If it is a store insn, 8922 reject PC in Rn. */ 8923 8924static void 8925encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) 8926{ 8927 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); 8928 8929 constraint (!inst.operands[i].isreg, 8930 _("Instruction does not support =N addresses")); 8931 8932 inst.instruction |= inst.operands[i].reg << 16; 8933 if (inst.operands[i].immisreg) 8934 { 8935 constraint (is_pc, BAD_PC_ADDRESSING); 8936 constraint (is_t || is_d, _("cannot use register index with this instruction")); 8937 constraint (inst.operands[i].negative, 8938 _("Thumb does not support negative register indexing")); 8939 constraint (inst.operands[i].postind, 8940 _("Thumb does not support register post-indexing")); 8941 constraint (inst.operands[i].writeback, 8942 _("Thumb does not support register indexing with writeback")); 8943 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, 8944 _("Thumb supports only LSL in shifted register indexing")); 8945 8946 inst.instruction |= inst.operands[i].imm; 8947 if (inst.operands[i].shifted) 8948 { 8949 constraint (inst.reloc.exp.X_op != O_constant, 8950 _("expression too complex")); 8951 constraint (inst.reloc.exp.X_add_number < 0 8952 || inst.reloc.exp.X_add_number > 3, 8953 _("shift out of range")); 8954 inst.instruction |= inst.reloc.exp.X_add_number << 4; 8955 } 8956 inst.reloc.type = BFD_RELOC_UNUSED; 8957 } 8958 else if (inst.operands[i].preind) 8959 { 8960 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); 8961 constraint (is_t && inst.operands[i].writeback, 8962 _("cannot use writeback with this instruction")); 8963 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0) 8964 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING); 8965 8966 if (is_d) 8967 { 8968 inst.instruction |= 0x01000000; 8969 if (inst.operands[i].writeback) 8970 inst.instruction |= 0x00200000; 8971 } 8972 else 8973 { 8974 inst.instruction |= 0x00000c00; 8975 if (inst.operands[i].writeback) 8976 inst.instruction |= 0x00000100; 8977 } 8978 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; 8979 } 8980 else if (inst.operands[i].postind) 8981 { 8982 gas_assert (inst.operands[i].writeback); 8983 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); 8984 constraint (is_t, _("cannot use post-indexing with this instruction")); 8985 8986 if (is_d) 8987 inst.instruction |= 0x00200000; 8988 else 8989 inst.instruction |= 0x00000900; 8990 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; 8991 } 8992 else /* unindexed - only for coprocessor */ 8993 inst.error = _("instruction does not accept unindexed addressing"); 8994} 8995 8996/* Table of Thumb instructions which exist in both 16- and 32-bit 8997 encodings (the latter only in post-V6T2 cores). The index is the 8998 value used in the insns table below. When there is more than one 8999 possible 16-bit encoding for the instruction, this table always 9000 holds variant (1). 9001 Also contains several pseudo-instructions used during relaxation. */ 9002#define T16_32_TAB \ 9003 X(_adc, 4140, eb400000), \ 9004 X(_adcs, 4140, eb500000), \ 9005 X(_add, 1c00, eb000000), \ 9006 X(_adds, 1c00, eb100000), \ 9007 X(_addi, 0000, f1000000), \ 9008 X(_addis, 0000, f1100000), \ 9009 X(_add_pc,000f, f20f0000), \ 9010 X(_add_sp,000d, f10d0000), \ 9011 X(_adr, 000f, f20f0000), \ 9012 X(_and, 4000, ea000000), \ 9013 X(_ands, 4000, ea100000), \ 9014 X(_asr, 1000, fa40f000), \ 9015 X(_asrs, 1000, fa50f000), \ 9016 X(_b, e000, f000b000), \ 9017 X(_bcond, d000, f0008000), \ 9018 X(_bic, 4380, ea200000), \ 9019 X(_bics, 4380, ea300000), \ 9020 X(_cmn, 42c0, eb100f00), \ 9021 X(_cmp, 2800, ebb00f00), \ 9022 X(_cpsie, b660, f3af8400), \ 9023 X(_cpsid, b670, f3af8600), \ 9024 X(_cpy, 4600, ea4f0000), \ 9025 X(_dec_sp,80dd, f1ad0d00), \ 9026 X(_eor, 4040, ea800000), \ 9027 X(_eors, 4040, ea900000), \ 9028 X(_inc_sp,00dd, f10d0d00), \ 9029 X(_ldmia, c800, e8900000), \ 9030 X(_ldr, 6800, f8500000), \ 9031 X(_ldrb, 7800, f8100000), \ 9032 X(_ldrh, 8800, f8300000), \ 9033 X(_ldrsb, 5600, f9100000), \ 9034 X(_ldrsh, 5e00, f9300000), \ 9035 X(_ldr_pc,4800, f85f0000), \ 9036 X(_ldr_pc2,4800, f85f0000), \ 9037 X(_ldr_sp,9800, f85d0000), \ 9038 X(_lsl, 0000, fa00f000), \ 9039 X(_lsls, 0000, fa10f000), \ 9040 X(_lsr, 0800, fa20f000), \ 9041 X(_lsrs, 0800, fa30f000), \ 9042 X(_mov, 2000, ea4f0000), \ 9043 X(_movs, 2000, ea5f0000), \ 9044 X(_mul, 4340, fb00f000), \ 9045 X(_muls, 4340, ffffffff), /* no 32b muls */ \ 9046 X(_mvn, 43c0, ea6f0000), \ 9047 X(_mvns, 43c0, ea7f0000), \ 9048 X(_neg, 4240, f1c00000), /* rsb #0 */ \ 9049 X(_negs, 4240, f1d00000), /* rsbs #0 */ \ 9050 X(_orr, 4300, ea400000), \ 9051 X(_orrs, 4300, ea500000), \ 9052 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ 9053 X(_push, b400, e92d0000), /* stmdb sp!,... */ \ 9054 X(_rev, ba00, fa90f080), \ 9055 X(_rev16, ba40, fa90f090), \ 9056 X(_revsh, bac0, fa90f0b0), \ 9057 X(_ror, 41c0, fa60f000), \ 9058 X(_rors, 41c0, fa70f000), \ 9059 X(_sbc, 4180, eb600000), \ 9060 X(_sbcs, 4180, eb700000), \ 9061 X(_stmia, c000, e8800000), \ 9062 X(_str, 6000, f8400000), \ 9063 X(_strb, 7000, f8000000), \ 9064 X(_strh, 8000, f8200000), \ 9065 X(_str_sp,9000, f84d0000), \ 9066 X(_sub, 1e00, eba00000), \ 9067 X(_subs, 1e00, ebb00000), \ 9068 X(_subi, 8000, f1a00000), \ 9069 X(_subis, 8000, f1b00000), \ 9070 X(_sxtb, b240, fa4ff080), \ 9071 X(_sxth, b200, fa0ff080), \ 9072 X(_tst, 4200, ea100f00), \ 9073 X(_uxtb, b2c0, fa5ff080), \ 9074 X(_uxth, b280, fa1ff080), \ 9075 X(_nop, bf00, f3af8000), \ 9076 X(_yield, bf10, f3af8001), \ 9077 X(_wfe, bf20, f3af8002), \ 9078 X(_wfi, bf30, f3af8003), \ 9079 X(_sev, bf40, f3af8004), 9080 9081/* To catch errors in encoding functions, the codes are all offset by 9082 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined 9083 as 16-bit instructions. */ 9084#define X(a,b,c) T_MNEM##a 9085enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; 9086#undef X 9087 9088#define X(a,b,c) 0x##b 9089static const unsigned short thumb_op16[] = { T16_32_TAB }; 9090#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) 9091#undef X 9092 9093#define X(a,b,c) 0x##c 9094static const unsigned int thumb_op32[] = { T16_32_TAB }; 9095#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) 9096#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) 9097#undef X 9098#undef T16_32_TAB 9099 9100/* Thumb instruction encoders, in alphabetical order. */ 9101 9102/* ADDW or SUBW. */ 9103 9104static void 9105do_t_add_sub_w (void) 9106{ 9107 int Rd, Rn; 9108 9109 Rd = inst.operands[0].reg; 9110 Rn = inst.operands[1].reg; 9111 9112 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this 9113 is the SP-{plus,minus}-immediate form of the instruction. */ 9114 if (Rn == REG_SP) 9115 constraint (Rd == REG_PC, BAD_PC); 9116 else 9117 reject_bad_reg (Rd); 9118 9119 inst.instruction |= (Rn << 16) | (Rd << 8); 9120 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; 9121} 9122 9123/* Parse an add or subtract instruction. We get here with inst.instruction 9124 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ 9125 9126static void 9127do_t_add_sub (void) 9128{ 9129 int Rd, Rs, Rn; 9130 9131 Rd = inst.operands[0].reg; 9132 Rs = (inst.operands[1].present 9133 ? inst.operands[1].reg /* Rd, Rs, foo */ 9134 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 9135 9136 if (Rd == REG_PC) 9137 set_it_insn_type_last (); 9138 9139 if (unified_syntax) 9140 { 9141 bfd_boolean flags; 9142 bfd_boolean narrow; 9143 int opcode; 9144 9145 flags = (inst.instruction == T_MNEM_adds 9146 || inst.instruction == T_MNEM_subs); 9147 if (flags) 9148 narrow = !in_it_block (); 9149 else 9150 narrow = in_it_block (); 9151 if (!inst.operands[2].isreg) 9152 { 9153 int add; 9154 9155 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); 9156 9157 add = (inst.instruction == T_MNEM_add 9158 || inst.instruction == T_MNEM_adds); 9159 opcode = 0; 9160 if (inst.size_req != 4) 9161 { 9162 /* Attempt to use a narrow opcode, with relaxation if 9163 appropriate. */ 9164 if (Rd == REG_SP && Rs == REG_SP && !flags) 9165 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; 9166 else if (Rd <= 7 && Rs == REG_SP && add && !flags) 9167 opcode = T_MNEM_add_sp; 9168 else if (Rd <= 7 && Rs == REG_PC && add && !flags) 9169 opcode = T_MNEM_add_pc; 9170 else if (Rd <= 7 && Rs <= 7 && narrow) 9171 { 9172 if (flags) 9173 opcode = add ? T_MNEM_addis : T_MNEM_subis; 9174 else 9175 opcode = add ? T_MNEM_addi : T_MNEM_subi; 9176 } 9177 if (opcode) 9178 { 9179 inst.instruction = THUMB_OP16(opcode); 9180 inst.instruction |= (Rd << 4) | Rs; 9181 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 9182 if (inst.size_req != 2) 9183 inst.relax = opcode; 9184 } 9185 else 9186 constraint (inst.size_req == 2, BAD_HIREG); 9187 } 9188 if (inst.size_req == 4 9189 || (inst.size_req != 2 && !opcode)) 9190 { 9191 if (Rd == REG_PC) 9192 { 9193 constraint (add, BAD_PC); 9194 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, 9195 _("only SUBS PC, LR, #const allowed")); 9196 constraint (inst.reloc.exp.X_op != O_constant, 9197 _("expression too complex")); 9198 constraint (inst.reloc.exp.X_add_number < 0 9199 || inst.reloc.exp.X_add_number > 0xff, 9200 _("immediate value out of range")); 9201 inst.instruction = T2_SUBS_PC_LR 9202 | inst.reloc.exp.X_add_number; 9203 inst.reloc.type = BFD_RELOC_UNUSED; 9204 return; 9205 } 9206 else if (Rs == REG_PC) 9207 { 9208 /* Always use addw/subw. */ 9209 inst.instruction = add ? 0xf20f0000 : 0xf2af0000; 9210 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; 9211 } 9212 else 9213 { 9214 inst.instruction = THUMB_OP32 (inst.instruction); 9215 inst.instruction = (inst.instruction & 0xe1ffffff) 9216 | 0x10000000; 9217 if (flags) 9218 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 9219 else 9220 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; 9221 } 9222 inst.instruction |= Rd << 8; 9223 inst.instruction |= Rs << 16; 9224 } 9225 } 9226 else 9227 { 9228 Rn = inst.operands[2].reg; 9229 /* See if we can do this with a 16-bit instruction. */ 9230 if (!inst.operands[2].shifted && inst.size_req != 4) 9231 { 9232 if (Rd > 7 || Rs > 7 || Rn > 7) 9233 narrow = FALSE; 9234 9235 if (narrow) 9236 { 9237 inst.instruction = ((inst.instruction == T_MNEM_adds 9238 || inst.instruction == T_MNEM_add) 9239 ? T_OPCODE_ADD_R3 9240 : T_OPCODE_SUB_R3); 9241 inst.instruction |= Rd | (Rs << 3) | (Rn << 6); 9242 return; 9243 } 9244 9245 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) 9246 { 9247 /* Thumb-1 cores (except v6-M) require at least one high 9248 register in a narrow non flag setting add. */ 9249 if (Rd > 7 || Rn > 7 9250 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) 9251 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) 9252 { 9253 if (Rd == Rn) 9254 { 9255 Rn = Rs; 9256 Rs = Rd; 9257 } 9258 inst.instruction = T_OPCODE_ADD_HI; 9259 inst.instruction |= (Rd & 8) << 4; 9260 inst.instruction |= (Rd & 7); 9261 inst.instruction |= Rn << 3; 9262 return; 9263 } 9264 } 9265 } 9266 9267 constraint (Rd == REG_PC, BAD_PC); 9268 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); 9269 constraint (Rs == REG_PC, BAD_PC); 9270 reject_bad_reg (Rn); 9271 9272 /* If we get here, it can't be done in 16 bits. */ 9273 constraint (inst.operands[2].shifted && inst.operands[2].immisreg, 9274 _("shift must be constant")); 9275 inst.instruction = THUMB_OP32 (inst.instruction); 9276 inst.instruction |= Rd << 8; 9277 inst.instruction |= Rs << 16; 9278 encode_thumb32_shifted_operand (2); 9279 } 9280 } 9281 else 9282 { 9283 constraint (inst.instruction == T_MNEM_adds 9284 || inst.instruction == T_MNEM_subs, 9285 BAD_THUMB32); 9286 9287 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ 9288 { 9289 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) 9290 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), 9291 BAD_HIREG); 9292 9293 inst.instruction = (inst.instruction == T_MNEM_add 9294 ? 0x0000 : 0x8000); 9295 inst.instruction |= (Rd << 4) | Rs; 9296 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 9297 return; 9298 } 9299 9300 Rn = inst.operands[2].reg; 9301 constraint (inst.operands[2].shifted, _("unshifted register required")); 9302 9303 /* We now have Rd, Rs, and Rn set to registers. */ 9304 if (Rd > 7 || Rs > 7 || Rn > 7) 9305 { 9306 /* Can't do this for SUB. */ 9307 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); 9308 inst.instruction = T_OPCODE_ADD_HI; 9309 inst.instruction |= (Rd & 8) << 4; 9310 inst.instruction |= (Rd & 7); 9311 if (Rs == Rd) 9312 inst.instruction |= Rn << 3; 9313 else if (Rn == Rd) 9314 inst.instruction |= Rs << 3; 9315 else 9316 constraint (1, _("dest must overlap one source register")); 9317 } 9318 else 9319 { 9320 inst.instruction = (inst.instruction == T_MNEM_add 9321 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); 9322 inst.instruction |= Rd | (Rs << 3) | (Rn << 6); 9323 } 9324 } 9325} 9326 9327static void 9328do_t_adr (void) 9329{ 9330 unsigned Rd; 9331 9332 Rd = inst.operands[0].reg; 9333 reject_bad_reg (Rd); 9334 9335 if (unified_syntax && inst.size_req == 0 && Rd <= 7) 9336 { 9337 /* Defer to section relaxation. */ 9338 inst.relax = inst.instruction; 9339 inst.instruction = THUMB_OP16 (inst.instruction); 9340 inst.instruction |= Rd << 4; 9341 } 9342 else if (unified_syntax && inst.size_req != 2) 9343 { 9344 /* Generate a 32-bit opcode. */ 9345 inst.instruction = THUMB_OP32 (inst.instruction); 9346 inst.instruction |= Rd << 8; 9347 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; 9348 inst.reloc.pc_rel = 1; 9349 } 9350 else 9351 { 9352 /* Generate a 16-bit opcode. */ 9353 inst.instruction = THUMB_OP16 (inst.instruction); 9354 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 9355 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ 9356 inst.reloc.pc_rel = 1; 9357 9358 inst.instruction |= Rd << 4; 9359 } 9360} 9361 9362/* Arithmetic instructions for which there is just one 16-bit 9363 instruction encoding, and it allows only two low registers. 9364 For maximal compatibility with ARM syntax, we allow three register 9365 operands even when Thumb-32 instructions are not available, as long 9366 as the first two are identical. For instance, both "sbc r0,r1" and 9367 "sbc r0,r0,r1" are allowed. */ 9368static void 9369do_t_arit3 (void) 9370{ 9371 int Rd, Rs, Rn; 9372 9373 Rd = inst.operands[0].reg; 9374 Rs = (inst.operands[1].present 9375 ? inst.operands[1].reg /* Rd, Rs, foo */ 9376 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 9377 Rn = inst.operands[2].reg; 9378 9379 reject_bad_reg (Rd); 9380 reject_bad_reg (Rs); 9381 if (inst.operands[2].isreg) 9382 reject_bad_reg (Rn); 9383 9384 if (unified_syntax) 9385 { 9386 if (!inst.operands[2].isreg) 9387 { 9388 /* For an immediate, we always generate a 32-bit opcode; 9389 section relaxation will shrink it later if possible. */ 9390 inst.instruction = THUMB_OP32 (inst.instruction); 9391 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 9392 inst.instruction |= Rd << 8; 9393 inst.instruction |= Rs << 16; 9394 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 9395 } 9396 else 9397 { 9398 bfd_boolean narrow; 9399 9400 /* See if we can do this with a 16-bit instruction. */ 9401 if (THUMB_SETS_FLAGS (inst.instruction)) 9402 narrow = !in_it_block (); 9403 else 9404 narrow = in_it_block (); 9405 9406 if (Rd > 7 || Rn > 7 || Rs > 7) 9407 narrow = FALSE; 9408 if (inst.operands[2].shifted) 9409 narrow = FALSE; 9410 if (inst.size_req == 4) 9411 narrow = FALSE; 9412 9413 if (narrow 9414 && Rd == Rs) 9415 { 9416 inst.instruction = THUMB_OP16 (inst.instruction); 9417 inst.instruction |= Rd; 9418 inst.instruction |= Rn << 3; 9419 return; 9420 } 9421 9422 /* If we get here, it can't be done in 16 bits. */ 9423 constraint (inst.operands[2].shifted 9424 && inst.operands[2].immisreg, 9425 _("shift must be constant")); 9426 inst.instruction = THUMB_OP32 (inst.instruction); 9427 inst.instruction |= Rd << 8; 9428 inst.instruction |= Rs << 16; 9429 encode_thumb32_shifted_operand (2); 9430 } 9431 } 9432 else 9433 { 9434 /* On its face this is a lie - the instruction does set the 9435 flags. However, the only supported mnemonic in this mode 9436 says it doesn't. */ 9437 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 9438 9439 constraint (!inst.operands[2].isreg || inst.operands[2].shifted, 9440 _("unshifted register required")); 9441 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); 9442 constraint (Rd != Rs, 9443 _("dest and source1 must be the same register")); 9444 9445 inst.instruction = THUMB_OP16 (inst.instruction); 9446 inst.instruction |= Rd; 9447 inst.instruction |= Rn << 3; 9448 } 9449} 9450 9451/* Similarly, but for instructions where the arithmetic operation is 9452 commutative, so we can allow either of them to be different from 9453 the destination operand in a 16-bit instruction. For instance, all 9454 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are 9455 accepted. */ 9456static void 9457do_t_arit3c (void) 9458{ 9459 int Rd, Rs, Rn; 9460 9461 Rd = inst.operands[0].reg; 9462 Rs = (inst.operands[1].present 9463 ? inst.operands[1].reg /* Rd, Rs, foo */ 9464 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 9465 Rn = inst.operands[2].reg; 9466 9467 reject_bad_reg (Rd); 9468 reject_bad_reg (Rs); 9469 if (inst.operands[2].isreg) 9470 reject_bad_reg (Rn); 9471 9472 if (unified_syntax) 9473 { 9474 if (!inst.operands[2].isreg) 9475 { 9476 /* For an immediate, we always generate a 32-bit opcode; 9477 section relaxation will shrink it later if possible. */ 9478 inst.instruction = THUMB_OP32 (inst.instruction); 9479 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 9480 inst.instruction |= Rd << 8; 9481 inst.instruction |= Rs << 16; 9482 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 9483 } 9484 else 9485 { 9486 bfd_boolean narrow; 9487 9488 /* See if we can do this with a 16-bit instruction. */ 9489 if (THUMB_SETS_FLAGS (inst.instruction)) 9490 narrow = !in_it_block (); 9491 else 9492 narrow = in_it_block (); 9493 9494 if (Rd > 7 || Rn > 7 || Rs > 7) 9495 narrow = FALSE; 9496 if (inst.operands[2].shifted) 9497 narrow = FALSE; 9498 if (inst.size_req == 4) 9499 narrow = FALSE; 9500 9501 if (narrow) 9502 { 9503 if (Rd == Rs) 9504 { 9505 inst.instruction = THUMB_OP16 (inst.instruction); 9506 inst.instruction |= Rd; 9507 inst.instruction |= Rn << 3; 9508 return; 9509 } 9510 if (Rd == Rn) 9511 { 9512 inst.instruction = THUMB_OP16 (inst.instruction); 9513 inst.instruction |= Rd; 9514 inst.instruction |= Rs << 3; 9515 return; 9516 } 9517 } 9518 9519 /* If we get here, it can't be done in 16 bits. */ 9520 constraint (inst.operands[2].shifted 9521 && inst.operands[2].immisreg, 9522 _("shift must be constant")); 9523 inst.instruction = THUMB_OP32 (inst.instruction); 9524 inst.instruction |= Rd << 8; 9525 inst.instruction |= Rs << 16; 9526 encode_thumb32_shifted_operand (2); 9527 } 9528 } 9529 else 9530 { 9531 /* On its face this is a lie - the instruction does set the 9532 flags. However, the only supported mnemonic in this mode 9533 says it doesn't. */ 9534 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 9535 9536 constraint (!inst.operands[2].isreg || inst.operands[2].shifted, 9537 _("unshifted register required")); 9538 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); 9539 9540 inst.instruction = THUMB_OP16 (inst.instruction); 9541 inst.instruction |= Rd; 9542 9543 if (Rd == Rs) 9544 inst.instruction |= Rn << 3; 9545 else if (Rd == Rn) 9546 inst.instruction |= Rs << 3; 9547 else 9548 constraint (1, _("dest must overlap one source register")); 9549 } 9550} 9551 9552static void 9553do_t_barrier (void) 9554{ 9555 if (inst.operands[0].present) 9556 { 9557 constraint ((inst.instruction & 0xf0) != 0x40 9558 && inst.operands[0].imm > 0xf 9559 && inst.operands[0].imm < 0x0, 9560 _("bad barrier type")); 9561 inst.instruction |= inst.operands[0].imm; 9562 } 9563 else 9564 inst.instruction |= 0xf; 9565} 9566 9567static void 9568do_t_bfc (void) 9569{ 9570 unsigned Rd; 9571 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; 9572 constraint (msb > 32, _("bit-field extends past end of register")); 9573 /* The instruction encoding stores the LSB and MSB, 9574 not the LSB and width. */ 9575 Rd = inst.operands[0].reg; 9576 reject_bad_reg (Rd); 9577 inst.instruction |= Rd << 8; 9578 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; 9579 inst.instruction |= (inst.operands[1].imm & 0x03) << 6; 9580 inst.instruction |= msb - 1; 9581} 9582 9583static void 9584do_t_bfi (void) 9585{ 9586 int Rd, Rn; 9587 unsigned int msb; 9588 9589 Rd = inst.operands[0].reg; 9590 reject_bad_reg (Rd); 9591 9592 /* #0 in second position is alternative syntax for bfc, which is 9593 the same instruction but with REG_PC in the Rm field. */ 9594 if (!inst.operands[1].isreg) 9595 Rn = REG_PC; 9596 else 9597 { 9598 Rn = inst.operands[1].reg; 9599 reject_bad_reg (Rn); 9600 } 9601 9602 msb = inst.operands[2].imm + inst.operands[3].imm; 9603 constraint (msb > 32, _("bit-field extends past end of register")); 9604 /* The instruction encoding stores the LSB and MSB, 9605 not the LSB and width. */ 9606 inst.instruction |= Rd << 8; 9607 inst.instruction |= Rn << 16; 9608 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; 9609 inst.instruction |= (inst.operands[2].imm & 0x03) << 6; 9610 inst.instruction |= msb - 1; 9611} 9612 9613static void 9614do_t_bfx (void) 9615{ 9616 unsigned Rd, Rn; 9617 9618 Rd = inst.operands[0].reg; 9619 Rn = inst.operands[1].reg; 9620 9621 reject_bad_reg (Rd); 9622 reject_bad_reg (Rn); 9623 9624 constraint (inst.operands[2].imm + inst.operands[3].imm > 32, 9625 _("bit-field extends past end of register")); 9626 inst.instruction |= Rd << 8; 9627 inst.instruction |= Rn << 16; 9628 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; 9629 inst.instruction |= (inst.operands[2].imm & 0x03) << 6; 9630 inst.instruction |= inst.operands[3].imm - 1; 9631} 9632 9633/* ARM V5 Thumb BLX (argument parse) 9634 BLX <target_addr> which is BLX(1) 9635 BLX <Rm> which is BLX(2) 9636 Unfortunately, there are two different opcodes for this mnemonic. 9637 So, the insns[].value is not used, and the code here zaps values 9638 into inst.instruction. 9639 9640 ??? How to take advantage of the additional two bits of displacement 9641 available in Thumb32 mode? Need new relocation? */ 9642 9643static void 9644do_t_blx (void) 9645{ 9646 set_it_insn_type_last (); 9647 9648 if (inst.operands[0].isreg) 9649 { 9650 constraint (inst.operands[0].reg == REG_PC, BAD_PC); 9651 /* We have a register, so this is BLX(2). */ 9652 inst.instruction |= inst.operands[0].reg << 3; 9653 } 9654 else 9655 { 9656 /* No register. This must be BLX(1). */ 9657 inst.instruction = 0xf000e800; 9658 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; 9659 inst.reloc.pc_rel = 1; 9660 } 9661} 9662 9663static void 9664do_t_branch (void) 9665{ 9666 int opcode; 9667 int cond; 9668 int reloc; 9669 9670 cond = inst.cond; 9671 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); 9672 9673 if (in_it_block ()) 9674 { 9675 /* Conditional branches inside IT blocks are encoded as unconditional 9676 branches. */ 9677 cond = COND_ALWAYS; 9678 } 9679 else 9680 cond = inst.cond; 9681 9682 if (cond != COND_ALWAYS) 9683 opcode = T_MNEM_bcond; 9684 else 9685 opcode = inst.instruction; 9686 9687 if (unified_syntax 9688 && (inst.size_req == 4 9689 || (inst.size_req != 2 && inst.operands[0].hasreloc))) 9690 { 9691 inst.instruction = THUMB_OP32(opcode); 9692 if (cond == COND_ALWAYS) 9693 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25; 9694 else 9695 { 9696 gas_assert (cond != 0xF); 9697 inst.instruction |= cond << 22; 9698 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20; 9699 } 9700 } 9701 else 9702 { 9703 inst.instruction = THUMB_OP16(opcode); 9704 if (cond == COND_ALWAYS) 9705 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12; 9706 else 9707 { 9708 inst.instruction |= cond << 8; 9709 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9; 9710 } 9711 /* Allow section relaxation. */ 9712 if (unified_syntax && inst.size_req != 2) 9713 inst.relax = opcode; 9714 } 9715 inst.reloc.type = reloc; 9716 inst.reloc.pc_rel = 1; 9717} 9718 9719static void 9720do_t_bkpt (void) 9721{ 9722 constraint (inst.cond != COND_ALWAYS, 9723 _("instruction is always unconditional")); 9724 if (inst.operands[0].present) 9725 { 9726 constraint (inst.operands[0].imm > 255, 9727 _("immediate value out of range")); 9728 inst.instruction |= inst.operands[0].imm; 9729 set_it_insn_type (NEUTRAL_IT_INSN); 9730 } 9731} 9732 9733static void 9734do_t_branch23 (void) 9735{ 9736 set_it_insn_type_last (); 9737 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; 9738 inst.reloc.pc_rel = 1; 9739 9740#if defined(OBJ_COFF) 9741 /* If the destination of the branch is a defined symbol which does not have 9742 the THUMB_FUNC attribute, then we must be calling a function which has 9743 the (interfacearm) attribute. We look for the Thumb entry point to that 9744 function and change the branch to refer to that function instead. */ 9745 if ( inst.reloc.exp.X_op == O_symbol 9746 && inst.reloc.exp.X_add_symbol != NULL 9747 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) 9748 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) 9749 inst.reloc.exp.X_add_symbol = 9750 find_real_start (inst.reloc.exp.X_add_symbol); 9751#endif 9752} 9753 9754static void 9755do_t_bx (void) 9756{ 9757 set_it_insn_type_last (); 9758 inst.instruction |= inst.operands[0].reg << 3; 9759 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc 9760 should cause the alignment to be checked once it is known. This is 9761 because BX PC only works if the instruction is word aligned. */ 9762} 9763 9764static void 9765do_t_bxj (void) 9766{ 9767 int Rm; 9768 9769 set_it_insn_type_last (); 9770 Rm = inst.operands[0].reg; 9771 reject_bad_reg (Rm); 9772 inst.instruction |= Rm << 16; 9773} 9774 9775static void 9776do_t_clz (void) 9777{ 9778 unsigned Rd; 9779 unsigned Rm; 9780 9781 Rd = inst.operands[0].reg; 9782 Rm = inst.operands[1].reg; 9783 9784 reject_bad_reg (Rd); 9785 reject_bad_reg (Rm); 9786 9787 inst.instruction |= Rd << 8; 9788 inst.instruction |= Rm << 16; 9789 inst.instruction |= Rm; 9790} 9791 9792static void 9793do_t_cps (void) 9794{ 9795 set_it_insn_type (OUTSIDE_IT_INSN); 9796 inst.instruction |= inst.operands[0].imm; 9797} 9798 9799static void 9800do_t_cpsi (void) 9801{ 9802 set_it_insn_type (OUTSIDE_IT_INSN); 9803 if (unified_syntax 9804 && (inst.operands[1].present || inst.size_req == 4) 9805 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) 9806 { 9807 unsigned int imod = (inst.instruction & 0x0030) >> 4; 9808 inst.instruction = 0xf3af8000; 9809 inst.instruction |= imod << 9; 9810 inst.instruction |= inst.operands[0].imm << 5; 9811 if (inst.operands[1].present) 9812 inst.instruction |= 0x100 | inst.operands[1].imm; 9813 } 9814 else 9815 { 9816 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) 9817 && (inst.operands[0].imm & 4), 9818 _("selected processor does not support 'A' form " 9819 "of this instruction")); 9820 constraint (inst.operands[1].present || inst.size_req == 4, 9821 _("Thumb does not support the 2-argument " 9822 "form of this instruction")); 9823 inst.instruction |= inst.operands[0].imm; 9824 } 9825} 9826 9827/* THUMB CPY instruction (argument parse). */ 9828 9829static void 9830do_t_cpy (void) 9831{ 9832 if (inst.size_req == 4) 9833 { 9834 inst.instruction = THUMB_OP32 (T_MNEM_mov); 9835 inst.instruction |= inst.operands[0].reg << 8; 9836 inst.instruction |= inst.operands[1].reg; 9837 } 9838 else 9839 { 9840 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9841 inst.instruction |= (inst.operands[0].reg & 0x7); 9842 inst.instruction |= inst.operands[1].reg << 3; 9843 } 9844} 9845 9846static void 9847do_t_cbz (void) 9848{ 9849 set_it_insn_type (OUTSIDE_IT_INSN); 9850 constraint (inst.operands[0].reg > 7, BAD_HIREG); 9851 inst.instruction |= inst.operands[0].reg; 9852 inst.reloc.pc_rel = 1; 9853 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; 9854} 9855 9856static void 9857do_t_dbg (void) 9858{ 9859 inst.instruction |= inst.operands[0].imm; 9860} 9861 9862static void 9863do_t_div (void) 9864{ 9865 unsigned Rd, Rn, Rm; 9866 9867 Rd = inst.operands[0].reg; 9868 Rn = (inst.operands[1].present 9869 ? inst.operands[1].reg : Rd); 9870 Rm = inst.operands[2].reg; 9871 9872 reject_bad_reg (Rd); 9873 reject_bad_reg (Rn); 9874 reject_bad_reg (Rm); 9875 9876 inst.instruction |= Rd << 8; 9877 inst.instruction |= Rn << 16; 9878 inst.instruction |= Rm; 9879} 9880 9881static void 9882do_t_hint (void) 9883{ 9884 if (unified_syntax && inst.size_req == 4) 9885 inst.instruction = THUMB_OP32 (inst.instruction); 9886 else 9887 inst.instruction = THUMB_OP16 (inst.instruction); 9888} 9889 9890static void 9891do_t_it (void) 9892{ 9893 unsigned int cond = inst.operands[0].imm; 9894 9895 set_it_insn_type (IT_INSN); 9896 now_it.mask = (inst.instruction & 0xf) | 0x10; 9897 now_it.cc = cond; 9898 9899 /* If the condition is a negative condition, invert the mask. */ 9900 if ((cond & 0x1) == 0x0) 9901 { 9902 unsigned int mask = inst.instruction & 0x000f; 9903 9904 if ((mask & 0x7) == 0) 9905 /* no conversion needed */; 9906 else if ((mask & 0x3) == 0) 9907 mask ^= 0x8; 9908 else if ((mask & 0x1) == 0) 9909 mask ^= 0xC; 9910 else 9911 mask ^= 0xE; 9912 9913 inst.instruction &= 0xfff0; 9914 inst.instruction |= mask; 9915 } 9916 9917 inst.instruction |= cond << 4; 9918} 9919 9920/* Helper function used for both push/pop and ldm/stm. */ 9921static void 9922encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) 9923{ 9924 bfd_boolean load; 9925 9926 load = (inst.instruction & (1 << 20)) != 0; 9927 9928 if (mask & (1 << 13)) 9929 inst.error = _("SP not allowed in register list"); 9930 9931 if ((mask & (1 << base)) != 0 9932 && writeback) 9933 inst.error = _("having the base register in the register list when " 9934 "using write back is UNPREDICTABLE"); 9935 9936 if (load) 9937 { 9938 if (mask & (1 << 15)) 9939 { 9940 if (mask & (1 << 14)) 9941 inst.error = _("LR and PC should not both be in register list"); 9942 else 9943 set_it_insn_type_last (); 9944 } 9945 } 9946 else 9947 { 9948 if (mask & (1 << 15)) 9949 inst.error = _("PC not allowed in register list"); 9950 } 9951 9952 if ((mask & (mask - 1)) == 0) 9953 { 9954 /* Single register transfers implemented as str/ldr. */ 9955 if (writeback) 9956 { 9957 if (inst.instruction & (1 << 23)) 9958 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ 9959 else 9960 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ 9961 } 9962 else 9963 { 9964 if (inst.instruction & (1 << 23)) 9965 inst.instruction = 0x00800000; /* ia -> [base] */ 9966 else 9967 inst.instruction = 0x00000c04; /* db -> [base, #-4] */ 9968 } 9969 9970 inst.instruction |= 0xf8400000; 9971 if (load) 9972 inst.instruction |= 0x00100000; 9973 9974 mask = ffs (mask) - 1; 9975 mask <<= 12; 9976 } 9977 else if (writeback) 9978 inst.instruction |= WRITE_BACK; 9979 9980 inst.instruction |= mask; 9981 inst.instruction |= base << 16; 9982} 9983 9984static void 9985do_t_ldmstm (void) 9986{ 9987 /* This really doesn't seem worth it. */ 9988 constraint (inst.reloc.type != BFD_RELOC_UNUSED, 9989 _("expression too complex")); 9990 constraint (inst.operands[1].writeback, 9991 _("Thumb load/store multiple does not support {reglist}^")); 9992 9993 if (unified_syntax) 9994 { 9995 bfd_boolean narrow; 9996 unsigned mask; 9997 9998 narrow = FALSE; 9999 /* See if we can use a 16-bit instruction. */ 10000 if (inst.instruction < 0xffff /* not ldmdb/stmdb */ 10001 && inst.size_req != 4 10002 && !(inst.operands[1].imm & ~0xff)) 10003 { 10004 mask = 1 << inst.operands[0].reg; 10005 10006 if (inst.operands[0].reg <= 7) 10007 { 10008 if (inst.instruction == T_MNEM_stmia 10009 ? inst.operands[0].writeback 10010 : (inst.operands[0].writeback 10011 == !(inst.operands[1].imm & mask))) 10012 { 10013 if (inst.instruction == T_MNEM_stmia 10014 && (inst.operands[1].imm & mask) 10015 && (inst.operands[1].imm & (mask - 1))) 10016 as_warn (_("value stored for r%d is UNKNOWN"), 10017 inst.operands[0].reg); 10018 10019 inst.instruction = THUMB_OP16 (inst.instruction); 10020 inst.instruction |= inst.operands[0].reg << 8; 10021 inst.instruction |= inst.operands[1].imm; 10022 narrow = TRUE; 10023 } 10024 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) 10025 { 10026 /* This means 1 register in reg list one of 3 situations: 10027 1. Instruction is stmia, but without writeback. 10028 2. lmdia without writeback, but with Rn not in 10029 reglist. 10030 3. ldmia with writeback, but with Rn in reglist. 10031 Case 3 is UNPREDICTABLE behaviour, so we handle 10032 case 1 and 2 which can be converted into a 16-bit 10033 str or ldr. The SP cases are handled below. */ 10034 unsigned long opcode; 10035 /* First, record an error for Case 3. */ 10036 if (inst.operands[1].imm & mask 10037 && inst.operands[0].writeback) 10038 inst.error = 10039 _("having the base register in the register list when " 10040 "using write back is UNPREDICTABLE"); 10041 10042 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str 10043 : T_MNEM_ldr); 10044 inst.instruction = THUMB_OP16 (opcode); 10045 inst.instruction |= inst.operands[0].reg << 3; 10046 inst.instruction |= (ffs (inst.operands[1].imm)-1); 10047 narrow = TRUE; 10048 } 10049 } 10050 else if (inst.operands[0] .reg == REG_SP) 10051 { 10052 if (inst.operands[0].writeback) 10053 { 10054 inst.instruction = 10055 THUMB_OP16 (inst.instruction == T_MNEM_stmia 10056 ? T_MNEM_push : T_MNEM_pop); 10057 inst.instruction |= inst.operands[1].imm; 10058 narrow = TRUE; 10059 } 10060 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) 10061 { 10062 inst.instruction = 10063 THUMB_OP16 (inst.instruction == T_MNEM_stmia 10064 ? T_MNEM_str_sp : T_MNEM_ldr_sp); 10065 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8); 10066 narrow = TRUE; 10067 } 10068 } 10069 } 10070 10071 if (!narrow) 10072 { 10073 if (inst.instruction < 0xffff) 10074 inst.instruction = THUMB_OP32 (inst.instruction); 10075 10076 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm, 10077 inst.operands[0].writeback); 10078 } 10079 } 10080 else 10081 { 10082 constraint (inst.operands[0].reg > 7 10083 || (inst.operands[1].imm & ~0xff), BAD_HIREG); 10084 constraint (inst.instruction != T_MNEM_ldmia 10085 && inst.instruction != T_MNEM_stmia, 10086 _("Thumb-2 instruction only valid in unified syntax")); 10087 if (inst.instruction == T_MNEM_stmia) 10088 { 10089 if (!inst.operands[0].writeback) 10090 as_warn (_("this instruction will write back the base register")); 10091 if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) 10092 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) 10093 as_warn (_("value stored for r%d is UNKNOWN"), 10094 inst.operands[0].reg); 10095 } 10096 else 10097 { 10098 if (!inst.operands[0].writeback 10099 && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) 10100 as_warn (_("this instruction will write back the base register")); 10101 else if (inst.operands[0].writeback 10102 && (inst.operands[1].imm & (1 << inst.operands[0].reg))) 10103 as_warn (_("this instruction will not write back the base register")); 10104 } 10105 10106 inst.instruction = THUMB_OP16 (inst.instruction); 10107 inst.instruction |= inst.operands[0].reg << 8; 10108 inst.instruction |= inst.operands[1].imm; 10109 } 10110} 10111 10112static void 10113do_t_ldrex (void) 10114{ 10115 constraint (!inst.operands[1].isreg || !inst.operands[1].preind 10116 || inst.operands[1].postind || inst.operands[1].writeback 10117 || inst.operands[1].immisreg || inst.operands[1].shifted 10118 || inst.operands[1].negative, 10119 BAD_ADDR_MODE); 10120 10121 constraint ((inst.operands[1].reg == REG_PC), BAD_PC); 10122 10123 inst.instruction |= inst.operands[0].reg << 12; 10124 inst.instruction |= inst.operands[1].reg << 16; 10125 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; 10126} 10127 10128static void 10129do_t_ldrexd (void) 10130{ 10131 if (!inst.operands[1].present) 10132 { 10133 constraint (inst.operands[0].reg == REG_LR, 10134 _("r14 not allowed as first register " 10135 "when second register is omitted")); 10136 inst.operands[1].reg = inst.operands[0].reg + 1; 10137 } 10138 constraint (inst.operands[0].reg == inst.operands[1].reg, 10139 BAD_OVERLAP); 10140 10141 inst.instruction |= inst.operands[0].reg << 12; 10142 inst.instruction |= inst.operands[1].reg << 8; 10143 inst.instruction |= inst.operands[2].reg << 16; 10144} 10145 10146static void 10147do_t_ldst (void) 10148{ 10149 unsigned long opcode; 10150 int Rn; 10151 10152 if (inst.operands[0].isreg 10153 && !inst.operands[0].preind 10154 && inst.operands[0].reg == REG_PC) 10155 set_it_insn_type_last (); 10156 10157 opcode = inst.instruction; 10158 if (unified_syntax) 10159 { 10160 if (!inst.operands[1].isreg) 10161 { 10162 if (opcode <= 0xffff) 10163 inst.instruction = THUMB_OP32 (opcode); 10164 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) 10165 return; 10166 } 10167 if (inst.operands[1].isreg 10168 && !inst.operands[1].writeback 10169 && !inst.operands[1].shifted && !inst.operands[1].postind 10170 && !inst.operands[1].negative && inst.operands[0].reg <= 7 10171 && opcode <= 0xffff 10172 && inst.size_req != 4) 10173 { 10174 /* Insn may have a 16-bit form. */ 10175 Rn = inst.operands[1].reg; 10176 if (inst.operands[1].immisreg) 10177 { 10178 inst.instruction = THUMB_OP16 (opcode); 10179 /* [Rn, Rik] */ 10180 if (Rn <= 7 && inst.operands[1].imm <= 7) 10181 goto op16; 10182 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) 10183 reject_bad_reg (inst.operands[1].imm); 10184 } 10185 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh 10186 && opcode != T_MNEM_ldrsb) 10187 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) 10188 || (Rn == REG_SP && opcode == T_MNEM_str)) 10189 { 10190 /* [Rn, #const] */ 10191 if (Rn > 7) 10192 { 10193 if (Rn == REG_PC) 10194 { 10195 if (inst.reloc.pc_rel) 10196 opcode = T_MNEM_ldr_pc2; 10197 else 10198 opcode = T_MNEM_ldr_pc; 10199 } 10200 else 10201 { 10202 if (opcode == T_MNEM_ldr) 10203 opcode = T_MNEM_ldr_sp; 10204 else 10205 opcode = T_MNEM_str_sp; 10206 } 10207 inst.instruction = inst.operands[0].reg << 8; 10208 } 10209 else 10210 { 10211 inst.instruction = inst.operands[0].reg; 10212 inst.instruction |= inst.operands[1].reg << 3; 10213 } 10214 inst.instruction |= THUMB_OP16 (opcode); 10215 if (inst.size_req == 2) 10216 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 10217 else 10218 inst.relax = opcode; 10219 return; 10220 } 10221 } 10222 /* Definitely a 32-bit variant. */ 10223 10224 /* Do some validations regarding addressing modes. */ 10225 if (inst.operands[1].immisreg && opcode != T_MNEM_ldr 10226 && opcode != T_MNEM_str) 10227 reject_bad_reg (inst.operands[1].imm); 10228 10229 inst.instruction = THUMB_OP32 (opcode); 10230 inst.instruction |= inst.operands[0].reg << 12; 10231 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); 10232 return; 10233 } 10234 10235 constraint (inst.operands[0].reg > 7, BAD_HIREG); 10236 10237 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) 10238 { 10239 /* Only [Rn,Rm] is acceptable. */ 10240 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); 10241 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg 10242 || inst.operands[1].postind || inst.operands[1].shifted 10243 || inst.operands[1].negative, 10244 _("Thumb does not support this addressing mode")); 10245 inst.instruction = THUMB_OP16 (inst.instruction); 10246 goto op16; 10247 } 10248 10249 inst.instruction = THUMB_OP16 (inst.instruction); 10250 if (!inst.operands[1].isreg) 10251 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) 10252 return; 10253 10254 constraint (!inst.operands[1].preind 10255 || inst.operands[1].shifted 10256 || inst.operands[1].writeback, 10257 _("Thumb does not support this addressing mode")); 10258 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) 10259 { 10260 constraint (inst.instruction & 0x0600, 10261 _("byte or halfword not valid for base register")); 10262 constraint (inst.operands[1].reg == REG_PC 10263 && !(inst.instruction & THUMB_LOAD_BIT), 10264 _("r15 based store not allowed")); 10265 constraint (inst.operands[1].immisreg, 10266 _("invalid base register for register offset")); 10267 10268 if (inst.operands[1].reg == REG_PC) 10269 inst.instruction = T_OPCODE_LDR_PC; 10270 else if (inst.instruction & THUMB_LOAD_BIT) 10271 inst.instruction = T_OPCODE_LDR_SP; 10272 else 10273 inst.instruction = T_OPCODE_STR_SP; 10274 10275 inst.instruction |= inst.operands[0].reg << 8; 10276 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 10277 return; 10278 } 10279 10280 constraint (inst.operands[1].reg > 7, BAD_HIREG); 10281 if (!inst.operands[1].immisreg) 10282 { 10283 /* Immediate offset. */ 10284 inst.instruction |= inst.operands[0].reg; 10285 inst.instruction |= inst.operands[1].reg << 3; 10286 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 10287 return; 10288 } 10289 10290 /* Register offset. */ 10291 constraint (inst.operands[1].imm > 7, BAD_HIREG); 10292 constraint (inst.operands[1].negative, 10293 _("Thumb does not support this addressing mode")); 10294 10295 op16: 10296 switch (inst.instruction) 10297 { 10298 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; 10299 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; 10300 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; 10301 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; 10302 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; 10303 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; 10304 case 0x5600 /* ldrsb */: 10305 case 0x5e00 /* ldrsh */: break; 10306 default: abort (); 10307 } 10308 10309 inst.instruction |= inst.operands[0].reg; 10310 inst.instruction |= inst.operands[1].reg << 3; 10311 inst.instruction |= inst.operands[1].imm << 6; 10312} 10313 10314static void 10315do_t_ldstd (void) 10316{ 10317 if (!inst.operands[1].present) 10318 { 10319 inst.operands[1].reg = inst.operands[0].reg + 1; 10320 constraint (inst.operands[0].reg == REG_LR, 10321 _("r14 not allowed here")); 10322 } 10323 inst.instruction |= inst.operands[0].reg << 12; 10324 inst.instruction |= inst.operands[1].reg << 8; 10325 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); 10326} 10327 10328static void 10329do_t_ldstt (void) 10330{ 10331 inst.instruction |= inst.operands[0].reg << 12; 10332 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); 10333} 10334 10335static void 10336do_t_mla (void) 10337{ 10338 unsigned Rd, Rn, Rm, Ra; 10339 10340 Rd = inst.operands[0].reg; 10341 Rn = inst.operands[1].reg; 10342 Rm = inst.operands[2].reg; 10343 Ra = inst.operands[3].reg; 10344 10345 reject_bad_reg (Rd); 10346 reject_bad_reg (Rn); 10347 reject_bad_reg (Rm); 10348 reject_bad_reg (Ra); 10349 10350 inst.instruction |= Rd << 8; 10351 inst.instruction |= Rn << 16; 10352 inst.instruction |= Rm; 10353 inst.instruction |= Ra << 12; 10354} 10355 10356static void 10357do_t_mlal (void) 10358{ 10359 unsigned RdLo, RdHi, Rn, Rm; 10360 10361 RdLo = inst.operands[0].reg; 10362 RdHi = inst.operands[1].reg; 10363 Rn = inst.operands[2].reg; 10364 Rm = inst.operands[3].reg; 10365 10366 reject_bad_reg (RdLo); 10367 reject_bad_reg (RdHi); 10368 reject_bad_reg (Rn); 10369 reject_bad_reg (Rm); 10370 10371 inst.instruction |= RdLo << 12; 10372 inst.instruction |= RdHi << 8; 10373 inst.instruction |= Rn << 16; 10374 inst.instruction |= Rm; 10375} 10376 10377static void 10378do_t_mov_cmp (void) 10379{ 10380 unsigned Rn, Rm; 10381 10382 Rn = inst.operands[0].reg; 10383 Rm = inst.operands[1].reg; 10384 10385 if (Rn == REG_PC) 10386 set_it_insn_type_last (); 10387 10388 if (unified_syntax) 10389 { 10390 int r0off = (inst.instruction == T_MNEM_mov 10391 || inst.instruction == T_MNEM_movs) ? 8 : 16; 10392 unsigned long opcode; 10393 bfd_boolean narrow; 10394 bfd_boolean low_regs; 10395 10396 low_regs = (Rn <= 7 && Rm <= 7); 10397 opcode = inst.instruction; 10398 if (in_it_block ()) 10399 narrow = opcode != T_MNEM_movs; 10400 else 10401 narrow = opcode != T_MNEM_movs || low_regs; 10402 if (inst.size_req == 4 10403 || inst.operands[1].shifted) 10404 narrow = FALSE; 10405 10406 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ 10407 if (opcode == T_MNEM_movs && inst.operands[1].isreg 10408 && !inst.operands[1].shifted 10409 && Rn == REG_PC 10410 && Rm == REG_LR) 10411 { 10412 inst.instruction = T2_SUBS_PC_LR; 10413 return; 10414 } 10415 10416 if (opcode == T_MNEM_cmp) 10417 { 10418 constraint (Rn == REG_PC, BAD_PC); 10419 if (narrow) 10420 { 10421 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, 10422 but valid. */ 10423 warn_deprecated_sp (Rm); 10424 /* R15 was documented as a valid choice for Rm in ARMv6, 10425 but as UNPREDICTABLE in ARMv7. ARM's proprietary 10426 tools reject R15, so we do too. */ 10427 constraint (Rm == REG_PC, BAD_PC); 10428 } 10429 else 10430 reject_bad_reg (Rm); 10431 } 10432 else if (opcode == T_MNEM_mov 10433 || opcode == T_MNEM_movs) 10434 { 10435 if (inst.operands[1].isreg) 10436 { 10437 if (opcode == T_MNEM_movs) 10438 { 10439 reject_bad_reg (Rn); 10440 reject_bad_reg (Rm); 10441 } 10442 else if (narrow) 10443 { 10444 /* This is mov.n. */ 10445 if ((Rn == REG_SP || Rn == REG_PC) 10446 && (Rm == REG_SP || Rm == REG_PC)) 10447 { 10448 as_warn (_("Use of r%u as a source register is " 10449 "deprecated when r%u is the destination " 10450 "register."), Rm, Rn); 10451 } 10452 } 10453 else 10454 { 10455 /* This is mov.w. */ 10456 constraint (Rn == REG_PC, BAD_PC); 10457 constraint (Rm == REG_PC, BAD_PC); 10458 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); 10459 } 10460 } 10461 else 10462 reject_bad_reg (Rn); 10463 } 10464 10465 if (!inst.operands[1].isreg) 10466 { 10467 /* Immediate operand. */ 10468 if (!in_it_block () && opcode == T_MNEM_mov) 10469 narrow = 0; 10470 if (low_regs && narrow) 10471 { 10472 inst.instruction = THUMB_OP16 (opcode); 10473 inst.instruction |= Rn << 8; 10474 if (inst.size_req == 2) 10475 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; 10476 else 10477 inst.relax = opcode; 10478 } 10479 else 10480 { 10481 inst.instruction = THUMB_OP32 (inst.instruction); 10482 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 10483 inst.instruction |= Rn << r0off; 10484 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 10485 } 10486 } 10487 else if (inst.operands[1].shifted && inst.operands[1].immisreg 10488 && (inst.instruction == T_MNEM_mov 10489 || inst.instruction == T_MNEM_movs)) 10490 { 10491 /* Register shifts are encoded as separate shift instructions. */ 10492 bfd_boolean flags = (inst.instruction == T_MNEM_movs); 10493 10494 if (in_it_block ()) 10495 narrow = !flags; 10496 else 10497 narrow = flags; 10498 10499 if (inst.size_req == 4) 10500 narrow = FALSE; 10501 10502 if (!low_regs || inst.operands[1].imm > 7) 10503 narrow = FALSE; 10504 10505 if (Rn != Rm) 10506 narrow = FALSE; 10507 10508 switch (inst.operands[1].shift_kind) 10509 { 10510 case SHIFT_LSL: 10511 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); 10512 break; 10513 case SHIFT_ASR: 10514 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); 10515 break; 10516 case SHIFT_LSR: 10517 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); 10518 break; 10519 case SHIFT_ROR: 10520 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); 10521 break; 10522 default: 10523 abort (); 10524 } 10525 10526 inst.instruction = opcode; 10527 if (narrow) 10528 { 10529 inst.instruction |= Rn; 10530 inst.instruction |= inst.operands[1].imm << 3; 10531 } 10532 else 10533 { 10534 if (flags) 10535 inst.instruction |= CONDS_BIT; 10536 10537 inst.instruction |= Rn << 8; 10538 inst.instruction |= Rm << 16; 10539 inst.instruction |= inst.operands[1].imm; 10540 } 10541 } 10542 else if (!narrow) 10543 { 10544 /* Some mov with immediate shift have narrow variants. 10545 Register shifts are handled above. */ 10546 if (low_regs && inst.operands[1].shifted 10547 && (inst.instruction == T_MNEM_mov 10548 || inst.instruction == T_MNEM_movs)) 10549 { 10550 if (in_it_block ()) 10551 narrow = (inst.instruction == T_MNEM_mov); 10552 else 10553 narrow = (inst.instruction == T_MNEM_movs); 10554 } 10555 10556 if (narrow) 10557 { 10558 switch (inst.operands[1].shift_kind) 10559 { 10560 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; 10561 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; 10562 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; 10563 default: narrow = FALSE; break; 10564 } 10565 } 10566 10567 if (narrow) 10568 { 10569 inst.instruction |= Rn; 10570 inst.instruction |= Rm << 3; 10571 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 10572 } 10573 else 10574 { 10575 inst.instruction = THUMB_OP32 (inst.instruction); 10576 inst.instruction |= Rn << r0off; 10577 encode_thumb32_shifted_operand (1); 10578 } 10579 } 10580 else 10581 switch (inst.instruction) 10582 { 10583 case T_MNEM_mov: 10584 inst.instruction = T_OPCODE_MOV_HR; 10585 inst.instruction |= (Rn & 0x8) << 4; 10586 inst.instruction |= (Rn & 0x7); 10587 inst.instruction |= Rm << 3; 10588 break; 10589 10590 case T_MNEM_movs: 10591 /* We know we have low registers at this point. 10592 Generate LSLS Rd, Rs, #0. */ 10593 inst.instruction = T_OPCODE_LSL_I; 10594 inst.instruction |= Rn; 10595 inst.instruction |= Rm << 3; 10596 break; 10597 10598 case T_MNEM_cmp: 10599 if (low_regs) 10600 { 10601 inst.instruction = T_OPCODE_CMP_LR; 10602 inst.instruction |= Rn; 10603 inst.instruction |= Rm << 3; 10604 } 10605 else 10606 { 10607 inst.instruction = T_OPCODE_CMP_HR; 10608 inst.instruction |= (Rn & 0x8) << 4; 10609 inst.instruction |= (Rn & 0x7); 10610 inst.instruction |= Rm << 3; 10611 } 10612 break; 10613 } 10614 return; 10615 } 10616 10617 inst.instruction = THUMB_OP16 (inst.instruction); 10618 10619 /* PR 10443: Do not silently ignore shifted operands. */ 10620 constraint (inst.operands[1].shifted, 10621 _("shifts in CMP/MOV instructions are only supported in unified syntax")); 10622 10623 if (inst.operands[1].isreg) 10624 { 10625 if (Rn < 8 && Rm < 8) 10626 { 10627 /* A move of two lowregs is encoded as ADD Rd, Rs, #0 10628 since a MOV instruction produces unpredictable results. */ 10629 if (inst.instruction == T_OPCODE_MOV_I8) 10630 inst.instruction = T_OPCODE_ADD_I3; 10631 else 10632 inst.instruction = T_OPCODE_CMP_LR; 10633 10634 inst.instruction |= Rn; 10635 inst.instruction |= Rm << 3; 10636 } 10637 else 10638 { 10639 if (inst.instruction == T_OPCODE_MOV_I8) 10640 inst.instruction = T_OPCODE_MOV_HR; 10641 else 10642 inst.instruction = T_OPCODE_CMP_HR; 10643 do_t_cpy (); 10644 } 10645 } 10646 else 10647 { 10648 constraint (Rn > 7, 10649 _("only lo regs allowed with immediate")); 10650 inst.instruction |= Rn << 8; 10651 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; 10652 } 10653} 10654 10655static void 10656do_t_mov16 (void) 10657{ 10658 unsigned Rd; 10659 bfd_vma imm; 10660 bfd_boolean top; 10661 10662 top = (inst.instruction & 0x00800000) != 0; 10663 if (inst.reloc.type == BFD_RELOC_ARM_MOVW) 10664 { 10665 constraint (top, _(":lower16: not allowed this instruction")); 10666 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; 10667 } 10668 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) 10669 { 10670 constraint (!top, _(":upper16: not allowed this instruction")); 10671 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; 10672 } 10673 10674 Rd = inst.operands[0].reg; 10675 reject_bad_reg (Rd); 10676 10677 inst.instruction |= Rd << 8; 10678 if (inst.reloc.type == BFD_RELOC_UNUSED) 10679 { 10680 imm = inst.reloc.exp.X_add_number; 10681 inst.instruction |= (imm & 0xf000) << 4; 10682 inst.instruction |= (imm & 0x0800) << 15; 10683 inst.instruction |= (imm & 0x0700) << 4; 10684 inst.instruction |= (imm & 0x00ff); 10685 } 10686} 10687 10688static void 10689do_t_mvn_tst (void) 10690{ 10691 unsigned Rn, Rm; 10692 10693 Rn = inst.operands[0].reg; 10694 Rm = inst.operands[1].reg; 10695 10696 if (inst.instruction == T_MNEM_cmp 10697 || inst.instruction == T_MNEM_cmn) 10698 constraint (Rn == REG_PC, BAD_PC); 10699 else 10700 reject_bad_reg (Rn); 10701 reject_bad_reg (Rm); 10702 10703 if (unified_syntax) 10704 { 10705 int r0off = (inst.instruction == T_MNEM_mvn 10706 || inst.instruction == T_MNEM_mvns) ? 8 : 16; 10707 bfd_boolean narrow; 10708 10709 if (inst.size_req == 4 10710 || inst.instruction > 0xffff 10711 || inst.operands[1].shifted 10712 || Rn > 7 || Rm > 7) 10713 narrow = FALSE; 10714 else if (inst.instruction == T_MNEM_cmn) 10715 narrow = TRUE; 10716 else if (THUMB_SETS_FLAGS (inst.instruction)) 10717 narrow = !in_it_block (); 10718 else 10719 narrow = in_it_block (); 10720 10721 if (!inst.operands[1].isreg) 10722 { 10723 /* For an immediate, we always generate a 32-bit opcode; 10724 section relaxation will shrink it later if possible. */ 10725 if (inst.instruction < 0xffff) 10726 inst.instruction = THUMB_OP32 (inst.instruction); 10727 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 10728 inst.instruction |= Rn << r0off; 10729 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 10730 } 10731 else 10732 { 10733 /* See if we can do this with a 16-bit instruction. */ 10734 if (narrow) 10735 { 10736 inst.instruction = THUMB_OP16 (inst.instruction); 10737 inst.instruction |= Rn; 10738 inst.instruction |= Rm << 3; 10739 } 10740 else 10741 { 10742 constraint (inst.operands[1].shifted 10743 && inst.operands[1].immisreg, 10744 _("shift must be constant")); 10745 if (inst.instruction < 0xffff) 10746 inst.instruction = THUMB_OP32 (inst.instruction); 10747 inst.instruction |= Rn << r0off; 10748 encode_thumb32_shifted_operand (1); 10749 } 10750 } 10751 } 10752 else 10753 { 10754 constraint (inst.instruction > 0xffff 10755 || inst.instruction == T_MNEM_mvns, BAD_THUMB32); 10756 constraint (!inst.operands[1].isreg || inst.operands[1].shifted, 10757 _("unshifted register required")); 10758 constraint (Rn > 7 || Rm > 7, 10759 BAD_HIREG); 10760 10761 inst.instruction = THUMB_OP16 (inst.instruction); 10762 inst.instruction |= Rn; 10763 inst.instruction |= Rm << 3; 10764 } 10765} 10766 10767static void 10768do_t_mrs (void) 10769{ 10770 unsigned Rd; 10771 10772 if (do_vfp_nsyn_mrs () == SUCCESS) 10773 return; 10774 10775 Rd = inst.operands[0].reg; 10776 reject_bad_reg (Rd); 10777 inst.instruction |= Rd << 8; 10778 10779 if (inst.operands[1].isreg) 10780 { 10781 unsigned br = inst.operands[1].reg; 10782 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000)) 10783 as_bad (_("bad register for mrs")); 10784 10785 inst.instruction |= br & (0xf << 16); 10786 inst.instruction |= (br & 0x300) >> 4; 10787 inst.instruction |= (br & SPSR_BIT) >> 2; 10788 } 10789 else 10790 { 10791 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); 10792 10793 if (flags == 0) 10794 { 10795 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m), 10796 _("selected processor does not support " 10797 "requested special purpose register")); 10798 } 10799 else 10800 { 10801 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), 10802 _("selected processor does not support " 10803 "requested special purpose register")); 10804 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ 10805 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), 10806 _("'CPSR' or 'SPSR' expected")); 10807 } 10808 10809 inst.instruction |= (flags & SPSR_BIT) >> 2; 10810 inst.instruction |= inst.operands[1].imm & 0xff; 10811 inst.instruction |= 0xf0000; 10812 } 10813} 10814 10815static void 10816do_t_msr (void) 10817{ 10818 int flags; 10819 unsigned Rn; 10820 10821 if (do_vfp_nsyn_msr () == SUCCESS) 10822 return; 10823 10824 constraint (!inst.operands[1].isreg, 10825 _("Thumb encoding does not support an immediate here")); 10826 10827 if (inst.operands[0].isreg) 10828 flags = (int)(inst.operands[0].reg); 10829 else 10830 flags = inst.operands[0].imm; 10831 10832 if (flags & ~0xff) 10833 { 10834 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), 10835 _("selected processor does not support " 10836 "requested special purpose register")); 10837 } 10838 else 10839 { 10840 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m), 10841 _("selected processor does not support " 10842 "requested special purpose register")); 10843 flags |= PSR_f; 10844 } 10845 10846 Rn = inst.operands[1].reg; 10847 reject_bad_reg (Rn); 10848 10849 inst.instruction |= (flags & SPSR_BIT) >> 2; 10850 inst.instruction |= (flags & 0xf0000) >> 8; 10851 inst.instruction |= (flags & 0x300) >> 4; 10852 inst.instruction |= (flags & 0xff); 10853 inst.instruction |= Rn << 16; 10854} 10855 10856static void 10857do_t_mul (void) 10858{ 10859 bfd_boolean narrow; 10860 unsigned Rd, Rn, Rm; 10861 10862 if (!inst.operands[2].present) 10863 inst.operands[2].reg = inst.operands[0].reg; 10864 10865 Rd = inst.operands[0].reg; 10866 Rn = inst.operands[1].reg; 10867 Rm = inst.operands[2].reg; 10868 10869 if (unified_syntax) 10870 { 10871 if (inst.size_req == 4 10872 || (Rd != Rn 10873 && Rd != Rm) 10874 || Rn > 7 10875 || Rm > 7) 10876 narrow = FALSE; 10877 else if (inst.instruction == T_MNEM_muls) 10878 narrow = !in_it_block (); 10879 else 10880 narrow = in_it_block (); 10881 } 10882 else 10883 { 10884 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); 10885 constraint (Rn > 7 || Rm > 7, 10886 BAD_HIREG); 10887 narrow = TRUE; 10888 } 10889 10890 if (narrow) 10891 { 10892 /* 16-bit MULS/Conditional MUL. */ 10893 inst.instruction = THUMB_OP16 (inst.instruction); 10894 inst.instruction |= Rd; 10895 10896 if (Rd == Rn) 10897 inst.instruction |= Rm << 3; 10898 else if (Rd == Rm) 10899 inst.instruction |= Rn << 3; 10900 else 10901 constraint (1, _("dest must overlap one source register")); 10902 } 10903 else 10904 { 10905 constraint (inst.instruction != T_MNEM_mul, 10906 _("Thumb-2 MUL must not set flags")); 10907 /* 32-bit MUL. */ 10908 inst.instruction = THUMB_OP32 (inst.instruction); 10909 inst.instruction |= Rd << 8; 10910 inst.instruction |= Rn << 16; 10911 inst.instruction |= Rm << 0; 10912 10913 reject_bad_reg (Rd); 10914 reject_bad_reg (Rn); 10915 reject_bad_reg (Rm); 10916 } 10917} 10918 10919static void 10920do_t_mull (void) 10921{ 10922 unsigned RdLo, RdHi, Rn, Rm; 10923 10924 RdLo = inst.operands[0].reg; 10925 RdHi = inst.operands[1].reg; 10926 Rn = inst.operands[2].reg; 10927 Rm = inst.operands[3].reg; 10928 10929 reject_bad_reg (RdLo); 10930 reject_bad_reg (RdHi); 10931 reject_bad_reg (Rn); 10932 reject_bad_reg (Rm); 10933 10934 inst.instruction |= RdLo << 12; 10935 inst.instruction |= RdHi << 8; 10936 inst.instruction |= Rn << 16; 10937 inst.instruction |= Rm; 10938 10939 if (RdLo == RdHi) 10940 as_tsktsk (_("rdhi and rdlo must be different")); 10941} 10942 10943static void 10944do_t_nop (void) 10945{ 10946 set_it_insn_type (NEUTRAL_IT_INSN); 10947 10948 if (unified_syntax) 10949 { 10950 if (inst.size_req == 4 || inst.operands[0].imm > 15) 10951 { 10952 inst.instruction = THUMB_OP32 (inst.instruction); 10953 inst.instruction |= inst.operands[0].imm; 10954 } 10955 else 10956 { 10957 /* PR9722: Check for Thumb2 availability before 10958 generating a thumb2 nop instruction. */ 10959 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) 10960 { 10961 inst.instruction = THUMB_OP16 (inst.instruction); 10962 inst.instruction |= inst.operands[0].imm << 4; 10963 } 10964 else 10965 inst.instruction = 0x46c0; 10966 } 10967 } 10968 else 10969 { 10970 constraint (inst.operands[0].present, 10971 _("Thumb does not support NOP with hints")); 10972 inst.instruction = 0x46c0; 10973 } 10974} 10975 10976static void 10977do_t_neg (void) 10978{ 10979 if (unified_syntax) 10980 { 10981 bfd_boolean narrow; 10982 10983 if (THUMB_SETS_FLAGS (inst.instruction)) 10984 narrow = !in_it_block (); 10985 else 10986 narrow = in_it_block (); 10987 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 10988 narrow = FALSE; 10989 if (inst.size_req == 4) 10990 narrow = FALSE; 10991 10992 if (!narrow) 10993 { 10994 inst.instruction = THUMB_OP32 (inst.instruction); 10995 inst.instruction |= inst.operands[0].reg << 8; 10996 inst.instruction |= inst.operands[1].reg << 16; 10997 } 10998 else 10999 { 11000 inst.instruction = THUMB_OP16 (inst.instruction); 11001 inst.instruction |= inst.operands[0].reg; 11002 inst.instruction |= inst.operands[1].reg << 3; 11003 } 11004 } 11005 else 11006 { 11007 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 11008 BAD_HIREG); 11009 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 11010 11011 inst.instruction = THUMB_OP16 (inst.instruction); 11012 inst.instruction |= inst.operands[0].reg; 11013 inst.instruction |= inst.operands[1].reg << 3; 11014 } 11015} 11016 11017static void 11018do_t_orn (void) 11019{ 11020 unsigned Rd, Rn; 11021 11022 Rd = inst.operands[0].reg; 11023 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; 11024 11025 reject_bad_reg (Rd); 11026 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ 11027 reject_bad_reg (Rn); 11028 11029 inst.instruction |= Rd << 8; 11030 inst.instruction |= Rn << 16; 11031 11032 if (!inst.operands[2].isreg) 11033 { 11034 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 11035 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 11036 } 11037 else 11038 { 11039 unsigned Rm; 11040 11041 Rm = inst.operands[2].reg; 11042 reject_bad_reg (Rm); 11043 11044 constraint (inst.operands[2].shifted 11045 && inst.operands[2].immisreg, 11046 _("shift must be constant")); 11047 encode_thumb32_shifted_operand (2); 11048 } 11049} 11050 11051static void 11052do_t_pkhbt (void) 11053{ 11054 unsigned Rd, Rn, Rm; 11055 11056 Rd = inst.operands[0].reg; 11057 Rn = inst.operands[1].reg; 11058 Rm = inst.operands[2].reg; 11059 11060 reject_bad_reg (Rd); 11061 reject_bad_reg (Rn); 11062 reject_bad_reg (Rm); 11063 11064 inst.instruction |= Rd << 8; 11065 inst.instruction |= Rn << 16; 11066 inst.instruction |= Rm; 11067 if (inst.operands[3].present) 11068 { 11069 unsigned int val = inst.reloc.exp.X_add_number; 11070 constraint (inst.reloc.exp.X_op != O_constant, 11071 _("expression too complex")); 11072 inst.instruction |= (val & 0x1c) << 10; 11073 inst.instruction |= (val & 0x03) << 6; 11074 } 11075} 11076 11077static void 11078do_t_pkhtb (void) 11079{ 11080 if (!inst.operands[3].present) 11081 { 11082 unsigned Rtmp; 11083 11084 inst.instruction &= ~0x00000020; 11085 11086 /* PR 10168. Swap the Rm and Rn registers. */ 11087 Rtmp = inst.operands[1].reg; 11088 inst.operands[1].reg = inst.operands[2].reg; 11089 inst.operands[2].reg = Rtmp; 11090 } 11091 do_t_pkhbt (); 11092} 11093 11094static void 11095do_t_pld (void) 11096{ 11097 if (inst.operands[0].immisreg) 11098 reject_bad_reg (inst.operands[0].imm); 11099 11100 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); 11101} 11102 11103static void 11104do_t_push_pop (void) 11105{ 11106 unsigned mask; 11107 11108 constraint (inst.operands[0].writeback, 11109 _("push/pop do not support {reglist}^")); 11110 constraint (inst.reloc.type != BFD_RELOC_UNUSED, 11111 _("expression too complex")); 11112 11113 mask = inst.operands[0].imm; 11114 if ((mask & ~0xff) == 0) 11115 inst.instruction = THUMB_OP16 (inst.instruction) | mask; 11116 else if ((inst.instruction == T_MNEM_push 11117 && (mask & ~0xff) == 1 << REG_LR) 11118 || (inst.instruction == T_MNEM_pop 11119 && (mask & ~0xff) == 1 << REG_PC)) 11120 { 11121 inst.instruction = THUMB_OP16 (inst.instruction); 11122 inst.instruction |= THUMB_PP_PC_LR; 11123 inst.instruction |= mask & 0xff; 11124 } 11125 else if (unified_syntax) 11126 { 11127 inst.instruction = THUMB_OP32 (inst.instruction); 11128 encode_thumb2_ldmstm (13, mask, TRUE); 11129 } 11130 else 11131 { 11132 inst.error = _("invalid register list to push/pop instruction"); 11133 return; 11134 } 11135} 11136 11137static void 11138do_t_rbit (void) 11139{ 11140 unsigned Rd, Rm; 11141 11142 Rd = inst.operands[0].reg; 11143 Rm = inst.operands[1].reg; 11144 11145 reject_bad_reg (Rd); 11146 reject_bad_reg (Rm); 11147 11148 inst.instruction |= Rd << 8; 11149 inst.instruction |= Rm << 16; 11150 inst.instruction |= Rm; 11151} 11152 11153static void 11154do_t_rev (void) 11155{ 11156 unsigned Rd, Rm; 11157 11158 Rd = inst.operands[0].reg; 11159 Rm = inst.operands[1].reg; 11160 11161 reject_bad_reg (Rd); 11162 reject_bad_reg (Rm); 11163 11164 if (Rd <= 7 && Rm <= 7 11165 && inst.size_req != 4) 11166 { 11167 inst.instruction = THUMB_OP16 (inst.instruction); 11168 inst.instruction |= Rd; 11169 inst.instruction |= Rm << 3; 11170 } 11171 else if (unified_syntax) 11172 { 11173 inst.instruction = THUMB_OP32 (inst.instruction); 11174 inst.instruction |= Rd << 8; 11175 inst.instruction |= Rm << 16; 11176 inst.instruction |= Rm; 11177 } 11178 else 11179 inst.error = BAD_HIREG; 11180} 11181 11182static void 11183do_t_rrx (void) 11184{ 11185 unsigned Rd, Rm; 11186 11187 Rd = inst.operands[0].reg; 11188 Rm = inst.operands[1].reg; 11189 11190 reject_bad_reg (Rd); 11191 reject_bad_reg (Rm); 11192 11193 inst.instruction |= Rd << 8; 11194 inst.instruction |= Rm; 11195} 11196 11197static void 11198do_t_rsb (void) 11199{ 11200 unsigned Rd, Rs; 11201 11202 Rd = inst.operands[0].reg; 11203 Rs = (inst.operands[1].present 11204 ? inst.operands[1].reg /* Rd, Rs, foo */ 11205 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 11206 11207 reject_bad_reg (Rd); 11208 reject_bad_reg (Rs); 11209 if (inst.operands[2].isreg) 11210 reject_bad_reg (inst.operands[2].reg); 11211 11212 inst.instruction |= Rd << 8; 11213 inst.instruction |= Rs << 16; 11214 if (!inst.operands[2].isreg) 11215 { 11216 bfd_boolean narrow; 11217 11218 if ((inst.instruction & 0x00100000) != 0) 11219 narrow = !in_it_block (); 11220 else 11221 narrow = in_it_block (); 11222 11223 if (Rd > 7 || Rs > 7) 11224 narrow = FALSE; 11225 11226 if (inst.size_req == 4 || !unified_syntax) 11227 narrow = FALSE; 11228 11229 if (inst.reloc.exp.X_op != O_constant 11230 || inst.reloc.exp.X_add_number != 0) 11231 narrow = FALSE; 11232 11233 /* Turn rsb #0 into 16-bit neg. We should probably do this via 11234 relaxation, but it doesn't seem worth the hassle. */ 11235 if (narrow) 11236 { 11237 inst.reloc.type = BFD_RELOC_UNUSED; 11238 inst.instruction = THUMB_OP16 (T_MNEM_negs); 11239 inst.instruction |= Rs << 3; 11240 inst.instruction |= Rd; 11241 } 11242 else 11243 { 11244 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 11245 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 11246 } 11247 } 11248 else 11249 encode_thumb32_shifted_operand (2); 11250} 11251 11252static void 11253do_t_setend (void) 11254{ 11255 set_it_insn_type (OUTSIDE_IT_INSN); 11256 if (inst.operands[0].imm) 11257 inst.instruction |= 0x8; 11258} 11259 11260static void 11261do_t_shift (void) 11262{ 11263 if (!inst.operands[1].present) 11264 inst.operands[1].reg = inst.operands[0].reg; 11265 11266 if (unified_syntax) 11267 { 11268 bfd_boolean narrow; 11269 int shift_kind; 11270 11271 switch (inst.instruction) 11272 { 11273 case T_MNEM_asr: 11274 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; 11275 case T_MNEM_lsl: 11276 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; 11277 case T_MNEM_lsr: 11278 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; 11279 case T_MNEM_ror: 11280 case T_MNEM_rors: shift_kind = SHIFT_ROR; break; 11281 default: abort (); 11282 } 11283 11284 if (THUMB_SETS_FLAGS (inst.instruction)) 11285 narrow = !in_it_block (); 11286 else 11287 narrow = in_it_block (); 11288 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 11289 narrow = FALSE; 11290 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) 11291 narrow = FALSE; 11292 if (inst.operands[2].isreg 11293 && (inst.operands[1].reg != inst.operands[0].reg 11294 || inst.operands[2].reg > 7)) 11295 narrow = FALSE; 11296 if (inst.size_req == 4) 11297 narrow = FALSE; 11298 11299 reject_bad_reg (inst.operands[0].reg); 11300 reject_bad_reg (inst.operands[1].reg); 11301 11302 if (!narrow) 11303 { 11304 if (inst.operands[2].isreg) 11305 { 11306 reject_bad_reg (inst.operands[2].reg); 11307 inst.instruction = THUMB_OP32 (inst.instruction); 11308 inst.instruction |= inst.operands[0].reg << 8; 11309 inst.instruction |= inst.operands[1].reg << 16; 11310 inst.instruction |= inst.operands[2].reg; 11311 } 11312 else 11313 { 11314 inst.operands[1].shifted = 1; 11315 inst.operands[1].shift_kind = shift_kind; 11316 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) 11317 ? T_MNEM_movs : T_MNEM_mov); 11318 inst.instruction |= inst.operands[0].reg << 8; 11319 encode_thumb32_shifted_operand (1); 11320 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ 11321 inst.reloc.type = BFD_RELOC_UNUSED; 11322 } 11323 } 11324 else 11325 { 11326 if (inst.operands[2].isreg) 11327 { 11328 switch (shift_kind) 11329 { 11330 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; 11331 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; 11332 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; 11333 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; 11334 default: abort (); 11335 } 11336 11337 inst.instruction |= inst.operands[0].reg; 11338 inst.instruction |= inst.operands[2].reg << 3; 11339 } 11340 else 11341 { 11342 switch (shift_kind) 11343 { 11344 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; 11345 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; 11346 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; 11347 default: abort (); 11348 } 11349 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 11350 inst.instruction |= inst.operands[0].reg; 11351 inst.instruction |= inst.operands[1].reg << 3; 11352 } 11353 } 11354 } 11355 else 11356 { 11357 constraint (inst.operands[0].reg > 7 11358 || inst.operands[1].reg > 7, BAD_HIREG); 11359 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 11360 11361 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ 11362 { 11363 constraint (inst.operands[2].reg > 7, BAD_HIREG); 11364 constraint (inst.operands[0].reg != inst.operands[1].reg, 11365 _("source1 and dest must be same register")); 11366 11367 switch (inst.instruction) 11368 { 11369 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; 11370 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; 11371 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; 11372 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; 11373 default: abort (); 11374 } 11375 11376 inst.instruction |= inst.operands[0].reg; 11377 inst.instruction |= inst.operands[2].reg << 3; 11378 } 11379 else 11380 { 11381 switch (inst.instruction) 11382 { 11383 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; 11384 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; 11385 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; 11386 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; 11387 default: abort (); 11388 } 11389 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 11390 inst.instruction |= inst.operands[0].reg; 11391 inst.instruction |= inst.operands[1].reg << 3; 11392 } 11393 } 11394} 11395 11396static void 11397do_t_simd (void) 11398{ 11399 unsigned Rd, Rn, Rm; 11400 11401 Rd = inst.operands[0].reg; 11402 Rn = inst.operands[1].reg; 11403 Rm = inst.operands[2].reg; 11404 11405 reject_bad_reg (Rd); 11406 reject_bad_reg (Rn); 11407 reject_bad_reg (Rm); 11408 11409 inst.instruction |= Rd << 8; 11410 inst.instruction |= Rn << 16; 11411 inst.instruction |= Rm; 11412} 11413 11414static void 11415do_t_simd2 (void) 11416{ 11417 unsigned Rd, Rn, Rm; 11418 11419 Rd = inst.operands[0].reg; 11420 Rm = inst.operands[1].reg; 11421 Rn = inst.operands[2].reg; 11422 11423 reject_bad_reg (Rd); 11424 reject_bad_reg (Rn); 11425 reject_bad_reg (Rm); 11426 11427 inst.instruction |= Rd << 8; 11428 inst.instruction |= Rn << 16; 11429 inst.instruction |= Rm; 11430} 11431 11432static void 11433do_t_smc (void) 11434{ 11435 unsigned int value = inst.reloc.exp.X_add_number; 11436 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a), 11437 _("SMC is not permitted on this architecture")); 11438 constraint (inst.reloc.exp.X_op != O_constant, 11439 _("expression too complex")); 11440 inst.reloc.type = BFD_RELOC_UNUSED; 11441 inst.instruction |= (value & 0xf000) >> 12; 11442 inst.instruction |= (value & 0x0ff0); 11443 inst.instruction |= (value & 0x000f) << 16; 11444} 11445 11446static void 11447do_t_hvc (void) 11448{ 11449 unsigned int value = inst.reloc.exp.X_add_number; 11450 11451 inst.reloc.type = BFD_RELOC_UNUSED; 11452 inst.instruction |= (value & 0x0fff); 11453 inst.instruction |= (value & 0xf000) << 4; 11454} 11455 11456static void 11457do_t_ssat_usat (int bias) 11458{ 11459 unsigned Rd, Rn; 11460 11461 Rd = inst.operands[0].reg; 11462 Rn = inst.operands[2].reg; 11463 11464 reject_bad_reg (Rd); 11465 reject_bad_reg (Rn); 11466 11467 inst.instruction |= Rd << 8; 11468 inst.instruction |= inst.operands[1].imm - bias; 11469 inst.instruction |= Rn << 16; 11470 11471 if (inst.operands[3].present) 11472 { 11473 offsetT shift_amount = inst.reloc.exp.X_add_number; 11474 11475 inst.reloc.type = BFD_RELOC_UNUSED; 11476 11477 constraint (inst.reloc.exp.X_op != O_constant, 11478 _("expression too complex")); 11479 11480 if (shift_amount != 0) 11481 { 11482 constraint (shift_amount > 31, 11483 _("shift expression is too large")); 11484 11485 if (inst.operands[3].shift_kind == SHIFT_ASR) 11486 inst.instruction |= 0x00200000; /* sh bit. */ 11487 11488 inst.instruction |= (shift_amount & 0x1c) << 10; 11489 inst.instruction |= (shift_amount & 0x03) << 6; 11490 } 11491 } 11492} 11493 11494static void 11495do_t_ssat (void) 11496{ 11497 do_t_ssat_usat (1); 11498} 11499 11500static void 11501do_t_ssat16 (void) 11502{ 11503 unsigned Rd, Rn; 11504 11505 Rd = inst.operands[0].reg; 11506 Rn = inst.operands[2].reg; 11507 11508 reject_bad_reg (Rd); 11509 reject_bad_reg (Rn); 11510 11511 inst.instruction |= Rd << 8; 11512 inst.instruction |= inst.operands[1].imm - 1; 11513 inst.instruction |= Rn << 16; 11514} 11515 11516static void 11517do_t_strex (void) 11518{ 11519 constraint (!inst.operands[2].isreg || !inst.operands[2].preind 11520 || inst.operands[2].postind || inst.operands[2].writeback 11521 || inst.operands[2].immisreg || inst.operands[2].shifted 11522 || inst.operands[2].negative, 11523 BAD_ADDR_MODE); 11524 11525 constraint (inst.operands[2].reg == REG_PC, BAD_PC); 11526 11527 inst.instruction |= inst.operands[0].reg << 8; 11528 inst.instruction |= inst.operands[1].reg << 12; 11529 inst.instruction |= inst.operands[2].reg << 16; 11530 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; 11531} 11532 11533static void 11534do_t_strexd (void) 11535{ 11536 if (!inst.operands[2].present) 11537 inst.operands[2].reg = inst.operands[1].reg + 1; 11538 11539 constraint (inst.operands[0].reg == inst.operands[1].reg 11540 || inst.operands[0].reg == inst.operands[2].reg 11541 || inst.operands[0].reg == inst.operands[3].reg, 11542 BAD_OVERLAP); 11543 11544 inst.instruction |= inst.operands[0].reg; 11545 inst.instruction |= inst.operands[1].reg << 12; 11546 inst.instruction |= inst.operands[2].reg << 8; 11547 inst.instruction |= inst.operands[3].reg << 16; 11548} 11549 11550static void 11551do_t_sxtah (void) 11552{ 11553 unsigned Rd, Rn, Rm; 11554 11555 Rd = inst.operands[0].reg; 11556 Rn = inst.operands[1].reg; 11557 Rm = inst.operands[2].reg; 11558 11559 reject_bad_reg (Rd); 11560 reject_bad_reg (Rn); 11561 reject_bad_reg (Rm); 11562 11563 inst.instruction |= Rd << 8; 11564 inst.instruction |= Rn << 16; 11565 inst.instruction |= Rm; 11566 inst.instruction |= inst.operands[3].imm << 4; 11567} 11568 11569static void 11570do_t_sxth (void) 11571{ 11572 unsigned Rd, Rm; 11573 11574 Rd = inst.operands[0].reg; 11575 Rm = inst.operands[1].reg; 11576 11577 reject_bad_reg (Rd); 11578 reject_bad_reg (Rm); 11579 11580 if (inst.instruction <= 0xffff 11581 && inst.size_req != 4 11582 && Rd <= 7 && Rm <= 7 11583 && (!inst.operands[2].present || inst.operands[2].imm == 0)) 11584 { 11585 inst.instruction = THUMB_OP16 (inst.instruction); 11586 inst.instruction |= Rd; 11587 inst.instruction |= Rm << 3; 11588 } 11589 else if (unified_syntax) 11590 { 11591 if (inst.instruction <= 0xffff) 11592 inst.instruction = THUMB_OP32 (inst.instruction); 11593 inst.instruction |= Rd << 8; 11594 inst.instruction |= Rm; 11595 inst.instruction |= inst.operands[2].imm << 4; 11596 } 11597 else 11598 { 11599 constraint (inst.operands[2].present && inst.operands[2].imm != 0, 11600 _("Thumb encoding does not support rotation")); 11601 constraint (1, BAD_HIREG); 11602 } 11603} 11604 11605static void 11606do_t_swi (void) 11607{ 11608 /* We have to do the following check manually as ARM_EXT_OS only applies 11609 to ARM_EXT_V6M. */ 11610 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m)) 11611 { 11612 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)) 11613 as_bad (_("SVC is not permitted on this architecture")); 11614 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os); 11615 } 11616 11617 inst.reloc.type = BFD_RELOC_ARM_SWI; 11618} 11619 11620static void 11621do_t_tb (void) 11622{ 11623 unsigned Rn, Rm; 11624 int half; 11625 11626 half = (inst.instruction & 0x10) != 0; 11627 set_it_insn_type_last (); 11628 constraint (inst.operands[0].immisreg, 11629 _("instruction requires register index")); 11630 11631 Rn = inst.operands[0].reg; 11632 Rm = inst.operands[0].imm; 11633 11634 constraint (Rn == REG_SP, BAD_SP); 11635 reject_bad_reg (Rm); 11636 11637 constraint (!half && inst.operands[0].shifted, 11638 _("instruction does not allow shifted index")); 11639 inst.instruction |= (Rn << 16) | Rm; 11640} 11641 11642static void 11643do_t_usat (void) 11644{ 11645 do_t_ssat_usat (0); 11646} 11647 11648static void 11649do_t_usat16 (void) 11650{ 11651 unsigned Rd, Rn; 11652 11653 Rd = inst.operands[0].reg; 11654 Rn = inst.operands[2].reg; 11655 11656 reject_bad_reg (Rd); 11657 reject_bad_reg (Rn); 11658 11659 inst.instruction |= Rd << 8; 11660 inst.instruction |= inst.operands[1].imm; 11661 inst.instruction |= Rn << 16; 11662} 11663 11664/* Neon instruction encoder helpers. */ 11665 11666/* Encodings for the different types for various Neon opcodes. */ 11667 11668/* An "invalid" code for the following tables. */ 11669#define N_INV -1u 11670 11671struct neon_tab_entry 11672{ 11673 unsigned integer; 11674 unsigned float_or_poly; 11675 unsigned scalar_or_imm; 11676}; 11677 11678/* Map overloaded Neon opcodes to their respective encodings. */ 11679#define NEON_ENC_TAB \ 11680 X(vabd, 0x0000700, 0x1200d00, N_INV), \ 11681 X(vmax, 0x0000600, 0x0000f00, N_INV), \ 11682 X(vmin, 0x0000610, 0x0200f00, N_INV), \ 11683 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ 11684 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ 11685 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ 11686 X(vadd, 0x0000800, 0x0000d00, N_INV), \ 11687 X(vsub, 0x1000800, 0x0200d00, N_INV), \ 11688 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ 11689 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ 11690 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ 11691 /* Register variants of the following two instructions are encoded as 11692 vcge / vcgt with the operands reversed. */ \ 11693 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ 11694 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ 11695 X(vfma, N_INV, 0x0000c10, N_INV), \ 11696 X(vfms, N_INV, 0x0200c10, N_INV), \ 11697 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ 11698 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ 11699 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ 11700 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ 11701 X(vmlal, 0x0800800, N_INV, 0x0800240), \ 11702 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ 11703 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ 11704 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ 11705 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ 11706 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ 11707 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ 11708 X(vshl, 0x0000400, N_INV, 0x0800510), \ 11709 X(vqshl, 0x0000410, N_INV, 0x0800710), \ 11710 X(vand, 0x0000110, N_INV, 0x0800030), \ 11711 X(vbic, 0x0100110, N_INV, 0x0800030), \ 11712 X(veor, 0x1000110, N_INV, N_INV), \ 11713 X(vorn, 0x0300110, N_INV, 0x0800010), \ 11714 X(vorr, 0x0200110, N_INV, 0x0800010), \ 11715 X(vmvn, 0x1b00580, N_INV, 0x0800030), \ 11716 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ 11717 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ 11718 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ 11719 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ 11720 X(vst1, 0x0000000, 0x0800000, N_INV), \ 11721 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ 11722 X(vst2, 0x0000100, 0x0800100, N_INV), \ 11723 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ 11724 X(vst3, 0x0000200, 0x0800200, N_INV), \ 11725 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ 11726 X(vst4, 0x0000300, 0x0800300, N_INV), \ 11727 X(vmovn, 0x1b20200, N_INV, N_INV), \ 11728 X(vtrn, 0x1b20080, N_INV, N_INV), \ 11729 X(vqmovn, 0x1b20200, N_INV, N_INV), \ 11730 X(vqmovun, 0x1b20240, N_INV, N_INV), \ 11731 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ 11732 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ 11733 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ 11734 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ 11735 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ 11736 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ 11737 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ 11738 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ 11739 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) 11740 11741enum neon_opc 11742{ 11743#define X(OPC,I,F,S) N_MNEM_##OPC 11744NEON_ENC_TAB 11745#undef X 11746}; 11747 11748static const struct neon_tab_entry neon_enc_tab[] = 11749{ 11750#define X(OPC,I,F,S) { (I), (F), (S) } 11751NEON_ENC_TAB 11752#undef X 11753}; 11754 11755/* Do not use these macros; instead, use NEON_ENCODE defined below. */ 11756#define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 11757#define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 11758#define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 11759#define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 11760#define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 11761#define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 11762#define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 11763#define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 11764#define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 11765#define NEON_ENC_SINGLE_(X) \ 11766 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) 11767#define NEON_ENC_DOUBLE_(X) \ 11768 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) 11769 11770#define NEON_ENCODE(type, inst) \ 11771 do \ 11772 { \ 11773 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ 11774 inst.is_neon = 1; \ 11775 } \ 11776 while (0) 11777 11778#define check_neon_suffixes \ 11779 do \ 11780 { \ 11781 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ 11782 { \ 11783 as_bad (_("invalid neon suffix for non neon instruction")); \ 11784 return; \ 11785 } \ 11786 } \ 11787 while (0) 11788 11789/* Define shapes for instruction operands. The following mnemonic characters 11790 are used in this table: 11791 11792 F - VFP S<n> register 11793 D - Neon D<n> register 11794 Q - Neon Q<n> register 11795 I - Immediate 11796 S - Scalar 11797 R - ARM register 11798 L - D<n> register list 11799 11800 This table is used to generate various data: 11801 - enumerations of the form NS_DDR to be used as arguments to 11802 neon_select_shape. 11803 - a table classifying shapes into single, double, quad, mixed. 11804 - a table used to drive neon_select_shape. */ 11805 11806#define NEON_SHAPE_DEF \ 11807 X(3, (D, D, D), DOUBLE), \ 11808 X(3, (Q, Q, Q), QUAD), \ 11809 X(3, (D, D, I), DOUBLE), \ 11810 X(3, (Q, Q, I), QUAD), \ 11811 X(3, (D, D, S), DOUBLE), \ 11812 X(3, (Q, Q, S), QUAD), \ 11813 X(2, (D, D), DOUBLE), \ 11814 X(2, (Q, Q), QUAD), \ 11815 X(2, (D, S), DOUBLE), \ 11816 X(2, (Q, S), QUAD), \ 11817 X(2, (D, R), DOUBLE), \ 11818 X(2, (Q, R), QUAD), \ 11819 X(2, (D, I), DOUBLE), \ 11820 X(2, (Q, I), QUAD), \ 11821 X(3, (D, L, D), DOUBLE), \ 11822 X(2, (D, Q), MIXED), \ 11823 X(2, (Q, D), MIXED), \ 11824 X(3, (D, Q, I), MIXED), \ 11825 X(3, (Q, D, I), MIXED), \ 11826 X(3, (Q, D, D), MIXED), \ 11827 X(3, (D, Q, Q), MIXED), \ 11828 X(3, (Q, Q, D), MIXED), \ 11829 X(3, (Q, D, S), MIXED), \ 11830 X(3, (D, Q, S), MIXED), \ 11831 X(4, (D, D, D, I), DOUBLE), \ 11832 X(4, (Q, Q, Q, I), QUAD), \ 11833 X(2, (F, F), SINGLE), \ 11834 X(3, (F, F, F), SINGLE), \ 11835 X(2, (F, I), SINGLE), \ 11836 X(2, (F, D), MIXED), \ 11837 X(2, (D, F), MIXED), \ 11838 X(3, (F, F, I), MIXED), \ 11839 X(4, (R, R, F, F), SINGLE), \ 11840 X(4, (F, F, R, R), SINGLE), \ 11841 X(3, (D, R, R), DOUBLE), \ 11842 X(3, (R, R, D), DOUBLE), \ 11843 X(2, (S, R), SINGLE), \ 11844 X(2, (R, S), SINGLE), \ 11845 X(2, (F, R), SINGLE), \ 11846 X(2, (R, F), SINGLE) 11847 11848#define S2(A,B) NS_##A##B 11849#define S3(A,B,C) NS_##A##B##C 11850#define S4(A,B,C,D) NS_##A##B##C##D 11851 11852#define X(N, L, C) S##N L 11853 11854enum neon_shape 11855{ 11856 NEON_SHAPE_DEF, 11857 NS_NULL 11858}; 11859 11860#undef X 11861#undef S2 11862#undef S3 11863#undef S4 11864 11865enum neon_shape_class 11866{ 11867 SC_SINGLE, 11868 SC_DOUBLE, 11869 SC_QUAD, 11870 SC_MIXED 11871}; 11872 11873#define X(N, L, C) SC_##C 11874 11875static enum neon_shape_class neon_shape_class[] = 11876{ 11877 NEON_SHAPE_DEF 11878}; 11879 11880#undef X 11881 11882enum neon_shape_el 11883{ 11884 SE_F, 11885 SE_D, 11886 SE_Q, 11887 SE_I, 11888 SE_S, 11889 SE_R, 11890 SE_L 11891}; 11892 11893/* Register widths of above. */ 11894static unsigned neon_shape_el_size[] = 11895{ 11896 32, 11897 64, 11898 128, 11899 0, 11900 32, 11901 32, 11902 0 11903}; 11904 11905struct neon_shape_info 11906{ 11907 unsigned els; 11908 enum neon_shape_el el[NEON_MAX_TYPE_ELS]; 11909}; 11910 11911#define S2(A,B) { SE_##A, SE_##B } 11912#define S3(A,B,C) { SE_##A, SE_##B, SE_##C } 11913#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } 11914 11915#define X(N, L, C) { N, S##N L } 11916 11917static struct neon_shape_info neon_shape_tab[] = 11918{ 11919 NEON_SHAPE_DEF 11920}; 11921 11922#undef X 11923#undef S2 11924#undef S3 11925#undef S4 11926 11927/* Bit masks used in type checking given instructions. 11928 'N_EQK' means the type must be the same as (or based on in some way) the key 11929 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is 11930 set, various other bits can be set as well in order to modify the meaning of 11931 the type constraint. */ 11932 11933enum neon_type_mask 11934{ 11935 N_S8 = 0x0000001, 11936 N_S16 = 0x0000002, 11937 N_S32 = 0x0000004, 11938 N_S64 = 0x0000008, 11939 N_U8 = 0x0000010, 11940 N_U16 = 0x0000020, 11941 N_U32 = 0x0000040, 11942 N_U64 = 0x0000080, 11943 N_I8 = 0x0000100, 11944 N_I16 = 0x0000200, 11945 N_I32 = 0x0000400, 11946 N_I64 = 0x0000800, 11947 N_8 = 0x0001000, 11948 N_16 = 0x0002000, 11949 N_32 = 0x0004000, 11950 N_64 = 0x0008000, 11951 N_P8 = 0x0010000, 11952 N_P16 = 0x0020000, 11953 N_F16 = 0x0040000, 11954 N_F32 = 0x0080000, 11955 N_F64 = 0x0100000, 11956 N_KEY = 0x1000000, /* Key element (main type specifier). */ 11957 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ 11958 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ 11959 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ 11960 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ 11961 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ 11962 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ 11963 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ 11964 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ 11965 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ 11966 N_UTYP = 0, 11967 N_MAX_NONSPECIAL = N_F64 11968}; 11969 11970#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) 11971 11972#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) 11973#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) 11974#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) 11975#define N_SUF_32 (N_SU_32 | N_F32) 11976#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) 11977#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) 11978 11979/* Pass this as the first type argument to neon_check_type to ignore types 11980 altogether. */ 11981#define N_IGNORE_TYPE (N_KEY | N_EQK) 11982 11983/* Select a "shape" for the current instruction (describing register types or 11984 sizes) from a list of alternatives. Return NS_NULL if the current instruction 11985 doesn't fit. For non-polymorphic shapes, checking is usually done as a 11986 function of operand parsing, so this function doesn't need to be called. 11987 Shapes should be listed in order of decreasing length. */ 11988 11989static enum neon_shape 11990neon_select_shape (enum neon_shape shape, ...) 11991{ 11992 va_list ap; 11993 enum neon_shape first_shape = shape; 11994 11995 /* Fix missing optional operands. FIXME: we don't know at this point how 11996 many arguments we should have, so this makes the assumption that we have 11997 > 1. This is true of all current Neon opcodes, I think, but may not be 11998 true in the future. */ 11999 if (!inst.operands[1].present) 12000 inst.operands[1] = inst.operands[0]; 12001 12002 va_start (ap, shape); 12003 12004 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) 12005 { 12006 unsigned j; 12007 int matches = 1; 12008 12009 for (j = 0; j < neon_shape_tab[shape].els; j++) 12010 { 12011 if (!inst.operands[j].present) 12012 { 12013 matches = 0; 12014 break; 12015 } 12016 12017 switch (neon_shape_tab[shape].el[j]) 12018 { 12019 case SE_F: 12020 if (!(inst.operands[j].isreg 12021 && inst.operands[j].isvec 12022 && inst.operands[j].issingle 12023 && !inst.operands[j].isquad)) 12024 matches = 0; 12025 break; 12026 12027 case SE_D: 12028 if (!(inst.operands[j].isreg 12029 && inst.operands[j].isvec 12030 && !inst.operands[j].isquad 12031 && !inst.operands[j].issingle)) 12032 matches = 0; 12033 break; 12034 12035 case SE_R: 12036 if (!(inst.operands[j].isreg 12037 && !inst.operands[j].isvec)) 12038 matches = 0; 12039 break; 12040 12041 case SE_Q: 12042 if (!(inst.operands[j].isreg 12043 && inst.operands[j].isvec 12044 && inst.operands[j].isquad 12045 && !inst.operands[j].issingle)) 12046 matches = 0; 12047 break; 12048 12049 case SE_I: 12050 if (!(!inst.operands[j].isreg 12051 && !inst.operands[j].isscalar)) 12052 matches = 0; 12053 break; 12054 12055 case SE_S: 12056 if (!(!inst.operands[j].isreg 12057 && inst.operands[j].isscalar)) 12058 matches = 0; 12059 break; 12060 12061 case SE_L: 12062 break; 12063 } 12064 if (!matches) 12065 break; 12066 } 12067 if (matches) 12068 break; 12069 } 12070 12071 va_end (ap); 12072 12073 if (shape == NS_NULL && first_shape != NS_NULL) 12074 first_error (_("invalid instruction shape")); 12075 12076 return shape; 12077} 12078 12079/* True if SHAPE is predominantly a quadword operation (most of the time, this 12080 means the Q bit should be set). */ 12081 12082static int 12083neon_quad (enum neon_shape shape) 12084{ 12085 return neon_shape_class[shape] == SC_QUAD; 12086} 12087 12088static void 12089neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, 12090 unsigned *g_size) 12091{ 12092 /* Allow modification to be made to types which are constrained to be 12093 based on the key element, based on bits set alongside N_EQK. */ 12094 if ((typebits & N_EQK) != 0) 12095 { 12096 if ((typebits & N_HLF) != 0) 12097 *g_size /= 2; 12098 else if ((typebits & N_DBL) != 0) 12099 *g_size *= 2; 12100 if ((typebits & N_SGN) != 0) 12101 *g_type = NT_signed; 12102 else if ((typebits & N_UNS) != 0) 12103 *g_type = NT_unsigned; 12104 else if ((typebits & N_INT) != 0) 12105 *g_type = NT_integer; 12106 else if ((typebits & N_FLT) != 0) 12107 *g_type = NT_float; 12108 else if ((typebits & N_SIZ) != 0) 12109 *g_type = NT_untyped; 12110 } 12111} 12112 12113/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" 12114 operand type, i.e. the single type specified in a Neon instruction when it 12115 is the only one given. */ 12116 12117static struct neon_type_el 12118neon_type_promote (struct neon_type_el *key, unsigned thisarg) 12119{ 12120 struct neon_type_el dest = *key; 12121 12122 gas_assert ((thisarg & N_EQK) != 0); 12123 12124 neon_modify_type_size (thisarg, &dest.type, &dest.size); 12125 12126 return dest; 12127} 12128 12129/* Convert Neon type and size into compact bitmask representation. */ 12130 12131static enum neon_type_mask 12132type_chk_of_el_type (enum neon_el_type type, unsigned size) 12133{ 12134 switch (type) 12135 { 12136 case NT_untyped: 12137 switch (size) 12138 { 12139 case 8: return N_8; 12140 case 16: return N_16; 12141 case 32: return N_32; 12142 case 64: return N_64; 12143 default: ; 12144 } 12145 break; 12146 12147 case NT_integer: 12148 switch (size) 12149 { 12150 case 8: return N_I8; 12151 case 16: return N_I16; 12152 case 32: return N_I32; 12153 case 64: return N_I64; 12154 default: ; 12155 } 12156 break; 12157 12158 case NT_float: 12159 switch (size) 12160 { 12161 case 16: return N_F16; 12162 case 32: return N_F32; 12163 case 64: return N_F64; 12164 default: ; 12165 } 12166 break; 12167 12168 case NT_poly: 12169 switch (size) 12170 { 12171 case 8: return N_P8; 12172 case 16: return N_P16; 12173 default: ; 12174 } 12175 break; 12176 12177 case NT_signed: 12178 switch (size) 12179 { 12180 case 8: return N_S8; 12181 case 16: return N_S16; 12182 case 32: return N_S32; 12183 case 64: return N_S64; 12184 default: ; 12185 } 12186 break; 12187 12188 case NT_unsigned: 12189 switch (size) 12190 { 12191 case 8: return N_U8; 12192 case 16: return N_U16; 12193 case 32: return N_U32; 12194 case 64: return N_U64; 12195 default: ; 12196 } 12197 break; 12198 12199 default: ; 12200 } 12201 12202 return N_UTYP; 12203} 12204 12205/* Convert compact Neon bitmask type representation to a type and size. Only 12206 handles the case where a single bit is set in the mask. */ 12207 12208static int 12209el_type_of_type_chk (enum neon_el_type *type, unsigned *size, 12210 enum neon_type_mask mask) 12211{ 12212 if ((mask & N_EQK) != 0) 12213 return FAIL; 12214 12215 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) 12216 *size = 8; 12217 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) 12218 *size = 16; 12219 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) 12220 *size = 32; 12221 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) 12222 *size = 64; 12223 else 12224 return FAIL; 12225 12226 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) 12227 *type = NT_signed; 12228 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) 12229 *type = NT_unsigned; 12230 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) 12231 *type = NT_integer; 12232 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) 12233 *type = NT_untyped; 12234 else if ((mask & (N_P8 | N_P16)) != 0) 12235 *type = NT_poly; 12236 else if ((mask & (N_F32 | N_F64)) != 0) 12237 *type = NT_float; 12238 else 12239 return FAIL; 12240 12241 return SUCCESS; 12242} 12243 12244/* Modify a bitmask of allowed types. This is only needed for type 12245 relaxation. */ 12246 12247static unsigned 12248modify_types_allowed (unsigned allowed, unsigned mods) 12249{ 12250 unsigned size; 12251 enum neon_el_type type; 12252 unsigned destmask; 12253 int i; 12254 12255 destmask = 0; 12256 12257 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) 12258 { 12259 if (el_type_of_type_chk (&type, &size, 12260 (enum neon_type_mask) (allowed & i)) == SUCCESS) 12261 { 12262 neon_modify_type_size (mods, &type, &size); 12263 destmask |= type_chk_of_el_type (type, size); 12264 } 12265 } 12266 12267 return destmask; 12268} 12269 12270/* Check type and return type classification. 12271 The manual states (paraphrase): If one datatype is given, it indicates the 12272 type given in: 12273 - the second operand, if there is one 12274 - the operand, if there is no second operand 12275 - the result, if there are no operands. 12276 This isn't quite good enough though, so we use a concept of a "key" datatype 12277 which is set on a per-instruction basis, which is the one which matters when 12278 only one data type is written. 12279 Note: this function has side-effects (e.g. filling in missing operands). All 12280 Neon instructions should call it before performing bit encoding. */ 12281 12282static struct neon_type_el 12283neon_check_type (unsigned els, enum neon_shape ns, ...) 12284{ 12285 va_list ap; 12286 unsigned i, pass, key_el = 0; 12287 unsigned types[NEON_MAX_TYPE_ELS]; 12288 enum neon_el_type k_type = NT_invtype; 12289 unsigned k_size = -1u; 12290 struct neon_type_el badtype = {NT_invtype, -1}; 12291 unsigned key_allowed = 0; 12292 12293 /* Optional registers in Neon instructions are always (not) in operand 1. 12294 Fill in the missing operand here, if it was omitted. */ 12295 if (els > 1 && !inst.operands[1].present) 12296 inst.operands[1] = inst.operands[0]; 12297 12298 /* Suck up all the varargs. */ 12299 va_start (ap, ns); 12300 for (i = 0; i < els; i++) 12301 { 12302 unsigned thisarg = va_arg (ap, unsigned); 12303 if (thisarg == N_IGNORE_TYPE) 12304 { 12305 va_end (ap); 12306 return badtype; 12307 } 12308 types[i] = thisarg; 12309 if ((thisarg & N_KEY) != 0) 12310 key_el = i; 12311 } 12312 va_end (ap); 12313 12314 if (inst.vectype.elems > 0) 12315 for (i = 0; i < els; i++) 12316 if (inst.operands[i].vectype.type != NT_invtype) 12317 { 12318 first_error (_("types specified in both the mnemonic and operands")); 12319 return badtype; 12320 } 12321 12322 /* Duplicate inst.vectype elements here as necessary. 12323 FIXME: No idea if this is exactly the same as the ARM assembler, 12324 particularly when an insn takes one register and one non-register 12325 operand. */ 12326 if (inst.vectype.elems == 1 && els > 1) 12327 { 12328 unsigned j; 12329 inst.vectype.elems = els; 12330 inst.vectype.el[key_el] = inst.vectype.el[0]; 12331 for (j = 0; j < els; j++) 12332 if (j != key_el) 12333 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], 12334 types[j]); 12335 } 12336 else if (inst.vectype.elems == 0 && els > 0) 12337 { 12338 unsigned j; 12339 /* No types were given after the mnemonic, so look for types specified 12340 after each operand. We allow some flexibility here; as long as the 12341 "key" operand has a type, we can infer the others. */ 12342 for (j = 0; j < els; j++) 12343 if (inst.operands[j].vectype.type != NT_invtype) 12344 inst.vectype.el[j] = inst.operands[j].vectype; 12345 12346 if (inst.operands[key_el].vectype.type != NT_invtype) 12347 { 12348 for (j = 0; j < els; j++) 12349 if (inst.operands[j].vectype.type == NT_invtype) 12350 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], 12351 types[j]); 12352 } 12353 else 12354 { 12355 first_error (_("operand types can't be inferred")); 12356 return badtype; 12357 } 12358 } 12359 else if (inst.vectype.elems != els) 12360 { 12361 first_error (_("type specifier has the wrong number of parts")); 12362 return badtype; 12363 } 12364 12365 for (pass = 0; pass < 2; pass++) 12366 { 12367 for (i = 0; i < els; i++) 12368 { 12369 unsigned thisarg = types[i]; 12370 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) 12371 ? modify_types_allowed (key_allowed, thisarg) : thisarg; 12372 enum neon_el_type g_type = inst.vectype.el[i].type; 12373 unsigned g_size = inst.vectype.el[i].size; 12374 12375 /* Decay more-specific signed & unsigned types to sign-insensitive 12376 integer types if sign-specific variants are unavailable. */ 12377 if ((g_type == NT_signed || g_type == NT_unsigned) 12378 && (types_allowed & N_SU_ALL) == 0) 12379 g_type = NT_integer; 12380 12381 /* If only untyped args are allowed, decay any more specific types to 12382 them. Some instructions only care about signs for some element 12383 sizes, so handle that properly. */ 12384 if ((g_size == 8 && (types_allowed & N_8) != 0) 12385 || (g_size == 16 && (types_allowed & N_16) != 0) 12386 || (g_size == 32 && (types_allowed & N_32) != 0) 12387 || (g_size == 64 && (types_allowed & N_64) != 0)) 12388 g_type = NT_untyped; 12389 12390 if (pass == 0) 12391 { 12392 if ((thisarg & N_KEY) != 0) 12393 { 12394 k_type = g_type; 12395 k_size = g_size; 12396 key_allowed = thisarg & ~N_KEY; 12397 } 12398 } 12399 else 12400 { 12401 if ((thisarg & N_VFP) != 0) 12402 { 12403 enum neon_shape_el regshape; 12404 unsigned regwidth, match; 12405 12406 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ 12407 if (ns == NS_NULL) 12408 { 12409 first_error (_("invalid instruction shape")); 12410 return badtype; 12411 } 12412 regshape = neon_shape_tab[ns].el[i]; 12413 regwidth = neon_shape_el_size[regshape]; 12414 12415 /* In VFP mode, operands must match register widths. If we 12416 have a key operand, use its width, else use the width of 12417 the current operand. */ 12418 if (k_size != -1u) 12419 match = k_size; 12420 else 12421 match = g_size; 12422 12423 if (regwidth != match) 12424 { 12425 first_error (_("operand size must match register width")); 12426 return badtype; 12427 } 12428 } 12429 12430 if ((thisarg & N_EQK) == 0) 12431 { 12432 unsigned given_type = type_chk_of_el_type (g_type, g_size); 12433 12434 if ((given_type & types_allowed) == 0) 12435 { 12436 first_error (_("bad type in Neon instruction")); 12437 return badtype; 12438 } 12439 } 12440 else 12441 { 12442 enum neon_el_type mod_k_type = k_type; 12443 unsigned mod_k_size = k_size; 12444 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); 12445 if (g_type != mod_k_type || g_size != mod_k_size) 12446 { 12447 first_error (_("inconsistent types in Neon instruction")); 12448 return badtype; 12449 } 12450 } 12451 } 12452 } 12453 } 12454 12455 return inst.vectype.el[key_el]; 12456} 12457 12458/* Neon-style VFP instruction forwarding. */ 12459 12460/* Thumb VFP instructions have 0xE in the condition field. */ 12461 12462static void 12463do_vfp_cond_or_thumb (void) 12464{ 12465 inst.is_neon = 1; 12466 12467 if (thumb_mode) 12468 inst.instruction |= 0xe0000000; 12469 else 12470 inst.instruction |= inst.cond << 28; 12471} 12472 12473/* Look up and encode a simple mnemonic, for use as a helper function for the 12474 Neon-style VFP syntax. This avoids duplication of bits of the insns table, 12475 etc. It is assumed that operand parsing has already been done, and that the 12476 operands are in the form expected by the given opcode (this isn't necessarily 12477 the same as the form in which they were parsed, hence some massaging must 12478 take place before this function is called). 12479 Checks current arch version against that in the looked-up opcode. */ 12480 12481static void 12482do_vfp_nsyn_opcode (const char *opname) 12483{ 12484 const struct asm_opcode *opcode; 12485 12486 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); 12487 12488 if (!opcode) 12489 abort (); 12490 12491 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, 12492 thumb_mode ? *opcode->tvariant : *opcode->avariant), 12493 _(BAD_FPU)); 12494 12495 inst.is_neon = 1; 12496 12497 if (thumb_mode) 12498 { 12499 inst.instruction = opcode->tvalue; 12500 opcode->tencode (); 12501 } 12502 else 12503 { 12504 inst.instruction = (inst.cond << 28) | opcode->avalue; 12505 opcode->aencode (); 12506 } 12507} 12508 12509static void 12510do_vfp_nsyn_add_sub (enum neon_shape rs) 12511{ 12512 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; 12513 12514 if (rs == NS_FFF) 12515 { 12516 if (is_add) 12517 do_vfp_nsyn_opcode ("fadds"); 12518 else 12519 do_vfp_nsyn_opcode ("fsubs"); 12520 } 12521 else 12522 { 12523 if (is_add) 12524 do_vfp_nsyn_opcode ("faddd"); 12525 else 12526 do_vfp_nsyn_opcode ("fsubd"); 12527 } 12528} 12529 12530/* Check operand types to see if this is a VFP instruction, and if so call 12531 PFN (). */ 12532 12533static int 12534try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) 12535{ 12536 enum neon_shape rs; 12537 struct neon_type_el et; 12538 12539 switch (args) 12540 { 12541 case 2: 12542 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 12543 et = neon_check_type (2, rs, 12544 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 12545 break; 12546 12547 case 3: 12548 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 12549 et = neon_check_type (3, rs, 12550 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 12551 break; 12552 12553 default: 12554 abort (); 12555 } 12556 12557 if (et.type != NT_invtype) 12558 { 12559 pfn (rs); 12560 return SUCCESS; 12561 } 12562 12563 inst.error = NULL; 12564 return FAIL; 12565} 12566 12567static void 12568do_vfp_nsyn_mla_mls (enum neon_shape rs) 12569{ 12570 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; 12571 12572 if (rs == NS_FFF) 12573 { 12574 if (is_mla) 12575 do_vfp_nsyn_opcode ("fmacs"); 12576 else 12577 do_vfp_nsyn_opcode ("fnmacs"); 12578 } 12579 else 12580 { 12581 if (is_mla) 12582 do_vfp_nsyn_opcode ("fmacd"); 12583 else 12584 do_vfp_nsyn_opcode ("fnmacd"); 12585 } 12586} 12587 12588static void 12589do_vfp_nsyn_fma_fms (enum neon_shape rs) 12590{ 12591 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; 12592 12593 if (rs == NS_FFF) 12594 { 12595 if (is_fma) 12596 do_vfp_nsyn_opcode ("ffmas"); 12597 else 12598 do_vfp_nsyn_opcode ("ffnmas"); 12599 } 12600 else 12601 { 12602 if (is_fma) 12603 do_vfp_nsyn_opcode ("ffmad"); 12604 else 12605 do_vfp_nsyn_opcode ("ffnmad"); 12606 } 12607} 12608 12609static void 12610do_vfp_nsyn_mul (enum neon_shape rs) 12611{ 12612 if (rs == NS_FFF) 12613 do_vfp_nsyn_opcode ("fmuls"); 12614 else 12615 do_vfp_nsyn_opcode ("fmuld"); 12616} 12617 12618static void 12619do_vfp_nsyn_abs_neg (enum neon_shape rs) 12620{ 12621 int is_neg = (inst.instruction & 0x80) != 0; 12622 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); 12623 12624 if (rs == NS_FF) 12625 { 12626 if (is_neg) 12627 do_vfp_nsyn_opcode ("fnegs"); 12628 else 12629 do_vfp_nsyn_opcode ("fabss"); 12630 } 12631 else 12632 { 12633 if (is_neg) 12634 do_vfp_nsyn_opcode ("fnegd"); 12635 else 12636 do_vfp_nsyn_opcode ("fabsd"); 12637 } 12638} 12639 12640/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision 12641 insns belong to Neon, and are handled elsewhere. */ 12642 12643static void 12644do_vfp_nsyn_ldm_stm (int is_dbmode) 12645{ 12646 int is_ldm = (inst.instruction & (1 << 20)) != 0; 12647 if (is_ldm) 12648 { 12649 if (is_dbmode) 12650 do_vfp_nsyn_opcode ("fldmdbs"); 12651 else 12652 do_vfp_nsyn_opcode ("fldmias"); 12653 } 12654 else 12655 { 12656 if (is_dbmode) 12657 do_vfp_nsyn_opcode ("fstmdbs"); 12658 else 12659 do_vfp_nsyn_opcode ("fstmias"); 12660 } 12661} 12662 12663static void 12664do_vfp_nsyn_sqrt (void) 12665{ 12666 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 12667 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 12668 12669 if (rs == NS_FF) 12670 do_vfp_nsyn_opcode ("fsqrts"); 12671 else 12672 do_vfp_nsyn_opcode ("fsqrtd"); 12673} 12674 12675static void 12676do_vfp_nsyn_div (void) 12677{ 12678 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 12679 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, 12680 N_F32 | N_F64 | N_KEY | N_VFP); 12681 12682 if (rs == NS_FFF) 12683 do_vfp_nsyn_opcode ("fdivs"); 12684 else 12685 do_vfp_nsyn_opcode ("fdivd"); 12686} 12687 12688static void 12689do_vfp_nsyn_nmul (void) 12690{ 12691 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 12692 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, 12693 N_F32 | N_F64 | N_KEY | N_VFP); 12694 12695 if (rs == NS_FFF) 12696 { 12697 NEON_ENCODE (SINGLE, inst); 12698 do_vfp_sp_dyadic (); 12699 } 12700 else 12701 { 12702 NEON_ENCODE (DOUBLE, inst); 12703 do_vfp_dp_rd_rn_rm (); 12704 } 12705 do_vfp_cond_or_thumb (); 12706} 12707 12708static void 12709do_vfp_nsyn_cmp (void) 12710{ 12711 if (inst.operands[1].isreg) 12712 { 12713 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 12714 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 12715 12716 if (rs == NS_FF) 12717 { 12718 NEON_ENCODE (SINGLE, inst); 12719 do_vfp_sp_monadic (); 12720 } 12721 else 12722 { 12723 NEON_ENCODE (DOUBLE, inst); 12724 do_vfp_dp_rd_rm (); 12725 } 12726 } 12727 else 12728 { 12729 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); 12730 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); 12731 12732 switch (inst.instruction & 0x0fffffff) 12733 { 12734 case N_MNEM_vcmp: 12735 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; 12736 break; 12737 case N_MNEM_vcmpe: 12738 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; 12739 break; 12740 default: 12741 abort (); 12742 } 12743 12744 if (rs == NS_FI) 12745 { 12746 NEON_ENCODE (SINGLE, inst); 12747 do_vfp_sp_compare_z (); 12748 } 12749 else 12750 { 12751 NEON_ENCODE (DOUBLE, inst); 12752 do_vfp_dp_rd (); 12753 } 12754 } 12755 do_vfp_cond_or_thumb (); 12756} 12757 12758static void 12759nsyn_insert_sp (void) 12760{ 12761 inst.operands[1] = inst.operands[0]; 12762 memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); 12763 inst.operands[0].reg = REG_SP; 12764 inst.operands[0].isreg = 1; 12765 inst.operands[0].writeback = 1; 12766 inst.operands[0].present = 1; 12767} 12768 12769static void 12770do_vfp_nsyn_push (void) 12771{ 12772 nsyn_insert_sp (); 12773 if (inst.operands[1].issingle) 12774 do_vfp_nsyn_opcode ("fstmdbs"); 12775 else 12776 do_vfp_nsyn_opcode ("fstmdbd"); 12777} 12778 12779static void 12780do_vfp_nsyn_pop (void) 12781{ 12782 nsyn_insert_sp (); 12783 if (inst.operands[1].issingle) 12784 do_vfp_nsyn_opcode ("fldmias"); 12785 else 12786 do_vfp_nsyn_opcode ("fldmiad"); 12787} 12788 12789/* Fix up Neon data-processing instructions, ORing in the correct bits for 12790 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ 12791 12792static void 12793neon_dp_fixup (struct arm_it* insn) 12794{ 12795 unsigned int i = insn->instruction; 12796 insn->is_neon = 1; 12797 12798 if (thumb_mode) 12799 { 12800 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ 12801 if (i & (1 << 24)) 12802 i |= 1 << 28; 12803 12804 i &= ~(1 << 24); 12805 12806 i |= 0xef000000; 12807 } 12808 else 12809 i |= 0xf2000000; 12810 12811 insn->instruction = i; 12812} 12813 12814/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 12815 (0, 1, 2, 3). */ 12816 12817static unsigned 12818neon_logbits (unsigned x) 12819{ 12820 return ffs (x) - 4; 12821} 12822 12823#define LOW4(R) ((R) & 0xf) 12824#define HI1(R) (((R) >> 4) & 1) 12825 12826/* Encode insns with bit pattern: 12827 12828 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| 12829 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | 12830 12831 SIZE is passed in bits. -1 means size field isn't changed, in case it has a 12832 different meaning for some instruction. */ 12833 12834static void 12835neon_three_same (int isquad, int ubit, int size) 12836{ 12837 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12838 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12839 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12840 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12841 inst.instruction |= LOW4 (inst.operands[2].reg); 12842 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 12843 inst.instruction |= (isquad != 0) << 6; 12844 inst.instruction |= (ubit != 0) << 24; 12845 if (size != -1) 12846 inst.instruction |= neon_logbits (size) << 20; 12847 12848 neon_dp_fixup (&inst); 12849} 12850 12851/* Encode instructions of the form: 12852 12853 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| 12854 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | 12855 12856 Don't write size if SIZE == -1. */ 12857 12858static void 12859neon_two_same (int qbit, int ubit, int size) 12860{ 12861 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12862 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12863 inst.instruction |= LOW4 (inst.operands[1].reg); 12864 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12865 inst.instruction |= (qbit != 0) << 6; 12866 inst.instruction |= (ubit != 0) << 24; 12867 12868 if (size != -1) 12869 inst.instruction |= neon_logbits (size) << 18; 12870 12871 neon_dp_fixup (&inst); 12872} 12873 12874/* Neon instruction encoders, in approximate order of appearance. */ 12875 12876static void 12877do_neon_dyadic_i_su (void) 12878{ 12879 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12880 struct neon_type_el et = neon_check_type (3, rs, 12881 N_EQK, N_EQK, N_SU_32 | N_KEY); 12882 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 12883} 12884 12885static void 12886do_neon_dyadic_i64_su (void) 12887{ 12888 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12889 struct neon_type_el et = neon_check_type (3, rs, 12890 N_EQK, N_EQK, N_SU_ALL | N_KEY); 12891 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 12892} 12893 12894static void 12895neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, 12896 unsigned immbits) 12897{ 12898 unsigned size = et.size >> 3; 12899 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12900 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12901 inst.instruction |= LOW4 (inst.operands[1].reg); 12902 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12903 inst.instruction |= (isquad != 0) << 6; 12904 inst.instruction |= immbits << 16; 12905 inst.instruction |= (size >> 3) << 7; 12906 inst.instruction |= (size & 0x7) << 19; 12907 if (write_ubit) 12908 inst.instruction |= (uval != 0) << 24; 12909 12910 neon_dp_fixup (&inst); 12911} 12912 12913static void 12914do_neon_shl_imm (void) 12915{ 12916 if (!inst.operands[2].isreg) 12917 { 12918 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12919 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); 12920 NEON_ENCODE (IMMED, inst); 12921 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); 12922 } 12923 else 12924 { 12925 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12926 struct neon_type_el et = neon_check_type (3, rs, 12927 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); 12928 unsigned int tmp; 12929 12930 /* VSHL/VQSHL 3-register variants have syntax such as: 12931 vshl.xx Dd, Dm, Dn 12932 whereas other 3-register operations encoded by neon_three_same have 12933 syntax like: 12934 vadd.xx Dd, Dn, Dm 12935 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg 12936 here. */ 12937 tmp = inst.operands[2].reg; 12938 inst.operands[2].reg = inst.operands[1].reg; 12939 inst.operands[1].reg = tmp; 12940 NEON_ENCODE (INTEGER, inst); 12941 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 12942 } 12943} 12944 12945static void 12946do_neon_qshl_imm (void) 12947{ 12948 if (!inst.operands[2].isreg) 12949 { 12950 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12951 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); 12952 12953 NEON_ENCODE (IMMED, inst); 12954 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, 12955 inst.operands[2].imm); 12956 } 12957 else 12958 { 12959 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12960 struct neon_type_el et = neon_check_type (3, rs, 12961 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); 12962 unsigned int tmp; 12963 12964 /* See note in do_neon_shl_imm. */ 12965 tmp = inst.operands[2].reg; 12966 inst.operands[2].reg = inst.operands[1].reg; 12967 inst.operands[1].reg = tmp; 12968 NEON_ENCODE (INTEGER, inst); 12969 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 12970 } 12971} 12972 12973static void 12974do_neon_rshl (void) 12975{ 12976 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12977 struct neon_type_el et = neon_check_type (3, rs, 12978 N_EQK, N_EQK, N_SU_ALL | N_KEY); 12979 unsigned int tmp; 12980 12981 tmp = inst.operands[2].reg; 12982 inst.operands[2].reg = inst.operands[1].reg; 12983 inst.operands[1].reg = tmp; 12984 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 12985} 12986 12987static int 12988neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) 12989{ 12990 /* Handle .I8 pseudo-instructions. */ 12991 if (size == 8) 12992 { 12993 /* Unfortunately, this will make everything apart from zero out-of-range. 12994 FIXME is this the intended semantics? There doesn't seem much point in 12995 accepting .I8 if so. */ 12996 immediate |= immediate << 8; 12997 size = 16; 12998 } 12999 13000 if (size >= 32) 13001 { 13002 if (immediate == (immediate & 0x000000ff)) 13003 { 13004 *immbits = immediate; 13005 return 0x1; 13006 } 13007 else if (immediate == (immediate & 0x0000ff00)) 13008 { 13009 *immbits = immediate >> 8; 13010 return 0x3; 13011 } 13012 else if (immediate == (immediate & 0x00ff0000)) 13013 { 13014 *immbits = immediate >> 16; 13015 return 0x5; 13016 } 13017 else if (immediate == (immediate & 0xff000000)) 13018 { 13019 *immbits = immediate >> 24; 13020 return 0x7; 13021 } 13022 if ((immediate & 0xffff) != (immediate >> 16)) 13023 goto bad_immediate; 13024 immediate &= 0xffff; 13025 } 13026 13027 if (immediate == (immediate & 0x000000ff)) 13028 { 13029 *immbits = immediate; 13030 return 0x9; 13031 } 13032 else if (immediate == (immediate & 0x0000ff00)) 13033 { 13034 *immbits = immediate >> 8; 13035 return 0xb; 13036 } 13037 13038 bad_immediate: 13039 first_error (_("immediate value out of range")); 13040 return FAIL; 13041} 13042 13043/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits 13044 A, B, C, D. */ 13045 13046static int 13047neon_bits_same_in_bytes (unsigned imm) 13048{ 13049 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) 13050 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) 13051 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) 13052 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); 13053} 13054 13055/* For immediate of above form, return 0bABCD. */ 13056 13057static unsigned 13058neon_squash_bits (unsigned imm) 13059{ 13060 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) 13061 | ((imm & 0x01000000) >> 21); 13062} 13063 13064/* Compress quarter-float representation to 0b...000 abcdefgh. */ 13065 13066static unsigned 13067neon_qfloat_bits (unsigned imm) 13068{ 13069 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); 13070} 13071 13072/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into 13073 the instruction. *OP is passed as the initial value of the op field, and 13074 may be set to a different value depending on the constant (i.e. 13075 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not 13076 MVN). If the immediate looks like a repeated pattern then also 13077 try smaller element sizes. */ 13078 13079static int 13080neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, 13081 unsigned *immbits, int *op, int size, 13082 enum neon_el_type type) 13083{ 13084 /* Only permit float immediates (including 0.0/-0.0) if the operand type is 13085 float. */ 13086 if (type == NT_float && !float_p) 13087 return FAIL; 13088 13089 if (type == NT_float && is_quarter_float (immlo) && immhi == 0) 13090 { 13091 if (size != 32 || *op == 1) 13092 return FAIL; 13093 *immbits = neon_qfloat_bits (immlo); 13094 return 0xf; 13095 } 13096 13097 if (size == 64) 13098 { 13099 if (neon_bits_same_in_bytes (immhi) 13100 && neon_bits_same_in_bytes (immlo)) 13101 { 13102 if (*op == 1) 13103 return FAIL; 13104 *immbits = (neon_squash_bits (immhi) << 4) 13105 | neon_squash_bits (immlo); 13106 *op = 1; 13107 return 0xe; 13108 } 13109 13110 if (immhi != immlo) 13111 return FAIL; 13112 } 13113 13114 if (size >= 32) 13115 { 13116 if (immlo == (immlo & 0x000000ff)) 13117 { 13118 *immbits = immlo; 13119 return 0x0; 13120 } 13121 else if (immlo == (immlo & 0x0000ff00)) 13122 { 13123 *immbits = immlo >> 8; 13124 return 0x2; 13125 } 13126 else if (immlo == (immlo & 0x00ff0000)) 13127 { 13128 *immbits = immlo >> 16; 13129 return 0x4; 13130 } 13131 else if (immlo == (immlo & 0xff000000)) 13132 { 13133 *immbits = immlo >> 24; 13134 return 0x6; 13135 } 13136 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) 13137 { 13138 *immbits = (immlo >> 8) & 0xff; 13139 return 0xc; 13140 } 13141 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) 13142 { 13143 *immbits = (immlo >> 16) & 0xff; 13144 return 0xd; 13145 } 13146 13147 if ((immlo & 0xffff) != (immlo >> 16)) 13148 return FAIL; 13149 immlo &= 0xffff; 13150 } 13151 13152 if (size >= 16) 13153 { 13154 if (immlo == (immlo & 0x000000ff)) 13155 { 13156 *immbits = immlo; 13157 return 0x8; 13158 } 13159 else if (immlo == (immlo & 0x0000ff00)) 13160 { 13161 *immbits = immlo >> 8; 13162 return 0xa; 13163 } 13164 13165 if ((immlo & 0xff) != (immlo >> 8)) 13166 return FAIL; 13167 immlo &= 0xff; 13168 } 13169 13170 if (immlo == (immlo & 0x000000ff)) 13171 { 13172 /* Don't allow MVN with 8-bit immediate. */ 13173 if (*op == 1) 13174 return FAIL; 13175 *immbits = immlo; 13176 return 0xe; 13177 } 13178 13179 return FAIL; 13180} 13181 13182/* Write immediate bits [7:0] to the following locations: 13183 13184 |28/24|23 19|18 16|15 4|3 0| 13185 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| 13186 13187 This function is used by VMOV/VMVN/VORR/VBIC. */ 13188 13189static void 13190neon_write_immbits (unsigned immbits) 13191{ 13192 inst.instruction |= immbits & 0xf; 13193 inst.instruction |= ((immbits >> 4) & 0x7) << 16; 13194 inst.instruction |= ((immbits >> 7) & 0x1) << 24; 13195} 13196 13197/* Invert low-order SIZE bits of XHI:XLO. */ 13198 13199static void 13200neon_invert_size (unsigned *xlo, unsigned *xhi, int size) 13201{ 13202 unsigned immlo = xlo ? *xlo : 0; 13203 unsigned immhi = xhi ? *xhi : 0; 13204 13205 switch (size) 13206 { 13207 case 8: 13208 immlo = (~immlo) & 0xff; 13209 break; 13210 13211 case 16: 13212 immlo = (~immlo) & 0xffff; 13213 break; 13214 13215 case 64: 13216 immhi = (~immhi) & 0xffffffff; 13217 /* fall through. */ 13218 13219 case 32: 13220 immlo = (~immlo) & 0xffffffff; 13221 break; 13222 13223 default: 13224 abort (); 13225 } 13226 13227 if (xlo) 13228 *xlo = immlo; 13229 13230 if (xhi) 13231 *xhi = immhi; 13232} 13233 13234static void 13235do_neon_logic (void) 13236{ 13237 if (inst.operands[2].present && inst.operands[2].isreg) 13238 { 13239 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 13240 neon_check_type (3, rs, N_IGNORE_TYPE); 13241 /* U bit and size field were set as part of the bitmask. */ 13242 NEON_ENCODE (INTEGER, inst); 13243 neon_three_same (neon_quad (rs), 0, -1); 13244 } 13245 else 13246 { 13247 const int three_ops_form = (inst.operands[2].present 13248 && !inst.operands[2].isreg); 13249 const int immoperand = (three_ops_form ? 2 : 1); 13250 enum neon_shape rs = (three_ops_form 13251 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) 13252 : neon_select_shape (NS_DI, NS_QI, NS_NULL)); 13253 struct neon_type_el et = neon_check_type (2, rs, 13254 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); 13255 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; 13256 unsigned immbits; 13257 int cmode; 13258 13259 if (et.type == NT_invtype) 13260 return; 13261 13262 if (three_ops_form) 13263 constraint (inst.operands[0].reg != inst.operands[1].reg, 13264 _("first and second operands shall be the same register")); 13265 13266 NEON_ENCODE (IMMED, inst); 13267 13268 immbits = inst.operands[immoperand].imm; 13269 if (et.size == 64) 13270 { 13271 /* .i64 is a pseudo-op, so the immediate must be a repeating 13272 pattern. */ 13273 if (immbits != (inst.operands[immoperand].regisimm ? 13274 inst.operands[immoperand].reg : 0)) 13275 { 13276 /* Set immbits to an invalid constant. */ 13277 immbits = 0xdeadbeef; 13278 } 13279 } 13280 13281 switch (opcode) 13282 { 13283 case N_MNEM_vbic: 13284 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 13285 break; 13286 13287 case N_MNEM_vorr: 13288 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 13289 break; 13290 13291 case N_MNEM_vand: 13292 /* Pseudo-instruction for VBIC. */ 13293 neon_invert_size (&immbits, 0, et.size); 13294 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 13295 break; 13296 13297 case N_MNEM_vorn: 13298 /* Pseudo-instruction for VORR. */ 13299 neon_invert_size (&immbits, 0, et.size); 13300 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 13301 break; 13302 13303 default: 13304 abort (); 13305 } 13306 13307 if (cmode == FAIL) 13308 return; 13309 13310 inst.instruction |= neon_quad (rs) << 6; 13311 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13312 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13313 inst.instruction |= cmode << 8; 13314 neon_write_immbits (immbits); 13315 13316 neon_dp_fixup (&inst); 13317 } 13318} 13319 13320static void 13321do_neon_bitfield (void) 13322{ 13323 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 13324 neon_check_type (3, rs, N_IGNORE_TYPE); 13325 neon_three_same (neon_quad (rs), 0, -1); 13326} 13327 13328static void 13329neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, 13330 unsigned destbits) 13331{ 13332 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 13333 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, 13334 types | N_KEY); 13335 if (et.type == NT_float) 13336 { 13337 NEON_ENCODE (FLOAT, inst); 13338 neon_three_same (neon_quad (rs), 0, -1); 13339 } 13340 else 13341 { 13342 NEON_ENCODE (INTEGER, inst); 13343 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); 13344 } 13345} 13346 13347static void 13348do_neon_dyadic_if_su (void) 13349{ 13350 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); 13351} 13352 13353static void 13354do_neon_dyadic_if_su_d (void) 13355{ 13356 /* This version only allow D registers, but that constraint is enforced during 13357 operand parsing so we don't need to do anything extra here. */ 13358 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); 13359} 13360 13361static void 13362do_neon_dyadic_if_i_d (void) 13363{ 13364 /* The "untyped" case can't happen. Do this to stop the "U" bit being 13365 affected if we specify unsigned args. */ 13366 neon_dyadic_misc (NT_untyped, N_IF_32, 0); 13367} 13368 13369enum vfp_or_neon_is_neon_bits 13370{ 13371 NEON_CHECK_CC = 1, 13372 NEON_CHECK_ARCH = 2 13373}; 13374 13375/* Call this function if an instruction which may have belonged to the VFP or 13376 Neon instruction sets, but turned out to be a Neon instruction (due to the 13377 operand types involved, etc.). We have to check and/or fix-up a couple of 13378 things: 13379 13380 - Make sure the user hasn't attempted to make a Neon instruction 13381 conditional. 13382 - Alter the value in the condition code field if necessary. 13383 - Make sure that the arch supports Neon instructions. 13384 13385 Which of these operations take place depends on bits from enum 13386 vfp_or_neon_is_neon_bits. 13387 13388 WARNING: This function has side effects! If NEON_CHECK_CC is used and the 13389 current instruction's condition is COND_ALWAYS, the condition field is 13390 changed to inst.uncond_value. This is necessary because instructions shared 13391 between VFP and Neon may be conditional for the VFP variants only, and the 13392 unconditional Neon version must have, e.g., 0xF in the condition field. */ 13393 13394static int 13395vfp_or_neon_is_neon (unsigned check) 13396{ 13397 /* Conditions are always legal in Thumb mode (IT blocks). */ 13398 if (!thumb_mode && (check & NEON_CHECK_CC)) 13399 { 13400 if (inst.cond != COND_ALWAYS) 13401 { 13402 first_error (_(BAD_COND)); 13403 return FAIL; 13404 } 13405 if (inst.uncond_value != -1) 13406 inst.instruction |= inst.uncond_value << 28; 13407 } 13408 13409 if ((check & NEON_CHECK_ARCH) 13410 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) 13411 { 13412 first_error (_(BAD_FPU)); 13413 return FAIL; 13414 } 13415 13416 return SUCCESS; 13417} 13418 13419static void 13420do_neon_addsub_if_i (void) 13421{ 13422 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) 13423 return; 13424 13425 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13426 return; 13427 13428 /* The "untyped" case can't happen. Do this to stop the "U" bit being 13429 affected if we specify unsigned args. */ 13430 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); 13431} 13432 13433/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the 13434 result to be: 13435 V<op> A,B (A is operand 0, B is operand 2) 13436 to mean: 13437 V<op> A,B,A 13438 not: 13439 V<op> A,B,B 13440 so handle that case specially. */ 13441 13442static void 13443neon_exchange_operands (void) 13444{ 13445 void *scratch = alloca (sizeof (inst.operands[0])); 13446 if (inst.operands[1].present) 13447 { 13448 /* Swap operands[1] and operands[2]. */ 13449 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); 13450 inst.operands[1] = inst.operands[2]; 13451 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); 13452 } 13453 else 13454 { 13455 inst.operands[1] = inst.operands[2]; 13456 inst.operands[2] = inst.operands[0]; 13457 } 13458} 13459 13460static void 13461neon_compare (unsigned regtypes, unsigned immtypes, int invert) 13462{ 13463 if (inst.operands[2].isreg) 13464 { 13465 if (invert) 13466 neon_exchange_operands (); 13467 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); 13468 } 13469 else 13470 { 13471 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 13472 struct neon_type_el et = neon_check_type (2, rs, 13473 N_EQK | N_SIZ, immtypes | N_KEY); 13474 13475 NEON_ENCODE (IMMED, inst); 13476 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13477 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13478 inst.instruction |= LOW4 (inst.operands[1].reg); 13479 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 13480 inst.instruction |= neon_quad (rs) << 6; 13481 inst.instruction |= (et.type == NT_float) << 10; 13482 inst.instruction |= neon_logbits (et.size) << 18; 13483 13484 neon_dp_fixup (&inst); 13485 } 13486} 13487 13488static void 13489do_neon_cmp (void) 13490{ 13491 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); 13492} 13493 13494static void 13495do_neon_cmp_inv (void) 13496{ 13497 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); 13498} 13499 13500static void 13501do_neon_ceq (void) 13502{ 13503 neon_compare (N_IF_32, N_IF_32, FALSE); 13504} 13505 13506/* For multiply instructions, we have the possibility of 16-bit or 32-bit 13507 scalars, which are encoded in 5 bits, M : Rm. 13508 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in 13509 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the 13510 index in M. */ 13511 13512static unsigned 13513neon_scalar_for_mul (unsigned scalar, unsigned elsize) 13514{ 13515 unsigned regno = NEON_SCALAR_REG (scalar); 13516 unsigned elno = NEON_SCALAR_INDEX (scalar); 13517 13518 switch (elsize) 13519 { 13520 case 16: 13521 if (regno > 7 || elno > 3) 13522 goto bad_scalar; 13523 return regno | (elno << 3); 13524 13525 case 32: 13526 if (regno > 15 || elno > 1) 13527 goto bad_scalar; 13528 return regno | (elno << 4); 13529 13530 default: 13531 bad_scalar: 13532 first_error (_("scalar out of range for multiply instruction")); 13533 } 13534 13535 return 0; 13536} 13537 13538/* Encode multiply / multiply-accumulate scalar instructions. */ 13539 13540static void 13541neon_mul_mac (struct neon_type_el et, int ubit) 13542{ 13543 unsigned scalar; 13544 13545 /* Give a more helpful error message if we have an invalid type. */ 13546 if (et.type == NT_invtype) 13547 return; 13548 13549 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); 13550 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13551 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13552 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 13553 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 13554 inst.instruction |= LOW4 (scalar); 13555 inst.instruction |= HI1 (scalar) << 5; 13556 inst.instruction |= (et.type == NT_float) << 8; 13557 inst.instruction |= neon_logbits (et.size) << 20; 13558 inst.instruction |= (ubit != 0) << 24; 13559 13560 neon_dp_fixup (&inst); 13561} 13562 13563static void 13564do_neon_mac_maybe_scalar (void) 13565{ 13566 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) 13567 return; 13568 13569 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13570 return; 13571 13572 if (inst.operands[2].isscalar) 13573 { 13574 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); 13575 struct neon_type_el et = neon_check_type (3, rs, 13576 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); 13577 NEON_ENCODE (SCALAR, inst); 13578 neon_mul_mac (et, neon_quad (rs)); 13579 } 13580 else 13581 { 13582 /* The "untyped" case can't happen. Do this to stop the "U" bit being 13583 affected if we specify unsigned args. */ 13584 neon_dyadic_misc (NT_untyped, N_IF_32, 0); 13585 } 13586} 13587 13588static void 13589do_neon_fmac (void) 13590{ 13591 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) 13592 return; 13593 13594 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13595 return; 13596 13597 neon_dyadic_misc (NT_untyped, N_IF_32, 0); 13598} 13599 13600static void 13601do_neon_tst (void) 13602{ 13603 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 13604 struct neon_type_el et = neon_check_type (3, rs, 13605 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); 13606 neon_three_same (neon_quad (rs), 0, et.size); 13607} 13608 13609/* VMUL with 3 registers allows the P8 type. The scalar version supports the 13610 same types as the MAC equivalents. The polynomial type for this instruction 13611 is encoded the same as the integer type. */ 13612 13613static void 13614do_neon_mul (void) 13615{ 13616 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) 13617 return; 13618 13619 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13620 return; 13621 13622 if (inst.operands[2].isscalar) 13623 do_neon_mac_maybe_scalar (); 13624 else 13625 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); 13626} 13627 13628static void 13629do_neon_qdmulh (void) 13630{ 13631 if (inst.operands[2].isscalar) 13632 { 13633 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); 13634 struct neon_type_el et = neon_check_type (3, rs, 13635 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); 13636 NEON_ENCODE (SCALAR, inst); 13637 neon_mul_mac (et, neon_quad (rs)); 13638 } 13639 else 13640 { 13641 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 13642 struct neon_type_el et = neon_check_type (3, rs, 13643 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); 13644 NEON_ENCODE (INTEGER, inst); 13645 /* The U bit (rounding) comes from bit mask. */ 13646 neon_three_same (neon_quad (rs), 0, et.size); 13647 } 13648} 13649 13650static void 13651do_neon_fcmp_absolute (void) 13652{ 13653 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 13654 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); 13655 /* Size field comes from bit mask. */ 13656 neon_three_same (neon_quad (rs), 1, -1); 13657} 13658 13659static void 13660do_neon_fcmp_absolute_inv (void) 13661{ 13662 neon_exchange_operands (); 13663 do_neon_fcmp_absolute (); 13664} 13665 13666static void 13667do_neon_step (void) 13668{ 13669 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 13670 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); 13671 neon_three_same (neon_quad (rs), 0, -1); 13672} 13673 13674static void 13675do_neon_abs_neg (void) 13676{ 13677 enum neon_shape rs; 13678 struct neon_type_el et; 13679 13680 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) 13681 return; 13682 13683 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13684 return; 13685 13686 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13687 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); 13688 13689 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13690 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13691 inst.instruction |= LOW4 (inst.operands[1].reg); 13692 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 13693 inst.instruction |= neon_quad (rs) << 6; 13694 inst.instruction |= (et.type == NT_float) << 10; 13695 inst.instruction |= neon_logbits (et.size) << 18; 13696 13697 neon_dp_fixup (&inst); 13698} 13699 13700static void 13701do_neon_sli (void) 13702{ 13703 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 13704 struct neon_type_el et = neon_check_type (2, rs, 13705 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 13706 int imm = inst.operands[2].imm; 13707 constraint (imm < 0 || (unsigned)imm >= et.size, 13708 _("immediate out of range for insert")); 13709 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); 13710} 13711 13712static void 13713do_neon_sri (void) 13714{ 13715 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 13716 struct neon_type_el et = neon_check_type (2, rs, 13717 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 13718 int imm = inst.operands[2].imm; 13719 constraint (imm < 1 || (unsigned)imm > et.size, 13720 _("immediate out of range for insert")); 13721 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); 13722} 13723 13724static void 13725do_neon_qshlu_imm (void) 13726{ 13727 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 13728 struct neon_type_el et = neon_check_type (2, rs, 13729 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); 13730 int imm = inst.operands[2].imm; 13731 constraint (imm < 0 || (unsigned)imm >= et.size, 13732 _("immediate out of range for shift")); 13733 /* Only encodes the 'U present' variant of the instruction. 13734 In this case, signed types have OP (bit 8) set to 0. 13735 Unsigned types have OP set to 1. */ 13736 inst.instruction |= (et.type == NT_unsigned) << 8; 13737 /* The rest of the bits are the same as other immediate shifts. */ 13738 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); 13739} 13740 13741static void 13742do_neon_qmovn (void) 13743{ 13744 struct neon_type_el et = neon_check_type (2, NS_DQ, 13745 N_EQK | N_HLF, N_SU_16_64 | N_KEY); 13746 /* Saturating move where operands can be signed or unsigned, and the 13747 destination has the same signedness. */ 13748 NEON_ENCODE (INTEGER, inst); 13749 if (et.type == NT_unsigned) 13750 inst.instruction |= 0xc0; 13751 else 13752 inst.instruction |= 0x80; 13753 neon_two_same (0, 1, et.size / 2); 13754} 13755 13756static void 13757do_neon_qmovun (void) 13758{ 13759 struct neon_type_el et = neon_check_type (2, NS_DQ, 13760 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); 13761 /* Saturating move with unsigned results. Operands must be signed. */ 13762 NEON_ENCODE (INTEGER, inst); 13763 neon_two_same (0, 1, et.size / 2); 13764} 13765 13766static void 13767do_neon_rshift_sat_narrow (void) 13768{ 13769 /* FIXME: Types for narrowing. If operands are signed, results can be signed 13770 or unsigned. If operands are unsigned, results must also be unsigned. */ 13771 struct neon_type_el et = neon_check_type (2, NS_DQI, 13772 N_EQK | N_HLF, N_SU_16_64 | N_KEY); 13773 int imm = inst.operands[2].imm; 13774 /* This gets the bounds check, size encoding and immediate bits calculation 13775 right. */ 13776 et.size /= 2; 13777 13778 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for 13779 VQMOVN.I<size> <Dd>, <Qm>. */ 13780 if (imm == 0) 13781 { 13782 inst.operands[2].present = 0; 13783 inst.instruction = N_MNEM_vqmovn; 13784 do_neon_qmovn (); 13785 return; 13786 } 13787 13788 constraint (imm < 1 || (unsigned)imm > et.size, 13789 _("immediate out of range")); 13790 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); 13791} 13792 13793static void 13794do_neon_rshift_sat_narrow_u (void) 13795{ 13796 /* FIXME: Types for narrowing. If operands are signed, results can be signed 13797 or unsigned. If operands are unsigned, results must also be unsigned. */ 13798 struct neon_type_el et = neon_check_type (2, NS_DQI, 13799 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); 13800 int imm = inst.operands[2].imm; 13801 /* This gets the bounds check, size encoding and immediate bits calculation 13802 right. */ 13803 et.size /= 2; 13804 13805 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for 13806 VQMOVUN.I<size> <Dd>, <Qm>. */ 13807 if (imm == 0) 13808 { 13809 inst.operands[2].present = 0; 13810 inst.instruction = N_MNEM_vqmovun; 13811 do_neon_qmovun (); 13812 return; 13813 } 13814 13815 constraint (imm < 1 || (unsigned)imm > et.size, 13816 _("immediate out of range")); 13817 /* FIXME: The manual is kind of unclear about what value U should have in 13818 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it 13819 must be 1. */ 13820 neon_imm_shift (TRUE, 1, 0, et, et.size - imm); 13821} 13822 13823static void 13824do_neon_movn (void) 13825{ 13826 struct neon_type_el et = neon_check_type (2, NS_DQ, 13827 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); 13828 NEON_ENCODE (INTEGER, inst); 13829 neon_two_same (0, 1, et.size / 2); 13830} 13831 13832static void 13833do_neon_rshift_narrow (void) 13834{ 13835 struct neon_type_el et = neon_check_type (2, NS_DQI, 13836 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); 13837 int imm = inst.operands[2].imm; 13838 /* This gets the bounds check, size encoding and immediate bits calculation 13839 right. */ 13840 et.size /= 2; 13841 13842 /* If immediate is zero then we are a pseudo-instruction for 13843 VMOVN.I<size> <Dd>, <Qm> */ 13844 if (imm == 0) 13845 { 13846 inst.operands[2].present = 0; 13847 inst.instruction = N_MNEM_vmovn; 13848 do_neon_movn (); 13849 return; 13850 } 13851 13852 constraint (imm < 1 || (unsigned)imm > et.size, 13853 _("immediate out of range for narrowing operation")); 13854 neon_imm_shift (FALSE, 0, 0, et, et.size - imm); 13855} 13856 13857static void 13858do_neon_shll (void) 13859{ 13860 /* FIXME: Type checking when lengthening. */ 13861 struct neon_type_el et = neon_check_type (2, NS_QDI, 13862 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); 13863 unsigned imm = inst.operands[2].imm; 13864 13865 if (imm == et.size) 13866 { 13867 /* Maximum shift variant. */ 13868 NEON_ENCODE (INTEGER, inst); 13869 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13870 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13871 inst.instruction |= LOW4 (inst.operands[1].reg); 13872 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 13873 inst.instruction |= neon_logbits (et.size) << 18; 13874 13875 neon_dp_fixup (&inst); 13876 } 13877 else 13878 { 13879 /* A more-specific type check for non-max versions. */ 13880 et = neon_check_type (2, NS_QDI, 13881 N_EQK | N_DBL, N_SU_32 | N_KEY); 13882 NEON_ENCODE (IMMED, inst); 13883 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); 13884 } 13885} 13886 13887/* Check the various types for the VCVT instruction, and return which version 13888 the current instruction is. */ 13889 13890static int 13891neon_cvt_flavour (enum neon_shape rs) 13892{ 13893#define CVT_VAR(C,X,Y) \ 13894 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ 13895 if (et.type != NT_invtype) \ 13896 { \ 13897 inst.error = NULL; \ 13898 return (C); \ 13899 } 13900 struct neon_type_el et; 13901 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF 13902 || rs == NS_FF) ? N_VFP : 0; 13903 /* The instruction versions which take an immediate take one register 13904 argument, which is extended to the width of the full register. Thus the 13905 "source" and "destination" registers must have the same width. Hack that 13906 here by making the size equal to the key (wider, in this case) operand. */ 13907 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; 13908 13909 CVT_VAR (0, N_S32, N_F32); 13910 CVT_VAR (1, N_U32, N_F32); 13911 CVT_VAR (2, N_F32, N_S32); 13912 CVT_VAR (3, N_F32, N_U32); 13913 /* Half-precision conversions. */ 13914 CVT_VAR (4, N_F32, N_F16); 13915 CVT_VAR (5, N_F16, N_F32); 13916 13917 whole_reg = N_VFP; 13918 13919 /* VFP instructions. */ 13920 CVT_VAR (6, N_F32, N_F64); 13921 CVT_VAR (7, N_F64, N_F32); 13922 CVT_VAR (8, N_S32, N_F64 | key); 13923 CVT_VAR (9, N_U32, N_F64 | key); 13924 CVT_VAR (10, N_F64 | key, N_S32); 13925 CVT_VAR (11, N_F64 | key, N_U32); 13926 /* VFP instructions with bitshift. */ 13927 CVT_VAR (12, N_F32 | key, N_S16); 13928 CVT_VAR (13, N_F32 | key, N_U16); 13929 CVT_VAR (14, N_F64 | key, N_S16); 13930 CVT_VAR (15, N_F64 | key, N_U16); 13931 CVT_VAR (16, N_S16, N_F32 | key); 13932 CVT_VAR (17, N_U16, N_F32 | key); 13933 CVT_VAR (18, N_S16, N_F64 | key); 13934 CVT_VAR (19, N_U16, N_F64 | key); 13935 13936 return -1; 13937#undef CVT_VAR 13938} 13939 13940/* Neon-syntax VFP conversions. */ 13941 13942static void 13943do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) 13944{ 13945 const char *opname = 0; 13946 13947 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) 13948 { 13949 /* Conversions with immediate bitshift. */ 13950 const char *enc[] = 13951 { 13952 "ftosls", 13953 "ftouls", 13954 "fsltos", 13955 "fultos", 13956 NULL, 13957 NULL, 13958 NULL, 13959 NULL, 13960 "ftosld", 13961 "ftould", 13962 "fsltod", 13963 "fultod", 13964 "fshtos", 13965 "fuhtos", 13966 "fshtod", 13967 "fuhtod", 13968 "ftoshs", 13969 "ftouhs", 13970 "ftoshd", 13971 "ftouhd" 13972 }; 13973 13974 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) 13975 { 13976 opname = enc[flavour]; 13977 constraint (inst.operands[0].reg != inst.operands[1].reg, 13978 _("operands 0 and 1 must be the same register")); 13979 inst.operands[1] = inst.operands[2]; 13980 memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); 13981 } 13982 } 13983 else 13984 { 13985 /* Conversions without bitshift. */ 13986 const char *enc[] = 13987 { 13988 "ftosis", 13989 "ftouis", 13990 "fsitos", 13991 "fuitos", 13992 "NULL", 13993 "NULL", 13994 "fcvtsd", 13995 "fcvtds", 13996 "ftosid", 13997 "ftouid", 13998 "fsitod", 13999 "fuitod" 14000 }; 14001 14002 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) 14003 opname = enc[flavour]; 14004 } 14005 14006 if (opname) 14007 do_vfp_nsyn_opcode (opname); 14008} 14009 14010static void 14011do_vfp_nsyn_cvtz (void) 14012{ 14013 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); 14014 int flavour = neon_cvt_flavour (rs); 14015 const char *enc[] = 14016 { 14017 "ftosizs", 14018 "ftouizs", 14019 NULL, 14020 NULL, 14021 NULL, 14022 NULL, 14023 NULL, 14024 NULL, 14025 "ftosizd", 14026 "ftouizd" 14027 }; 14028 14029 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) 14030 do_vfp_nsyn_opcode (enc[flavour]); 14031} 14032 14033static void 14034do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED) 14035{ 14036 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, 14037 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL); 14038 int flavour = neon_cvt_flavour (rs); 14039 14040 /* PR11109: Handle round-to-zero for VCVT conversions. */ 14041 if (round_to_zero 14042 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) 14043 && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9) 14044 && (rs == NS_FD || rs == NS_FF)) 14045 { 14046 do_vfp_nsyn_cvtz (); 14047 return; 14048 } 14049 14050 /* VFP rather than Neon conversions. */ 14051 if (flavour >= 6) 14052 { 14053 do_vfp_nsyn_cvt (rs, flavour); 14054 return; 14055 } 14056 14057 switch (rs) 14058 { 14059 case NS_DDI: 14060 case NS_QQI: 14061 { 14062 unsigned immbits; 14063 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; 14064 14065 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 14066 return; 14067 14068 /* Fixed-point conversion with #0 immediate is encoded as an 14069 integer conversion. */ 14070 if (inst.operands[2].present && inst.operands[2].imm == 0) 14071 goto int_encode; 14072 immbits = 32 - inst.operands[2].imm; 14073 NEON_ENCODE (IMMED, inst); 14074 if (flavour != -1) 14075 inst.instruction |= enctab[flavour]; 14076 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 14077 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 14078 inst.instruction |= LOW4 (inst.operands[1].reg); 14079 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 14080 inst.instruction |= neon_quad (rs) << 6; 14081 inst.instruction |= 1 << 21; 14082 inst.instruction |= immbits << 16; 14083 14084 neon_dp_fixup (&inst); 14085 } 14086 break; 14087 14088 case NS_DD: 14089 case NS_QQ: 14090 int_encode: 14091 { 14092 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; 14093 14094 NEON_ENCODE (INTEGER, inst); 14095 14096 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 14097 return; 14098 14099 if (flavour != -1) 14100 inst.instruction |= enctab[flavour]; 14101 14102 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 14103 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 14104 inst.instruction |= LOW4 (inst.operands[1].reg); 14105 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 14106 inst.instruction |= neon_quad (rs) << 6; 14107 inst.instruction |= 2 << 18; 14108 14109 neon_dp_fixup (&inst); 14110 } 14111 break; 14112 14113 /* Half-precision conversions for Advanced SIMD -- neon. */ 14114 case NS_QD: 14115 case NS_DQ: 14116 14117 if ((rs == NS_DQ) 14118 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) 14119 { 14120 as_bad (_("operand size must match register width")); 14121 break; 14122 } 14123 14124 if ((rs == NS_QD) 14125 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) 14126 { 14127 as_bad (_("operand size must match register width")); 14128 break; 14129 } 14130 14131 if (rs == NS_DQ) 14132 inst.instruction = 0x3b60600; 14133 else 14134 inst.instruction = 0x3b60700; 14135 14136 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 14137 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 14138 inst.instruction |= LOW4 (inst.operands[1].reg); 14139 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 14140 neon_dp_fixup (&inst); 14141 break; 14142 14143 default: 14144 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ 14145 do_vfp_nsyn_cvt (rs, flavour); 14146 } 14147} 14148 14149static void 14150do_neon_cvtr (void) 14151{ 14152 do_neon_cvt_1 (FALSE); 14153} 14154 14155static void 14156do_neon_cvt (void) 14157{ 14158 do_neon_cvt_1 (TRUE); 14159} 14160 14161static void 14162do_neon_cvtb (void) 14163{ 14164 inst.instruction = 0xeb20a40; 14165 14166 /* The sizes are attached to the mnemonic. */ 14167 if (inst.vectype.el[0].type != NT_invtype 14168 && inst.vectype.el[0].size == 16) 14169 inst.instruction |= 0x00010000; 14170 14171 /* Programmer's syntax: the sizes are attached to the operands. */ 14172 else if (inst.operands[0].vectype.type != NT_invtype 14173 && inst.operands[0].vectype.size == 16) 14174 inst.instruction |= 0x00010000; 14175 14176 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 14177 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); 14178 do_vfp_cond_or_thumb (); 14179} 14180 14181 14182static void 14183do_neon_cvtt (void) 14184{ 14185 do_neon_cvtb (); 14186 inst.instruction |= 0x80; 14187} 14188 14189static void 14190neon_move_immediate (void) 14191{ 14192 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); 14193 struct neon_type_el et = neon_check_type (2, rs, 14194 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); 14195 unsigned immlo, immhi = 0, immbits; 14196 int op, cmode, float_p; 14197 14198 constraint (et.type == NT_invtype, 14199 _("operand size must be specified for immediate VMOV")); 14200 14201 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ 14202 op = (inst.instruction & (1 << 5)) != 0; 14203 14204 immlo = inst.operands[1].imm; 14205 if (inst.operands[1].regisimm) 14206 immhi = inst.operands[1].reg; 14207 14208 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, 14209 _("immediate has bits set outside the operand size")); 14210 14211 float_p = inst.operands[1].immisfloat; 14212 14213 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, 14214 et.size, et.type)) == FAIL) 14215 { 14216 /* Invert relevant bits only. */ 14217 neon_invert_size (&immlo, &immhi, et.size); 14218 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable 14219 with one or the other; those cases are caught by 14220 neon_cmode_for_move_imm. */ 14221 op = !op; 14222 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, 14223 &op, et.size, et.type)) == FAIL) 14224 { 14225 first_error (_("immediate out of range")); 14226 return; 14227 } 14228 } 14229 14230 inst.instruction &= ~(1 << 5); 14231 inst.instruction |= op << 5; 14232 14233 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 14234 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 14235 inst.instruction |= neon_quad (rs) << 6; 14236 inst.instruction |= cmode << 8; 14237 14238 neon_write_immbits (immbits); 14239} 14240 14241static void 14242do_neon_mvn (void) 14243{ 14244 if (inst.operands[1].isreg) 14245 { 14246 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 14247 14248 NEON_ENCODE (INTEGER, inst); 14249 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 14250 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 14251 inst.instruction |= LOW4 (inst.operands[1].reg); 14252 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 14253 inst.instruction |= neon_quad (rs) << 6; 14254 } 14255 else 14256 { 14257 NEON_ENCODE (IMMED, inst); 14258 neon_move_immediate (); 14259 } 14260 14261 neon_dp_fixup (&inst); 14262} 14263 14264/* Encode instructions of form: 14265 14266 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| 14267 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ 14268 14269static void 14270neon_mixed_length (struct neon_type_el et, unsigned size) 14271{ 14272 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 14273 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 14274 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 14275 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 14276 inst.instruction |= LOW4 (inst.operands[2].reg); 14277 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 14278 inst.instruction |= (et.type == NT_unsigned) << 24; 14279 inst.instruction |= neon_logbits (size) << 20; 14280 14281 neon_dp_fixup (&inst); 14282} 14283 14284static void 14285do_neon_dyadic_long (void) 14286{ 14287 /* FIXME: Type checking for lengthening op. */ 14288 struct neon_type_el et = neon_check_type (3, NS_QDD, 14289 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); 14290 neon_mixed_length (et, et.size); 14291} 14292 14293static void 14294do_neon_abal (void) 14295{ 14296 struct neon_type_el et = neon_check_type (3, NS_QDD, 14297 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); 14298 neon_mixed_length (et, et.size); 14299} 14300 14301static void 14302neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) 14303{ 14304 if (inst.operands[2].isscalar) 14305 { 14306 struct neon_type_el et = neon_check_type (3, NS_QDS, 14307 N_EQK | N_DBL, N_EQK, regtypes | N_KEY); 14308 NEON_ENCODE (SCALAR, inst); 14309 neon_mul_mac (et, et.type == NT_unsigned); 14310 } 14311 else 14312 { 14313 struct neon_type_el et = neon_check_type (3, NS_QDD, 14314 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); 14315 NEON_ENCODE (INTEGER, inst); 14316 neon_mixed_length (et, et.size); 14317 } 14318} 14319 14320static void 14321do_neon_mac_maybe_scalar_long (void) 14322{ 14323 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); 14324} 14325 14326static void 14327do_neon_dyadic_wide (void) 14328{ 14329 struct neon_type_el et = neon_check_type (3, NS_QQD, 14330 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); 14331 neon_mixed_length (et, et.size); 14332} 14333 14334static void 14335do_neon_dyadic_narrow (void) 14336{ 14337 struct neon_type_el et = neon_check_type (3, NS_QDD, 14338 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); 14339 /* Operand sign is unimportant, and the U bit is part of the opcode, 14340 so force the operand type to integer. */ 14341 et.type = NT_integer; 14342 neon_mixed_length (et, et.size / 2); 14343} 14344 14345static void 14346do_neon_mul_sat_scalar_long (void) 14347{ 14348 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); 14349} 14350 14351static void 14352do_neon_vmull (void) 14353{ 14354 if (inst.operands[2].isscalar) 14355 do_neon_mac_maybe_scalar_long (); 14356 else 14357 { 14358 struct neon_type_el et = neon_check_type (3, NS_QDD, 14359 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); 14360 if (et.type == NT_poly) 14361 NEON_ENCODE (POLY, inst); 14362 else 14363 NEON_ENCODE (INTEGER, inst); 14364 /* For polynomial encoding, size field must be 0b00 and the U bit must be 14365 zero. Should be OK as-is. */ 14366 neon_mixed_length (et, et.size); 14367 } 14368} 14369 14370static void 14371do_neon_ext (void) 14372{ 14373 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); 14374 struct neon_type_el et = neon_check_type (3, rs, 14375 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 14376 unsigned imm = (inst.operands[3].imm * et.size) / 8; 14377 14378 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), 14379 _("shift out of range")); 14380 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 14381 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 14382 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 14383 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 14384 inst.instruction |= LOW4 (inst.operands[2].reg); 14385 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 14386 inst.instruction |= neon_quad (rs) << 6; 14387 inst.instruction |= imm << 8; 14388 14389 neon_dp_fixup (&inst); 14390} 14391 14392static void 14393do_neon_rev (void) 14394{ 14395 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 14396 struct neon_type_el et = neon_check_type (2, rs, 14397 N_EQK, N_8 | N_16 | N_32 | N_KEY); 14398 unsigned op = (inst.instruction >> 7) & 3; 14399 /* N (width of reversed regions) is encoded as part of the bitmask. We 14400 extract it here to check the elements to be reversed are smaller. 14401 Otherwise we'd get a reserved instruction. */ 14402 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; 14403 gas_assert (elsize != 0); 14404 constraint (et.size >= elsize, 14405 _("elements must be smaller than reversal region")); 14406 neon_two_same (neon_quad (rs), 1, et.size); 14407} 14408 14409static void 14410do_neon_dup (void) 14411{ 14412 if (inst.operands[1].isscalar) 14413 { 14414 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); 14415 struct neon_type_el et = neon_check_type (2, rs, 14416 N_EQK, N_8 | N_16 | N_32 | N_KEY); 14417 unsigned sizebits = et.size >> 3; 14418 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); 14419 int logsize = neon_logbits (et.size); 14420 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; 14421 14422 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) 14423 return; 14424 14425 NEON_ENCODE (SCALAR, inst); 14426 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 14427 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 14428 inst.instruction |= LOW4 (dm); 14429 inst.instruction |= HI1 (dm) << 5; 14430 inst.instruction |= neon_quad (rs) << 6; 14431 inst.instruction |= x << 17; 14432 inst.instruction |= sizebits << 16; 14433 14434 neon_dp_fixup (&inst); 14435 } 14436 else 14437 { 14438 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); 14439 struct neon_type_el et = neon_check_type (2, rs, 14440 N_8 | N_16 | N_32 | N_KEY, N_EQK); 14441 /* Duplicate ARM register to lanes of vector. */ 14442 NEON_ENCODE (ARMREG, inst); 14443 switch (et.size) 14444 { 14445 case 8: inst.instruction |= 0x400000; break; 14446 case 16: inst.instruction |= 0x000020; break; 14447 case 32: inst.instruction |= 0x000000; break; 14448 default: break; 14449 } 14450 inst.instruction |= LOW4 (inst.operands[1].reg) << 12; 14451 inst.instruction |= LOW4 (inst.operands[0].reg) << 16; 14452 inst.instruction |= HI1 (inst.operands[0].reg) << 7; 14453 inst.instruction |= neon_quad (rs) << 21; 14454 /* The encoding for this instruction is identical for the ARM and Thumb 14455 variants, except for the condition field. */ 14456 do_vfp_cond_or_thumb (); 14457 } 14458} 14459 14460/* VMOV has particularly many variations. It can be one of: 14461 0. VMOV<c><q> <Qd>, <Qm> 14462 1. VMOV<c><q> <Dd>, <Dm> 14463 (Register operations, which are VORR with Rm = Rn.) 14464 2. VMOV<c><q>.<dt> <Qd>, #<imm> 14465 3. VMOV<c><q>.<dt> <Dd>, #<imm> 14466 (Immediate loads.) 14467 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> 14468 (ARM register to scalar.) 14469 5. VMOV<c><q> <Dm>, <Rd>, <Rn> 14470 (Two ARM registers to vector.) 14471 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> 14472 (Scalar to ARM register.) 14473 7. VMOV<c><q> <Rd>, <Rn>, <Dm> 14474 (Vector to two ARM registers.) 14475 8. VMOV.F32 <Sd>, <Sm> 14476 9. VMOV.F64 <Dd>, <Dm> 14477 (VFP register moves.) 14478 10. VMOV.F32 <Sd>, #imm 14479 11. VMOV.F64 <Dd>, #imm 14480 (VFP float immediate load.) 14481 12. VMOV <Rd>, <Sm> 14482 (VFP single to ARM reg.) 14483 13. VMOV <Sd>, <Rm> 14484 (ARM reg to VFP single.) 14485 14. VMOV <Rd>, <Re>, <Sn>, <Sm> 14486 (Two ARM regs to two VFP singles.) 14487 15. VMOV <Sd>, <Se>, <Rn>, <Rm> 14488 (Two VFP singles to two ARM regs.) 14489 14490 These cases can be disambiguated using neon_select_shape, except cases 1/9 14491 and 3/11 which depend on the operand type too. 14492 14493 All the encoded bits are hardcoded by this function. 14494 14495 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). 14496 Cases 5, 7 may be used with VFPv2 and above. 14497 14498 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you 14499 can specify a type where it doesn't make sense to, and is ignored). */ 14500 14501static void 14502do_neon_mov (void) 14503{ 14504 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, 14505 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, 14506 NS_NULL); 14507 struct neon_type_el et; 14508 const char *ldconst = 0; 14509 14510 switch (rs) 14511 { 14512 case NS_DD: /* case 1/9. */ 14513 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); 14514 /* It is not an error here if no type is given. */ 14515 inst.error = NULL; 14516 if (et.type == NT_float && et.size == 64) 14517 { 14518 do_vfp_nsyn_opcode ("fcpyd"); 14519 break; 14520 } 14521 /* fall through. */ 14522 14523 case NS_QQ: /* case 0/1. */ 14524 { 14525 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 14526 return; 14527 /* The architecture manual I have doesn't explicitly state which 14528 value the U bit should have for register->register moves, but 14529 the equivalent VORR instruction has U = 0, so do that. */ 14530 inst.instruction = 0x0200110; 14531 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 14532 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 14533 inst.instruction |= LOW4 (inst.operands[1].reg); 14534 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 14535 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 14536 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 14537 inst.instruction |= neon_quad (rs) << 6; 14538 14539 neon_dp_fixup (&inst); 14540 } 14541 break; 14542 14543 case NS_DI: /* case 3/11. */ 14544 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); 14545 inst.error = NULL; 14546 if (et.type == NT_float && et.size == 64) 14547 { 14548 /* case 11 (fconstd). */ 14549 ldconst = "fconstd"; 14550 goto encode_fconstd; 14551 } 14552 /* fall through. */ 14553 14554 case NS_QI: /* case 2/3. */ 14555 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 14556 return; 14557 inst.instruction = 0x0800010; 14558 neon_move_immediate (); 14559 neon_dp_fixup (&inst); 14560 break; 14561 14562 case NS_SR: /* case 4. */ 14563 { 14564 unsigned bcdebits = 0; 14565 int logsize; 14566 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); 14567 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); 14568 14569 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); 14570 logsize = neon_logbits (et.size); 14571 14572 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), 14573 _(BAD_FPU)); 14574 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) 14575 && et.size != 32, _(BAD_FPU)); 14576 constraint (et.type == NT_invtype, _("bad type for scalar")); 14577 constraint (x >= 64 / et.size, _("scalar index out of range")); 14578 14579 switch (et.size) 14580 { 14581 case 8: bcdebits = 0x8; break; 14582 case 16: bcdebits = 0x1; break; 14583 case 32: bcdebits = 0x0; break; 14584 default: ; 14585 } 14586 14587 bcdebits |= x << logsize; 14588 14589 inst.instruction = 0xe000b10; 14590 do_vfp_cond_or_thumb (); 14591 inst.instruction |= LOW4 (dn) << 16; 14592 inst.instruction |= HI1 (dn) << 7; 14593 inst.instruction |= inst.operands[1].reg << 12; 14594 inst.instruction |= (bcdebits & 3) << 5; 14595 inst.instruction |= (bcdebits >> 2) << 21; 14596 } 14597 break; 14598 14599 case NS_DRR: /* case 5 (fmdrr). */ 14600 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), 14601 _(BAD_FPU)); 14602 14603 inst.instruction = 0xc400b10; 14604 do_vfp_cond_or_thumb (); 14605 inst.instruction |= LOW4 (inst.operands[0].reg); 14606 inst.instruction |= HI1 (inst.operands[0].reg) << 5; 14607 inst.instruction |= inst.operands[1].reg << 12; 14608 inst.instruction |= inst.operands[2].reg << 16; 14609 break; 14610 14611 case NS_RS: /* case 6. */ 14612 { 14613 unsigned logsize; 14614 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); 14615 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); 14616 unsigned abcdebits = 0; 14617 14618 et = neon_check_type (2, NS_NULL, 14619 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); 14620 logsize = neon_logbits (et.size); 14621 14622 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), 14623 _(BAD_FPU)); 14624 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) 14625 && et.size != 32, _(BAD_FPU)); 14626 constraint (et.type == NT_invtype, _("bad type for scalar")); 14627 constraint (x >= 64 / et.size, _("scalar index out of range")); 14628 14629 switch (et.size) 14630 { 14631 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; 14632 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; 14633 case 32: abcdebits = 0x00; break; 14634 default: ; 14635 } 14636 14637 abcdebits |= x << logsize; 14638 inst.instruction = 0xe100b10; 14639 do_vfp_cond_or_thumb (); 14640 inst.instruction |= LOW4 (dn) << 16; 14641 inst.instruction |= HI1 (dn) << 7; 14642 inst.instruction |= inst.operands[0].reg << 12; 14643 inst.instruction |= (abcdebits & 3) << 5; 14644 inst.instruction |= (abcdebits >> 2) << 21; 14645 } 14646 break; 14647 14648 case NS_RRD: /* case 7 (fmrrd). */ 14649 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), 14650 _(BAD_FPU)); 14651 14652 inst.instruction = 0xc500b10; 14653 do_vfp_cond_or_thumb (); 14654 inst.instruction |= inst.operands[0].reg << 12; 14655 inst.instruction |= inst.operands[1].reg << 16; 14656 inst.instruction |= LOW4 (inst.operands[2].reg); 14657 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 14658 break; 14659 14660 case NS_FF: /* case 8 (fcpys). */ 14661 do_vfp_nsyn_opcode ("fcpys"); 14662 break; 14663 14664 case NS_FI: /* case 10 (fconsts). */ 14665 ldconst = "fconsts"; 14666 encode_fconstd: 14667 if (is_quarter_float (inst.operands[1].imm)) 14668 { 14669 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); 14670 do_vfp_nsyn_opcode (ldconst); 14671 } 14672 else 14673 first_error (_("immediate out of range")); 14674 break; 14675 14676 case NS_RF: /* case 12 (fmrs). */ 14677 do_vfp_nsyn_opcode ("fmrs"); 14678 break; 14679 14680 case NS_FR: /* case 13 (fmsr). */ 14681 do_vfp_nsyn_opcode ("fmsr"); 14682 break; 14683 14684 /* The encoders for the fmrrs and fmsrr instructions expect three operands 14685 (one of which is a list), but we have parsed four. Do some fiddling to 14686 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 14687 expect. */ 14688 case NS_RRFF: /* case 14 (fmrrs). */ 14689 constraint (inst.operands[3].reg != inst.operands[2].reg + 1, 14690 _("VFP registers must be adjacent")); 14691 inst.operands[2].imm = 2; 14692 memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); 14693 do_vfp_nsyn_opcode ("fmrrs"); 14694 break; 14695 14696 case NS_FFRR: /* case 15 (fmsrr). */ 14697 constraint (inst.operands[1].reg != inst.operands[0].reg + 1, 14698 _("VFP registers must be adjacent")); 14699 inst.operands[1] = inst.operands[2]; 14700 inst.operands[2] = inst.operands[3]; 14701 inst.operands[0].imm = 2; 14702 memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); 14703 do_vfp_nsyn_opcode ("fmsrr"); 14704 break; 14705 14706 default: 14707 abort (); 14708 } 14709} 14710 14711static void 14712do_neon_rshift_round_imm (void) 14713{ 14714 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 14715 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); 14716 int imm = inst.operands[2].imm; 14717 14718 /* imm == 0 case is encoded as VMOV for V{R}SHR. */ 14719 if (imm == 0) 14720 { 14721 inst.operands[2].present = 0; 14722 do_neon_mov (); 14723 return; 14724 } 14725 14726 constraint (imm < 1 || (unsigned)imm > et.size, 14727 _("immediate out of range for shift")); 14728 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, 14729 et.size - imm); 14730} 14731 14732static void 14733do_neon_movl (void) 14734{ 14735 struct neon_type_el et = neon_check_type (2, NS_QD, 14736 N_EQK | N_DBL, N_SU_32 | N_KEY); 14737 unsigned sizebits = et.size >> 3; 14738 inst.instruction |= sizebits << 19; 14739 neon_two_same (0, et.type == NT_unsigned, -1); 14740} 14741 14742static void 14743do_neon_trn (void) 14744{ 14745 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 14746 struct neon_type_el et = neon_check_type (2, rs, 14747 N_EQK, N_8 | N_16 | N_32 | N_KEY); 14748 NEON_ENCODE (INTEGER, inst); 14749 neon_two_same (neon_quad (rs), 1, et.size); 14750} 14751 14752static void 14753do_neon_zip_uzp (void) 14754{ 14755 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 14756 struct neon_type_el et = neon_check_type (2, rs, 14757 N_EQK, N_8 | N_16 | N_32 | N_KEY); 14758 if (rs == NS_DD && et.size == 32) 14759 { 14760 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ 14761 inst.instruction = N_MNEM_vtrn; 14762 do_neon_trn (); 14763 return; 14764 } 14765 neon_two_same (neon_quad (rs), 1, et.size); 14766} 14767 14768static void 14769do_neon_sat_abs_neg (void) 14770{ 14771 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 14772 struct neon_type_el et = neon_check_type (2, rs, 14773 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); 14774 neon_two_same (neon_quad (rs), 1, et.size); 14775} 14776 14777static void 14778do_neon_pair_long (void) 14779{ 14780 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 14781 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); 14782 /* Unsigned is encoded in OP field (bit 7) for these instruction. */ 14783 inst.instruction |= (et.type == NT_unsigned) << 7; 14784 neon_two_same (neon_quad (rs), 1, et.size); 14785} 14786 14787static void 14788do_neon_recip_est (void) 14789{ 14790 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 14791 struct neon_type_el et = neon_check_type (2, rs, 14792 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); 14793 inst.instruction |= (et.type == NT_float) << 8; 14794 neon_two_same (neon_quad (rs), 1, et.size); 14795} 14796 14797static void 14798do_neon_cls (void) 14799{ 14800 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 14801 struct neon_type_el et = neon_check_type (2, rs, 14802 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); 14803 neon_two_same (neon_quad (rs), 1, et.size); 14804} 14805 14806static void 14807do_neon_clz (void) 14808{ 14809 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 14810 struct neon_type_el et = neon_check_type (2, rs, 14811 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); 14812 neon_two_same (neon_quad (rs), 1, et.size); 14813} 14814 14815static void 14816do_neon_cnt (void) 14817{ 14818 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 14819 struct neon_type_el et = neon_check_type (2, rs, 14820 N_EQK | N_INT, N_8 | N_KEY); 14821 neon_two_same (neon_quad (rs), 1, et.size); 14822} 14823 14824static void 14825do_neon_swp (void) 14826{ 14827 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 14828 neon_two_same (neon_quad (rs), 1, -1); 14829} 14830 14831static void 14832do_neon_tbl_tbx (void) 14833{ 14834 unsigned listlenbits; 14835 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); 14836 14837 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) 14838 { 14839 first_error (_("bad list length for table lookup")); 14840 return; 14841 } 14842 14843 listlenbits = inst.operands[1].imm - 1; 14844 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 14845 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 14846 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 14847 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 14848 inst.instruction |= LOW4 (inst.operands[2].reg); 14849 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 14850 inst.instruction |= listlenbits << 8; 14851 14852 neon_dp_fixup (&inst); 14853} 14854 14855static void 14856do_neon_ldm_stm (void) 14857{ 14858 /* P, U and L bits are part of bitmask. */ 14859 int is_dbmode = (inst.instruction & (1 << 24)) != 0; 14860 unsigned offsetbits = inst.operands[1].imm * 2; 14861 14862 if (inst.operands[1].issingle) 14863 { 14864 do_vfp_nsyn_ldm_stm (is_dbmode); 14865 return; 14866 } 14867 14868 constraint (is_dbmode && !inst.operands[0].writeback, 14869 _("writeback (!) must be used for VLDMDB and VSTMDB")); 14870 14871 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, 14872 _("register list must contain at least 1 and at most 16 " 14873 "registers")); 14874 14875 inst.instruction |= inst.operands[0].reg << 16; 14876 inst.instruction |= inst.operands[0].writeback << 21; 14877 inst.instruction |= LOW4 (inst.operands[1].reg) << 12; 14878 inst.instruction |= HI1 (inst.operands[1].reg) << 22; 14879 14880 inst.instruction |= offsetbits; 14881 14882 do_vfp_cond_or_thumb (); 14883} 14884 14885static void 14886do_neon_ldr_str (void) 14887{ 14888 int is_ldr = (inst.instruction & (1 << 20)) != 0; 14889 14890 /* Use of PC in vstr in ARM mode is deprecated in ARMv7. 14891 And is UNPREDICTABLE in thumb mode. */ 14892 if (!is_ldr 14893 && inst.operands[1].reg == REG_PC 14894 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) 14895 { 14896 if (!thumb_mode && warn_on_deprecated) 14897 as_warn (_("Use of PC here is deprecated")); 14898 else 14899 inst.error = _("Use of PC here is UNPREDICTABLE"); 14900 } 14901 14902 if (inst.operands[0].issingle) 14903 { 14904 if (is_ldr) 14905 do_vfp_nsyn_opcode ("flds"); 14906 else 14907 do_vfp_nsyn_opcode ("fsts"); 14908 } 14909 else 14910 { 14911 if (is_ldr) 14912 do_vfp_nsyn_opcode ("fldd"); 14913 else 14914 do_vfp_nsyn_opcode ("fstd"); 14915 } 14916} 14917 14918/* "interleave" version also handles non-interleaving register VLD1/VST1 14919 instructions. */ 14920 14921static void 14922do_neon_ld_st_interleave (void) 14923{ 14924 struct neon_type_el et = neon_check_type (1, NS_NULL, 14925 N_8 | N_16 | N_32 | N_64); 14926 unsigned alignbits = 0; 14927 unsigned idx; 14928 /* The bits in this table go: 14929 0: register stride of one (0) or two (1) 14930 1,2: register list length, minus one (1, 2, 3, 4). 14931 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). 14932 We use -1 for invalid entries. */ 14933 const int typetable[] = 14934 { 14935 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ 14936 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ 14937 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ 14938 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ 14939 }; 14940 int typebits; 14941 14942 if (et.type == NT_invtype) 14943 return; 14944 14945 if (inst.operands[1].immisalign) 14946 switch (inst.operands[1].imm >> 8) 14947 { 14948 case 64: alignbits = 1; break; 14949 case 128: 14950 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 14951 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) 14952 goto bad_alignment; 14953 alignbits = 2; 14954 break; 14955 case 256: 14956 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) 14957 goto bad_alignment; 14958 alignbits = 3; 14959 break; 14960 default: 14961 bad_alignment: 14962 first_error (_("bad alignment")); 14963 return; 14964 } 14965 14966 inst.instruction |= alignbits << 4; 14967 inst.instruction |= neon_logbits (et.size) << 6; 14968 14969 /* Bits [4:6] of the immediate in a list specifier encode register stride 14970 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of 14971 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look 14972 up the right value for "type" in a table based on this value and the given 14973 list style, then stick it back. */ 14974 idx = ((inst.operands[0].imm >> 4) & 7) 14975 | (((inst.instruction >> 8) & 3) << 3); 14976 14977 typebits = typetable[idx]; 14978 14979 constraint (typebits == -1, _("bad list type for instruction")); 14980 14981 inst.instruction &= ~0xf00; 14982 inst.instruction |= typebits << 8; 14983} 14984 14985/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. 14986 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 14987 otherwise. The variable arguments are a list of pairs of legal (size, align) 14988 values, terminated with -1. */ 14989 14990static int 14991neon_alignment_bit (int size, int align, int *do_align, ...) 14992{ 14993 va_list ap; 14994 int result = FAIL, thissize, thisalign; 14995 14996 if (!inst.operands[1].immisalign) 14997 { 14998 *do_align = 0; 14999 return SUCCESS; 15000 } 15001 15002 va_start (ap, do_align); 15003 15004 do 15005 { 15006 thissize = va_arg (ap, int); 15007 if (thissize == -1) 15008 break; 15009 thisalign = va_arg (ap, int); 15010 15011 if (size == thissize && align == thisalign) 15012 result = SUCCESS; 15013 } 15014 while (result != SUCCESS); 15015 15016 va_end (ap); 15017 15018 if (result == SUCCESS) 15019 *do_align = 1; 15020 else 15021 first_error (_("unsupported alignment for instruction")); 15022 15023 return result; 15024} 15025 15026static void 15027do_neon_ld_st_lane (void) 15028{ 15029 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); 15030 int align_good, do_align = 0; 15031 int logsize = neon_logbits (et.size); 15032 int align = inst.operands[1].imm >> 8; 15033 int n = (inst.instruction >> 8) & 3; 15034 int max_el = 64 / et.size; 15035 15036 if (et.type == NT_invtype) 15037 return; 15038 15039 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, 15040 _("bad list length")); 15041 constraint (NEON_LANE (inst.operands[0].imm) >= max_el, 15042 _("scalar index out of range")); 15043 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 15044 && et.size == 8, 15045 _("stride of 2 unavailable when element size is 8")); 15046 15047 switch (n) 15048 { 15049 case 0: /* VLD1 / VST1. */ 15050 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, 15051 32, 32, -1); 15052 if (align_good == FAIL) 15053 return; 15054 if (do_align) 15055 { 15056 unsigned alignbits = 0; 15057 switch (et.size) 15058 { 15059 case 16: alignbits = 0x1; break; 15060 case 32: alignbits = 0x3; break; 15061 default: ; 15062 } 15063 inst.instruction |= alignbits << 4; 15064 } 15065 break; 15066 15067 case 1: /* VLD2 / VST2. */ 15068 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, 15069 32, 64, -1); 15070 if (align_good == FAIL) 15071 return; 15072 if (do_align) 15073 inst.instruction |= 1 << 4; 15074 break; 15075 15076 case 2: /* VLD3 / VST3. */ 15077 constraint (inst.operands[1].immisalign, 15078 _("can't use alignment with this instruction")); 15079 break; 15080 15081 case 3: /* VLD4 / VST4. */ 15082 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, 15083 16, 64, 32, 64, 32, 128, -1); 15084 if (align_good == FAIL) 15085 return; 15086 if (do_align) 15087 { 15088 unsigned alignbits = 0; 15089 switch (et.size) 15090 { 15091 case 8: alignbits = 0x1; break; 15092 case 16: alignbits = 0x1; break; 15093 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; 15094 default: ; 15095 } 15096 inst.instruction |= alignbits << 4; 15097 } 15098 break; 15099 15100 default: ; 15101 } 15102 15103 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ 15104 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) 15105 inst.instruction |= 1 << (4 + logsize); 15106 15107 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); 15108 inst.instruction |= logsize << 10; 15109} 15110 15111/* Encode single n-element structure to all lanes VLD<n> instructions. */ 15112 15113static void 15114do_neon_ld_dup (void) 15115{ 15116 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); 15117 int align_good, do_align = 0; 15118 15119 if (et.type == NT_invtype) 15120 return; 15121 15122 switch ((inst.instruction >> 8) & 3) 15123 { 15124 case 0: /* VLD1. */ 15125 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); 15126 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, 15127 &do_align, 16, 16, 32, 32, -1); 15128 if (align_good == FAIL) 15129 return; 15130 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) 15131 { 15132 case 1: break; 15133 case 2: inst.instruction |= 1 << 5; break; 15134 default: first_error (_("bad list length")); return; 15135 } 15136 inst.instruction |= neon_logbits (et.size) << 6; 15137 break; 15138 15139 case 1: /* VLD2. */ 15140 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, 15141 &do_align, 8, 16, 16, 32, 32, 64, -1); 15142 if (align_good == FAIL) 15143 return; 15144 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, 15145 _("bad list length")); 15146 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 15147 inst.instruction |= 1 << 5; 15148 inst.instruction |= neon_logbits (et.size) << 6; 15149 break; 15150 15151 case 2: /* VLD3. */ 15152 constraint (inst.operands[1].immisalign, 15153 _("can't use alignment with this instruction")); 15154 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, 15155 _("bad list length")); 15156 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 15157 inst.instruction |= 1 << 5; 15158 inst.instruction |= neon_logbits (et.size) << 6; 15159 break; 15160 15161 case 3: /* VLD4. */ 15162 { 15163 int align = inst.operands[1].imm >> 8; 15164 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, 15165 16, 64, 32, 64, 32, 128, -1); 15166 if (align_good == FAIL) 15167 return; 15168 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, 15169 _("bad list length")); 15170 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 15171 inst.instruction |= 1 << 5; 15172 if (et.size == 32 && align == 128) 15173 inst.instruction |= 0x3 << 6; 15174 else 15175 inst.instruction |= neon_logbits (et.size) << 6; 15176 } 15177 break; 15178 15179 default: ; 15180 } 15181 15182 inst.instruction |= do_align << 4; 15183} 15184 15185/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those 15186 apart from bits [11:4]. */ 15187 15188static void 15189do_neon_ldx_stx (void) 15190{ 15191 if (inst.operands[1].isreg) 15192 constraint (inst.operands[1].reg == REG_PC, BAD_PC); 15193 15194 switch (NEON_LANE (inst.operands[0].imm)) 15195 { 15196 case NEON_INTERLEAVE_LANES: 15197 NEON_ENCODE (INTERLV, inst); 15198 do_neon_ld_st_interleave (); 15199 break; 15200 15201 case NEON_ALL_LANES: 15202 NEON_ENCODE (DUP, inst); 15203 do_neon_ld_dup (); 15204 break; 15205 15206 default: 15207 NEON_ENCODE (LANE, inst); 15208 do_neon_ld_st_lane (); 15209 } 15210 15211 /* L bit comes from bit mask. */ 15212 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 15213 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 15214 inst.instruction |= inst.operands[1].reg << 16; 15215 15216 if (inst.operands[1].postind) 15217 { 15218 int postreg = inst.operands[1].imm & 0xf; 15219 constraint (!inst.operands[1].immisreg, 15220 _("post-index must be a register")); 15221 constraint (postreg == 0xd || postreg == 0xf, 15222 _("bad register for post-index")); 15223 inst.instruction |= postreg; 15224 } 15225 else if (inst.operands[1].writeback) 15226 { 15227 inst.instruction |= 0xd; 15228 } 15229 else 15230 inst.instruction |= 0xf; 15231 15232 if (thumb_mode) 15233 inst.instruction |= 0xf9000000; 15234 else 15235 inst.instruction |= 0xf4000000; 15236} 15237 15238/* Overall per-instruction processing. */ 15239 15240/* We need to be able to fix up arbitrary expressions in some statements. 15241 This is so that we can handle symbols that are an arbitrary distance from 15242 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), 15243 which returns part of an address in a form which will be valid for 15244 a data instruction. We do this by pushing the expression into a symbol 15245 in the expr_section, and creating a fix for that. */ 15246 15247static void 15248fix_new_arm (fragS * frag, 15249 int where, 15250 short int size, 15251 expressionS * exp, 15252 int pc_rel, 15253 int reloc) 15254{ 15255 fixS * new_fix; 15256 15257 switch (exp->X_op) 15258 { 15259 case O_constant: 15260 case O_symbol: 15261 case O_add: 15262 case O_subtract: 15263 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, 15264 (enum bfd_reloc_code_real) reloc); 15265 break; 15266 15267 default: 15268 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, 15269 pc_rel, (enum bfd_reloc_code_real) reloc); 15270 break; 15271 } 15272 15273 /* Mark whether the fix is to a THUMB instruction, or an ARM 15274 instruction. */ 15275 new_fix->tc_fix_data = thumb_mode; 15276} 15277 15278/* Create a frg for an instruction requiring relaxation. */ 15279static void 15280output_relax_insn (void) 15281{ 15282 char * to; 15283 symbolS *sym; 15284 int offset; 15285 15286 /* The size of the instruction is unknown, so tie the debug info to the 15287 start of the instruction. */ 15288 dwarf2_emit_insn (0); 15289 15290 switch (inst.reloc.exp.X_op) 15291 { 15292 case O_symbol: 15293 sym = inst.reloc.exp.X_add_symbol; 15294 offset = inst.reloc.exp.X_add_number; 15295 break; 15296 case O_constant: 15297 sym = NULL; 15298 offset = inst.reloc.exp.X_add_number; 15299 break; 15300 default: 15301 sym = make_expr_symbol (&inst.reloc.exp); 15302 offset = 0; 15303 break; 15304 } 15305 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, 15306 inst.relax, sym, offset, NULL/*offset, opcode*/); 15307 md_number_to_chars (to, inst.instruction, THUMB_SIZE); 15308} 15309 15310/* Write a 32-bit thumb instruction to buf. */ 15311static void 15312put_thumb32_insn (char * buf, unsigned long insn) 15313{ 15314 md_number_to_chars (buf, insn >> 16, THUMB_SIZE); 15315 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); 15316} 15317 15318static void 15319output_inst (const char * str) 15320{ 15321 char * to = NULL; 15322 15323 if (inst.error) 15324 { 15325 as_bad ("%s -- `%s'", inst.error, str); 15326 return; 15327 } 15328 if (inst.relax) 15329 { 15330 output_relax_insn (); 15331 return; 15332 } 15333 if (inst.size == 0) 15334 return; 15335 15336 to = frag_more (inst.size); 15337 /* PR 9814: Record the thumb mode into the current frag so that we know 15338 what type of NOP padding to use, if necessary. We override any previous 15339 setting so that if the mode has changed then the NOPS that we use will 15340 match the encoding of the last instruction in the frag. */ 15341 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; 15342 15343 if (thumb_mode && (inst.size > THUMB_SIZE)) 15344 { 15345 gas_assert (inst.size == (2 * THUMB_SIZE)); 15346 put_thumb32_insn (to, inst.instruction); 15347 } 15348 else if (inst.size > INSN_SIZE) 15349 { 15350 gas_assert (inst.size == (2 * INSN_SIZE)); 15351 md_number_to_chars (to, inst.instruction, INSN_SIZE); 15352 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); 15353 } 15354 else 15355 md_number_to_chars (to, inst.instruction, inst.size); 15356 15357 if (inst.reloc.type != BFD_RELOC_UNUSED) 15358 fix_new_arm (frag_now, to - frag_now->fr_literal, 15359 inst.size, & inst.reloc.exp, inst.reloc.pc_rel, 15360 inst.reloc.type); 15361 15362 dwarf2_emit_insn (inst.size); 15363} 15364 15365static char * 15366output_it_inst (int cond, int mask, char * to) 15367{ 15368 unsigned long instruction = 0xbf00; 15369 15370 mask &= 0xf; 15371 instruction |= mask; 15372 instruction |= cond << 4; 15373 15374 if (to == NULL) 15375 { 15376 to = frag_more (2); 15377#ifdef OBJ_ELF 15378 dwarf2_emit_insn (2); 15379#endif 15380 } 15381 15382 md_number_to_chars (to, instruction, 2); 15383 15384 return to; 15385} 15386 15387/* Tag values used in struct asm_opcode's tag field. */ 15388enum opcode_tag 15389{ 15390 OT_unconditional, /* Instruction cannot be conditionalized. 15391 The ARM condition field is still 0xE. */ 15392 OT_unconditionalF, /* Instruction cannot be conditionalized 15393 and carries 0xF in its ARM condition field. */ 15394 OT_csuffix, /* Instruction takes a conditional suffix. */ 15395 OT_csuffixF, /* Some forms of the instruction take a conditional 15396 suffix, others place 0xF where the condition field 15397 would be. */ 15398 OT_cinfix3, /* Instruction takes a conditional infix, 15399 beginning at character index 3. (In 15400 unified mode, it becomes a suffix.) */ 15401 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for 15402 tsts, cmps, cmns, and teqs. */ 15403 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at 15404 character index 3, even in unified mode. Used for 15405 legacy instructions where suffix and infix forms 15406 may be ambiguous. */ 15407 OT_csuf_or_in3, /* Instruction takes either a conditional 15408 suffix or an infix at character index 3. */ 15409 OT_odd_infix_unc, /* This is the unconditional variant of an 15410 instruction that takes a conditional infix 15411 at an unusual position. In unified mode, 15412 this variant will accept a suffix. */ 15413 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 15414 are the conditional variants of instructions that 15415 take conditional infixes in unusual positions. 15416 The infix appears at character index 15417 (tag - OT_odd_infix_0). These are not accepted 15418 in unified mode. */ 15419}; 15420 15421/* Subroutine of md_assemble, responsible for looking up the primary 15422 opcode from the mnemonic the user wrote. STR points to the 15423 beginning of the mnemonic. 15424 15425 This is not simply a hash table lookup, because of conditional 15426 variants. Most instructions have conditional variants, which are 15427 expressed with a _conditional affix_ to the mnemonic. If we were 15428 to encode each conditional variant as a literal string in the opcode 15429 table, it would have approximately 20,000 entries. 15430 15431 Most mnemonics take this affix as a suffix, and in unified syntax, 15432 'most' is upgraded to 'all'. However, in the divided syntax, some 15433 instructions take the affix as an infix, notably the s-variants of 15434 the arithmetic instructions. Of those instructions, all but six 15435 have the infix appear after the third character of the mnemonic. 15436 15437 Accordingly, the algorithm for looking up primary opcodes given 15438 an identifier is: 15439 15440 1. Look up the identifier in the opcode table. 15441 If we find a match, go to step U. 15442 15443 2. Look up the last two characters of the identifier in the 15444 conditions table. If we find a match, look up the first N-2 15445 characters of the identifier in the opcode table. If we 15446 find a match, go to step CE. 15447 15448 3. Look up the fourth and fifth characters of the identifier in 15449 the conditions table. If we find a match, extract those 15450 characters from the identifier, and look up the remaining 15451 characters in the opcode table. If we find a match, go 15452 to step CM. 15453 15454 4. Fail. 15455 15456 U. Examine the tag field of the opcode structure, in case this is 15457 one of the six instructions with its conditional infix in an 15458 unusual place. If it is, the tag tells us where to find the 15459 infix; look it up in the conditions table and set inst.cond 15460 accordingly. Otherwise, this is an unconditional instruction. 15461 Again set inst.cond accordingly. Return the opcode structure. 15462 15463 CE. Examine the tag field to make sure this is an instruction that 15464 should receive a conditional suffix. If it is not, fail. 15465 Otherwise, set inst.cond from the suffix we already looked up, 15466 and return the opcode structure. 15467 15468 CM. Examine the tag field to make sure this is an instruction that 15469 should receive a conditional infix after the third character. 15470 If it is not, fail. Otherwise, undo the edits to the current 15471 line of input and proceed as for case CE. */ 15472 15473static const struct asm_opcode * 15474opcode_lookup (char **str) 15475{ 15476 char *end, *base; 15477 char *affix; 15478 const struct asm_opcode *opcode; 15479 const struct asm_cond *cond; 15480 char save[2]; 15481 15482 /* Scan up to the end of the mnemonic, which must end in white space, 15483 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ 15484 for (base = end = *str; *end != '\0'; end++) 15485 if (*end == ' ' || *end == '.') 15486 break; 15487 15488 if (end == base) 15489 return NULL; 15490 15491 /* Handle a possible width suffix and/or Neon type suffix. */ 15492 if (end[0] == '.') 15493 { 15494 int offset = 2; 15495 15496 /* The .w and .n suffixes are only valid if the unified syntax is in 15497 use. */ 15498 if (unified_syntax && end[1] == 'w') 15499 inst.size_req = 4; 15500 else if (unified_syntax && end[1] == 'n') 15501 inst.size_req = 2; 15502 else 15503 offset = 0; 15504 15505 inst.vectype.elems = 0; 15506 15507 *str = end + offset; 15508 15509 if (end[offset] == '.') 15510 { 15511 /* See if we have a Neon type suffix (possible in either unified or 15512 non-unified ARM syntax mode). */ 15513 if (parse_neon_type (&inst.vectype, str) == FAIL) 15514 return NULL; 15515 } 15516 else if (end[offset] != '\0' && end[offset] != ' ') 15517 return NULL; 15518 } 15519 else 15520 *str = end; 15521 15522 /* Look for unaffixed or special-case affixed mnemonic. */ 15523 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, 15524 end - base); 15525 if (opcode) 15526 { 15527 /* step U */ 15528 if (opcode->tag < OT_odd_infix_0) 15529 { 15530 inst.cond = COND_ALWAYS; 15531 return opcode; 15532 } 15533 15534 if (warn_on_deprecated && unified_syntax) 15535 as_warn (_("conditional infixes are deprecated in unified syntax")); 15536 affix = base + (opcode->tag - OT_odd_infix_0); 15537 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); 15538 gas_assert (cond); 15539 15540 inst.cond = cond->value; 15541 return opcode; 15542 } 15543 15544 /* Cannot have a conditional suffix on a mnemonic of less than two 15545 characters. */ 15546 if (end - base < 3) 15547 return NULL; 15548 15549 /* Look for suffixed mnemonic. */ 15550 affix = end - 2; 15551 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); 15552 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, 15553 affix - base); 15554 if (opcode && cond) 15555 { 15556 /* step CE */ 15557 switch (opcode->tag) 15558 { 15559 case OT_cinfix3_legacy: 15560 /* Ignore conditional suffixes matched on infix only mnemonics. */ 15561 break; 15562 15563 case OT_cinfix3: 15564 case OT_cinfix3_deprecated: 15565 case OT_odd_infix_unc: 15566 if (!unified_syntax) 15567 return 0; 15568 /* else fall through */ 15569 15570 case OT_csuffix: 15571 case OT_csuffixF: 15572 case OT_csuf_or_in3: 15573 inst.cond = cond->value; 15574 return opcode; 15575 15576 case OT_unconditional: 15577 case OT_unconditionalF: 15578 if (thumb_mode) 15579 inst.cond = cond->value; 15580 else 15581 { 15582 /* Delayed diagnostic. */ 15583 inst.error = BAD_COND; 15584 inst.cond = COND_ALWAYS; 15585 } 15586 return opcode; 15587 15588 default: 15589 return NULL; 15590 } 15591 } 15592 15593 /* Cannot have a usual-position infix on a mnemonic of less than 15594 six characters (five would be a suffix). */ 15595 if (end - base < 6) 15596 return NULL; 15597 15598 /* Look for infixed mnemonic in the usual position. */ 15599 affix = base + 3; 15600 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); 15601 if (!cond) 15602 return NULL; 15603 15604 memcpy (save, affix, 2); 15605 memmove (affix, affix + 2, (end - affix) - 2); 15606 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, 15607 (end - base) - 2); 15608 memmove (affix + 2, affix, (end - affix) - 2); 15609 memcpy (affix, save, 2); 15610 15611 if (opcode 15612 && (opcode->tag == OT_cinfix3 15613 || opcode->tag == OT_cinfix3_deprecated 15614 || opcode->tag == OT_csuf_or_in3 15615 || opcode->tag == OT_cinfix3_legacy)) 15616 { 15617 /* Step CM. */ 15618 if (warn_on_deprecated && unified_syntax 15619 && (opcode->tag == OT_cinfix3 15620 || opcode->tag == OT_cinfix3_deprecated)) 15621 as_warn (_("conditional infixes are deprecated in unified syntax")); 15622 15623 inst.cond = cond->value; 15624 return opcode; 15625 } 15626 15627 return NULL; 15628} 15629 15630/* This function generates an initial IT instruction, leaving its block 15631 virtually open for the new instructions. Eventually, 15632 the mask will be updated by now_it_add_mask () each time 15633 a new instruction needs to be included in the IT block. 15634 Finally, the block is closed with close_automatic_it_block (). 15635 The block closure can be requested either from md_assemble (), 15636 a tencode (), or due to a label hook. */ 15637 15638static void 15639new_automatic_it_block (int cond) 15640{ 15641 now_it.state = AUTOMATIC_IT_BLOCK; 15642 now_it.mask = 0x18; 15643 now_it.cc = cond; 15644 now_it.block_length = 1; 15645 mapping_state (MAP_THUMB); 15646 now_it.insn = output_it_inst (cond, now_it.mask, NULL); 15647} 15648 15649/* Close an automatic IT block. 15650 See comments in new_automatic_it_block (). */ 15651 15652static void 15653close_automatic_it_block (void) 15654{ 15655 now_it.mask = 0x10; 15656 now_it.block_length = 0; 15657} 15658 15659/* Update the mask of the current automatically-generated IT 15660 instruction. See comments in new_automatic_it_block (). */ 15661 15662static void 15663now_it_add_mask (int cond) 15664{ 15665#define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) 15666#define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ 15667 | ((bitvalue) << (nbit))) 15668 const int resulting_bit = (cond & 1); 15669 15670 now_it.mask &= 0xf; 15671 now_it.mask = SET_BIT_VALUE (now_it.mask, 15672 resulting_bit, 15673 (5 - now_it.block_length)); 15674 now_it.mask = SET_BIT_VALUE (now_it.mask, 15675 1, 15676 ((5 - now_it.block_length) - 1) ); 15677 output_it_inst (now_it.cc, now_it.mask, now_it.insn); 15678 15679#undef CLEAR_BIT 15680#undef SET_BIT_VALUE 15681} 15682 15683/* The IT blocks handling machinery is accessed through the these functions: 15684 it_fsm_pre_encode () from md_assemble () 15685 set_it_insn_type () optional, from the tencode functions 15686 set_it_insn_type_last () ditto 15687 in_it_block () ditto 15688 it_fsm_post_encode () from md_assemble () 15689 force_automatic_it_block_close () from label habdling functions 15690 15691 Rationale: 15692 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), 15693 initializing the IT insn type with a generic initial value depending 15694 on the inst.condition. 15695 2) During the tencode function, two things may happen: 15696 a) The tencode function overrides the IT insn type by 15697 calling either set_it_insn_type (type) or set_it_insn_type_last (). 15698 b) The tencode function queries the IT block state by 15699 calling in_it_block () (i.e. to determine narrow/not narrow mode). 15700 15701 Both set_it_insn_type and in_it_block run the internal FSM state 15702 handling function (handle_it_state), because: a) setting the IT insn 15703 type may incur in an invalid state (exiting the function), 15704 and b) querying the state requires the FSM to be updated. 15705 Specifically we want to avoid creating an IT block for conditional 15706 branches, so it_fsm_pre_encode is actually a guess and we can't 15707 determine whether an IT block is required until the tencode () routine 15708 has decided what type of instruction this actually it. 15709 Because of this, if set_it_insn_type and in_it_block have to be used, 15710 set_it_insn_type has to be called first. 15711 15712 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that 15713 determines the insn IT type depending on the inst.cond code. 15714 When a tencode () routine encodes an instruction that can be 15715 either outside an IT block, or, in the case of being inside, has to be 15716 the last one, set_it_insn_type_last () will determine the proper 15717 IT instruction type based on the inst.cond code. Otherwise, 15718 set_it_insn_type can be called for overriding that logic or 15719 for covering other cases. 15720 15721 Calling handle_it_state () may not transition the IT block state to 15722 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be 15723 still queried. Instead, if the FSM determines that the state should 15724 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed 15725 after the tencode () function: that's what it_fsm_post_encode () does. 15726 15727 Since in_it_block () calls the state handling function to get an 15728 updated state, an error may occur (due to invalid insns combination). 15729 In that case, inst.error is set. 15730 Therefore, inst.error has to be checked after the execution of 15731 the tencode () routine. 15732 15733 3) Back in md_assemble(), it_fsm_post_encode () is called to commit 15734 any pending state change (if any) that didn't take place in 15735 handle_it_state () as explained above. */ 15736 15737static void 15738it_fsm_pre_encode (void) 15739{ 15740 if (inst.cond != COND_ALWAYS) 15741 inst.it_insn_type = INSIDE_IT_INSN; 15742 else 15743 inst.it_insn_type = OUTSIDE_IT_INSN; 15744 15745 now_it.state_handled = 0; 15746} 15747 15748/* IT state FSM handling function. */ 15749 15750static int 15751handle_it_state (void) 15752{ 15753 now_it.state_handled = 1; 15754 15755 switch (now_it.state) 15756 { 15757 case OUTSIDE_IT_BLOCK: 15758 switch (inst.it_insn_type) 15759 { 15760 case OUTSIDE_IT_INSN: 15761 break; 15762 15763 case INSIDE_IT_INSN: 15764 case INSIDE_IT_LAST_INSN: 15765 if (thumb_mode == 0) 15766 { 15767 if (unified_syntax 15768 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) 15769 as_tsktsk (_("Warning: conditional outside an IT block"\ 15770 " for Thumb.")); 15771 } 15772 else 15773 { 15774 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) 15775 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) 15776 { 15777 /* Automatically generate the IT instruction. */ 15778 new_automatic_it_block (inst.cond); 15779 if (inst.it_insn_type == INSIDE_IT_LAST_INSN) 15780 close_automatic_it_block (); 15781 } 15782 else 15783 { 15784 inst.error = BAD_OUT_IT; 15785 return FAIL; 15786 } 15787 } 15788 break; 15789 15790 case IF_INSIDE_IT_LAST_INSN: 15791 case NEUTRAL_IT_INSN: 15792 break; 15793 15794 case IT_INSN: 15795 now_it.state = MANUAL_IT_BLOCK; 15796 now_it.block_length = 0; 15797 break; 15798 } 15799 break; 15800 15801 case AUTOMATIC_IT_BLOCK: 15802 /* Three things may happen now: 15803 a) We should increment current it block size; 15804 b) We should close current it block (closing insn or 4 insns); 15805 c) We should close current it block and start a new one (due 15806 to incompatible conditions or 15807 4 insns-length block reached). */ 15808 15809 switch (inst.it_insn_type) 15810 { 15811 case OUTSIDE_IT_INSN: 15812 /* The closure of the block shall happen immediatelly, 15813 so any in_it_block () call reports the block as closed. */ 15814 force_automatic_it_block_close (); 15815 break; 15816 15817 case INSIDE_IT_INSN: 15818 case INSIDE_IT_LAST_INSN: 15819 case IF_INSIDE_IT_LAST_INSN: 15820 now_it.block_length++; 15821 15822 if (now_it.block_length > 4 15823 || !now_it_compatible (inst.cond)) 15824 { 15825 force_automatic_it_block_close (); 15826 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN) 15827 new_automatic_it_block (inst.cond); 15828 } 15829 else 15830 { 15831 now_it_add_mask (inst.cond); 15832 } 15833 15834 if (now_it.state == AUTOMATIC_IT_BLOCK 15835 && (inst.it_insn_type == INSIDE_IT_LAST_INSN 15836 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN)) 15837 close_automatic_it_block (); 15838 break; 15839 15840 case NEUTRAL_IT_INSN: 15841 now_it.block_length++; 15842 15843 if (now_it.block_length > 4) 15844 force_automatic_it_block_close (); 15845 else 15846 now_it_add_mask (now_it.cc & 1); 15847 break; 15848 15849 case IT_INSN: 15850 close_automatic_it_block (); 15851 now_it.state = MANUAL_IT_BLOCK; 15852 break; 15853 } 15854 break; 15855 15856 case MANUAL_IT_BLOCK: 15857 { 15858 /* Check conditional suffixes. */ 15859 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1; 15860 int is_last; 15861 now_it.mask <<= 1; 15862 now_it.mask &= 0x1f; 15863 is_last = (now_it.mask == 0x10); 15864 15865 switch (inst.it_insn_type) 15866 { 15867 case OUTSIDE_IT_INSN: 15868 inst.error = BAD_NOT_IT; 15869 return FAIL; 15870 15871 case INSIDE_IT_INSN: 15872 if (cond != inst.cond) 15873 { 15874 inst.error = BAD_IT_COND; 15875 return FAIL; 15876 } 15877 break; 15878 15879 case INSIDE_IT_LAST_INSN: 15880 case IF_INSIDE_IT_LAST_INSN: 15881 if (cond != inst.cond) 15882 { 15883 inst.error = BAD_IT_COND; 15884 return FAIL; 15885 } 15886 if (!is_last) 15887 { 15888 inst.error = BAD_BRANCH; 15889 return FAIL; 15890 } 15891 break; 15892 15893 case NEUTRAL_IT_INSN: 15894 /* The BKPT instruction is unconditional even in an IT block. */ 15895 break; 15896 15897 case IT_INSN: 15898 inst.error = BAD_IT_IT; 15899 return FAIL; 15900 } 15901 } 15902 break; 15903 } 15904 15905 return SUCCESS; 15906} 15907 15908static void 15909it_fsm_post_encode (void) 15910{ 15911 int is_last; 15912 15913 if (!now_it.state_handled) 15914 handle_it_state (); 15915 15916 is_last = (now_it.mask == 0x10); 15917 if (is_last) 15918 { 15919 now_it.state = OUTSIDE_IT_BLOCK; 15920 now_it.mask = 0; 15921 } 15922} 15923 15924static void 15925force_automatic_it_block_close (void) 15926{ 15927 if (now_it.state == AUTOMATIC_IT_BLOCK) 15928 { 15929 close_automatic_it_block (); 15930 now_it.state = OUTSIDE_IT_BLOCK; 15931 now_it.mask = 0; 15932 } 15933} 15934 15935static int 15936in_it_block (void) 15937{ 15938 if (!now_it.state_handled) 15939 handle_it_state (); 15940 15941 return now_it.state != OUTSIDE_IT_BLOCK; 15942} 15943 15944void 15945md_assemble (char *str) 15946{ 15947 char *p = str; 15948 const struct asm_opcode * opcode; 15949 15950 /* Align the previous label if needed. */ 15951 if (last_label_seen != NULL) 15952 { 15953 symbol_set_frag (last_label_seen, frag_now); 15954 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); 15955 S_SET_SEGMENT (last_label_seen, now_seg); 15956 } 15957 15958 memset (&inst, '\0', sizeof (inst)); 15959 inst.reloc.type = BFD_RELOC_UNUSED; 15960 15961 opcode = opcode_lookup (&p); 15962 if (!opcode) 15963 { 15964 /* It wasn't an instruction, but it might be a register alias of 15965 the form alias .req reg, or a Neon .dn/.qn directive. */ 15966 if (! create_register_alias (str, p) 15967 && ! create_neon_reg_alias (str, p)) 15968 as_bad (_("bad instruction `%s'"), str); 15969 15970 return; 15971 } 15972 15973 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) 15974 as_warn (_("s suffix on comparison instruction is deprecated")); 15975 15976 /* The value which unconditional instructions should have in place of the 15977 condition field. */ 15978 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; 15979 15980 if (thumb_mode) 15981 { 15982 arm_feature_set variant; 15983 15984 variant = cpu_variant; 15985 /* Only allow coprocessor instructions on Thumb-2 capable devices. */ 15986 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) 15987 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); 15988 /* Check that this instruction is supported for this CPU. */ 15989 if (!opcode->tvariant 15990 || (thumb_mode == 1 15991 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) 15992 { 15993 as_bad (_("selected processor does not support Thumb mode `%s'"), str); 15994 return; 15995 } 15996 if (inst.cond != COND_ALWAYS && !unified_syntax 15997 && opcode->tencode != do_t_branch) 15998 { 15999 as_bad (_("Thumb does not support conditional execution")); 16000 return; 16001 } 16002 16003 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)) 16004 { 16005 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 16006 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr) 16007 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier))) 16008 { 16009 /* Two things are addressed here. 16010 1) Implicit require narrow instructions on Thumb-1. 16011 This avoids relaxation accidentally introducing Thumb-2 16012 instructions. 16013 2) Reject wide instructions in non Thumb-2 cores. */ 16014 if (inst.size_req == 0) 16015 inst.size_req = 2; 16016 else if (inst.size_req == 4) 16017 { 16018 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str); 16019 return; 16020 } 16021 } 16022 } 16023 16024 inst.instruction = opcode->tvalue; 16025 16026 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) 16027 { 16028 /* Prepare the it_insn_type for those encodings that don't set 16029 it. */ 16030 it_fsm_pre_encode (); 16031 16032 opcode->tencode (); 16033 16034 it_fsm_post_encode (); 16035 } 16036 16037 if (!(inst.error || inst.relax)) 16038 { 16039 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); 16040 inst.size = (inst.instruction > 0xffff ? 4 : 2); 16041 if (inst.size_req && inst.size_req != inst.size) 16042 { 16043 as_bad (_("cannot honor width suffix -- `%s'"), str); 16044 return; 16045 } 16046 } 16047 16048 /* Something has gone badly wrong if we try to relax a fixed size 16049 instruction. */ 16050 gas_assert (inst.size_req == 0 || !inst.relax); 16051 16052 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 16053 *opcode->tvariant); 16054 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly 16055 set those bits when Thumb-2 32-bit instructions are seen. ie. 16056 anything other than bl/blx and v6-M instructions. 16057 This is overly pessimistic for relaxable instructions. */ 16058 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) 16059 || inst.relax) 16060 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) 16061 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))) 16062 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 16063 arm_ext_v6t2); 16064 16065 check_neon_suffixes; 16066 16067 if (!inst.error) 16068 { 16069 mapping_state (MAP_THUMB); 16070 } 16071 } 16072 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 16073 { 16074 bfd_boolean is_bx; 16075 16076 /* bx is allowed on v5 cores, and sometimes on v4 cores. */ 16077 is_bx = (opcode->aencode == do_bx); 16078 16079 /* Check that this instruction is supported for this CPU. */ 16080 if (!(is_bx && fix_v4bx) 16081 && !(opcode->avariant && 16082 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) 16083 { 16084 as_bad (_("selected processor does not support ARM mode `%s'"), str); 16085 return; 16086 } 16087 if (inst.size_req) 16088 { 16089 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); 16090 return; 16091 } 16092 16093 inst.instruction = opcode->avalue; 16094 if (opcode->tag == OT_unconditionalF) 16095 inst.instruction |= 0xF << 28; 16096 else 16097 inst.instruction |= inst.cond << 28; 16098 inst.size = INSN_SIZE; 16099 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) 16100 { 16101 it_fsm_pre_encode (); 16102 opcode->aencode (); 16103 it_fsm_post_encode (); 16104 } 16105 /* Arm mode bx is marked as both v4T and v5 because it's still required 16106 on a hypothetical non-thumb v5 core. */ 16107 if (is_bx) 16108 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); 16109 else 16110 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 16111 *opcode->avariant); 16112 16113 check_neon_suffixes; 16114 16115 if (!inst.error) 16116 { 16117 mapping_state (MAP_ARM); 16118 } 16119 } 16120 else 16121 { 16122 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " 16123 "-- `%s'"), str); 16124 return; 16125 } 16126 output_inst (str); 16127} 16128 16129static void 16130check_it_blocks_finished (void) 16131{ 16132#ifdef OBJ_ELF 16133 asection *sect; 16134 16135 for (sect = stdoutput->sections; sect != NULL; sect = sect->next) 16136 { 16137 segment_info_type *seginfo = seg_info (sect); 16138 16139 if (seginfo && seginfo->tc_segment_info_data.current_it.state 16140 == MANUAL_IT_BLOCK) 16141 { 16142 as_warn (_("section '%s' finished with an open IT block."), 16143 sect->name); 16144 } 16145 } 16146#else 16147 if (now_it.state == MANUAL_IT_BLOCK) 16148 as_warn (_("file finished with an open IT block.")); 16149#endif 16150} 16151 16152/* Various frobbings of labels and their addresses. */ 16153 16154void 16155arm_start_line_hook (void) 16156{ 16157 last_label_seen = NULL; 16158} 16159 16160void 16161arm_frob_label (symbolS * sym) 16162{ 16163 last_label_seen = sym; 16164 16165 ARM_SET_THUMB (sym, thumb_mode); 16166 16167#if defined OBJ_COFF || defined OBJ_ELF 16168 ARM_SET_INTERWORK (sym, support_interwork); 16169#endif 16170 16171 force_automatic_it_block_close (); 16172 16173 /* Note - do not allow local symbols (.Lxxx) to be labelled 16174 as Thumb functions. This is because these labels, whilst 16175 they exist inside Thumb code, are not the entry points for 16176 possible ARM->Thumb calls. Also, these labels can be used 16177 as part of a computed goto or switch statement. eg gcc 16178 can generate code that looks like this: 16179 16180 ldr r2, [pc, .Laaa] 16181 lsl r3, r3, #2 16182 ldr r2, [r3, r2] 16183 mov pc, r2 16184 16185 .Lbbb: .word .Lxxx 16186 .Lccc: .word .Lyyy 16187 ..etc... 16188 .Laaa: .word Lbbb 16189 16190 The first instruction loads the address of the jump table. 16191 The second instruction converts a table index into a byte offset. 16192 The third instruction gets the jump address out of the table. 16193 The fourth instruction performs the jump. 16194 16195 If the address stored at .Laaa is that of a symbol which has the 16196 Thumb_Func bit set, then the linker will arrange for this address 16197 to have the bottom bit set, which in turn would mean that the 16198 address computation performed by the third instruction would end 16199 up with the bottom bit set. Since the ARM is capable of unaligned 16200 word loads, the instruction would then load the incorrect address 16201 out of the jump table, and chaos would ensue. */ 16202 if (label_is_thumb_function_name 16203 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') 16204 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) 16205 { 16206 /* When the address of a Thumb function is taken the bottom 16207 bit of that address should be set. This will allow 16208 interworking between Arm and Thumb functions to work 16209 correctly. */ 16210 16211 THUMB_SET_FUNC (sym, 1); 16212 16213 label_is_thumb_function_name = FALSE; 16214 } 16215 16216 dwarf2_emit_label (sym); 16217} 16218 16219bfd_boolean 16220arm_data_in_code (void) 16221{ 16222 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) 16223 { 16224 *input_line_pointer = '/'; 16225 input_line_pointer += 5; 16226 *input_line_pointer = 0; 16227 return TRUE; 16228 } 16229 16230 return FALSE; 16231} 16232 16233char * 16234arm_canonicalize_symbol_name (char * name) 16235{ 16236 int len; 16237 16238 if (thumb_mode && (len = strlen (name)) > 5 16239 && streq (name + len - 5, "/data")) 16240 *(name + len - 5) = 0; 16241 16242 return name; 16243} 16244 16245/* Table of all register names defined by default. The user can 16246 define additional names with .req. Note that all register names 16247 should appear in both upper and lowercase variants. Some registers 16248 also have mixed-case names. */ 16249 16250#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } 16251#define REGNUM(p,n,t) REGDEF(p##n, n, t) 16252#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) 16253#define REGSET(p,t) \ 16254 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ 16255 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ 16256 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ 16257 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) 16258#define REGSETH(p,t) \ 16259 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ 16260 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ 16261 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ 16262 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) 16263#define REGSET2(p,t) \ 16264 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ 16265 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ 16266 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ 16267 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) 16268#define SPLRBANK(base,bank,t) \ 16269 REGDEF(lr_##bank, 768|((base+0)<<16), t), \ 16270 REGDEF(sp_##bank, 768|((base+1)<<16), t), \ 16271 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \ 16272 REGDEF(LR_##bank, 768|((base+0)<<16), t), \ 16273 REGDEF(SP_##bank, 768|((base+1)<<16), t), \ 16274 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t) 16275 16276static const struct reg_entry reg_names[] = 16277{ 16278 /* ARM integer registers. */ 16279 REGSET(r, RN), REGSET(R, RN), 16280 16281 /* ATPCS synonyms. */ 16282 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), 16283 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), 16284 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), 16285 16286 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), 16287 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), 16288 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), 16289 16290 /* Well-known aliases. */ 16291 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), 16292 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), 16293 16294 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), 16295 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), 16296 16297 /* Coprocessor numbers. */ 16298 REGSET(p, CP), REGSET(P, CP), 16299 16300 /* Coprocessor register numbers. The "cr" variants are for backward 16301 compatibility. */ 16302 REGSET(c, CN), REGSET(C, CN), 16303 REGSET(cr, CN), REGSET(CR, CN), 16304 16305 /* ARM banked registers. */ 16306 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB), 16307 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB), 16308 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB), 16309 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB), 16310 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB), 16311 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB), 16312 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB), 16313 16314 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB), 16315 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB), 16316 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB), 16317 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB), 16318 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB), 16319 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB), 16320 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB), 16321 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB), 16322 16323 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB), 16324 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB), 16325 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB), 16326 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB), 16327 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB), 16328 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB), 16329 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB), 16330 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB), 16331 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB), 16332 16333 /* FPA registers. */ 16334 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), 16335 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), 16336 16337 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), 16338 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), 16339 16340 /* VFP SP registers. */ 16341 REGSET(s,VFS), REGSET(S,VFS), 16342 REGSETH(s,VFS), REGSETH(S,VFS), 16343 16344 /* VFP DP Registers. */ 16345 REGSET(d,VFD), REGSET(D,VFD), 16346 /* Extra Neon DP registers. */ 16347 REGSETH(d,VFD), REGSETH(D,VFD), 16348 16349 /* Neon QP registers. */ 16350 REGSET2(q,NQ), REGSET2(Q,NQ), 16351 16352 /* VFP control registers. */ 16353 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), 16354 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), 16355 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), 16356 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), 16357 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), 16358 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), 16359 16360 /* Maverick DSP coprocessor registers. */ 16361 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), 16362 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), 16363 16364 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), 16365 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), 16366 REGDEF(dspsc,0,DSPSC), 16367 16368 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), 16369 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), 16370 REGDEF(DSPSC,0,DSPSC), 16371 16372 /* iWMMXt data registers - p0, c0-15. */ 16373 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), 16374 16375 /* iWMMXt control registers - p1, c0-3. */ 16376 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), 16377 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), 16378 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), 16379 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), 16380 16381 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ 16382 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), 16383 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), 16384 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), 16385 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), 16386 16387 /* XScale accumulator registers. */ 16388 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), 16389}; 16390#undef REGDEF 16391#undef REGNUM 16392#undef REGSET 16393 16394/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled 16395 within psr_required_here. */ 16396static const struct asm_psr psrs[] = 16397{ 16398 /* Backward compatibility notation. Note that "all" is no longer 16399 truly all possible PSR bits. */ 16400 {"all", PSR_c | PSR_f}, 16401 {"flg", PSR_f}, 16402 {"ctl", PSR_c}, 16403 16404 /* Individual flags. */ 16405 {"f", PSR_f}, 16406 {"c", PSR_c}, 16407 {"x", PSR_x}, 16408 {"s", PSR_s}, 16409 {"g", PSR_s}, 16410 16411 /* Combinations of flags. */ 16412 {"fs", PSR_f | PSR_s}, 16413 {"fx", PSR_f | PSR_x}, 16414 {"fc", PSR_f | PSR_c}, 16415 {"sf", PSR_s | PSR_f}, 16416 {"sx", PSR_s | PSR_x}, 16417 {"sc", PSR_s | PSR_c}, 16418 {"xf", PSR_x | PSR_f}, 16419 {"xs", PSR_x | PSR_s}, 16420 {"xc", PSR_x | PSR_c}, 16421 {"cf", PSR_c | PSR_f}, 16422 {"cs", PSR_c | PSR_s}, 16423 {"cx", PSR_c | PSR_x}, 16424 {"fsx", PSR_f | PSR_s | PSR_x}, 16425 {"fsc", PSR_f | PSR_s | PSR_c}, 16426 {"fxs", PSR_f | PSR_x | PSR_s}, 16427 {"fxc", PSR_f | PSR_x | PSR_c}, 16428 {"fcs", PSR_f | PSR_c | PSR_s}, 16429 {"fcx", PSR_f | PSR_c | PSR_x}, 16430 {"sfx", PSR_s | PSR_f | PSR_x}, 16431 {"sfc", PSR_s | PSR_f | PSR_c}, 16432 {"sxf", PSR_s | PSR_x | PSR_f}, 16433 {"sxc", PSR_s | PSR_x | PSR_c}, 16434 {"scf", PSR_s | PSR_c | PSR_f}, 16435 {"scx", PSR_s | PSR_c | PSR_x}, 16436 {"xfs", PSR_x | PSR_f | PSR_s}, 16437 {"xfc", PSR_x | PSR_f | PSR_c}, 16438 {"xsf", PSR_x | PSR_s | PSR_f}, 16439 {"xsc", PSR_x | PSR_s | PSR_c}, 16440 {"xcf", PSR_x | PSR_c | PSR_f}, 16441 {"xcs", PSR_x | PSR_c | PSR_s}, 16442 {"cfs", PSR_c | PSR_f | PSR_s}, 16443 {"cfx", PSR_c | PSR_f | PSR_x}, 16444 {"csf", PSR_c | PSR_s | PSR_f}, 16445 {"csx", PSR_c | PSR_s | PSR_x}, 16446 {"cxf", PSR_c | PSR_x | PSR_f}, 16447 {"cxs", PSR_c | PSR_x | PSR_s}, 16448 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, 16449 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, 16450 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, 16451 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, 16452 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, 16453 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, 16454 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, 16455 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, 16456 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, 16457 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, 16458 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, 16459 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, 16460 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, 16461 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, 16462 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, 16463 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, 16464 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, 16465 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, 16466 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, 16467 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, 16468 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, 16469 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, 16470 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, 16471 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, 16472 16473 /* APSR flags */ 16474 {"nzcvq", PSR_f}, 16475 {"nzcvqg", PSR_s | PSR_f} 16476}; 16477 16478/* Table of V7M psr names. */ 16479static const struct asm_psr v7m_psrs[] = 16480{ 16481 {"apsr", 0 }, {"APSR", 0 }, 16482 {"iapsr", 1 }, {"IAPSR", 1 }, 16483 {"eapsr", 2 }, {"EAPSR", 2 }, 16484 {"psr", 3 }, {"PSR", 3 }, 16485 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, 16486 {"ipsr", 5 }, {"IPSR", 5 }, 16487 {"epsr", 6 }, {"EPSR", 6 }, 16488 {"iepsr", 7 }, {"IEPSR", 7 }, 16489 {"msp", 8 }, {"MSP", 8 }, 16490 {"psp", 9 }, {"PSP", 9 }, 16491 {"primask", 16}, {"PRIMASK", 16}, 16492 {"basepri", 17}, {"BASEPRI", 17}, 16493 {"basepri_max", 18}, {"BASEPRI_MAX", 18}, 16494 {"faultmask", 19}, {"FAULTMASK", 19}, 16495 {"control", 20}, {"CONTROL", 20} 16496}; 16497 16498/* Table of all shift-in-operand names. */ 16499static const struct asm_shift_name shift_names [] = 16500{ 16501 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, 16502 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, 16503 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, 16504 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, 16505 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, 16506 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } 16507}; 16508 16509/* Table of all explicit relocation names. */ 16510#ifdef OBJ_ELF 16511static struct reloc_entry reloc_names[] = 16512{ 16513 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, 16514 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, 16515 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, 16516 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, 16517 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, 16518 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, 16519 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, 16520 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, 16521 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, 16522 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, 16523 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, 16524 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL} 16525}; 16526#endif 16527 16528/* Table of all conditional affixes. 0xF is not defined as a condition code. */ 16529static const struct asm_cond conds[] = 16530{ 16531 {"eq", 0x0}, 16532 {"ne", 0x1}, 16533 {"cs", 0x2}, {"hs", 0x2}, 16534 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, 16535 {"mi", 0x4}, 16536 {"pl", 0x5}, 16537 {"vs", 0x6}, 16538 {"vc", 0x7}, 16539 {"hi", 0x8}, 16540 {"ls", 0x9}, 16541 {"ge", 0xa}, 16542 {"lt", 0xb}, 16543 {"gt", 0xc}, 16544 {"le", 0xd}, 16545 {"al", 0xe} 16546}; 16547 16548static struct asm_barrier_opt barrier_opt_names[] = 16549{ 16550 { "sy", 0xf }, { "SY", 0xf }, 16551 { "un", 0x7 }, { "UN", 0x7 }, 16552 { "st", 0xe }, { "ST", 0xe }, 16553 { "unst", 0x6 }, { "UNST", 0x6 }, 16554 { "ish", 0xb }, { "ISH", 0xb }, 16555 { "sh", 0xb }, { "SH", 0xb }, 16556 { "ishst", 0xa }, { "ISHST", 0xa }, 16557 { "shst", 0xa }, { "SHST", 0xa }, 16558 { "nsh", 0x7 }, { "NSH", 0x7 }, 16559 { "nshst", 0x6 }, { "NSHST", 0x6 }, 16560 { "osh", 0x3 }, { "OSH", 0x3 }, 16561 { "oshst", 0x2 }, { "OSHST", 0x2 } 16562}; 16563 16564/* Table of ARM-format instructions. */ 16565 16566/* Macros for gluing together operand strings. N.B. In all cases 16567 other than OPS0, the trailing OP_stop comes from default 16568 zero-initialization of the unspecified elements of the array. */ 16569#define OPS0() { OP_stop, } 16570#define OPS1(a) { OP_##a, } 16571#define OPS2(a,b) { OP_##a,OP_##b, } 16572#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } 16573#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } 16574#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } 16575#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } 16576 16577/* These macros are similar to the OPSn, but do not prepend the OP_ prefix. 16578 This is useful when mixing operands for ARM and THUMB, i.e. using the 16579 MIX_ARM_THUMB_OPERANDS macro. 16580 In order to use these macros, prefix the number of operands with _ 16581 e.g. _3. */ 16582#define OPS_1(a) { a, } 16583#define OPS_2(a,b) { a,b, } 16584#define OPS_3(a,b,c) { a,b,c, } 16585#define OPS_4(a,b,c,d) { a,b,c,d, } 16586#define OPS_5(a,b,c,d,e) { a,b,c,d,e, } 16587#define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } 16588 16589/* These macros abstract out the exact format of the mnemonic table and 16590 save some repeated characters. */ 16591 16592/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ 16593#define TxCE(mnem, op, top, nops, ops, ae, te) \ 16594 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ 16595 THUMB_VARIANT, do_##ae, do_##te } 16596 16597/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for 16598 a T_MNEM_xyz enumerator. */ 16599#define TCE(mnem, aop, top, nops, ops, ae, te) \ 16600 TxCE (mnem, aop, 0x##top, nops, ops, ae, te) 16601#define tCE(mnem, aop, top, nops, ops, ae, te) \ 16602 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) 16603 16604/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional 16605 infix after the third character. */ 16606#define TxC3(mnem, op, top, nops, ops, ae, te) \ 16607 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ 16608 THUMB_VARIANT, do_##ae, do_##te } 16609#define TxC3w(mnem, op, top, nops, ops, ae, te) \ 16610 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ 16611 THUMB_VARIANT, do_##ae, do_##te } 16612#define TC3(mnem, aop, top, nops, ops, ae, te) \ 16613 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) 16614#define TC3w(mnem, aop, top, nops, ops, ae, te) \ 16615 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) 16616#define tC3(mnem, aop, top, nops, ops, ae, te) \ 16617 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) 16618#define tC3w(mnem, aop, top, nops, ops, ae, te) \ 16619 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) 16620 16621/* Mnemonic with a conditional infix in an unusual place. Each and every variant has to 16622 appear in the condition table. */ 16623#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ 16624 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ 16625 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } 16626 16627#define TxCM(m1, m2, op, top, nops, ops, ae, te) \ 16628 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \ 16629 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \ 16630 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \ 16631 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \ 16632 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \ 16633 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \ 16634 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \ 16635 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \ 16636 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \ 16637 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \ 16638 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \ 16639 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \ 16640 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \ 16641 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \ 16642 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \ 16643 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \ 16644 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \ 16645 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \ 16646 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te) 16647 16648#define TCM(m1,m2, aop, top, nops, ops, ae, te) \ 16649 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te) 16650#define tCM(m1,m2, aop, top, nops, ops, ae, te) \ 16651 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te) 16652 16653/* Mnemonic that cannot be conditionalized. The ARM condition-code 16654 field is still 0xE. Many of the Thumb variants can be executed 16655 conditionally, so this is checked separately. */ 16656#define TUE(mnem, op, top, nops, ops, ae, te) \ 16657 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ 16658 THUMB_VARIANT, do_##ae, do_##te } 16659 16660/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM 16661 condition code field. */ 16662#define TUF(mnem, op, top, nops, ops, ae, te) \ 16663 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ 16664 THUMB_VARIANT, do_##ae, do_##te } 16665 16666/* ARM-only variants of all the above. */ 16667#define CE(mnem, op, nops, ops, ae) \ 16668 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 16669 16670#define C3(mnem, op, nops, ops, ae) \ 16671 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 16672 16673/* Legacy mnemonics that always have conditional infix after the third 16674 character. */ 16675#define CL(mnem, op, nops, ops, ae) \ 16676 { mnem, OPS##nops ops, OT_cinfix3_legacy, \ 16677 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 16678 16679/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ 16680#define cCE(mnem, op, nops, ops, ae) \ 16681 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 16682 16683/* Legacy coprocessor instructions where conditional infix and conditional 16684 suffix are ambiguous. For consistency this includes all FPA instructions, 16685 not just the potentially ambiguous ones. */ 16686#define cCL(mnem, op, nops, ops, ae) \ 16687 { mnem, OPS##nops ops, OT_cinfix3_legacy, \ 16688 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 16689 16690/* Coprocessor, takes either a suffix or a position-3 infix 16691 (for an FPA corner case). */ 16692#define C3E(mnem, op, nops, ops, ae) \ 16693 { mnem, OPS##nops ops, OT_csuf_or_in3, \ 16694 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 16695 16696#define xCM_(m1, m2, m3, op, nops, ops, ae) \ 16697 { m1 #m2 m3, OPS##nops ops, \ 16698 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ 16699 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 16700 16701#define CM(m1, m2, op, nops, ops, ae) \ 16702 xCM_ (m1, , m2, op, nops, ops, ae), \ 16703 xCM_ (m1, eq, m2, op, nops, ops, ae), \ 16704 xCM_ (m1, ne, m2, op, nops, ops, ae), \ 16705 xCM_ (m1, cs, m2, op, nops, ops, ae), \ 16706 xCM_ (m1, hs, m2, op, nops, ops, ae), \ 16707 xCM_ (m1, cc, m2, op, nops, ops, ae), \ 16708 xCM_ (m1, ul, m2, op, nops, ops, ae), \ 16709 xCM_ (m1, lo, m2, op, nops, ops, ae), \ 16710 xCM_ (m1, mi, m2, op, nops, ops, ae), \ 16711 xCM_ (m1, pl, m2, op, nops, ops, ae), \ 16712 xCM_ (m1, vs, m2, op, nops, ops, ae), \ 16713 xCM_ (m1, vc, m2, op, nops, ops, ae), \ 16714 xCM_ (m1, hi, m2, op, nops, ops, ae), \ 16715 xCM_ (m1, ls, m2, op, nops, ops, ae), \ 16716 xCM_ (m1, ge, m2, op, nops, ops, ae), \ 16717 xCM_ (m1, lt, m2, op, nops, ops, ae), \ 16718 xCM_ (m1, gt, m2, op, nops, ops, ae), \ 16719 xCM_ (m1, le, m2, op, nops, ops, ae), \ 16720 xCM_ (m1, al, m2, op, nops, ops, ae) 16721 16722#define UE(mnem, op, nops, ops, ae) \ 16723 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } 16724 16725#define UF(mnem, op, nops, ops, ae) \ 16726 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } 16727 16728/* Neon data-processing. ARM versions are unconditional with cond=0xf. 16729 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we 16730 use the same encoding function for each. */ 16731#define NUF(mnem, op, nops, ops, enc) \ 16732 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ 16733 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 16734 16735/* Neon data processing, version which indirects through neon_enc_tab for 16736 the various overloaded versions of opcodes. */ 16737#define nUF(mnem, op, nops, ops, enc) \ 16738 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ 16739 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 16740 16741/* Neon insn with conditional suffix for the ARM version, non-overloaded 16742 version. */ 16743#define NCE_tag(mnem, op, nops, ops, enc, tag) \ 16744 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ 16745 THUMB_VARIANT, do_##enc, do_##enc } 16746 16747#define NCE(mnem, op, nops, ops, enc) \ 16748 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix) 16749 16750#define NCEF(mnem, op, nops, ops, enc) \ 16751 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) 16752 16753/* Neon insn with conditional suffix for the ARM version, overloaded types. */ 16754#define nCE_tag(mnem, op, nops, ops, enc, tag) \ 16755 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ 16756 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 16757 16758#define nCE(mnem, op, nops, ops, enc) \ 16759 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix) 16760 16761#define nCEF(mnem, op, nops, ops, enc) \ 16762 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) 16763 16764#define do_0 0 16765 16766static const struct asm_opcode insns[] = 16767{ 16768#define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ 16769#define THUMB_VARIANT &arm_ext_v4t 16770 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), 16771 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), 16772 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), 16773 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), 16774 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), 16775 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), 16776 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), 16777 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), 16778 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), 16779 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), 16780 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), 16781 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), 16782 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), 16783 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), 16784 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), 16785 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), 16786 16787 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism 16788 for setting PSR flag bits. They are obsolete in V6 and do not 16789 have Thumb equivalents. */ 16790 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), 16791 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), 16792 CL("tstp", 110f000, 2, (RR, SH), cmp), 16793 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), 16794 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), 16795 CL("cmpp", 150f000, 2, (RR, SH), cmp), 16796 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), 16797 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), 16798 CL("cmnp", 170f000, 2, (RR, SH), cmp), 16799 16800 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), 16801 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp), 16802 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), 16803 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), 16804 16805 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), 16806 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), 16807 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, 16808 OP_RRnpc), 16809 OP_ADDRGLDR),ldst, t_ldst), 16810 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), 16811 16812 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 16813 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 16814 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 16815 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 16816 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 16817 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 16818 16819 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), 16820 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), 16821 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), 16822 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), 16823 16824 /* Pseudo ops. */ 16825 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), 16826 C3(adrl, 28f0000, 2, (RR, EXP), adrl), 16827 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), 16828 16829 /* Thumb-compatibility pseudo ops. */ 16830 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), 16831 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), 16832 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), 16833 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), 16834 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), 16835 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), 16836 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), 16837 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), 16838 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), 16839 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), 16840 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), 16841 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), 16842 16843 /* These may simplify to neg. */ 16844 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), 16845 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), 16846 16847#undef THUMB_VARIANT 16848#define THUMB_VARIANT & arm_ext_v6 16849 16850 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), 16851 16852 /* V1 instructions with no Thumb analogue prior to V6T2. */ 16853#undef THUMB_VARIANT 16854#define THUMB_VARIANT & arm_ext_v6t2 16855 16856 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), 16857 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), 16858 CL("teqp", 130f000, 2, (RR, SH), cmp), 16859 16860 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), 16861 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), 16862 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), 16863 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), 16864 16865 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 16866 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 16867 16868 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 16869 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 16870 16871 /* V1 instructions with no Thumb analogue at all. */ 16872 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), 16873 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), 16874 16875 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), 16876 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), 16877 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), 16878 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), 16879 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), 16880 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), 16881 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), 16882 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), 16883 16884#undef ARM_VARIANT 16885#define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ 16886#undef THUMB_VARIANT 16887#define THUMB_VARIANT & arm_ext_v4t 16888 16889 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), 16890 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), 16891 16892#undef THUMB_VARIANT 16893#define THUMB_VARIANT & arm_ext_v6t2 16894 16895 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), 16896 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), 16897 16898 /* Generic coprocessor instructions. */ 16899 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), 16900 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 16901 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 16902 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 16903 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 16904 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 16905 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), 16906 16907#undef ARM_VARIANT 16908#define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ 16909 16910 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), 16911 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), 16912 16913#undef ARM_VARIANT 16914#define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ 16915#undef THUMB_VARIANT 16916#define THUMB_VARIANT & arm_ext_msr 16917 16918 TCE("mrs", 1000000, f3e08000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs), 16919 TCE("msr", 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr), 16920 16921#undef ARM_VARIANT 16922#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ 16923#undef THUMB_VARIANT 16924#define THUMB_VARIANT & arm_ext_v6t2 16925 16926 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 16927 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 16928 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 16929 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 16930 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 16931 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 16932 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 16933 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 16934 16935#undef ARM_VARIANT 16936#define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ 16937#undef THUMB_VARIANT 16938#define THUMB_VARIANT & arm_ext_v4t 16939 16940 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), 16941 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), 16942 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), 16943 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), 16944 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), 16945 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), 16946 16947#undef ARM_VARIANT 16948#define ARM_VARIANT & arm_ext_v4t_5 16949 16950 /* ARM Architecture 4T. */ 16951 /* Note: bx (and blx) are required on V5, even if the processor does 16952 not support Thumb. */ 16953 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), 16954 16955#undef ARM_VARIANT 16956#define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ 16957#undef THUMB_VARIANT 16958#define THUMB_VARIANT & arm_ext_v5t 16959 16960 /* Note: blx has 2 variants; the .value coded here is for 16961 BLX(2). Only this variant has conditional execution. */ 16962 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), 16963 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), 16964 16965#undef THUMB_VARIANT 16966#define THUMB_VARIANT & arm_ext_v6t2 16967 16968 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), 16969 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 16970 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 16971 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 16972 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 16973 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), 16974 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 16975 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 16976 16977#undef ARM_VARIANT 16978#define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ 16979#undef THUMB_VARIANT 16980#define THUMB_VARIANT &arm_ext_v5exp 16981 16982 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 16983 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 16984 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 16985 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 16986 16987 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 16988 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 16989 16990 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 16991 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 16992 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 16993 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 16994 16995 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 16996 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 16997 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 16998 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 16999 17000 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 17001 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 17002 17003 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), 17004 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), 17005 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), 17006 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), 17007 17008#undef ARM_VARIANT 17009#define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ 17010#undef THUMB_VARIANT 17011#define THUMB_VARIANT &arm_ext_v6t2 17012 17013 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), 17014 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), 17015 ldrd, t_ldstd), 17016 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, 17017 ADDRGLDRS), ldrd, t_ldstd), 17018 17019 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 17020 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 17021 17022#undef ARM_VARIANT 17023#define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ 17024 17025 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), 17026 17027#undef ARM_VARIANT 17028#define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ 17029#undef THUMB_VARIANT 17030#define THUMB_VARIANT & arm_ext_v6 17031 17032 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), 17033 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), 17034 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), 17035 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), 17036 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), 17037 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 17038 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 17039 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 17040 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 17041 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), 17042 17043#undef THUMB_VARIANT 17044#define THUMB_VARIANT & arm_ext_v6t2 17045 17046 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), 17047 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), 17048 strex, t_strex), 17049 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 17050 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 17051 17052 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), 17053 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), 17054 17055/* ARM V6 not included in V7M. */ 17056#undef THUMB_VARIANT 17057#define THUMB_VARIANT & arm_ext_v6_notm 17058 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), 17059 UF(rfeib, 9900a00, 1, (RRw), rfe), 17060 UF(rfeda, 8100a00, 1, (RRw), rfe), 17061 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), 17062 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), 17063 UF(rfefa, 9900a00, 1, (RRw), rfe), 17064 UF(rfeea, 8100a00, 1, (RRw), rfe), 17065 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe), 17066 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), 17067 UF(srsib, 9c00500, 2, (oRRw, I31w), srs), 17068 UF(srsda, 8400500, 2, (oRRw, I31w), srs), 17069 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), 17070 17071/* ARM V6 not included in V7M (eg. integer SIMD). */ 17072#undef THUMB_VARIANT 17073#define THUMB_VARIANT & arm_ext_v6_dsp 17074 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), 17075 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), 17076 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), 17077 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17078 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17079 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17080 /* Old name for QASX. */ 17081 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17082 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17083 /* Old name for QSAX. */ 17084 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17085 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17086 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17087 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17088 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17089 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17090 /* Old name for SASX. */ 17091 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17092 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17093 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17094 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17095 /* Old name for SHASX. */ 17096 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17097 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17098 /* Old name for SHSAX. */ 17099 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17100 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17101 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17102 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17103 /* Old name for SSAX. */ 17104 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17105 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17106 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17107 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17108 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17109 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17110 /* Old name for UASX. */ 17111 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17112 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17113 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17114 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17115 /* Old name for UHASX. */ 17116 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17117 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17118 /* Old name for UHSAX. */ 17119 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17120 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17121 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17122 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17123 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17124 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17125 /* Old name for UQASX. */ 17126 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17127 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17128 /* Old name for UQSAX. */ 17129 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17130 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17131 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17132 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17133 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17134 /* Old name for USAX. */ 17135 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17136 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17137 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 17138 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 17139 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 17140 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 17141 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 17142 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 17143 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 17144 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 17145 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 17146 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 17147 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 17148 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 17149 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 17150 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 17151 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 17152 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 17153 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 17154 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 17155 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 17156 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 17157 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 17158 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 17159 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 17160 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 17161 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 17162 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 17163 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 17164 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), 17165 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), 17166 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 17167 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 17168 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), 17169 17170#undef ARM_VARIANT 17171#define ARM_VARIANT & arm_ext_v6k 17172#undef THUMB_VARIANT 17173#define THUMB_VARIANT & arm_ext_v6k 17174 17175 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), 17176 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), 17177 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), 17178 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), 17179 17180#undef THUMB_VARIANT 17181#define THUMB_VARIANT & arm_ext_v6_notm 17182 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), 17183 ldrexd, t_ldrexd), 17184 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, 17185 RRnpcb), strexd, t_strexd), 17186 17187#undef THUMB_VARIANT 17188#define THUMB_VARIANT & arm_ext_v6t2 17189 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), 17190 rd_rn, rd_rn), 17191 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), 17192 rd_rn, rd_rn), 17193 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), 17194 strex, rm_rd_rn), 17195 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), 17196 strex, rm_rd_rn), 17197 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), 17198 17199#undef ARM_VARIANT 17200#define ARM_VARIANT & arm_ext_sec 17201#undef THUMB_VARIANT 17202#define THUMB_VARIANT & arm_ext_sec 17203 17204 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), 17205 17206#undef ARM_VARIANT 17207#define ARM_VARIANT & arm_ext_virt 17208#undef THUMB_VARIANT 17209#define THUMB_VARIANT & arm_ext_virt 17210 17211 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc), 17212 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs), 17213 17214#undef ARM_VARIANT 17215#define ARM_VARIANT & arm_ext_v6t2 17216#undef THUMB_VARIANT 17217#define THUMB_VARIANT & arm_ext_v6t2 17218 17219 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), 17220 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), 17221 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), 17222 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), 17223 17224 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), 17225 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), 17226 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), 17227 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), 17228 17229 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), 17230 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), 17231 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), 17232 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), 17233 17234 /* Thumb-only instructions. */ 17235#undef ARM_VARIANT 17236#define ARM_VARIANT NULL 17237 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), 17238 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), 17239 17240 /* ARM does not really have an IT instruction, so always allow it. 17241 The opcode is copied from Thumb in order to allow warnings in 17242 -mimplicit-it=[never | arm] modes. */ 17243#undef ARM_VARIANT 17244#define ARM_VARIANT & arm_ext_v1 17245 17246 TUE("it", bf08, bf08, 1, (COND), it, t_it), 17247 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), 17248 TUE("ite", bf04, bf04, 1, (COND), it, t_it), 17249 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), 17250 TUE("itet", bf06, bf06, 1, (COND), it, t_it), 17251 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), 17252 TUE("itee", bf02, bf02, 1, (COND), it, t_it), 17253 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), 17254 TUE("itett", bf07, bf07, 1, (COND), it, t_it), 17255 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), 17256 TUE("iteet", bf03, bf03, 1, (COND), it, t_it), 17257 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), 17258 TUE("itete", bf05, bf05, 1, (COND), it, t_it), 17259 TUE("ittee", bf09, bf09, 1, (COND), it, t_it), 17260 TUE("iteee", bf01, bf01, 1, (COND), it, t_it), 17261 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ 17262 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), 17263 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), 17264 17265 /* Thumb2 only instructions. */ 17266#undef ARM_VARIANT 17267#define ARM_VARIANT NULL 17268 17269 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), 17270 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), 17271 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), 17272 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), 17273 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), 17274 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), 17275 17276 /* Hardware division instructions. */ 17277#undef ARM_VARIANT 17278#define ARM_VARIANT & arm_ext_adiv 17279#undef THUMB_VARIANT 17280#define THUMB_VARIANT & arm_ext_div 17281 17282 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div), 17283 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div), 17284 17285 /* ARM V6M/V7 instructions. */ 17286#undef ARM_VARIANT 17287#define ARM_VARIANT & arm_ext_barrier 17288#undef THUMB_VARIANT 17289#define THUMB_VARIANT & arm_ext_barrier 17290 17291 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier), 17292 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier), 17293 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier), 17294 17295 /* ARM V7 instructions. */ 17296#undef ARM_VARIANT 17297#define ARM_VARIANT & arm_ext_v7 17298#undef THUMB_VARIANT 17299#define THUMB_VARIANT & arm_ext_v7 17300 17301 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), 17302 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), 17303 17304#undef ARM_VARIANT 17305#define ARM_VARIANT & arm_ext_mp 17306#undef THUMB_VARIANT 17307#define THUMB_VARIANT & arm_ext_mp 17308 17309 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld), 17310 17311#undef ARM_VARIANT 17312#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ 17313 17314 cCE("wfs", e200110, 1, (RR), rd), 17315 cCE("rfs", e300110, 1, (RR), rd), 17316 cCE("wfc", e400110, 1, (RR), rd), 17317 cCE("rfc", e500110, 1, (RR), rd), 17318 17319 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), 17320 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), 17321 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), 17322 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), 17323 17324 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), 17325 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), 17326 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), 17327 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), 17328 17329 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), 17330 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), 17331 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), 17332 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), 17333 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), 17334 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), 17335 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), 17336 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), 17337 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), 17338 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), 17339 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), 17340 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), 17341 17342 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), 17343 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), 17344 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), 17345 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), 17346 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), 17347 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), 17348 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), 17349 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), 17350 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), 17351 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), 17352 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), 17353 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), 17354 17355 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), 17356 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), 17357 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), 17358 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), 17359 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), 17360 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), 17361 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), 17362 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), 17363 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), 17364 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), 17365 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), 17366 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), 17367 17368 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), 17369 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), 17370 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), 17371 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), 17372 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), 17373 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), 17374 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), 17375 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), 17376 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), 17377 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), 17378 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), 17379 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), 17380 17381 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), 17382 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), 17383 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), 17384 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), 17385 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), 17386 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), 17387 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), 17388 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), 17389 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), 17390 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), 17391 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), 17392 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), 17393 17394 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), 17395 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), 17396 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), 17397 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), 17398 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), 17399 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), 17400 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), 17401 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), 17402 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), 17403 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), 17404 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), 17405 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), 17406 17407 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), 17408 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), 17409 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), 17410 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), 17411 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), 17412 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), 17413 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), 17414 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), 17415 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), 17416 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), 17417 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), 17418 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), 17419 17420 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), 17421 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), 17422 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), 17423 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), 17424 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), 17425 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), 17426 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), 17427 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), 17428 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), 17429 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), 17430 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), 17431 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), 17432 17433 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), 17434 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), 17435 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), 17436 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), 17437 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), 17438 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), 17439 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), 17440 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), 17441 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), 17442 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), 17443 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), 17444 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), 17445 17446 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), 17447 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), 17448 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), 17449 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), 17450 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), 17451 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), 17452 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), 17453 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), 17454 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), 17455 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), 17456 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), 17457 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), 17458 17459 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), 17460 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), 17461 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), 17462 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), 17463 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), 17464 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), 17465 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), 17466 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), 17467 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), 17468 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), 17469 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), 17470 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), 17471 17472 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), 17473 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), 17474 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), 17475 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), 17476 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), 17477 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), 17478 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), 17479 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), 17480 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), 17481 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), 17482 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), 17483 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), 17484 17485 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), 17486 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), 17487 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), 17488 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), 17489 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), 17490 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), 17491 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), 17492 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), 17493 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), 17494 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), 17495 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), 17496 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), 17497 17498 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), 17499 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), 17500 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), 17501 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), 17502 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), 17503 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), 17504 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), 17505 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), 17506 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), 17507 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), 17508 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), 17509 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), 17510 17511 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), 17512 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), 17513 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), 17514 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), 17515 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), 17516 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), 17517 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), 17518 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), 17519 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), 17520 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), 17521 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), 17522 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), 17523 17524 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), 17525 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), 17526 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), 17527 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), 17528 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), 17529 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), 17530 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), 17531 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), 17532 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), 17533 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), 17534 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), 17535 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), 17536 17537 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), 17538 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), 17539 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), 17540 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), 17541 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), 17542 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 17543 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 17544 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 17545 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), 17546 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), 17547 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), 17548 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), 17549 17550 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), 17551 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), 17552 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), 17553 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), 17554 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), 17555 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 17556 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 17557 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 17558 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), 17559 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), 17560 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), 17561 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), 17562 17563 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), 17564 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), 17565 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), 17566 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), 17567 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), 17568 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 17569 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 17570 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 17571 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), 17572 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), 17573 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), 17574 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), 17575 17576 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), 17577 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), 17578 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), 17579 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), 17580 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), 17581 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 17582 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 17583 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 17584 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), 17585 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), 17586 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), 17587 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), 17588 17589 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), 17590 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), 17591 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), 17592 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), 17593 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), 17594 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 17595 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 17596 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 17597 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), 17598 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), 17599 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), 17600 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), 17601 17602 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), 17603 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), 17604 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), 17605 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), 17606 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), 17607 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 17608 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 17609 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 17610 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), 17611 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), 17612 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), 17613 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), 17614 17615 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), 17616 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), 17617 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), 17618 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), 17619 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), 17620 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 17621 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 17622 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 17623 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), 17624 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), 17625 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), 17626 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), 17627 17628 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), 17629 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), 17630 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), 17631 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), 17632 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), 17633 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 17634 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 17635 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 17636 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), 17637 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), 17638 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), 17639 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), 17640 17641 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), 17642 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), 17643 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), 17644 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), 17645 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), 17646 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 17647 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 17648 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 17649 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), 17650 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), 17651 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), 17652 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), 17653 17654 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), 17655 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), 17656 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), 17657 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), 17658 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), 17659 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 17660 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 17661 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 17662 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), 17663 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), 17664 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), 17665 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), 17666 17667 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), 17668 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), 17669 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), 17670 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), 17671 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), 17672 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 17673 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 17674 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 17675 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), 17676 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), 17677 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), 17678 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), 17679 17680 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), 17681 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), 17682 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), 17683 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), 17684 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), 17685 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 17686 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 17687 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 17688 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), 17689 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), 17690 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), 17691 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), 17692 17693 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), 17694 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), 17695 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), 17696 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), 17697 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), 17698 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 17699 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 17700 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 17701 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), 17702 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), 17703 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), 17704 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), 17705 17706 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), 17707 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), 17708 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), 17709 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), 17710 17711 cCL("flts", e000110, 2, (RF, RR), rn_rd), 17712 cCL("fltsp", e000130, 2, (RF, RR), rn_rd), 17713 cCL("fltsm", e000150, 2, (RF, RR), rn_rd), 17714 cCL("fltsz", e000170, 2, (RF, RR), rn_rd), 17715 cCL("fltd", e000190, 2, (RF, RR), rn_rd), 17716 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), 17717 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), 17718 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), 17719 cCL("flte", e080110, 2, (RF, RR), rn_rd), 17720 cCL("fltep", e080130, 2, (RF, RR), rn_rd), 17721 cCL("fltem", e080150, 2, (RF, RR), rn_rd), 17722 cCL("fltez", e080170, 2, (RF, RR), rn_rd), 17723 17724 /* The implementation of the FIX instruction is broken on some 17725 assemblers, in that it accepts a precision specifier as well as a 17726 rounding specifier, despite the fact that this is meaningless. 17727 To be more compatible, we accept it as well, though of course it 17728 does not set any bits. */ 17729 cCE("fix", e100110, 2, (RR, RF), rd_rm), 17730 cCL("fixp", e100130, 2, (RR, RF), rd_rm), 17731 cCL("fixm", e100150, 2, (RR, RF), rd_rm), 17732 cCL("fixz", e100170, 2, (RR, RF), rd_rm), 17733 cCL("fixsp", e100130, 2, (RR, RF), rd_rm), 17734 cCL("fixsm", e100150, 2, (RR, RF), rd_rm), 17735 cCL("fixsz", e100170, 2, (RR, RF), rd_rm), 17736 cCL("fixdp", e100130, 2, (RR, RF), rd_rm), 17737 cCL("fixdm", e100150, 2, (RR, RF), rd_rm), 17738 cCL("fixdz", e100170, 2, (RR, RF), rd_rm), 17739 cCL("fixep", e100130, 2, (RR, RF), rd_rm), 17740 cCL("fixem", e100150, 2, (RR, RF), rd_rm), 17741 cCL("fixez", e100170, 2, (RR, RF), rd_rm), 17742 17743 /* Instructions that were new with the real FPA, call them V2. */ 17744#undef ARM_VARIANT 17745#define ARM_VARIANT & fpu_fpa_ext_v2 17746 17747 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), 17748 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), 17749 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), 17750 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), 17751 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), 17752 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), 17753 17754#undef ARM_VARIANT 17755#define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ 17756 17757 /* Moves and type conversions. */ 17758 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic), 17759 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp), 17760 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg), 17761 cCE("fmstat", ef1fa10, 0, (), noargs), 17762 cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs), 17763 cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr), 17764 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), 17765 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), 17766 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), 17767 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), 17768 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), 17769 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), 17770 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), 17771 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), 17772 17773 /* Memory operations. */ 17774 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), 17775 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), 17776 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), 17777 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), 17778 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), 17779 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), 17780 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), 17781 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), 17782 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), 17783 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), 17784 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), 17785 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), 17786 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), 17787 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), 17788 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), 17789 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), 17790 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), 17791 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), 17792 17793 /* Monadic operations. */ 17794 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), 17795 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), 17796 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), 17797 17798 /* Dyadic operations. */ 17799 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 17800 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 17801 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 17802 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 17803 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 17804 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 17805 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 17806 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 17807 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 17808 17809 /* Comparisons. */ 17810 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), 17811 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), 17812 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), 17813 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), 17814 17815 /* Double precision load/store are still present on single precision 17816 implementations. */ 17817 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), 17818 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), 17819 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), 17820 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), 17821 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), 17822 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), 17823 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), 17824 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), 17825 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), 17826 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), 17827 17828#undef ARM_VARIANT 17829#define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ 17830 17831 /* Moves and type conversions. */ 17832 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), 17833 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), 17834 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 17835 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), 17836 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), 17837 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), 17838 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), 17839 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), 17840 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), 17841 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), 17842 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 17843 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), 17844 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 17845 17846 /* Monadic operations. */ 17847 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 17848 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), 17849 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 17850 17851 /* Dyadic operations. */ 17852 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 17853 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 17854 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 17855 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 17856 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 17857 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 17858 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 17859 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 17860 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 17861 17862 /* Comparisons. */ 17863 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), 17864 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), 17865 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 17866 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), 17867 17868#undef ARM_VARIANT 17869#define ARM_VARIANT & fpu_vfp_ext_v2 17870 17871 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), 17872 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), 17873 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), 17874 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), 17875 17876/* Instructions which may belong to either the Neon or VFP instruction sets. 17877 Individual encoder functions perform additional architecture checks. */ 17878#undef ARM_VARIANT 17879#define ARM_VARIANT & fpu_vfp_ext_v1xd 17880#undef THUMB_VARIANT 17881#define THUMB_VARIANT & fpu_vfp_ext_v1xd 17882 17883 /* These mnemonics are unique to VFP. */ 17884 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), 17885 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), 17886 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 17887 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 17888 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 17889 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), 17890 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), 17891 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), 17892 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), 17893 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), 17894 17895 /* Mnemonics shared by Neon and VFP. */ 17896 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), 17897 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), 17898 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), 17899 17900 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), 17901 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), 17902 17903 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), 17904 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), 17905 17906 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), 17907 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), 17908 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), 17909 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), 17910 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), 17911 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), 17912 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), 17913 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), 17914 17915 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt), 17916 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), 17917 nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb), 17918 nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt), 17919 17920 17921 /* NOTE: All VMOV encoding is special-cased! */ 17922 NCE(vmov, 0, 1, (VMOV), neon_mov), 17923 NCE(vmovq, 0, 1, (VMOV), neon_mov), 17924 17925#undef THUMB_VARIANT 17926#define THUMB_VARIANT & fpu_neon_ext_v1 17927#undef ARM_VARIANT 17928#define ARM_VARIANT & fpu_neon_ext_v1 17929 17930 /* Data processing with three registers of the same length. */ 17931 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ 17932 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), 17933 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), 17934 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 17935 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 17936 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 17937 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 17938 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 17939 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 17940 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ 17941 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), 17942 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), 17943 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), 17944 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), 17945 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), 17946 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), 17947 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), 17948 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), 17949 /* If not immediate, fall back to neon_dyadic_i64_su. 17950 shl_imm should accept I8 I16 I32 I64, 17951 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ 17952 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), 17953 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), 17954 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), 17955 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), 17956 /* Logic ops, types optional & ignored. */ 17957 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), 17958 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), 17959 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), 17960 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), 17961 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), 17962 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), 17963 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), 17964 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), 17965 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), 17966 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), 17967 /* Bitfield ops, untyped. */ 17968 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 17969 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 17970 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 17971 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 17972 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 17973 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 17974 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ 17975 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 17976 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 17977 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 17978 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 17979 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 17980 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 17981 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall 17982 back to neon_dyadic_if_su. */ 17983 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), 17984 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), 17985 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), 17986 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), 17987 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), 17988 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), 17989 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), 17990 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), 17991 /* Comparison. Type I8 I16 I32 F32. */ 17992 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), 17993 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), 17994 /* As above, D registers only. */ 17995 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), 17996 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), 17997 /* Int and float variants, signedness unimportant. */ 17998 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), 17999 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), 18000 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), 18001 /* Add/sub take types I8 I16 I32 I64 F32. */ 18002 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), 18003 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), 18004 /* vtst takes sizes 8, 16, 32. */ 18005 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), 18006 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), 18007 /* VMUL takes I8 I16 I32 F32 P8. */ 18008 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), 18009 /* VQD{R}MULH takes S16 S32. */ 18010 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), 18011 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), 18012 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), 18013 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), 18014 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), 18015 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), 18016 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), 18017 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), 18018 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), 18019 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), 18020 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), 18021 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), 18022 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), 18023 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), 18024 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), 18025 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), 18026 18027 /* Two address, int/float. Types S8 S16 S32 F32. */ 18028 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), 18029 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), 18030 18031 /* Data processing with two registers and a shift amount. */ 18032 /* Right shifts, and variants with rounding. 18033 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ 18034 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), 18035 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), 18036 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), 18037 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), 18038 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), 18039 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), 18040 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), 18041 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), 18042 /* Shift and insert. Sizes accepted 8 16 32 64. */ 18043 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), 18044 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), 18045 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), 18046 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), 18047 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ 18048 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), 18049 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), 18050 /* Right shift immediate, saturating & narrowing, with rounding variants. 18051 Types accepted S16 S32 S64 U16 U32 U64. */ 18052 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), 18053 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), 18054 /* As above, unsigned. Types accepted S16 S32 S64. */ 18055 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), 18056 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), 18057 /* Right shift narrowing. Types accepted I16 I32 I64. */ 18058 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), 18059 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), 18060 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ 18061 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), 18062 /* CVT with optional immediate for fixed-point variant. */ 18063 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), 18064 18065 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn), 18066 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), 18067 18068 /* Data processing, three registers of different lengths. */ 18069 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ 18070 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), 18071 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), 18072 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), 18073 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), 18074 /* If not scalar, fall back to neon_dyadic_long. 18075 Vector types as above, scalar types S16 S32 U16 U32. */ 18076 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), 18077 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), 18078 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ 18079 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), 18080 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), 18081 /* Dyadic, narrowing insns. Types I16 I32 I64. */ 18082 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 18083 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 18084 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 18085 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 18086 /* Saturating doubling multiplies. Types S16 S32. */ 18087 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 18088 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 18089 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 18090 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types 18091 S16 S32 U16 U32. */ 18092 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), 18093 18094 /* Extract. Size 8. */ 18095 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), 18096 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), 18097 18098 /* Two registers, miscellaneous. */ 18099 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ 18100 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), 18101 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), 18102 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), 18103 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), 18104 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), 18105 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), 18106 /* Vector replicate. Sizes 8 16 32. */ 18107 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup), 18108 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), 18109 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ 18110 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), 18111 /* VMOVN. Types I16 I32 I64. */ 18112 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), 18113 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ 18114 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), 18115 /* VQMOVUN. Types S16 S32 S64. */ 18116 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), 18117 /* VZIP / VUZP. Sizes 8 16 32. */ 18118 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), 18119 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), 18120 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), 18121 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), 18122 /* VQABS / VQNEG. Types S8 S16 S32. */ 18123 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), 18124 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), 18125 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), 18126 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), 18127 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ 18128 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), 18129 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), 18130 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), 18131 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), 18132 /* Reciprocal estimates. Types U32 F32. */ 18133 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), 18134 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), 18135 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), 18136 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), 18137 /* VCLS. Types S8 S16 S32. */ 18138 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), 18139 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), 18140 /* VCLZ. Types I8 I16 I32. */ 18141 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), 18142 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), 18143 /* VCNT. Size 8. */ 18144 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), 18145 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), 18146 /* Two address, untyped. */ 18147 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), 18148 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), 18149 /* VTRN. Sizes 8 16 32. */ 18150 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), 18151 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), 18152 18153 /* Table lookup. Size 8. */ 18154 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), 18155 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), 18156 18157#undef THUMB_VARIANT 18158#define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext 18159#undef ARM_VARIANT 18160#define ARM_VARIANT & fpu_vfp_v3_or_neon_ext 18161 18162 /* Neon element/structure load/store. */ 18163 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), 18164 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), 18165 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), 18166 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), 18167 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), 18168 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), 18169 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), 18170 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), 18171 18172#undef THUMB_VARIANT 18173#define THUMB_VARIANT &fpu_vfp_ext_v3xd 18174#undef ARM_VARIANT 18175#define ARM_VARIANT &fpu_vfp_ext_v3xd 18176 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), 18177 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), 18178 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), 18179 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), 18180 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), 18181 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), 18182 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), 18183 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), 18184 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), 18185 18186#undef THUMB_VARIANT 18187#define THUMB_VARIANT & fpu_vfp_ext_v3 18188#undef ARM_VARIANT 18189#define ARM_VARIANT & fpu_vfp_ext_v3 18190 18191 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), 18192 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), 18193 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), 18194 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), 18195 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), 18196 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), 18197 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), 18198 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), 18199 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), 18200 18201#undef ARM_VARIANT 18202#define ARM_VARIANT &fpu_vfp_ext_fma 18203#undef THUMB_VARIANT 18204#define THUMB_VARIANT &fpu_vfp_ext_fma 18205 /* Mnemonics shared by Neon and VFP. These are included in the 18206 VFP FMA variant; NEON and VFP FMA always includes the NEON 18207 FMA instructions. */ 18208 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), 18209 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), 18210 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; 18211 the v form should always be used. */ 18212 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 18213 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 18214 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 18215 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 18216 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 18217 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 18218 18219#undef THUMB_VARIANT 18220#undef ARM_VARIANT 18221#define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ 18222 18223 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 18224 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 18225 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 18226 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 18227 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 18228 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 18229 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), 18230 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), 18231 18232#undef ARM_VARIANT 18233#define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ 18234 18235 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), 18236 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), 18237 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), 18238 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), 18239 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), 18240 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), 18241 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), 18242 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), 18243 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), 18244 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), 18245 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), 18246 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), 18247 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), 18248 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), 18249 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), 18250 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), 18251 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), 18252 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), 18253 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), 18254 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), 18255 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), 18256 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), 18257 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 18258 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 18259 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 18260 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 18261 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn), 18262 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn), 18263 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn), 18264 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), 18265 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), 18266 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), 18267 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), 18268 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), 18269 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), 18270 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), 18271 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), 18272 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18273 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18274 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18275 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18276 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18277 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18278 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18279 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18280 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18281 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), 18282 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18283 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18284 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18285 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18286 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18287 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18288 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18289 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18290 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18291 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18292 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18293 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18294 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18295 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18296 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18297 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18298 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18299 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18300 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18301 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 18302 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 18303 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), 18304 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), 18305 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18306 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18307 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18308 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18309 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18310 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18311 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18312 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18313 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18314 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18315 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18316 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18317 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18318 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18319 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18320 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18321 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18322 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18323 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), 18324 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18325 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18326 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18327 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18328 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18329 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18330 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18331 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18332 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18333 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18334 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18335 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 18336 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 18337 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 18338 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 18339 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 18340 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 18341 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18342 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18343 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18344 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18345 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), 18346 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 18347 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 18348 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 18349 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 18350 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 18351 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 18352 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 18353 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 18354 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 18355 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 18356 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 18357 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 18358 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 18359 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 18360 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 18361 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 18362 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 18363 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 18364 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 18365 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 18366 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), 18367 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), 18368 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18369 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18370 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18371 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18372 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18373 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18374 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18375 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18376 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18377 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), 18378 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), 18379 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), 18380 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), 18381 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), 18382 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), 18383 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18384 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18385 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18386 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), 18387 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), 18388 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), 18389 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), 18390 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), 18391 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), 18392 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18393 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18394 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18395 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18396 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), 18397 18398#undef ARM_VARIANT 18399#define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ 18400 18401 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), 18402 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), 18403 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), 18404 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), 18405 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), 18406 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), 18407 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18408 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18409 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18410 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18411 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18412 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18413 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18414 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18415 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18416 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18417 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18418 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18419 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18420 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18421 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), 18422 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18423 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18424 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18425 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18426 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18427 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18428 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18429 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18430 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18431 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18432 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18433 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18434 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18435 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18436 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18437 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18438 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18439 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18440 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18441 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18442 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18443 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18444 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18445 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18446 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18447 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18448 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18449 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18450 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18451 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18452 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18453 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18454 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18455 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18456 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18457 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 18458 18459#undef ARM_VARIANT 18460#define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ 18461 18462 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), 18463 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), 18464 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), 18465 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), 18466 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), 18467 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), 18468 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), 18469 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), 18470 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), 18471 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), 18472 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), 18473 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), 18474 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), 18475 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), 18476 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd), 18477 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn), 18478 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd), 18479 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn), 18480 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn), 18481 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn), 18482 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn), 18483 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn), 18484 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn), 18485 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn), 18486 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), 18487 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), 18488 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), 18489 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), 18490 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc), 18491 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd), 18492 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), 18493 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), 18494 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), 18495 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), 18496 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn), 18497 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn), 18498 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn), 18499 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn), 18500 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn), 18501 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn), 18502 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), 18503 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), 18504 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple), 18505 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple), 18506 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), 18507 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), 18508 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), 18509 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), 18510 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), 18511 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), 18512 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), 18513 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), 18514 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), 18515 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), 18516 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), 18517 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), 18518 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), 18519 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), 18520 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), 18521 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), 18522 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), 18523 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), 18524 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), 18525 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), 18526 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 18527 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 18528 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 18529 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 18530 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 18531 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 18532 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 18533 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 18534 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), 18535 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), 18536 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), 18537 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), 18538}; 18539#undef ARM_VARIANT 18540#undef THUMB_VARIANT 18541#undef TCE 18542#undef TCM 18543#undef TUE 18544#undef TUF 18545#undef TCC 18546#undef cCE 18547#undef cCL 18548#undef C3E 18549#undef CE 18550#undef CM 18551#undef UE 18552#undef UF 18553#undef UT 18554#undef NUF 18555#undef nUF 18556#undef NCE 18557#undef nCE 18558#undef OPS0 18559#undef OPS1 18560#undef OPS2 18561#undef OPS3 18562#undef OPS4 18563#undef OPS5 18564#undef OPS6 18565#undef do_0 18566 18567/* MD interface: bits in the object file. */ 18568 18569/* Turn an integer of n bytes (in val) into a stream of bytes appropriate 18570 for use in the a.out file, and stores them in the array pointed to by buf. 18571 This knows about the endian-ness of the target machine and does 18572 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) 18573 2 (short) and 4 (long) Floating numbers are put out as a series of 18574 LITTLENUMS (shorts, here at least). */ 18575 18576void 18577md_number_to_chars (char * buf, valueT val, int n) 18578{ 18579 if (target_big_endian) 18580 number_to_chars_bigendian (buf, val, n); 18581 else 18582 number_to_chars_littleendian (buf, val, n); 18583} 18584 18585static valueT 18586md_chars_to_number (char * buf, int n) 18587{ 18588 valueT result = 0; 18589 unsigned char * where = (unsigned char *) buf; 18590 18591 if (target_big_endian) 18592 { 18593 while (n--) 18594 { 18595 result <<= 8; 18596 result |= (*where++ & 255); 18597 } 18598 } 18599 else 18600 { 18601 while (n--) 18602 { 18603 result <<= 8; 18604 result |= (where[n] & 255); 18605 } 18606 } 18607 18608 return result; 18609} 18610 18611/* MD interface: Sections. */ 18612 18613/* Estimate the size of a frag before relaxing. Assume everything fits in 18614 2 bytes. */ 18615 18616int 18617md_estimate_size_before_relax (fragS * fragp, 18618 segT segtype ATTRIBUTE_UNUSED) 18619{ 18620 fragp->fr_var = 2; 18621 return 2; 18622} 18623 18624/* Convert a machine dependent frag. */ 18625 18626void 18627md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) 18628{ 18629 unsigned long insn; 18630 unsigned long old_op; 18631 char *buf; 18632 expressionS exp; 18633 fixS *fixp; 18634 int reloc_type; 18635 int pc_rel; 18636 int opcode; 18637 18638 buf = fragp->fr_literal + fragp->fr_fix; 18639 18640 old_op = bfd_get_16(abfd, buf); 18641 if (fragp->fr_symbol) 18642 { 18643 exp.X_op = O_symbol; 18644 exp.X_add_symbol = fragp->fr_symbol; 18645 } 18646 else 18647 { 18648 exp.X_op = O_constant; 18649 } 18650 exp.X_add_number = fragp->fr_offset; 18651 opcode = fragp->fr_subtype; 18652 switch (opcode) 18653 { 18654 case T_MNEM_ldr_pc: 18655 case T_MNEM_ldr_pc2: 18656 case T_MNEM_ldr_sp: 18657 case T_MNEM_str_sp: 18658 case T_MNEM_ldr: 18659 case T_MNEM_ldrb: 18660 case T_MNEM_ldrh: 18661 case T_MNEM_str: 18662 case T_MNEM_strb: 18663 case T_MNEM_strh: 18664 if (fragp->fr_var == 4) 18665 { 18666 insn = THUMB_OP32 (opcode); 18667 if ((old_op >> 12) == 4 || (old_op >> 12) == 9) 18668 { 18669 insn |= (old_op & 0x700) << 4; 18670 } 18671 else 18672 { 18673 insn |= (old_op & 7) << 12; 18674 insn |= (old_op & 0x38) << 13; 18675 } 18676 insn |= 0x00000c00; 18677 put_thumb32_insn (buf, insn); 18678 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; 18679 } 18680 else 18681 { 18682 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; 18683 } 18684 pc_rel = (opcode == T_MNEM_ldr_pc2); 18685 break; 18686 case T_MNEM_adr: 18687 if (fragp->fr_var == 4) 18688 { 18689 insn = THUMB_OP32 (opcode); 18690 insn |= (old_op & 0xf0) << 4; 18691 put_thumb32_insn (buf, insn); 18692 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; 18693 } 18694 else 18695 { 18696 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 18697 exp.X_add_number -= 4; 18698 } 18699 pc_rel = 1; 18700 break; 18701 case T_MNEM_mov: 18702 case T_MNEM_movs: 18703 case T_MNEM_cmp: 18704 case T_MNEM_cmn: 18705 if (fragp->fr_var == 4) 18706 { 18707 int r0off = (opcode == T_MNEM_mov 18708 || opcode == T_MNEM_movs) ? 0 : 8; 18709 insn = THUMB_OP32 (opcode); 18710 insn = (insn & 0xe1ffffff) | 0x10000000; 18711 insn |= (old_op & 0x700) << r0off; 18712 put_thumb32_insn (buf, insn); 18713 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; 18714 } 18715 else 18716 { 18717 reloc_type = BFD_RELOC_ARM_THUMB_IMM; 18718 } 18719 pc_rel = 0; 18720 break; 18721 case T_MNEM_b: 18722 if (fragp->fr_var == 4) 18723 { 18724 insn = THUMB_OP32(opcode); 18725 put_thumb32_insn (buf, insn); 18726 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; 18727 } 18728 else 18729 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; 18730 pc_rel = 1; 18731 break; 18732 case T_MNEM_bcond: 18733 if (fragp->fr_var == 4) 18734 { 18735 insn = THUMB_OP32(opcode); 18736 insn |= (old_op & 0xf00) << 14; 18737 put_thumb32_insn (buf, insn); 18738 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; 18739 } 18740 else 18741 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; 18742 pc_rel = 1; 18743 break; 18744 case T_MNEM_add_sp: 18745 case T_MNEM_add_pc: 18746 case T_MNEM_inc_sp: 18747 case T_MNEM_dec_sp: 18748 if (fragp->fr_var == 4) 18749 { 18750 /* ??? Choose between add and addw. */ 18751 insn = THUMB_OP32 (opcode); 18752 insn |= (old_op & 0xf0) << 4; 18753 put_thumb32_insn (buf, insn); 18754 if (opcode == T_MNEM_add_pc) 18755 reloc_type = BFD_RELOC_ARM_T32_IMM12; 18756 else 18757 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; 18758 } 18759 else 18760 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 18761 pc_rel = 0; 18762 break; 18763 18764 case T_MNEM_addi: 18765 case T_MNEM_addis: 18766 case T_MNEM_subi: 18767 case T_MNEM_subis: 18768 if (fragp->fr_var == 4) 18769 { 18770 insn = THUMB_OP32 (opcode); 18771 insn |= (old_op & 0xf0) << 4; 18772 insn |= (old_op & 0xf) << 16; 18773 put_thumb32_insn (buf, insn); 18774 if (insn & (1 << 20)) 18775 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; 18776 else 18777 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; 18778 } 18779 else 18780 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 18781 pc_rel = 0; 18782 break; 18783 default: 18784 abort (); 18785 } 18786 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, 18787 (enum bfd_reloc_code_real) reloc_type); 18788 fixp->fx_file = fragp->fr_file; 18789 fixp->fx_line = fragp->fr_line; 18790 fragp->fr_fix += fragp->fr_var; 18791} 18792 18793/* Return the size of a relaxable immediate operand instruction. 18794 SHIFT and SIZE specify the form of the allowable immediate. */ 18795static int 18796relax_immediate (fragS *fragp, int size, int shift) 18797{ 18798 offsetT offset; 18799 offsetT mask; 18800 offsetT low; 18801 18802 /* ??? Should be able to do better than this. */ 18803 if (fragp->fr_symbol) 18804 return 4; 18805 18806 low = (1 << shift) - 1; 18807 mask = (1 << (shift + size)) - (1 << shift); 18808 offset = fragp->fr_offset; 18809 /* Force misaligned offsets to 32-bit variant. */ 18810 if (offset & low) 18811 return 4; 18812 if (offset & ~mask) 18813 return 4; 18814 return 2; 18815} 18816 18817/* Get the address of a symbol during relaxation. */ 18818static addressT 18819relaxed_symbol_addr (fragS *fragp, long stretch) 18820{ 18821 fragS *sym_frag; 18822 addressT addr; 18823 symbolS *sym; 18824 18825 sym = fragp->fr_symbol; 18826 sym_frag = symbol_get_frag (sym); 18827 know (S_GET_SEGMENT (sym) != absolute_section 18828 || sym_frag == &zero_address_frag); 18829 addr = S_GET_VALUE (sym) + fragp->fr_offset; 18830 18831 /* If frag has yet to be reached on this pass, assume it will 18832 move by STRETCH just as we did. If this is not so, it will 18833 be because some frag between grows, and that will force 18834 another pass. */ 18835 18836 if (stretch != 0 18837 && sym_frag->relax_marker != fragp->relax_marker) 18838 { 18839 fragS *f; 18840 18841 /* Adjust stretch for any alignment frag. Note that if have 18842 been expanding the earlier code, the symbol may be 18843 defined in what appears to be an earlier frag. FIXME: 18844 This doesn't handle the fr_subtype field, which specifies 18845 a maximum number of bytes to skip when doing an 18846 alignment. */ 18847 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) 18848 { 18849 if (f->fr_type == rs_align || f->fr_type == rs_align_code) 18850 { 18851 if (stretch < 0) 18852 stretch = - ((- stretch) 18853 & ~ ((1 << (int) f->fr_offset) - 1)); 18854 else 18855 stretch &= ~ ((1 << (int) f->fr_offset) - 1); 18856 if (stretch == 0) 18857 break; 18858 } 18859 } 18860 if (f != NULL) 18861 addr += stretch; 18862 } 18863 18864 return addr; 18865} 18866 18867/* Return the size of a relaxable adr pseudo-instruction or PC-relative 18868 load. */ 18869static int 18870relax_adr (fragS *fragp, asection *sec, long stretch) 18871{ 18872 addressT addr; 18873 offsetT val; 18874 18875 /* Assume worst case for symbols not known to be in the same section. */ 18876 if (fragp->fr_symbol == NULL 18877 || !S_IS_DEFINED (fragp->fr_symbol) 18878 || sec != S_GET_SEGMENT (fragp->fr_symbol) 18879 || S_IS_WEAK (fragp->fr_symbol)) 18880 return 4; 18881 18882 val = relaxed_symbol_addr (fragp, stretch); 18883 addr = fragp->fr_address + fragp->fr_fix; 18884 addr = (addr + 4) & ~3; 18885 /* Force misaligned targets to 32-bit variant. */ 18886 if (val & 3) 18887 return 4; 18888 val -= addr; 18889 if (val < 0 || val > 1020) 18890 return 4; 18891 return 2; 18892} 18893 18894/* Return the size of a relaxable add/sub immediate instruction. */ 18895static int 18896relax_addsub (fragS *fragp, asection *sec) 18897{ 18898 char *buf; 18899 int op; 18900 18901 buf = fragp->fr_literal + fragp->fr_fix; 18902 op = bfd_get_16(sec->owner, buf); 18903 if ((op & 0xf) == ((op >> 4) & 0xf)) 18904 return relax_immediate (fragp, 8, 0); 18905 else 18906 return relax_immediate (fragp, 3, 0); 18907} 18908 18909 18910/* Return the size of a relaxable branch instruction. BITS is the 18911 size of the offset field in the narrow instruction. */ 18912 18913static int 18914relax_branch (fragS *fragp, asection *sec, int bits, long stretch) 18915{ 18916 addressT addr; 18917 offsetT val; 18918 offsetT limit; 18919 18920 /* Assume worst case for symbols not known to be in the same section. */ 18921 if (!S_IS_DEFINED (fragp->fr_symbol) 18922 || sec != S_GET_SEGMENT (fragp->fr_symbol) 18923 || S_IS_WEAK (fragp->fr_symbol)) 18924 return 4; 18925 18926#ifdef OBJ_ELF 18927 if (S_IS_DEFINED (fragp->fr_symbol) 18928 && ARM_IS_FUNC (fragp->fr_symbol)) 18929 return 4; 18930#endif 18931 18932 val = relaxed_symbol_addr (fragp, stretch); 18933 addr = fragp->fr_address + fragp->fr_fix + 4; 18934 val -= addr; 18935 18936 /* Offset is a signed value *2 */ 18937 limit = 1 << bits; 18938 if (val >= limit || val < -limit) 18939 return 4; 18940 return 2; 18941} 18942 18943 18944/* Relax a machine dependent frag. This returns the amount by which 18945 the current size of the frag should change. */ 18946 18947int 18948arm_relax_frag (asection *sec, fragS *fragp, long stretch) 18949{ 18950 int oldsize; 18951 int newsize; 18952 18953 oldsize = fragp->fr_var; 18954 switch (fragp->fr_subtype) 18955 { 18956 case T_MNEM_ldr_pc2: 18957 newsize = relax_adr (fragp, sec, stretch); 18958 break; 18959 case T_MNEM_ldr_pc: 18960 case T_MNEM_ldr_sp: 18961 case T_MNEM_str_sp: 18962 newsize = relax_immediate (fragp, 8, 2); 18963 break; 18964 case T_MNEM_ldr: 18965 case T_MNEM_str: 18966 newsize = relax_immediate (fragp, 5, 2); 18967 break; 18968 case T_MNEM_ldrh: 18969 case T_MNEM_strh: 18970 newsize = relax_immediate (fragp, 5, 1); 18971 break; 18972 case T_MNEM_ldrb: 18973 case T_MNEM_strb: 18974 newsize = relax_immediate (fragp, 5, 0); 18975 break; 18976 case T_MNEM_adr: 18977 newsize = relax_adr (fragp, sec, stretch); 18978 break; 18979 case T_MNEM_mov: 18980 case T_MNEM_movs: 18981 case T_MNEM_cmp: 18982 case T_MNEM_cmn: 18983 newsize = relax_immediate (fragp, 8, 0); 18984 break; 18985 case T_MNEM_b: 18986 newsize = relax_branch (fragp, sec, 11, stretch); 18987 break; 18988 case T_MNEM_bcond: 18989 newsize = relax_branch (fragp, sec, 8, stretch); 18990 break; 18991 case T_MNEM_add_sp: 18992 case T_MNEM_add_pc: 18993 newsize = relax_immediate (fragp, 8, 2); 18994 break; 18995 case T_MNEM_inc_sp: 18996 case T_MNEM_dec_sp: 18997 newsize = relax_immediate (fragp, 7, 2); 18998 break; 18999 case T_MNEM_addi: 19000 case T_MNEM_addis: 19001 case T_MNEM_subi: 19002 case T_MNEM_subis: 19003 newsize = relax_addsub (fragp, sec); 19004 break; 19005 default: 19006 abort (); 19007 } 19008 19009 fragp->fr_var = newsize; 19010 /* Freeze wide instructions that are at or before the same location as 19011 in the previous pass. This avoids infinite loops. 19012 Don't freeze them unconditionally because targets may be artificially 19013 misaligned by the expansion of preceding frags. */ 19014 if (stretch <= 0 && newsize > 2) 19015 { 19016 md_convert_frag (sec->owner, sec, fragp); 19017 frag_wane (fragp); 19018 } 19019 19020 return newsize - oldsize; 19021} 19022 19023/* Round up a section size to the appropriate boundary. */ 19024 19025valueT 19026md_section_align (segT segment ATTRIBUTE_UNUSED, 19027 valueT size) 19028{ 19029#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 19030 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 19031 { 19032 /* For a.out, force the section size to be aligned. If we don't do 19033 this, BFD will align it for us, but it will not write out the 19034 final bytes of the section. This may be a bug in BFD, but it is 19035 easier to fix it here since that is how the other a.out targets 19036 work. */ 19037 int align; 19038 19039 align = bfd_get_section_alignment (stdoutput, segment); 19040 size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); 19041 } 19042#endif 19043 19044 return size; 19045} 19046 19047/* This is called from HANDLE_ALIGN in write.c. Fill in the contents 19048 of an rs_align_code fragment. */ 19049 19050void 19051arm_handle_align (fragS * fragP) 19052{ 19053 static char const arm_noop[2][2][4] = 19054 { 19055 { /* ARMv1 */ 19056 {0x00, 0x00, 0xa0, 0xe1}, /* LE */ 19057 {0xe1, 0xa0, 0x00, 0x00}, /* BE */ 19058 }, 19059 { /* ARMv6k */ 19060 {0x00, 0xf0, 0x20, 0xe3}, /* LE */ 19061 {0xe3, 0x20, 0xf0, 0x00}, /* BE */ 19062 }, 19063 }; 19064 static char const thumb_noop[2][2][2] = 19065 { 19066 { /* Thumb-1 */ 19067 {0xc0, 0x46}, /* LE */ 19068 {0x46, 0xc0}, /* BE */ 19069 }, 19070 { /* Thumb-2 */ 19071 {0x00, 0xbf}, /* LE */ 19072 {0xbf, 0x00} /* BE */ 19073 } 19074 }; 19075 static char const wide_thumb_noop[2][4] = 19076 { /* Wide Thumb-2 */ 19077 {0xaf, 0xf3, 0x00, 0x80}, /* LE */ 19078 {0xf3, 0xaf, 0x80, 0x00}, /* BE */ 19079 }; 19080 19081 unsigned bytes, fix, noop_size; 19082 char * p; 19083 const char * noop; 19084 const char *narrow_noop = NULL; 19085#ifdef OBJ_ELF 19086 enum mstate state; 19087#endif 19088 19089 if (fragP->fr_type != rs_align_code) 19090 return; 19091 19092 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; 19093 p = fragP->fr_literal + fragP->fr_fix; 19094 fix = 0; 19095 19096 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) 19097 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; 19098 19099 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); 19100 19101 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) 19102 { 19103 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) 19104 { 19105 narrow_noop = thumb_noop[1][target_big_endian]; 19106 noop = wide_thumb_noop[target_big_endian]; 19107 } 19108 else 19109 noop = thumb_noop[0][target_big_endian]; 19110 noop_size = 2; 19111#ifdef OBJ_ELF 19112 state = MAP_THUMB; 19113#endif 19114 } 19115 else 19116 { 19117 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0] 19118 [target_big_endian]; 19119 noop_size = 4; 19120#ifdef OBJ_ELF 19121 state = MAP_ARM; 19122#endif 19123 } 19124 19125 fragP->fr_var = noop_size; 19126 19127 if (bytes & (noop_size - 1)) 19128 { 19129 fix = bytes & (noop_size - 1); 19130#ifdef OBJ_ELF 19131 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); 19132#endif 19133 memset (p, 0, fix); 19134 p += fix; 19135 bytes -= fix; 19136 } 19137 19138 if (narrow_noop) 19139 { 19140 if (bytes & noop_size) 19141 { 19142 /* Insert a narrow noop. */ 19143 memcpy (p, narrow_noop, noop_size); 19144 p += noop_size; 19145 bytes -= noop_size; 19146 fix += noop_size; 19147 } 19148 19149 /* Use wide noops for the remainder */ 19150 noop_size = 4; 19151 } 19152 19153 while (bytes >= noop_size) 19154 { 19155 memcpy (p, noop, noop_size); 19156 p += noop_size; 19157 bytes -= noop_size; 19158 fix += noop_size; 19159 } 19160 19161 fragP->fr_fix += fix; 19162} 19163 19164/* Called from md_do_align. Used to create an alignment 19165 frag in a code section. */ 19166 19167void 19168arm_frag_align_code (int n, int max) 19169{ 19170 char * p; 19171 19172 /* We assume that there will never be a requirement 19173 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ 19174 if (max > MAX_MEM_FOR_RS_ALIGN_CODE) 19175 { 19176 char err_msg[128]; 19177 19178 sprintf (err_msg, 19179 _("alignments greater than %d bytes not supported in .text sections."), 19180 MAX_MEM_FOR_RS_ALIGN_CODE + 1); 19181 as_fatal ("%s", err_msg); 19182 } 19183 19184 p = frag_var (rs_align_code, 19185 MAX_MEM_FOR_RS_ALIGN_CODE, 19186 1, 19187 (relax_substateT) max, 19188 (symbolS *) NULL, 19189 (offsetT) n, 19190 (char *) NULL); 19191 *p = 0; 19192} 19193 19194/* Perform target specific initialisation of a frag. 19195 Note - despite the name this initialisation is not done when the frag 19196 is created, but only when its type is assigned. A frag can be created 19197 and used a long time before its type is set, so beware of assuming that 19198 this initialisationis performed first. */ 19199 19200#ifndef OBJ_ELF 19201void 19202arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) 19203{ 19204 /* Record whether this frag is in an ARM or a THUMB area. */ 19205 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; 19206} 19207 19208#else /* OBJ_ELF is defined. */ 19209void 19210arm_init_frag (fragS * fragP, int max_chars) 19211{ 19212 /* If the current ARM vs THUMB mode has not already 19213 been recorded into this frag then do so now. */ 19214 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) 19215 { 19216 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; 19217 19218 /* Record a mapping symbol for alignment frags. We will delete this 19219 later if the alignment ends up empty. */ 19220 switch (fragP->fr_type) 19221 { 19222 case rs_align: 19223 case rs_align_test: 19224 case rs_fill: 19225 mapping_state_2 (MAP_DATA, max_chars); 19226 break; 19227 case rs_align_code: 19228 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); 19229 break; 19230 default: 19231 break; 19232 } 19233 } 19234} 19235 19236/* When we change sections we need to issue a new mapping symbol. */ 19237 19238void 19239arm_elf_change_section (void) 19240{ 19241 /* Link an unlinked unwind index table section to the .text section. */ 19242 if (elf_section_type (now_seg) == SHT_ARM_EXIDX 19243 && elf_linked_to_section (now_seg) == NULL) 19244 elf_linked_to_section (now_seg) = text_section; 19245} 19246 19247int 19248arm_elf_section_type (const char * str, size_t len) 19249{ 19250 if (len == 5 && strncmp (str, "exidx", 5) == 0) 19251 return SHT_ARM_EXIDX; 19252 19253 return -1; 19254} 19255 19256/* Code to deal with unwinding tables. */ 19257 19258static void add_unwind_adjustsp (offsetT); 19259 19260/* Generate any deferred unwind frame offset. */ 19261 19262static void 19263flush_pending_unwind (void) 19264{ 19265 offsetT offset; 19266 19267 offset = unwind.pending_offset; 19268 unwind.pending_offset = 0; 19269 if (offset != 0) 19270 add_unwind_adjustsp (offset); 19271} 19272 19273/* Add an opcode to this list for this function. Two-byte opcodes should 19274 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse 19275 order. */ 19276 19277static void 19278add_unwind_opcode (valueT op, int length) 19279{ 19280 /* Add any deferred stack adjustment. */ 19281 if (unwind.pending_offset) 19282 flush_pending_unwind (); 19283 19284 unwind.sp_restored = 0; 19285 19286 if (unwind.opcode_count + length > unwind.opcode_alloc) 19287 { 19288 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; 19289 if (unwind.opcodes) 19290 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes, 19291 unwind.opcode_alloc); 19292 else 19293 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc); 19294 } 19295 while (length > 0) 19296 { 19297 length--; 19298 unwind.opcodes[unwind.opcode_count] = op & 0xff; 19299 op >>= 8; 19300 unwind.opcode_count++; 19301 } 19302} 19303 19304/* Add unwind opcodes to adjust the stack pointer. */ 19305 19306static void 19307add_unwind_adjustsp (offsetT offset) 19308{ 19309 valueT op; 19310 19311 if (offset > 0x200) 19312 { 19313 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ 19314 char bytes[5]; 19315 int n; 19316 valueT o; 19317 19318 /* Long form: 0xb2, uleb128. */ 19319 /* This might not fit in a word so add the individual bytes, 19320 remembering the list is built in reverse order. */ 19321 o = (valueT) ((offset - 0x204) >> 2); 19322 if (o == 0) 19323 add_unwind_opcode (0, 1); 19324 19325 /* Calculate the uleb128 encoding of the offset. */ 19326 n = 0; 19327 while (o) 19328 { 19329 bytes[n] = o & 0x7f; 19330 o >>= 7; 19331 if (o) 19332 bytes[n] |= 0x80; 19333 n++; 19334 } 19335 /* Add the insn. */ 19336 for (; n; n--) 19337 add_unwind_opcode (bytes[n - 1], 1); 19338 add_unwind_opcode (0xb2, 1); 19339 } 19340 else if (offset > 0x100) 19341 { 19342 /* Two short opcodes. */ 19343 add_unwind_opcode (0x3f, 1); 19344 op = (offset - 0x104) >> 2; 19345 add_unwind_opcode (op, 1); 19346 } 19347 else if (offset > 0) 19348 { 19349 /* Short opcode. */ 19350 op = (offset - 4) >> 2; 19351 add_unwind_opcode (op, 1); 19352 } 19353 else if (offset < 0) 19354 { 19355 offset = -offset; 19356 while (offset > 0x100) 19357 { 19358 add_unwind_opcode (0x7f, 1); 19359 offset -= 0x100; 19360 } 19361 op = ((offset - 4) >> 2) | 0x40; 19362 add_unwind_opcode (op, 1); 19363 } 19364} 19365 19366/* Finish the list of unwind opcodes for this function. */ 19367static void 19368finish_unwind_opcodes (void) 19369{ 19370 valueT op; 19371 19372 if (unwind.fp_used) 19373 { 19374 /* Adjust sp as necessary. */ 19375 unwind.pending_offset += unwind.fp_offset - unwind.frame_size; 19376 flush_pending_unwind (); 19377 19378 /* After restoring sp from the frame pointer. */ 19379 op = 0x90 | unwind.fp_reg; 19380 add_unwind_opcode (op, 1); 19381 } 19382 else 19383 flush_pending_unwind (); 19384} 19385 19386 19387/* Start an exception table entry. If idx is nonzero this is an index table 19388 entry. */ 19389 19390static void 19391start_unwind_section (const segT text_seg, int idx) 19392{ 19393 const char * text_name; 19394 const char * prefix; 19395 const char * prefix_once; 19396 const char * group_name; 19397 size_t prefix_len; 19398 size_t text_len; 19399 char * sec_name; 19400 size_t sec_name_len; 19401 int type; 19402 int flags; 19403 int linkonce; 19404 19405 if (idx) 19406 { 19407 prefix = ELF_STRING_ARM_unwind; 19408 prefix_once = ELF_STRING_ARM_unwind_once; 19409 type = SHT_ARM_EXIDX; 19410 } 19411 else 19412 { 19413 prefix = ELF_STRING_ARM_unwind_info; 19414 prefix_once = ELF_STRING_ARM_unwind_info_once; 19415 type = SHT_PROGBITS; 19416 } 19417 19418 text_name = segment_name (text_seg); 19419 if (streq (text_name, ".text")) 19420 text_name = ""; 19421 19422 if (strncmp (text_name, ".gnu.linkonce.t.", 19423 strlen (".gnu.linkonce.t.")) == 0) 19424 { 19425 prefix = prefix_once; 19426 text_name += strlen (".gnu.linkonce.t."); 19427 } 19428 19429 prefix_len = strlen (prefix); 19430 text_len = strlen (text_name); 19431 sec_name_len = prefix_len + text_len; 19432 sec_name = (char *) xmalloc (sec_name_len + 1); 19433 memcpy (sec_name, prefix, prefix_len); 19434 memcpy (sec_name + prefix_len, text_name, text_len); 19435 sec_name[prefix_len + text_len] = '\0'; 19436 19437 flags = SHF_ALLOC; 19438 linkonce = 0; 19439 group_name = 0; 19440 19441 /* Handle COMDAT group. */ 19442 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) 19443 { 19444 group_name = elf_group_name (text_seg); 19445 if (group_name == NULL) 19446 { 19447 as_bad (_("Group section `%s' has no group signature"), 19448 segment_name (text_seg)); 19449 ignore_rest_of_line (); 19450 return; 19451 } 19452 flags |= SHF_GROUP; 19453 linkonce = 1; 19454 } 19455 19456 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); 19457 19458 /* Set the section link for index tables. */ 19459 if (idx) 19460 elf_linked_to_section (now_seg) = text_seg; 19461} 19462 19463 19464/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional 19465 personality routine data. Returns zero, or the index table value for 19466 and inline entry. */ 19467 19468static valueT 19469create_unwind_entry (int have_data) 19470{ 19471 int size; 19472 addressT where; 19473 char *ptr; 19474 /* The current word of data. */ 19475 valueT data; 19476 /* The number of bytes left in this word. */ 19477 int n; 19478 19479 finish_unwind_opcodes (); 19480 19481 /* Remember the current text section. */ 19482 unwind.saved_seg = now_seg; 19483 unwind.saved_subseg = now_subseg; 19484 19485 start_unwind_section (now_seg, 0); 19486 19487 if (unwind.personality_routine == NULL) 19488 { 19489 if (unwind.personality_index == -2) 19490 { 19491 if (have_data) 19492 as_bad (_("handlerdata in cantunwind frame")); 19493 return 1; /* EXIDX_CANTUNWIND. */ 19494 } 19495 19496 /* Use a default personality routine if none is specified. */ 19497 if (unwind.personality_index == -1) 19498 { 19499 if (unwind.opcode_count > 3) 19500 unwind.personality_index = 1; 19501 else 19502 unwind.personality_index = 0; 19503 } 19504 19505 /* Space for the personality routine entry. */ 19506 if (unwind.personality_index == 0) 19507 { 19508 if (unwind.opcode_count > 3) 19509 as_bad (_("too many unwind opcodes for personality routine 0")); 19510 19511 if (!have_data) 19512 { 19513 /* All the data is inline in the index table. */ 19514 data = 0x80; 19515 n = 3; 19516 while (unwind.opcode_count > 0) 19517 { 19518 unwind.opcode_count--; 19519 data = (data << 8) | unwind.opcodes[unwind.opcode_count]; 19520 n--; 19521 } 19522 19523 /* Pad with "finish" opcodes. */ 19524 while (n--) 19525 data = (data << 8) | 0xb0; 19526 19527 return data; 19528 } 19529 size = 0; 19530 } 19531 else 19532 /* We get two opcodes "free" in the first word. */ 19533 size = unwind.opcode_count - 2; 19534 } 19535 else 19536 /* An extra byte is required for the opcode count. */ 19537 size = unwind.opcode_count + 1; 19538 19539 size = (size + 3) >> 2; 19540 if (size > 0xff) 19541 as_bad (_("too many unwind opcodes")); 19542 19543 frag_align (2, 0, 0); 19544 record_alignment (now_seg, 2); 19545 unwind.table_entry = expr_build_dot (); 19546 19547 /* Allocate the table entry. */ 19548 ptr = frag_more ((size << 2) + 4); 19549 where = frag_now_fix () - ((size << 2) + 4); 19550 19551 switch (unwind.personality_index) 19552 { 19553 case -1: 19554 /* ??? Should this be a PLT generating relocation? */ 19555 /* Custom personality routine. */ 19556 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, 19557 BFD_RELOC_ARM_PREL31); 19558 19559 where += 4; 19560 ptr += 4; 19561 19562 /* Set the first byte to the number of additional words. */ 19563 data = size - 1; 19564 n = 3; 19565 break; 19566 19567 /* ABI defined personality routines. */ 19568 case 0: 19569 /* Three opcodes bytes are packed into the first word. */ 19570 data = 0x80; 19571 n = 3; 19572 break; 19573 19574 case 1: 19575 case 2: 19576 /* The size and first two opcode bytes go in the first word. */ 19577 data = ((0x80 + unwind.personality_index) << 8) | size; 19578 n = 2; 19579 break; 19580 19581 default: 19582 /* Should never happen. */ 19583 abort (); 19584 } 19585 19586 /* Pack the opcodes into words (MSB first), reversing the list at the same 19587 time. */ 19588 while (unwind.opcode_count > 0) 19589 { 19590 if (n == 0) 19591 { 19592 md_number_to_chars (ptr, data, 4); 19593 ptr += 4; 19594 n = 4; 19595 data = 0; 19596 } 19597 unwind.opcode_count--; 19598 n--; 19599 data = (data << 8) | unwind.opcodes[unwind.opcode_count]; 19600 } 19601 19602 /* Finish off the last word. */ 19603 if (n < 4) 19604 { 19605 /* Pad with "finish" opcodes. */ 19606 while (n--) 19607 data = (data << 8) | 0xb0; 19608 19609 md_number_to_chars (ptr, data, 4); 19610 } 19611 19612 if (!have_data) 19613 { 19614 /* Add an empty descriptor if there is no user-specified data. */ 19615 ptr = frag_more (4); 19616 md_number_to_chars (ptr, 0, 4); 19617 } 19618 19619 return 0; 19620} 19621 19622 19623/* Initialize the DWARF-2 unwind information for this procedure. */ 19624 19625void 19626tc_arm_frame_initial_instructions (void) 19627{ 19628 cfi_add_CFA_def_cfa (REG_SP, 0); 19629} 19630#endif /* OBJ_ELF */ 19631 19632/* Convert REGNAME to a DWARF-2 register number. */ 19633 19634int 19635tc_arm_regname_to_dw2regnum (char *regname) 19636{ 19637 int reg = arm_reg_parse (®name, REG_TYPE_RN); 19638 19639 if (reg == FAIL) 19640 return -1; 19641 19642 return reg; 19643} 19644 19645#ifdef TE_PE 19646void 19647tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) 19648{ 19649 expressionS exp; 19650 19651 exp.X_op = O_secrel; 19652 exp.X_add_symbol = symbol; 19653 exp.X_add_number = 0; 19654 emit_expr (&exp, size); 19655} 19656#endif 19657 19658/* MD interface: Symbol and relocation handling. */ 19659 19660/* Return the address within the segment that a PC-relative fixup is 19661 relative to. For ARM, PC-relative fixups applied to instructions 19662 are generally relative to the location of the fixup plus 8 bytes. 19663 Thumb branches are offset by 4, and Thumb loads relative to PC 19664 require special handling. */ 19665 19666long 19667md_pcrel_from_section (fixS * fixP, segT seg) 19668{ 19669 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; 19670 19671 /* If this is pc-relative and we are going to emit a relocation 19672 then we just want to put out any pipeline compensation that the linker 19673 will need. Otherwise we want to use the calculated base. 19674 For WinCE we skip the bias for externals as well, since this 19675 is how the MS ARM-CE assembler behaves and we want to be compatible. */ 19676 if (fixP->fx_pcrel 19677 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) 19678 || (arm_force_relocation (fixP) 19679#ifdef TE_WINCE 19680 && !S_IS_EXTERNAL (fixP->fx_addsy) 19681#endif 19682 ))) 19683 base = 0; 19684 19685 19686 switch (fixP->fx_r_type) 19687 { 19688 /* PC relative addressing on the Thumb is slightly odd as the 19689 bottom two bits of the PC are forced to zero for the 19690 calculation. This happens *after* application of the 19691 pipeline offset. However, Thumb adrl already adjusts for 19692 this, so we need not do it again. */ 19693 case BFD_RELOC_ARM_THUMB_ADD: 19694 return base & ~3; 19695 19696 case BFD_RELOC_ARM_THUMB_OFFSET: 19697 case BFD_RELOC_ARM_T32_OFFSET_IMM: 19698 case BFD_RELOC_ARM_T32_ADD_PC12: 19699 case BFD_RELOC_ARM_T32_CP_OFF_IMM: 19700 return (base + 4) & ~3; 19701 19702 /* Thumb branches are simply offset by +4. */ 19703 case BFD_RELOC_THUMB_PCREL_BRANCH7: 19704 case BFD_RELOC_THUMB_PCREL_BRANCH9: 19705 case BFD_RELOC_THUMB_PCREL_BRANCH12: 19706 case BFD_RELOC_THUMB_PCREL_BRANCH20: 19707 case BFD_RELOC_THUMB_PCREL_BRANCH25: 19708 return base + 4; 19709 19710 case BFD_RELOC_THUMB_PCREL_BRANCH23: 19711 if (fixP->fx_addsy 19712 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 19713 && (!S_IS_EXTERNAL (fixP->fx_addsy)) 19714 && ARM_IS_FUNC (fixP->fx_addsy) 19715 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) 19716 base = fixP->fx_where + fixP->fx_frag->fr_address; 19717 return base + 4; 19718 19719 /* BLX is like branches above, but forces the low two bits of PC to 19720 zero. */ 19721 case BFD_RELOC_THUMB_PCREL_BLX: 19722 if (fixP->fx_addsy 19723 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 19724 && (!S_IS_EXTERNAL (fixP->fx_addsy)) 19725 && THUMB_IS_FUNC (fixP->fx_addsy) 19726 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) 19727 base = fixP->fx_where + fixP->fx_frag->fr_address; 19728 return (base + 4) & ~3; 19729 19730 /* ARM mode branches are offset by +8. However, the Windows CE 19731 loader expects the relocation not to take this into account. */ 19732 case BFD_RELOC_ARM_PCREL_BLX: 19733 if (fixP->fx_addsy 19734 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 19735 && (!S_IS_EXTERNAL (fixP->fx_addsy)) 19736 && ARM_IS_FUNC (fixP->fx_addsy) 19737 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) 19738 base = fixP->fx_where + fixP->fx_frag->fr_address; 19739 return base + 8; 19740 19741 case BFD_RELOC_ARM_PCREL_CALL: 19742 if (fixP->fx_addsy 19743 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 19744 && (!S_IS_EXTERNAL (fixP->fx_addsy)) 19745 && THUMB_IS_FUNC (fixP->fx_addsy) 19746 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) 19747 base = fixP->fx_where + fixP->fx_frag->fr_address; 19748 return base + 8; 19749 19750 case BFD_RELOC_ARM_PCREL_BRANCH: 19751 case BFD_RELOC_ARM_PCREL_JUMP: 19752 case BFD_RELOC_ARM_PLT32: 19753#ifdef TE_WINCE 19754 /* When handling fixups immediately, because we have already 19755 discovered the value of a symbol, or the address of the frag involved 19756 we must account for the offset by +8, as the OS loader will never see the reloc. 19757 see fixup_segment() in write.c 19758 The S_IS_EXTERNAL test handles the case of global symbols. 19759 Those need the calculated base, not just the pipe compensation the linker will need. */ 19760 if (fixP->fx_pcrel 19761 && fixP->fx_addsy != NULL 19762 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 19763 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) 19764 return base + 8; 19765 return base; 19766#else 19767 return base + 8; 19768#endif 19769 19770 19771 /* ARM mode loads relative to PC are also offset by +8. Unlike 19772 branches, the Windows CE loader *does* expect the relocation 19773 to take this into account. */ 19774 case BFD_RELOC_ARM_OFFSET_IMM: 19775 case BFD_RELOC_ARM_OFFSET_IMM8: 19776 case BFD_RELOC_ARM_HWLITERAL: 19777 case BFD_RELOC_ARM_LITERAL: 19778 case BFD_RELOC_ARM_CP_OFF_IMM: 19779 return base + 8; 19780 19781 19782 /* Other PC-relative relocations are un-offset. */ 19783 default: 19784 return base; 19785 } 19786} 19787 19788/* Under ELF we need to default _GLOBAL_OFFSET_TABLE. 19789 Otherwise we have no need to default values of symbols. */ 19790 19791symbolS * 19792md_undefined_symbol (char * name ATTRIBUTE_UNUSED) 19793{ 19794#ifdef OBJ_ELF 19795 if (name[0] == '_' && name[1] == 'G' 19796 && streq (name, GLOBAL_OFFSET_TABLE_NAME)) 19797 { 19798 if (!GOT_symbol) 19799 { 19800 if (symbol_find (name)) 19801 as_bad (_("GOT already in the symbol table")); 19802 19803 GOT_symbol = symbol_new (name, undefined_section, 19804 (valueT) 0, & zero_address_frag); 19805 } 19806 19807 return GOT_symbol; 19808 } 19809#endif 19810 19811 return NULL; 19812} 19813 19814/* Subroutine of md_apply_fix. Check to see if an immediate can be 19815 computed as two separate immediate values, added together. We 19816 already know that this value cannot be computed by just one ARM 19817 instruction. */ 19818 19819static unsigned int 19820validate_immediate_twopart (unsigned int val, 19821 unsigned int * highpart) 19822{ 19823 unsigned int a; 19824 unsigned int i; 19825 19826 for (i = 0; i < 32; i += 2) 19827 if (((a = rotate_left (val, i)) & 0xff) != 0) 19828 { 19829 if (a & 0xff00) 19830 { 19831 if (a & ~ 0xffff) 19832 continue; 19833 * highpart = (a >> 8) | ((i + 24) << 7); 19834 } 19835 else if (a & 0xff0000) 19836 { 19837 if (a & 0xff000000) 19838 continue; 19839 * highpart = (a >> 16) | ((i + 16) << 7); 19840 } 19841 else 19842 { 19843 gas_assert (a & 0xff000000); 19844 * highpart = (a >> 24) | ((i + 8) << 7); 19845 } 19846 19847 return (a & 0xff) | (i << 7); 19848 } 19849 19850 return FAIL; 19851} 19852 19853static int 19854validate_offset_imm (unsigned int val, int hwse) 19855{ 19856 if ((hwse && val > 255) || val > 4095) 19857 return FAIL; 19858 return val; 19859} 19860 19861/* Subroutine of md_apply_fix. Do those data_ops which can take a 19862 negative immediate constant by altering the instruction. A bit of 19863 a hack really. 19864 MOV <-> MVN 19865 AND <-> BIC 19866 ADC <-> SBC 19867 by inverting the second operand, and 19868 ADD <-> SUB 19869 CMP <-> CMN 19870 by negating the second operand. */ 19871 19872static int 19873negate_data_op (unsigned long * instruction, 19874 unsigned long value) 19875{ 19876 int op, new_inst; 19877 unsigned long negated, inverted; 19878 19879 negated = encode_arm_immediate (-value); 19880 inverted = encode_arm_immediate (~value); 19881 19882 op = (*instruction >> DATA_OP_SHIFT) & 0xf; 19883 switch (op) 19884 { 19885 /* First negates. */ 19886 case OPCODE_SUB: /* ADD <-> SUB */ 19887 new_inst = OPCODE_ADD; 19888 value = negated; 19889 break; 19890 19891 case OPCODE_ADD: 19892 new_inst = OPCODE_SUB; 19893 value = negated; 19894 break; 19895 19896 case OPCODE_CMP: /* CMP <-> CMN */ 19897 new_inst = OPCODE_CMN; 19898 value = negated; 19899 break; 19900 19901 case OPCODE_CMN: 19902 new_inst = OPCODE_CMP; 19903 value = negated; 19904 break; 19905 19906 /* Now Inverted ops. */ 19907 case OPCODE_MOV: /* MOV <-> MVN */ 19908 new_inst = OPCODE_MVN; 19909 value = inverted; 19910 break; 19911 19912 case OPCODE_MVN: 19913 new_inst = OPCODE_MOV; 19914 value = inverted; 19915 break; 19916 19917 case OPCODE_AND: /* AND <-> BIC */ 19918 new_inst = OPCODE_BIC; 19919 value = inverted; 19920 break; 19921 19922 case OPCODE_BIC: 19923 new_inst = OPCODE_AND; 19924 value = inverted; 19925 break; 19926 19927 case OPCODE_ADC: /* ADC <-> SBC */ 19928 new_inst = OPCODE_SBC; 19929 value = inverted; 19930 break; 19931 19932 case OPCODE_SBC: 19933 new_inst = OPCODE_ADC; 19934 value = inverted; 19935 break; 19936 19937 /* We cannot do anything. */ 19938 default: 19939 return FAIL; 19940 } 19941 19942 if (value == (unsigned) FAIL) 19943 return FAIL; 19944 19945 *instruction &= OPCODE_MASK; 19946 *instruction |= new_inst << DATA_OP_SHIFT; 19947 return value; 19948} 19949 19950/* Like negate_data_op, but for Thumb-2. */ 19951 19952static unsigned int 19953thumb32_negate_data_op (offsetT *instruction, unsigned int value) 19954{ 19955 int op, new_inst; 19956 int rd; 19957 unsigned int negated, inverted; 19958 19959 negated = encode_thumb32_immediate (-value); 19960 inverted = encode_thumb32_immediate (~value); 19961 19962 rd = (*instruction >> 8) & 0xf; 19963 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; 19964 switch (op) 19965 { 19966 /* ADD <-> SUB. Includes CMP <-> CMN. */ 19967 case T2_OPCODE_SUB: 19968 new_inst = T2_OPCODE_ADD; 19969 value = negated; 19970 break; 19971 19972 case T2_OPCODE_ADD: 19973 new_inst = T2_OPCODE_SUB; 19974 value = negated; 19975 break; 19976 19977 /* ORR <-> ORN. Includes MOV <-> MVN. */ 19978 case T2_OPCODE_ORR: 19979 new_inst = T2_OPCODE_ORN; 19980 value = inverted; 19981 break; 19982 19983 case T2_OPCODE_ORN: 19984 new_inst = T2_OPCODE_ORR; 19985 value = inverted; 19986 break; 19987 19988 /* AND <-> BIC. TST has no inverted equivalent. */ 19989 case T2_OPCODE_AND: 19990 new_inst = T2_OPCODE_BIC; 19991 if (rd == 15) 19992 value = FAIL; 19993 else 19994 value = inverted; 19995 break; 19996 19997 case T2_OPCODE_BIC: 19998 new_inst = T2_OPCODE_AND; 19999 value = inverted; 20000 break; 20001 20002 /* ADC <-> SBC */ 20003 case T2_OPCODE_ADC: 20004 new_inst = T2_OPCODE_SBC; 20005 value = inverted; 20006 break; 20007 20008 case T2_OPCODE_SBC: 20009 new_inst = T2_OPCODE_ADC; 20010 value = inverted; 20011 break; 20012 20013 /* We cannot do anything. */ 20014 default: 20015 return FAIL; 20016 } 20017 20018 if (value == (unsigned int)FAIL) 20019 return FAIL; 20020 20021 *instruction &= T2_OPCODE_MASK; 20022 *instruction |= new_inst << T2_DATA_OP_SHIFT; 20023 return value; 20024} 20025 20026/* Read a 32-bit thumb instruction from buf. */ 20027static unsigned long 20028get_thumb32_insn (char * buf) 20029{ 20030 unsigned long insn; 20031 insn = md_chars_to_number (buf, THUMB_SIZE) << 16; 20032 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 20033 20034 return insn; 20035} 20036 20037 20038/* We usually want to set the low bit on the address of thumb function 20039 symbols. In particular .word foo - . should have the low bit set. 20040 Generic code tries to fold the difference of two symbols to 20041 a constant. Prevent this and force a relocation when the first symbols 20042 is a thumb function. */ 20043 20044bfd_boolean 20045arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) 20046{ 20047 if (op == O_subtract 20048 && l->X_op == O_symbol 20049 && r->X_op == O_symbol 20050 && THUMB_IS_FUNC (l->X_add_symbol)) 20051 { 20052 l->X_op = O_subtract; 20053 l->X_op_symbol = r->X_add_symbol; 20054 l->X_add_number -= r->X_add_number; 20055 return TRUE; 20056 } 20057 20058 /* Process as normal. */ 20059 return FALSE; 20060} 20061 20062/* Encode Thumb2 unconditional branches and calls. The encoding 20063 for the 2 are identical for the immediate values. */ 20064 20065static void 20066encode_thumb2_b_bl_offset (char * buf, offsetT value) 20067{ 20068#define T2I1I2MASK ((1 << 13) | (1 << 11)) 20069 offsetT newval; 20070 offsetT newval2; 20071 addressT S, I1, I2, lo, hi; 20072 20073 S = (value >> 24) & 0x01; 20074 I1 = (value >> 23) & 0x01; 20075 I2 = (value >> 22) & 0x01; 20076 hi = (value >> 12) & 0x3ff; 20077 lo = (value >> 1) & 0x7ff; 20078 newval = md_chars_to_number (buf, THUMB_SIZE); 20079 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 20080 newval |= (S << 10) | hi; 20081 newval2 &= ~T2I1I2MASK; 20082 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; 20083 md_number_to_chars (buf, newval, THUMB_SIZE); 20084 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 20085} 20086 20087void 20088md_apply_fix (fixS * fixP, 20089 valueT * valP, 20090 segT seg) 20091{ 20092 offsetT value = * valP; 20093 offsetT newval; 20094 unsigned int newimm; 20095 unsigned long temp; 20096 int sign; 20097 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; 20098 20099 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); 20100 20101 /* Note whether this will delete the relocation. */ 20102 20103 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 20104 fixP->fx_done = 1; 20105 20106 /* On a 64-bit host, silently truncate 'value' to 32 bits for 20107 consistency with the behaviour on 32-bit hosts. Remember value 20108 for emit_reloc. */ 20109 value &= 0xffffffff; 20110 value ^= 0x80000000; 20111 value -= 0x80000000; 20112 20113 *valP = value; 20114 fixP->fx_addnumber = value; 20115 20116 /* Same treatment for fixP->fx_offset. */ 20117 fixP->fx_offset &= 0xffffffff; 20118 fixP->fx_offset ^= 0x80000000; 20119 fixP->fx_offset -= 0x80000000; 20120 20121 switch (fixP->fx_r_type) 20122 { 20123 case BFD_RELOC_NONE: 20124 /* This will need to go in the object file. */ 20125 fixP->fx_done = 0; 20126 break; 20127 20128 case BFD_RELOC_ARM_IMMEDIATE: 20129 /* We claim that this fixup has been processed here, 20130 even if in fact we generate an error because we do 20131 not have a reloc for it, so tc_gen_reloc will reject it. */ 20132 fixP->fx_done = 1; 20133 20134 if (fixP->fx_addsy) 20135 { 20136 const char *msg = 0; 20137 20138 if (! S_IS_DEFINED (fixP->fx_addsy)) 20139 msg = _("undefined symbol %s used as an immediate value"); 20140 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) 20141 msg = _("symbol %s is in a different section"); 20142 else if (S_IS_WEAK (fixP->fx_addsy)) 20143 msg = _("symbol %s is weak and may be overridden later"); 20144 20145 if (msg) 20146 { 20147 as_bad_where (fixP->fx_file, fixP->fx_line, 20148 msg, S_GET_NAME (fixP->fx_addsy)); 20149 break; 20150 } 20151 } 20152 20153 newimm = encode_arm_immediate (value); 20154 temp = md_chars_to_number (buf, INSN_SIZE); 20155 20156 /* If the instruction will fail, see if we can fix things up by 20157 changing the opcode. */ 20158 if (newimm == (unsigned int) FAIL 20159 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) 20160 { 20161 as_bad_where (fixP->fx_file, fixP->fx_line, 20162 _("invalid constant (%lx) after fixup"), 20163 (unsigned long) value); 20164 break; 20165 } 20166 20167 newimm |= (temp & 0xfffff000); 20168 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); 20169 break; 20170 20171 case BFD_RELOC_ARM_ADRL_IMMEDIATE: 20172 { 20173 unsigned int highpart = 0; 20174 unsigned int newinsn = 0xe1a00000; /* nop. */ 20175 20176 if (fixP->fx_addsy) 20177 { 20178 const char *msg = 0; 20179 20180 if (! S_IS_DEFINED (fixP->fx_addsy)) 20181 msg = _("undefined symbol %s used as an immediate value"); 20182 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) 20183 msg = _("symbol %s is in a different section"); 20184 else if (S_IS_WEAK (fixP->fx_addsy)) 20185 msg = _("symbol %s is weak and may be overridden later"); 20186 20187 if (msg) 20188 { 20189 as_bad_where (fixP->fx_file, fixP->fx_line, 20190 msg, S_GET_NAME (fixP->fx_addsy)); 20191 break; 20192 } 20193 } 20194 20195 newimm = encode_arm_immediate (value); 20196 temp = md_chars_to_number (buf, INSN_SIZE); 20197 20198 /* If the instruction will fail, see if we can fix things up by 20199 changing the opcode. */ 20200 if (newimm == (unsigned int) FAIL 20201 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) 20202 { 20203 /* No ? OK - try using two ADD instructions to generate 20204 the value. */ 20205 newimm = validate_immediate_twopart (value, & highpart); 20206 20207 /* Yes - then make sure that the second instruction is 20208 also an add. */ 20209 if (newimm != (unsigned int) FAIL) 20210 newinsn = temp; 20211 /* Still No ? Try using a negated value. */ 20212 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) 20213 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; 20214 /* Otherwise - give up. */ 20215 else 20216 { 20217 as_bad_where (fixP->fx_file, fixP->fx_line, 20218 _("unable to compute ADRL instructions for PC offset of 0x%lx"), 20219 (long) value); 20220 break; 20221 } 20222 20223 /* Replace the first operand in the 2nd instruction (which 20224 is the PC) with the destination register. We have 20225 already added in the PC in the first instruction and we 20226 do not want to do it again. */ 20227 newinsn &= ~ 0xf0000; 20228 newinsn |= ((newinsn & 0x0f000) << 4); 20229 } 20230 20231 newimm |= (temp & 0xfffff000); 20232 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); 20233 20234 highpart |= (newinsn & 0xfffff000); 20235 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); 20236 } 20237 break; 20238 20239 case BFD_RELOC_ARM_OFFSET_IMM: 20240 if (!fixP->fx_done && seg->use_rela_p) 20241 value = 0; 20242 20243 case BFD_RELOC_ARM_LITERAL: 20244 sign = value >= 0; 20245 20246 if (value < 0) 20247 value = - value; 20248 20249 if (validate_offset_imm (value, 0) == FAIL) 20250 { 20251 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) 20252 as_bad_where (fixP->fx_file, fixP->fx_line, 20253 _("invalid literal constant: pool needs to be closer")); 20254 else 20255 as_bad_where (fixP->fx_file, fixP->fx_line, 20256 _("bad immediate value for offset (%ld)"), 20257 (long) value); 20258 break; 20259 } 20260 20261 newval = md_chars_to_number (buf, INSN_SIZE); 20262 newval &= 0xff7ff000; 20263 newval |= value | (sign ? INDEX_UP : 0); 20264 md_number_to_chars (buf, newval, INSN_SIZE); 20265 break; 20266 20267 case BFD_RELOC_ARM_OFFSET_IMM8: 20268 case BFD_RELOC_ARM_HWLITERAL: 20269 sign = value >= 0; 20270 20271 if (value < 0) 20272 value = - value; 20273 20274 if (validate_offset_imm (value, 1) == FAIL) 20275 { 20276 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) 20277 as_bad_where (fixP->fx_file, fixP->fx_line, 20278 _("invalid literal constant: pool needs to be closer")); 20279 else 20280 as_bad (_("bad immediate value for 8-bit offset (%ld)"), 20281 (long) value); 20282 break; 20283 } 20284 20285 newval = md_chars_to_number (buf, INSN_SIZE); 20286 newval &= 0xff7ff0f0; 20287 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); 20288 md_number_to_chars (buf, newval, INSN_SIZE); 20289 break; 20290 20291 case BFD_RELOC_ARM_T32_OFFSET_U8: 20292 if (value < 0 || value > 1020 || value % 4 != 0) 20293 as_bad_where (fixP->fx_file, fixP->fx_line, 20294 _("bad immediate value for offset (%ld)"), (long) value); 20295 value /= 4; 20296 20297 newval = md_chars_to_number (buf+2, THUMB_SIZE); 20298 newval |= value; 20299 md_number_to_chars (buf+2, newval, THUMB_SIZE); 20300 break; 20301 20302 case BFD_RELOC_ARM_T32_OFFSET_IMM: 20303 /* This is a complicated relocation used for all varieties of Thumb32 20304 load/store instruction with immediate offset: 20305 20306 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, 20307 *4, optional writeback(W) 20308 (doubleword load/store) 20309 20310 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel 20311 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit 20312 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) 20313 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit 20314 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit 20315 20316 Uppercase letters indicate bits that are already encoded at 20317 this point. Lowercase letters are our problem. For the 20318 second block of instructions, the secondary opcode nybble 20319 (bits 8..11) is present, and bit 23 is zero, even if this is 20320 a PC-relative operation. */ 20321 newval = md_chars_to_number (buf, THUMB_SIZE); 20322 newval <<= 16; 20323 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); 20324 20325 if ((newval & 0xf0000000) == 0xe0000000) 20326 { 20327 /* Doubleword load/store: 8-bit offset, scaled by 4. */ 20328 if (value >= 0) 20329 newval |= (1 << 23); 20330 else 20331 value = -value; 20332 if (value % 4 != 0) 20333 { 20334 as_bad_where (fixP->fx_file, fixP->fx_line, 20335 _("offset not a multiple of 4")); 20336 break; 20337 } 20338 value /= 4; 20339 if (value > 0xff) 20340 { 20341 as_bad_where (fixP->fx_file, fixP->fx_line, 20342 _("offset out of range")); 20343 break; 20344 } 20345 newval &= ~0xff; 20346 } 20347 else if ((newval & 0x000f0000) == 0x000f0000) 20348 { 20349 /* PC-relative, 12-bit offset. */ 20350 if (value >= 0) 20351 newval |= (1 << 23); 20352 else 20353 value = -value; 20354 if (value > 0xfff) 20355 { 20356 as_bad_where (fixP->fx_file, fixP->fx_line, 20357 _("offset out of range")); 20358 break; 20359 } 20360 newval &= ~0xfff; 20361 } 20362 else if ((newval & 0x00000100) == 0x00000100) 20363 { 20364 /* Writeback: 8-bit, +/- offset. */ 20365 if (value >= 0) 20366 newval |= (1 << 9); 20367 else 20368 value = -value; 20369 if (value > 0xff) 20370 { 20371 as_bad_where (fixP->fx_file, fixP->fx_line, 20372 _("offset out of range")); 20373 break; 20374 } 20375 newval &= ~0xff; 20376 } 20377 else if ((newval & 0x00000f00) == 0x00000e00) 20378 { 20379 /* T-instruction: positive 8-bit offset. */ 20380 if (value < 0 || value > 0xff) 20381 { 20382 as_bad_where (fixP->fx_file, fixP->fx_line, 20383 _("offset out of range")); 20384 break; 20385 } 20386 newval &= ~0xff; 20387 newval |= value; 20388 } 20389 else 20390 { 20391 /* Positive 12-bit or negative 8-bit offset. */ 20392 int limit; 20393 if (value >= 0) 20394 { 20395 newval |= (1 << 23); 20396 limit = 0xfff; 20397 } 20398 else 20399 { 20400 value = -value; 20401 limit = 0xff; 20402 } 20403 if (value > limit) 20404 { 20405 as_bad_where (fixP->fx_file, fixP->fx_line, 20406 _("offset out of range")); 20407 break; 20408 } 20409 newval &= ~limit; 20410 } 20411 20412 newval |= value; 20413 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); 20414 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); 20415 break; 20416 20417 case BFD_RELOC_ARM_SHIFT_IMM: 20418 newval = md_chars_to_number (buf, INSN_SIZE); 20419 if (((unsigned long) value) > 32 20420 || (value == 32 20421 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) 20422 { 20423 as_bad_where (fixP->fx_file, fixP->fx_line, 20424 _("shift expression is too large")); 20425 break; 20426 } 20427 20428 if (value == 0) 20429 /* Shifts of zero must be done as lsl. */ 20430 newval &= ~0x60; 20431 else if (value == 32) 20432 value = 0; 20433 newval &= 0xfffff07f; 20434 newval |= (value & 0x1f) << 7; 20435 md_number_to_chars (buf, newval, INSN_SIZE); 20436 break; 20437 20438 case BFD_RELOC_ARM_T32_IMMEDIATE: 20439 case BFD_RELOC_ARM_T32_ADD_IMM: 20440 case BFD_RELOC_ARM_T32_IMM12: 20441 case BFD_RELOC_ARM_T32_ADD_PC12: 20442 /* We claim that this fixup has been processed here, 20443 even if in fact we generate an error because we do 20444 not have a reloc for it, so tc_gen_reloc will reject it. */ 20445 fixP->fx_done = 1; 20446 20447 if (fixP->fx_addsy 20448 && ! S_IS_DEFINED (fixP->fx_addsy)) 20449 { 20450 as_bad_where (fixP->fx_file, fixP->fx_line, 20451 _("undefined symbol %s used as an immediate value"), 20452 S_GET_NAME (fixP->fx_addsy)); 20453 break; 20454 } 20455 20456 newval = md_chars_to_number (buf, THUMB_SIZE); 20457 newval <<= 16; 20458 newval |= md_chars_to_number (buf+2, THUMB_SIZE); 20459 20460 newimm = FAIL; 20461 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE 20462 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) 20463 { 20464 newimm = encode_thumb32_immediate (value); 20465 if (newimm == (unsigned int) FAIL) 20466 newimm = thumb32_negate_data_op (&newval, value); 20467 } 20468 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE 20469 && newimm == (unsigned int) FAIL) 20470 { 20471 /* Turn add/sum into addw/subw. */ 20472 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) 20473 newval = (newval & 0xfeffffff) | 0x02000000; 20474 /* No flat 12-bit imm encoding for addsw/subsw. */ 20475 if ((newval & 0x00100000) == 0) 20476 { 20477 /* 12 bit immediate for addw/subw. */ 20478 if (value < 0) 20479 { 20480 value = -value; 20481 newval ^= 0x00a00000; 20482 } 20483 if (value > 0xfff) 20484 newimm = (unsigned int) FAIL; 20485 else 20486 newimm = value; 20487 } 20488 } 20489 20490 if (newimm == (unsigned int)FAIL) 20491 { 20492 as_bad_where (fixP->fx_file, fixP->fx_line, 20493 _("invalid constant (%lx) after fixup"), 20494 (unsigned long) value); 20495 break; 20496 } 20497 20498 newval |= (newimm & 0x800) << 15; 20499 newval |= (newimm & 0x700) << 4; 20500 newval |= (newimm & 0x0ff); 20501 20502 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); 20503 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); 20504 break; 20505 20506 case BFD_RELOC_ARM_SMC: 20507 if (((unsigned long) value) > 0xffff) 20508 as_bad_where (fixP->fx_file, fixP->fx_line, 20509 _("invalid smc expression")); 20510 newval = md_chars_to_number (buf, INSN_SIZE); 20511 newval |= (value & 0xf) | ((value & 0xfff0) << 4); 20512 md_number_to_chars (buf, newval, INSN_SIZE); 20513 break; 20514 20515 case BFD_RELOC_ARM_HVC: 20516 if (((unsigned long) value) > 0xffff) 20517 as_bad_where (fixP->fx_file, fixP->fx_line, 20518 _("invalid hvc expression")); 20519 newval = md_chars_to_number (buf, INSN_SIZE); 20520 newval |= (value & 0xf) | ((value & 0xfff0) << 4); 20521 md_number_to_chars (buf, newval, INSN_SIZE); 20522 break; 20523 20524 case BFD_RELOC_ARM_SWI: 20525 if (fixP->tc_fix_data != 0) 20526 { 20527 if (((unsigned long) value) > 0xff) 20528 as_bad_where (fixP->fx_file, fixP->fx_line, 20529 _("invalid swi expression")); 20530 newval = md_chars_to_number (buf, THUMB_SIZE); 20531 newval |= value; 20532 md_number_to_chars (buf, newval, THUMB_SIZE); 20533 } 20534 else 20535 { 20536 if (((unsigned long) value) > 0x00ffffff) 20537 as_bad_where (fixP->fx_file, fixP->fx_line, 20538 _("invalid swi expression")); 20539 newval = md_chars_to_number (buf, INSN_SIZE); 20540 newval |= value; 20541 md_number_to_chars (buf, newval, INSN_SIZE); 20542 } 20543 break; 20544 20545 case BFD_RELOC_ARM_MULTI: 20546 if (((unsigned long) value) > 0xffff) 20547 as_bad_where (fixP->fx_file, fixP->fx_line, 20548 _("invalid expression in load/store multiple")); 20549 newval = value | md_chars_to_number (buf, INSN_SIZE); 20550 md_number_to_chars (buf, newval, INSN_SIZE); 20551 break; 20552 20553#ifdef OBJ_ELF 20554 case BFD_RELOC_ARM_PCREL_CALL: 20555 20556 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) 20557 && fixP->fx_addsy 20558 && !S_IS_EXTERNAL (fixP->fx_addsy) 20559 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 20560 && THUMB_IS_FUNC (fixP->fx_addsy)) 20561 /* Flip the bl to blx. This is a simple flip 20562 bit here because we generate PCREL_CALL for 20563 unconditional bls. */ 20564 { 20565 newval = md_chars_to_number (buf, INSN_SIZE); 20566 newval = newval | 0x10000000; 20567 md_number_to_chars (buf, newval, INSN_SIZE); 20568 temp = 1; 20569 fixP->fx_done = 1; 20570 } 20571 else 20572 temp = 3; 20573 goto arm_branch_common; 20574 20575 case BFD_RELOC_ARM_PCREL_JUMP: 20576 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) 20577 && fixP->fx_addsy 20578 && !S_IS_EXTERNAL (fixP->fx_addsy) 20579 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 20580 && THUMB_IS_FUNC (fixP->fx_addsy)) 20581 { 20582 /* This would map to a bl<cond>, b<cond>, 20583 b<always> to a Thumb function. We 20584 need to force a relocation for this particular 20585 case. */ 20586 newval = md_chars_to_number (buf, INSN_SIZE); 20587 fixP->fx_done = 0; 20588 } 20589 20590 case BFD_RELOC_ARM_PLT32: 20591#endif 20592 case BFD_RELOC_ARM_PCREL_BRANCH: 20593 temp = 3; 20594 goto arm_branch_common; 20595 20596 case BFD_RELOC_ARM_PCREL_BLX: 20597 20598 temp = 1; 20599 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) 20600 && fixP->fx_addsy 20601 && !S_IS_EXTERNAL (fixP->fx_addsy) 20602 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 20603 && ARM_IS_FUNC (fixP->fx_addsy)) 20604 { 20605 /* Flip the blx to a bl and warn. */ 20606 const char *name = S_GET_NAME (fixP->fx_addsy); 20607 newval = 0xeb000000; 20608 as_warn_where (fixP->fx_file, fixP->fx_line, 20609 _("blx to '%s' an ARM ISA state function changed to bl"), 20610 name); 20611 md_number_to_chars (buf, newval, INSN_SIZE); 20612 temp = 3; 20613 fixP->fx_done = 1; 20614 } 20615 20616#ifdef OBJ_ELF 20617 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 20618 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; 20619#endif 20620 20621 arm_branch_common: 20622 /* We are going to store value (shifted right by two) in the 20623 instruction, in a 24 bit, signed field. Bits 26 through 32 either 20624 all clear or all set and bit 0 must be clear. For B/BL bit 1 must 20625 also be be clear. */ 20626 if (value & temp) 20627 as_bad_where (fixP->fx_file, fixP->fx_line, 20628 _("misaligned branch destination")); 20629 if ((value & (offsetT)0xfe000000) != (offsetT)0 20630 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) 20631 as_bad_where (fixP->fx_file, fixP->fx_line, 20632 _("branch out of range")); 20633 20634 if (fixP->fx_done || !seg->use_rela_p) 20635 { 20636 newval = md_chars_to_number (buf, INSN_SIZE); 20637 newval |= (value >> 2) & 0x00ffffff; 20638 /* Set the H bit on BLX instructions. */ 20639 if (temp == 1) 20640 { 20641 if (value & 2) 20642 newval |= 0x01000000; 20643 else 20644 newval &= ~0x01000000; 20645 } 20646 md_number_to_chars (buf, newval, INSN_SIZE); 20647 } 20648 break; 20649 20650 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ 20651 /* CBZ can only branch forward. */ 20652 20653 /* Attempts to use CBZ to branch to the next instruction 20654 (which, strictly speaking, are prohibited) will be turned into 20655 no-ops. 20656 20657 FIXME: It may be better to remove the instruction completely and 20658 perform relaxation. */ 20659 if (value == -2) 20660 { 20661 newval = md_chars_to_number (buf, THUMB_SIZE); 20662 newval = 0xbf00; /* NOP encoding T1 */ 20663 md_number_to_chars (buf, newval, THUMB_SIZE); 20664 } 20665 else 20666 { 20667 if (value & ~0x7e) 20668 as_bad_where (fixP->fx_file, fixP->fx_line, 20669 _("branch out of range")); 20670 20671 if (fixP->fx_done || !seg->use_rela_p) 20672 { 20673 newval = md_chars_to_number (buf, THUMB_SIZE); 20674 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); 20675 md_number_to_chars (buf, newval, THUMB_SIZE); 20676 } 20677 } 20678 break; 20679 20680 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ 20681 if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) 20682 as_bad_where (fixP->fx_file, fixP->fx_line, 20683 _("branch out of range")); 20684 20685 if (fixP->fx_done || !seg->use_rela_p) 20686 { 20687 newval = md_chars_to_number (buf, THUMB_SIZE); 20688 newval |= (value & 0x1ff) >> 1; 20689 md_number_to_chars (buf, newval, THUMB_SIZE); 20690 } 20691 break; 20692 20693 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ 20694 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) 20695 as_bad_where (fixP->fx_file, fixP->fx_line, 20696 _("branch out of range")); 20697 20698 if (fixP->fx_done || !seg->use_rela_p) 20699 { 20700 newval = md_chars_to_number (buf, THUMB_SIZE); 20701 newval |= (value & 0xfff) >> 1; 20702 md_number_to_chars (buf, newval, THUMB_SIZE); 20703 } 20704 break; 20705 20706 case BFD_RELOC_THUMB_PCREL_BRANCH20: 20707 if (fixP->fx_addsy 20708 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 20709 && !S_IS_EXTERNAL (fixP->fx_addsy) 20710 && S_IS_DEFINED (fixP->fx_addsy) 20711 && ARM_IS_FUNC (fixP->fx_addsy) 20712 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) 20713 { 20714 /* Force a relocation for a branch 20 bits wide. */ 20715 fixP->fx_done = 0; 20716 } 20717 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) 20718 as_bad_where (fixP->fx_file, fixP->fx_line, 20719 _("conditional branch out of range")); 20720 20721 if (fixP->fx_done || !seg->use_rela_p) 20722 { 20723 offsetT newval2; 20724 addressT S, J1, J2, lo, hi; 20725 20726 S = (value & 0x00100000) >> 20; 20727 J2 = (value & 0x00080000) >> 19; 20728 J1 = (value & 0x00040000) >> 18; 20729 hi = (value & 0x0003f000) >> 12; 20730 lo = (value & 0x00000ffe) >> 1; 20731 20732 newval = md_chars_to_number (buf, THUMB_SIZE); 20733 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 20734 newval |= (S << 10) | hi; 20735 newval2 |= (J1 << 13) | (J2 << 11) | lo; 20736 md_number_to_chars (buf, newval, THUMB_SIZE); 20737 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 20738 } 20739 break; 20740 20741 case BFD_RELOC_THUMB_PCREL_BLX: 20742 20743 /* If there is a blx from a thumb state function to 20744 another thumb function flip this to a bl and warn 20745 about it. */ 20746 20747 if (fixP->fx_addsy 20748 && S_IS_DEFINED (fixP->fx_addsy) 20749 && !S_IS_EXTERNAL (fixP->fx_addsy) 20750 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 20751 && THUMB_IS_FUNC (fixP->fx_addsy)) 20752 { 20753 const char *name = S_GET_NAME (fixP->fx_addsy); 20754 as_warn_where (fixP->fx_file, fixP->fx_line, 20755 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), 20756 name); 20757 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 20758 newval = newval | 0x1000; 20759 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); 20760 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; 20761 fixP->fx_done = 1; 20762 } 20763 20764 20765 goto thumb_bl_common; 20766 20767 case BFD_RELOC_THUMB_PCREL_BRANCH23: 20768 20769 /* A bl from Thumb state ISA to an internal ARM state function 20770 is converted to a blx. */ 20771 if (fixP->fx_addsy 20772 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 20773 && !S_IS_EXTERNAL (fixP->fx_addsy) 20774 && S_IS_DEFINED (fixP->fx_addsy) 20775 && ARM_IS_FUNC (fixP->fx_addsy) 20776 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) 20777 { 20778 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 20779 newval = newval & ~0x1000; 20780 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); 20781 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; 20782 fixP->fx_done = 1; 20783 } 20784 20785 thumb_bl_common: 20786 20787#ifdef OBJ_ELF 20788 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 && 20789 fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) 20790 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; 20791#endif 20792 20793 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) 20794 /* For a BLX instruction, make sure that the relocation is rounded up 20795 to a word boundary. This follows the semantics of the instruction 20796 which specifies that bit 1 of the target address will come from bit 20797 1 of the base address. */ 20798 value = (value + 1) & ~ 1; 20799 20800 20801 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) 20802 { 20803 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))) 20804 { 20805 as_bad_where (fixP->fx_file, fixP->fx_line, 20806 _("branch out of range")); 20807 } 20808 else if ((value & ~0x1ffffff) 20809 && ((value & ~0x1ffffff) != ~0x1ffffff)) 20810 { 20811 as_bad_where (fixP->fx_file, fixP->fx_line, 20812 _("Thumb2 branch out of range")); 20813 } 20814 } 20815 20816 if (fixP->fx_done || !seg->use_rela_p) 20817 encode_thumb2_b_bl_offset (buf, value); 20818 20819 break; 20820 20821 case BFD_RELOC_THUMB_PCREL_BRANCH25: 20822 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) 20823 as_bad_where (fixP->fx_file, fixP->fx_line, 20824 _("branch out of range")); 20825 20826 if (fixP->fx_done || !seg->use_rela_p) 20827 encode_thumb2_b_bl_offset (buf, value); 20828 20829 break; 20830 20831 case BFD_RELOC_8: 20832 if (fixP->fx_done || !seg->use_rela_p) 20833 md_number_to_chars (buf, value, 1); 20834 break; 20835 20836 case BFD_RELOC_16: 20837 if (fixP->fx_done || !seg->use_rela_p) 20838 md_number_to_chars (buf, value, 2); 20839 break; 20840 20841#ifdef OBJ_ELF 20842 case BFD_RELOC_ARM_TLS_GD32: 20843 case BFD_RELOC_ARM_TLS_LE32: 20844 case BFD_RELOC_ARM_TLS_IE32: 20845 case BFD_RELOC_ARM_TLS_LDM32: 20846 case BFD_RELOC_ARM_TLS_LDO32: 20847 S_SET_THREAD_LOCAL (fixP->fx_addsy); 20848 /* fall through */ 20849 20850 case BFD_RELOC_ARM_GOT32: 20851 case BFD_RELOC_ARM_GOTOFF: 20852 if (fixP->fx_done || !seg->use_rela_p) 20853 md_number_to_chars (buf, 0, 4); 20854 break; 20855 20856 case BFD_RELOC_ARM_GOT_PREL: 20857 if (fixP->fx_done || !seg->use_rela_p) 20858 md_number_to_chars (buf, value, 4); 20859 break; 20860 20861 case BFD_RELOC_ARM_TARGET2: 20862 /* TARGET2 is not partial-inplace, so we need to write the 20863 addend here for REL targets, because it won't be written out 20864 during reloc processing later. */ 20865 if (fixP->fx_done || !seg->use_rela_p) 20866 md_number_to_chars (buf, fixP->fx_offset, 4); 20867 break; 20868#endif 20869 20870 case BFD_RELOC_RVA: 20871 case BFD_RELOC_32: 20872 case BFD_RELOC_ARM_TARGET1: 20873 case BFD_RELOC_ARM_ROSEGREL32: 20874 case BFD_RELOC_ARM_SBREL32: 20875 case BFD_RELOC_32_PCREL: 20876#ifdef TE_PE 20877 case BFD_RELOC_32_SECREL: 20878#endif 20879 if (fixP->fx_done || !seg->use_rela_p) 20880#ifdef TE_WINCE 20881 /* For WinCE we only do this for pcrel fixups. */ 20882 if (fixP->fx_done || fixP->fx_pcrel) 20883#endif 20884 md_number_to_chars (buf, value, 4); 20885 break; 20886 20887#ifdef OBJ_ELF 20888 case BFD_RELOC_ARM_PREL31: 20889 if (fixP->fx_done || !seg->use_rela_p) 20890 { 20891 newval = md_chars_to_number (buf, 4) & 0x80000000; 20892 if ((value ^ (value >> 1)) & 0x40000000) 20893 { 20894 as_bad_where (fixP->fx_file, fixP->fx_line, 20895 _("rel31 relocation overflow")); 20896 } 20897 newval |= value & 0x7fffffff; 20898 md_number_to_chars (buf, newval, 4); 20899 } 20900 break; 20901#endif 20902 20903 case BFD_RELOC_ARM_CP_OFF_IMM: 20904 case BFD_RELOC_ARM_T32_CP_OFF_IMM: 20905 if (value < -1023 || value > 1023 || (value & 3)) 20906 as_bad_where (fixP->fx_file, fixP->fx_line, 20907 _("co-processor offset out of range")); 20908 cp_off_common: 20909 sign = value >= 0; 20910 if (value < 0) 20911 value = -value; 20912 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM 20913 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) 20914 newval = md_chars_to_number (buf, INSN_SIZE); 20915 else 20916 newval = get_thumb32_insn (buf); 20917 newval &= 0xff7fff00; 20918 newval |= (value >> 2) | (sign ? INDEX_UP : 0); 20919 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM 20920 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) 20921 md_number_to_chars (buf, newval, INSN_SIZE); 20922 else 20923 put_thumb32_insn (buf, newval); 20924 break; 20925 20926 case BFD_RELOC_ARM_CP_OFF_IMM_S2: 20927 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: 20928 if (value < -255 || value > 255) 20929 as_bad_where (fixP->fx_file, fixP->fx_line, 20930 _("co-processor offset out of range")); 20931 value *= 4; 20932 goto cp_off_common; 20933 20934 case BFD_RELOC_ARM_THUMB_OFFSET: 20935 newval = md_chars_to_number (buf, THUMB_SIZE); 20936 /* Exactly what ranges, and where the offset is inserted depends 20937 on the type of instruction, we can establish this from the 20938 top 4 bits. */ 20939 switch (newval >> 12) 20940 { 20941 case 4: /* PC load. */ 20942 /* Thumb PC loads are somewhat odd, bit 1 of the PC is 20943 forced to zero for these loads; md_pcrel_from has already 20944 compensated for this. */ 20945 if (value & 3) 20946 as_bad_where (fixP->fx_file, fixP->fx_line, 20947 _("invalid offset, target not word aligned (0x%08lX)"), 20948 (((unsigned long) fixP->fx_frag->fr_address 20949 + (unsigned long) fixP->fx_where) & ~3) 20950 + (unsigned long) value); 20951 20952 if (value & ~0x3fc) 20953 as_bad_where (fixP->fx_file, fixP->fx_line, 20954 _("invalid offset, value too big (0x%08lX)"), 20955 (long) value); 20956 20957 newval |= value >> 2; 20958 break; 20959 20960 case 9: /* SP load/store. */ 20961 if (value & ~0x3fc) 20962 as_bad_where (fixP->fx_file, fixP->fx_line, 20963 _("invalid offset, value too big (0x%08lX)"), 20964 (long) value); 20965 newval |= value >> 2; 20966 break; 20967 20968 case 6: /* Word load/store. */ 20969 if (value & ~0x7c) 20970 as_bad_where (fixP->fx_file, fixP->fx_line, 20971 _("invalid offset, value too big (0x%08lX)"), 20972 (long) value); 20973 newval |= value << 4; /* 6 - 2. */ 20974 break; 20975 20976 case 7: /* Byte load/store. */ 20977 if (value & ~0x1f) 20978 as_bad_where (fixP->fx_file, fixP->fx_line, 20979 _("invalid offset, value too big (0x%08lX)"), 20980 (long) value); 20981 newval |= value << 6; 20982 break; 20983 20984 case 8: /* Halfword load/store. */ 20985 if (value & ~0x3e) 20986 as_bad_where (fixP->fx_file, fixP->fx_line, 20987 _("invalid offset, value too big (0x%08lX)"), 20988 (long) value); 20989 newval |= value << 5; /* 6 - 1. */ 20990 break; 20991 20992 default: 20993 as_bad_where (fixP->fx_file, fixP->fx_line, 20994 "Unable to process relocation for thumb opcode: %lx", 20995 (unsigned long) newval); 20996 break; 20997 } 20998 md_number_to_chars (buf, newval, THUMB_SIZE); 20999 break; 21000 21001 case BFD_RELOC_ARM_THUMB_ADD: 21002 /* This is a complicated relocation, since we use it for all of 21003 the following immediate relocations: 21004 21005 3bit ADD/SUB 21006 8bit ADD/SUB 21007 9bit ADD/SUB SP word-aligned 21008 10bit ADD PC/SP word-aligned 21009 21010 The type of instruction being processed is encoded in the 21011 instruction field: 21012 21013 0x8000 SUB 21014 0x00F0 Rd 21015 0x000F Rs 21016 */ 21017 newval = md_chars_to_number (buf, THUMB_SIZE); 21018 { 21019 int rd = (newval >> 4) & 0xf; 21020 int rs = newval & 0xf; 21021 int subtract = !!(newval & 0x8000); 21022 21023 /* Check for HI regs, only very restricted cases allowed: 21024 Adjusting SP, and using PC or SP to get an address. */ 21025 if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) 21026 || (rs > 7 && rs != REG_SP && rs != REG_PC)) 21027 as_bad_where (fixP->fx_file, fixP->fx_line, 21028 _("invalid Hi register with immediate")); 21029 21030 /* If value is negative, choose the opposite instruction. */ 21031 if (value < 0) 21032 { 21033 value = -value; 21034 subtract = !subtract; 21035 if (value < 0) 21036 as_bad_where (fixP->fx_file, fixP->fx_line, 21037 _("immediate value out of range")); 21038 } 21039 21040 if (rd == REG_SP) 21041 { 21042 if (value & ~0x1fc) 21043 as_bad_where (fixP->fx_file, fixP->fx_line, 21044 _("invalid immediate for stack address calculation")); 21045 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; 21046 newval |= value >> 2; 21047 } 21048 else if (rs == REG_PC || rs == REG_SP) 21049 { 21050 if (subtract || value & ~0x3fc) 21051 as_bad_where (fixP->fx_file, fixP->fx_line, 21052 _("invalid immediate for address calculation (value = 0x%08lX)"), 21053 (unsigned long) value); 21054 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); 21055 newval |= rd << 8; 21056 newval |= value >> 2; 21057 } 21058 else if (rs == rd) 21059 { 21060 if (value & ~0xff) 21061 as_bad_where (fixP->fx_file, fixP->fx_line, 21062 _("immediate value out of range")); 21063 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; 21064 newval |= (rd << 8) | value; 21065 } 21066 else 21067 { 21068 if (value & ~0x7) 21069 as_bad_where (fixP->fx_file, fixP->fx_line, 21070 _("immediate value out of range")); 21071 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; 21072 newval |= rd | (rs << 3) | (value << 6); 21073 } 21074 } 21075 md_number_to_chars (buf, newval, THUMB_SIZE); 21076 break; 21077 21078 case BFD_RELOC_ARM_THUMB_IMM: 21079 newval = md_chars_to_number (buf, THUMB_SIZE); 21080 if (value < 0 || value > 255) 21081 as_bad_where (fixP->fx_file, fixP->fx_line, 21082 _("invalid immediate: %ld is out of range"), 21083 (long) value); 21084 newval |= value; 21085 md_number_to_chars (buf, newval, THUMB_SIZE); 21086 break; 21087 21088 case BFD_RELOC_ARM_THUMB_SHIFT: 21089 /* 5bit shift value (0..32). LSL cannot take 32. */ 21090 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; 21091 temp = newval & 0xf800; 21092 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) 21093 as_bad_where (fixP->fx_file, fixP->fx_line, 21094 _("invalid shift value: %ld"), (long) value); 21095 /* Shifts of zero must be encoded as LSL. */ 21096 if (value == 0) 21097 newval = (newval & 0x003f) | T_OPCODE_LSL_I; 21098 /* Shifts of 32 are encoded as zero. */ 21099 else if (value == 32) 21100 value = 0; 21101 newval |= value << 6; 21102 md_number_to_chars (buf, newval, THUMB_SIZE); 21103 break; 21104 21105 case BFD_RELOC_VTABLE_INHERIT: 21106 case BFD_RELOC_VTABLE_ENTRY: 21107 fixP->fx_done = 0; 21108 return; 21109 21110 case BFD_RELOC_ARM_MOVW: 21111 case BFD_RELOC_ARM_MOVT: 21112 case BFD_RELOC_ARM_THUMB_MOVW: 21113 case BFD_RELOC_ARM_THUMB_MOVT: 21114 if (fixP->fx_done || !seg->use_rela_p) 21115 { 21116 /* REL format relocations are limited to a 16-bit addend. */ 21117 if (!fixP->fx_done) 21118 { 21119 if (value < -0x8000 || value > 0x7fff) 21120 as_bad_where (fixP->fx_file, fixP->fx_line, 21121 _("offset out of range")); 21122 } 21123 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT 21124 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 21125 { 21126 value >>= 16; 21127 } 21128 21129 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW 21130 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 21131 { 21132 newval = get_thumb32_insn (buf); 21133 newval &= 0xfbf08f00; 21134 newval |= (value & 0xf000) << 4; 21135 newval |= (value & 0x0800) << 15; 21136 newval |= (value & 0x0700) << 4; 21137 newval |= (value & 0x00ff); 21138 put_thumb32_insn (buf, newval); 21139 } 21140 else 21141 { 21142 newval = md_chars_to_number (buf, 4); 21143 newval &= 0xfff0f000; 21144 newval |= value & 0x0fff; 21145 newval |= (value & 0xf000) << 4; 21146 md_number_to_chars (buf, newval, 4); 21147 } 21148 } 21149 return; 21150 21151 case BFD_RELOC_ARM_ALU_PC_G0_NC: 21152 case BFD_RELOC_ARM_ALU_PC_G0: 21153 case BFD_RELOC_ARM_ALU_PC_G1_NC: 21154 case BFD_RELOC_ARM_ALU_PC_G1: 21155 case BFD_RELOC_ARM_ALU_PC_G2: 21156 case BFD_RELOC_ARM_ALU_SB_G0_NC: 21157 case BFD_RELOC_ARM_ALU_SB_G0: 21158 case BFD_RELOC_ARM_ALU_SB_G1_NC: 21159 case BFD_RELOC_ARM_ALU_SB_G1: 21160 case BFD_RELOC_ARM_ALU_SB_G2: 21161 gas_assert (!fixP->fx_done); 21162 if (!seg->use_rela_p) 21163 { 21164 bfd_vma insn; 21165 bfd_vma encoded_addend; 21166 bfd_vma addend_abs = abs (value); 21167 21168 /* Check that the absolute value of the addend can be 21169 expressed as an 8-bit constant plus a rotation. */ 21170 encoded_addend = encode_arm_immediate (addend_abs); 21171 if (encoded_addend == (unsigned int) FAIL) 21172 as_bad_where (fixP->fx_file, fixP->fx_line, 21173 _("the offset 0x%08lX is not representable"), 21174 (unsigned long) addend_abs); 21175 21176 /* Extract the instruction. */ 21177 insn = md_chars_to_number (buf, INSN_SIZE); 21178 21179 /* If the addend is positive, use an ADD instruction. 21180 Otherwise use a SUB. Take care not to destroy the S bit. */ 21181 insn &= 0xff1fffff; 21182 if (value < 0) 21183 insn |= 1 << 22; 21184 else 21185 insn |= 1 << 23; 21186 21187 /* Place the encoded addend into the first 12 bits of the 21188 instruction. */ 21189 insn &= 0xfffff000; 21190 insn |= encoded_addend; 21191 21192 /* Update the instruction. */ 21193 md_number_to_chars (buf, insn, INSN_SIZE); 21194 } 21195 break; 21196 21197 case BFD_RELOC_ARM_LDR_PC_G0: 21198 case BFD_RELOC_ARM_LDR_PC_G1: 21199 case BFD_RELOC_ARM_LDR_PC_G2: 21200 case BFD_RELOC_ARM_LDR_SB_G0: 21201 case BFD_RELOC_ARM_LDR_SB_G1: 21202 case BFD_RELOC_ARM_LDR_SB_G2: 21203 gas_assert (!fixP->fx_done); 21204 if (!seg->use_rela_p) 21205 { 21206 bfd_vma insn; 21207 bfd_vma addend_abs = abs (value); 21208 21209 /* Check that the absolute value of the addend can be 21210 encoded in 12 bits. */ 21211 if (addend_abs >= 0x1000) 21212 as_bad_where (fixP->fx_file, fixP->fx_line, 21213 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), 21214 (unsigned long) addend_abs); 21215 21216 /* Extract the instruction. */ 21217 insn = md_chars_to_number (buf, INSN_SIZE); 21218 21219 /* If the addend is negative, clear bit 23 of the instruction. 21220 Otherwise set it. */ 21221 if (value < 0) 21222 insn &= ~(1 << 23); 21223 else 21224 insn |= 1 << 23; 21225 21226 /* Place the absolute value of the addend into the first 12 bits 21227 of the instruction. */ 21228 insn &= 0xfffff000; 21229 insn |= addend_abs; 21230 21231 /* Update the instruction. */ 21232 md_number_to_chars (buf, insn, INSN_SIZE); 21233 } 21234 break; 21235 21236 case BFD_RELOC_ARM_LDRS_PC_G0: 21237 case BFD_RELOC_ARM_LDRS_PC_G1: 21238 case BFD_RELOC_ARM_LDRS_PC_G2: 21239 case BFD_RELOC_ARM_LDRS_SB_G0: 21240 case BFD_RELOC_ARM_LDRS_SB_G1: 21241 case BFD_RELOC_ARM_LDRS_SB_G2: 21242 gas_assert (!fixP->fx_done); 21243 if (!seg->use_rela_p) 21244 { 21245 bfd_vma insn; 21246 bfd_vma addend_abs = abs (value); 21247 21248 /* Check that the absolute value of the addend can be 21249 encoded in 8 bits. */ 21250 if (addend_abs >= 0x100) 21251 as_bad_where (fixP->fx_file, fixP->fx_line, 21252 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), 21253 (unsigned long) addend_abs); 21254 21255 /* Extract the instruction. */ 21256 insn = md_chars_to_number (buf, INSN_SIZE); 21257 21258 /* If the addend is negative, clear bit 23 of the instruction. 21259 Otherwise set it. */ 21260 if (value < 0) 21261 insn &= ~(1 << 23); 21262 else 21263 insn |= 1 << 23; 21264 21265 /* Place the first four bits of the absolute value of the addend 21266 into the first 4 bits of the instruction, and the remaining 21267 four into bits 8 .. 11. */ 21268 insn &= 0xfffff0f0; 21269 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); 21270 21271 /* Update the instruction. */ 21272 md_number_to_chars (buf, insn, INSN_SIZE); 21273 } 21274 break; 21275 21276 case BFD_RELOC_ARM_LDC_PC_G0: 21277 case BFD_RELOC_ARM_LDC_PC_G1: 21278 case BFD_RELOC_ARM_LDC_PC_G2: 21279 case BFD_RELOC_ARM_LDC_SB_G0: 21280 case BFD_RELOC_ARM_LDC_SB_G1: 21281 case BFD_RELOC_ARM_LDC_SB_G2: 21282 gas_assert (!fixP->fx_done); 21283 if (!seg->use_rela_p) 21284 { 21285 bfd_vma insn; 21286 bfd_vma addend_abs = abs (value); 21287 21288 /* Check that the absolute value of the addend is a multiple of 21289 four and, when divided by four, fits in 8 bits. */ 21290 if (addend_abs & 0x3) 21291 as_bad_where (fixP->fx_file, fixP->fx_line, 21292 _("bad offset 0x%08lX (must be word-aligned)"), 21293 (unsigned long) addend_abs); 21294 21295 if ((addend_abs >> 2) > 0xff) 21296 as_bad_where (fixP->fx_file, fixP->fx_line, 21297 _("bad offset 0x%08lX (must be an 8-bit number of words)"), 21298 (unsigned long) addend_abs); 21299 21300 /* Extract the instruction. */ 21301 insn = md_chars_to_number (buf, INSN_SIZE); 21302 21303 /* If the addend is negative, clear bit 23 of the instruction. 21304 Otherwise set it. */ 21305 if (value < 0) 21306 insn &= ~(1 << 23); 21307 else 21308 insn |= 1 << 23; 21309 21310 /* Place the addend (divided by four) into the first eight 21311 bits of the instruction. */ 21312 insn &= 0xfffffff0; 21313 insn |= addend_abs >> 2; 21314 21315 /* Update the instruction. */ 21316 md_number_to_chars (buf, insn, INSN_SIZE); 21317 } 21318 break; 21319 21320 case BFD_RELOC_ARM_V4BX: 21321 /* This will need to go in the object file. */ 21322 fixP->fx_done = 0; 21323 break; 21324 21325 case BFD_RELOC_UNUSED: 21326 default: 21327 as_bad_where (fixP->fx_file, fixP->fx_line, 21328 _("bad relocation fixup type (%d)"), fixP->fx_r_type); 21329 } 21330} 21331 21332/* Translate internal representation of relocation info to BFD target 21333 format. */ 21334 21335arelent * 21336tc_gen_reloc (asection *section, fixS *fixp) 21337{ 21338 arelent * reloc; 21339 bfd_reloc_code_real_type code; 21340 21341 reloc = (arelent *) xmalloc (sizeof (arelent)); 21342 21343 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 21344 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 21345 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 21346 21347 if (fixp->fx_pcrel) 21348 { 21349 if (section->use_rela_p) 21350 fixp->fx_offset -= md_pcrel_from_section (fixp, section); 21351 else 21352 fixp->fx_offset = reloc->address; 21353 } 21354 reloc->addend = fixp->fx_offset; 21355 21356 switch (fixp->fx_r_type) 21357 { 21358 case BFD_RELOC_8: 21359 if (fixp->fx_pcrel) 21360 { 21361 code = BFD_RELOC_8_PCREL; 21362 break; 21363 } 21364 21365 case BFD_RELOC_16: 21366 if (fixp->fx_pcrel) 21367 { 21368 code = BFD_RELOC_16_PCREL; 21369 break; 21370 } 21371 21372 case BFD_RELOC_32: 21373 if (fixp->fx_pcrel) 21374 { 21375 code = BFD_RELOC_32_PCREL; 21376 break; 21377 } 21378 21379 case BFD_RELOC_ARM_MOVW: 21380 if (fixp->fx_pcrel) 21381 { 21382 code = BFD_RELOC_ARM_MOVW_PCREL; 21383 break; 21384 } 21385 21386 case BFD_RELOC_ARM_MOVT: 21387 if (fixp->fx_pcrel) 21388 { 21389 code = BFD_RELOC_ARM_MOVT_PCREL; 21390 break; 21391 } 21392 21393 case BFD_RELOC_ARM_THUMB_MOVW: 21394 if (fixp->fx_pcrel) 21395 { 21396 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; 21397 break; 21398 } 21399 21400 case BFD_RELOC_ARM_THUMB_MOVT: 21401 if (fixp->fx_pcrel) 21402 { 21403 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; 21404 break; 21405 } 21406 21407 case BFD_RELOC_NONE: 21408 case BFD_RELOC_ARM_PCREL_BRANCH: 21409 case BFD_RELOC_ARM_PCREL_BLX: 21410 case BFD_RELOC_RVA: 21411 case BFD_RELOC_THUMB_PCREL_BRANCH7: 21412 case BFD_RELOC_THUMB_PCREL_BRANCH9: 21413 case BFD_RELOC_THUMB_PCREL_BRANCH12: 21414 case BFD_RELOC_THUMB_PCREL_BRANCH20: 21415 case BFD_RELOC_THUMB_PCREL_BRANCH23: 21416 case BFD_RELOC_THUMB_PCREL_BRANCH25: 21417 case BFD_RELOC_VTABLE_ENTRY: 21418 case BFD_RELOC_VTABLE_INHERIT: 21419#ifdef TE_PE 21420 case BFD_RELOC_32_SECREL: 21421#endif 21422 code = fixp->fx_r_type; 21423 break; 21424 21425 case BFD_RELOC_THUMB_PCREL_BLX: 21426#ifdef OBJ_ELF 21427 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 21428 code = BFD_RELOC_THUMB_PCREL_BRANCH23; 21429 else 21430#endif 21431 code = BFD_RELOC_THUMB_PCREL_BLX; 21432 break; 21433 21434 case BFD_RELOC_ARM_LITERAL: 21435 case BFD_RELOC_ARM_HWLITERAL: 21436 /* If this is called then the a literal has 21437 been referenced across a section boundary. */ 21438 as_bad_where (fixp->fx_file, fixp->fx_line, 21439 _("literal referenced across section boundary")); 21440 return NULL; 21441 21442#ifdef OBJ_ELF 21443 case BFD_RELOC_ARM_GOT32: 21444 case BFD_RELOC_ARM_GOTOFF: 21445 case BFD_RELOC_ARM_GOT_PREL: 21446 case BFD_RELOC_ARM_PLT32: 21447 case BFD_RELOC_ARM_TARGET1: 21448 case BFD_RELOC_ARM_ROSEGREL32: 21449 case BFD_RELOC_ARM_SBREL32: 21450 case BFD_RELOC_ARM_PREL31: 21451 case BFD_RELOC_ARM_TARGET2: 21452 case BFD_RELOC_ARM_TLS_LE32: 21453 case BFD_RELOC_ARM_TLS_LDO32: 21454 case BFD_RELOC_ARM_PCREL_CALL: 21455 case BFD_RELOC_ARM_PCREL_JUMP: 21456 case BFD_RELOC_ARM_ALU_PC_G0_NC: 21457 case BFD_RELOC_ARM_ALU_PC_G0: 21458 case BFD_RELOC_ARM_ALU_PC_G1_NC: 21459 case BFD_RELOC_ARM_ALU_PC_G1: 21460 case BFD_RELOC_ARM_ALU_PC_G2: 21461 case BFD_RELOC_ARM_LDR_PC_G0: 21462 case BFD_RELOC_ARM_LDR_PC_G1: 21463 case BFD_RELOC_ARM_LDR_PC_G2: 21464 case BFD_RELOC_ARM_LDRS_PC_G0: 21465 case BFD_RELOC_ARM_LDRS_PC_G1: 21466 case BFD_RELOC_ARM_LDRS_PC_G2: 21467 case BFD_RELOC_ARM_LDC_PC_G0: 21468 case BFD_RELOC_ARM_LDC_PC_G1: 21469 case BFD_RELOC_ARM_LDC_PC_G2: 21470 case BFD_RELOC_ARM_ALU_SB_G0_NC: 21471 case BFD_RELOC_ARM_ALU_SB_G0: 21472 case BFD_RELOC_ARM_ALU_SB_G1_NC: 21473 case BFD_RELOC_ARM_ALU_SB_G1: 21474 case BFD_RELOC_ARM_ALU_SB_G2: 21475 case BFD_RELOC_ARM_LDR_SB_G0: 21476 case BFD_RELOC_ARM_LDR_SB_G1: 21477 case BFD_RELOC_ARM_LDR_SB_G2: 21478 case BFD_RELOC_ARM_LDRS_SB_G0: 21479 case BFD_RELOC_ARM_LDRS_SB_G1: 21480 case BFD_RELOC_ARM_LDRS_SB_G2: 21481 case BFD_RELOC_ARM_LDC_SB_G0: 21482 case BFD_RELOC_ARM_LDC_SB_G1: 21483 case BFD_RELOC_ARM_LDC_SB_G2: 21484 case BFD_RELOC_ARM_V4BX: 21485 code = fixp->fx_r_type; 21486 break; 21487 21488 case BFD_RELOC_ARM_TLS_GD32: 21489 case BFD_RELOC_ARM_TLS_IE32: 21490 case BFD_RELOC_ARM_TLS_LDM32: 21491 /* BFD will include the symbol's address in the addend. 21492 But we don't want that, so subtract it out again here. */ 21493 if (!S_IS_COMMON (fixp->fx_addsy)) 21494 reloc->addend -= (*reloc->sym_ptr_ptr)->value; 21495 code = fixp->fx_r_type; 21496 break; 21497#endif 21498 21499 case BFD_RELOC_ARM_IMMEDIATE: 21500 as_bad_where (fixp->fx_file, fixp->fx_line, 21501 _("internal relocation (type: IMMEDIATE) not fixed up")); 21502 return NULL; 21503 21504 case BFD_RELOC_ARM_ADRL_IMMEDIATE: 21505 as_bad_where (fixp->fx_file, fixp->fx_line, 21506 _("ADRL used for a symbol not defined in the same file")); 21507 return NULL; 21508 21509 case BFD_RELOC_ARM_OFFSET_IMM: 21510 if (section->use_rela_p) 21511 { 21512 code = fixp->fx_r_type; 21513 break; 21514 } 21515 21516 if (fixp->fx_addsy != NULL 21517 && !S_IS_DEFINED (fixp->fx_addsy) 21518 && S_IS_LOCAL (fixp->fx_addsy)) 21519 { 21520 as_bad_where (fixp->fx_file, fixp->fx_line, 21521 _("undefined local label `%s'"), 21522 S_GET_NAME (fixp->fx_addsy)); 21523 return NULL; 21524 } 21525 21526 as_bad_where (fixp->fx_file, fixp->fx_line, 21527 _("internal_relocation (type: OFFSET_IMM) not fixed up")); 21528 return NULL; 21529 21530 default: 21531 { 21532 char * type; 21533 21534 switch (fixp->fx_r_type) 21535 { 21536 case BFD_RELOC_NONE: type = "NONE"; break; 21537 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; 21538 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; 21539 case BFD_RELOC_ARM_SMC: type = "SMC"; break; 21540 case BFD_RELOC_ARM_SWI: type = "SWI"; break; 21541 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; 21542 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; 21543 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break; 21544 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; 21545 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; 21546 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; 21547 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; 21548 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; 21549 default: type = _("<unknown>"); break; 21550 } 21551 as_bad_where (fixp->fx_file, fixp->fx_line, 21552 _("cannot represent %s relocation in this object file format"), 21553 type); 21554 return NULL; 21555 } 21556 } 21557 21558#ifdef OBJ_ELF 21559 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) 21560 && GOT_symbol 21561 && fixp->fx_addsy == GOT_symbol) 21562 { 21563 code = BFD_RELOC_ARM_GOTPC; 21564 reloc->addend = fixp->fx_offset = reloc->address; 21565 } 21566#endif 21567 21568 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 21569 21570 if (reloc->howto == NULL) 21571 { 21572 as_bad_where (fixp->fx_file, fixp->fx_line, 21573 _("cannot represent %s relocation in this object file format"), 21574 bfd_get_reloc_code_name (code)); 21575 return NULL; 21576 } 21577 21578 /* HACK: Since arm ELF uses Rel instead of Rela, encode the 21579 vtable entry to be used in the relocation's section offset. */ 21580 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 21581 reloc->address = fixp->fx_offset; 21582 21583 return reloc; 21584} 21585 21586/* This fix_new is called by cons via TC_CONS_FIX_NEW. */ 21587 21588void 21589cons_fix_new_arm (fragS * frag, 21590 int where, 21591 int size, 21592 expressionS * exp) 21593{ 21594 bfd_reloc_code_real_type type; 21595 int pcrel = 0; 21596 21597 /* Pick a reloc. 21598 FIXME: @@ Should look at CPU word size. */ 21599 switch (size) 21600 { 21601 case 1: 21602 type = BFD_RELOC_8; 21603 break; 21604 case 2: 21605 type = BFD_RELOC_16; 21606 break; 21607 case 4: 21608 default: 21609 type = BFD_RELOC_32; 21610 break; 21611 case 8: 21612 type = BFD_RELOC_64; 21613 break; 21614 } 21615 21616#ifdef TE_PE 21617 if (exp->X_op == O_secrel) 21618 { 21619 exp->X_op = O_symbol; 21620 type = BFD_RELOC_32_SECREL; 21621 } 21622#endif 21623 21624 fix_new_exp (frag, where, (int) size, exp, pcrel, type); 21625} 21626 21627#if defined (OBJ_COFF) 21628void 21629arm_validate_fix (fixS * fixP) 21630{ 21631 /* If the destination of the branch is a defined symbol which does not have 21632 the THUMB_FUNC attribute, then we must be calling a function which has 21633 the (interfacearm) attribute. We look for the Thumb entry point to that 21634 function and change the branch to refer to that function instead. */ 21635 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 21636 && fixP->fx_addsy != NULL 21637 && S_IS_DEFINED (fixP->fx_addsy) 21638 && ! THUMB_IS_FUNC (fixP->fx_addsy)) 21639 { 21640 fixP->fx_addsy = find_real_start (fixP->fx_addsy); 21641 } 21642} 21643#endif 21644 21645 21646int 21647arm_force_relocation (struct fix * fixp) 21648{ 21649#if defined (OBJ_COFF) && defined (TE_PE) 21650 if (fixp->fx_r_type == BFD_RELOC_RVA) 21651 return 1; 21652#endif 21653 21654 /* In case we have a call or a branch to a function in ARM ISA mode from 21655 a thumb function or vice-versa force the relocation. These relocations 21656 are cleared off for some cores that might have blx and simple transformations 21657 are possible. */ 21658 21659#ifdef OBJ_ELF 21660 switch (fixp->fx_r_type) 21661 { 21662 case BFD_RELOC_ARM_PCREL_JUMP: 21663 case BFD_RELOC_ARM_PCREL_CALL: 21664 case BFD_RELOC_THUMB_PCREL_BLX: 21665 if (THUMB_IS_FUNC (fixp->fx_addsy)) 21666 return 1; 21667 break; 21668 21669 case BFD_RELOC_ARM_PCREL_BLX: 21670 case BFD_RELOC_THUMB_PCREL_BRANCH25: 21671 case BFD_RELOC_THUMB_PCREL_BRANCH20: 21672 case BFD_RELOC_THUMB_PCREL_BRANCH23: 21673 if (ARM_IS_FUNC (fixp->fx_addsy)) 21674 return 1; 21675 break; 21676 21677 default: 21678 break; 21679 } 21680#endif 21681 21682 /* Resolve these relocations even if the symbol is extern or weak. */ 21683 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE 21684 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM 21685 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE 21686 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM 21687 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE 21688 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 21689 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) 21690 return 0; 21691 21692 /* Always leave these relocations for the linker. */ 21693 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC 21694 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) 21695 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) 21696 return 1; 21697 21698 /* Always generate relocations against function symbols. */ 21699 if (fixp->fx_r_type == BFD_RELOC_32 21700 && fixp->fx_addsy 21701 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) 21702 return 1; 21703 21704 return generic_force_reloc (fixp); 21705} 21706 21707#if defined (OBJ_ELF) || defined (OBJ_COFF) 21708/* Relocations against function names must be left unadjusted, 21709 so that the linker can use this information to generate interworking 21710 stubs. The MIPS version of this function 21711 also prevents relocations that are mips-16 specific, but I do not 21712 know why it does this. 21713 21714 FIXME: 21715 There is one other problem that ought to be addressed here, but 21716 which currently is not: Taking the address of a label (rather 21717 than a function) and then later jumping to that address. Such 21718 addresses also ought to have their bottom bit set (assuming that 21719 they reside in Thumb code), but at the moment they will not. */ 21720 21721bfd_boolean 21722arm_fix_adjustable (fixS * fixP) 21723{ 21724 if (fixP->fx_addsy == NULL) 21725 return 1; 21726 21727 /* Preserve relocations against symbols with function type. */ 21728 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) 21729 return FALSE; 21730 21731 if (THUMB_IS_FUNC (fixP->fx_addsy) 21732 && fixP->fx_subsy == NULL) 21733 return FALSE; 21734 21735 /* We need the symbol name for the VTABLE entries. */ 21736 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 21737 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 21738 return FALSE; 21739 21740 /* Don't allow symbols to be discarded on GOT related relocs. */ 21741 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 21742 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 21743 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF 21744 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 21745 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 21746 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 21747 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 21748 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 21749 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) 21750 return FALSE; 21751 21752 /* Similarly for group relocations. */ 21753 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC 21754 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) 21755 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) 21756 return FALSE; 21757 21758 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ 21759 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW 21760 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT 21761 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL 21762 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL 21763 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW 21764 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT 21765 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL 21766 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) 21767 return FALSE; 21768 21769 return TRUE; 21770} 21771#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ 21772 21773#ifdef OBJ_ELF 21774 21775const char * 21776elf32_arm_target_format (void) 21777{ 21778#ifdef TE_SYMBIAN 21779 return (target_big_endian 21780 ? "elf32-bigarm-symbian" 21781 : "elf32-littlearm-symbian"); 21782#elif defined (TE_VXWORKS) 21783 return (target_big_endian 21784 ? "elf32-bigarm-vxworks" 21785 : "elf32-littlearm-vxworks"); 21786#else 21787 if (target_big_endian) 21788 return "elf32-bigarm"; 21789 else 21790 return "elf32-littlearm"; 21791#endif 21792} 21793 21794void 21795armelf_frob_symbol (symbolS * symp, 21796 int * puntp) 21797{ 21798 elf_frob_symbol (symp, puntp); 21799} 21800#endif 21801 21802/* MD interface: Finalization. */ 21803 21804void 21805arm_cleanup (void) 21806{ 21807 literal_pool * pool; 21808 21809 /* Ensure that all the IT blocks are properly closed. */ 21810 check_it_blocks_finished (); 21811 21812 for (pool = list_of_pools; pool; pool = pool->next) 21813 { 21814 /* Put it at the end of the relevant section. */ 21815 subseg_set (pool->section, pool->sub_section); 21816#ifdef OBJ_ELF 21817 arm_elf_change_section (); 21818#endif 21819 s_ltorg (0); 21820 } 21821} 21822 21823#ifdef OBJ_ELF 21824/* Remove any excess mapping symbols generated for alignment frags in 21825 SEC. We may have created a mapping symbol before a zero byte 21826 alignment; remove it if there's a mapping symbol after the 21827 alignment. */ 21828static void 21829check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, 21830 void *dummy ATTRIBUTE_UNUSED) 21831{ 21832 segment_info_type *seginfo = seg_info (sec); 21833 fragS *fragp; 21834 21835 if (seginfo == NULL || seginfo->frchainP == NULL) 21836 return; 21837 21838 for (fragp = seginfo->frchainP->frch_root; 21839 fragp != NULL; 21840 fragp = fragp->fr_next) 21841 { 21842 symbolS *sym = fragp->tc_frag_data.last_map; 21843 fragS *next = fragp->fr_next; 21844 21845 /* Variable-sized frags have been converted to fixed size by 21846 this point. But if this was variable-sized to start with, 21847 there will be a fixed-size frag after it. So don't handle 21848 next == NULL. */ 21849 if (sym == NULL || next == NULL) 21850 continue; 21851 21852 if (S_GET_VALUE (sym) < next->fr_address) 21853 /* Not at the end of this frag. */ 21854 continue; 21855 know (S_GET_VALUE (sym) == next->fr_address); 21856 21857 do 21858 { 21859 if (next->tc_frag_data.first_map != NULL) 21860 { 21861 /* Next frag starts with a mapping symbol. Discard this 21862 one. */ 21863 symbol_remove (sym, &symbol_rootP, &symbol_lastP); 21864 break; 21865 } 21866 21867 if (next->fr_next == NULL) 21868 { 21869 /* This mapping symbol is at the end of the section. Discard 21870 it. */ 21871 know (next->fr_fix == 0 && next->fr_var == 0); 21872 symbol_remove (sym, &symbol_rootP, &symbol_lastP); 21873 break; 21874 } 21875 21876 /* As long as we have empty frags without any mapping symbols, 21877 keep looking. */ 21878 /* If the next frag is non-empty and does not start with a 21879 mapping symbol, then this mapping symbol is required. */ 21880 if (next->fr_address != next->fr_next->fr_address) 21881 break; 21882 21883 next = next->fr_next; 21884 } 21885 while (next != NULL); 21886 } 21887} 21888#endif 21889 21890/* Adjust the symbol table. This marks Thumb symbols as distinct from 21891 ARM ones. */ 21892 21893void 21894arm_adjust_symtab (void) 21895{ 21896#ifdef OBJ_COFF 21897 symbolS * sym; 21898 21899 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 21900 { 21901 if (ARM_IS_THUMB (sym)) 21902 { 21903 if (THUMB_IS_FUNC (sym)) 21904 { 21905 /* Mark the symbol as a Thumb function. */ 21906 if ( S_GET_STORAGE_CLASS (sym) == C_STAT 21907 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ 21908 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); 21909 21910 else if (S_GET_STORAGE_CLASS (sym) == C_EXT) 21911 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); 21912 else 21913 as_bad (_("%s: unexpected function type: %d"), 21914 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); 21915 } 21916 else switch (S_GET_STORAGE_CLASS (sym)) 21917 { 21918 case C_EXT: 21919 S_SET_STORAGE_CLASS (sym, C_THUMBEXT); 21920 break; 21921 case C_STAT: 21922 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); 21923 break; 21924 case C_LABEL: 21925 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); 21926 break; 21927 default: 21928 /* Do nothing. */ 21929 break; 21930 } 21931 } 21932 21933 if (ARM_IS_INTERWORK (sym)) 21934 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; 21935 } 21936#endif 21937#ifdef OBJ_ELF 21938 symbolS * sym; 21939 char bind; 21940 21941 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 21942 { 21943 if (ARM_IS_THUMB (sym)) 21944 { 21945 elf_symbol_type * elf_sym; 21946 21947 elf_sym = elf_symbol (symbol_get_bfdsym (sym)); 21948 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); 21949 21950 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, 21951 BFD_ARM_SPECIAL_SYM_TYPE_ANY)) 21952 { 21953 /* If it's a .thumb_func, declare it as so, 21954 otherwise tag label as .code 16. */ 21955 if (THUMB_IS_FUNC (sym)) 21956 elf_sym->internal_elf_sym.st_info = 21957 ELF_ST_INFO (bind, STT_ARM_TFUNC); 21958 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) 21959 elf_sym->internal_elf_sym.st_info = 21960 ELF_ST_INFO (bind, STT_ARM_16BIT); 21961 } 21962 } 21963 } 21964 21965 /* Remove any overlapping mapping symbols generated by alignment frags. */ 21966 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); 21967 /* Now do generic ELF adjustments. */ 21968 elf_adjust_symtab (); 21969#endif 21970} 21971 21972/* MD interface: Initialization. */ 21973 21974static void 21975set_constant_flonums (void) 21976{ 21977 int i; 21978 21979 for (i = 0; i < NUM_FLOAT_VALS; i++) 21980 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) 21981 abort (); 21982} 21983 21984/* Auto-select Thumb mode if it's the only available instruction set for the 21985 given architecture. */ 21986 21987static void 21988autoselect_thumb_from_cpu_variant (void) 21989{ 21990 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 21991 opcode_select (16); 21992} 21993 21994void 21995md_begin (void) 21996{ 21997 unsigned mach; 21998 unsigned int i; 21999 22000 if ( (arm_ops_hsh = hash_new ()) == NULL 22001 || (arm_cond_hsh = hash_new ()) == NULL 22002 || (arm_shift_hsh = hash_new ()) == NULL 22003 || (arm_psr_hsh = hash_new ()) == NULL 22004 || (arm_v7m_psr_hsh = hash_new ()) == NULL 22005 || (arm_reg_hsh = hash_new ()) == NULL 22006 || (arm_reloc_hsh = hash_new ()) == NULL 22007 || (arm_barrier_opt_hsh = hash_new ()) == NULL) 22008 as_fatal (_("virtual memory exhausted")); 22009 22010 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) 22011 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); 22012 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) 22013 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); 22014 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) 22015 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); 22016 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) 22017 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); 22018 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) 22019 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, 22020 (void *) (v7m_psrs + i)); 22021 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) 22022 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); 22023 for (i = 0; 22024 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); 22025 i++) 22026 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, 22027 (void *) (barrier_opt_names + i)); 22028#ifdef OBJ_ELF 22029 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) 22030 hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i)); 22031#endif 22032 22033 set_constant_flonums (); 22034 22035 /* Set the cpu variant based on the command-line options. We prefer 22036 -mcpu= over -march= if both are set (as for GCC); and we prefer 22037 -mfpu= over any other way of setting the floating point unit. 22038 Use of legacy options with new options are faulted. */ 22039 if (legacy_cpu) 22040 { 22041 if (mcpu_cpu_opt || march_cpu_opt) 22042 as_bad (_("use of old and new-style options to set CPU type")); 22043 22044 mcpu_cpu_opt = legacy_cpu; 22045 } 22046 else if (!mcpu_cpu_opt) 22047 mcpu_cpu_opt = march_cpu_opt; 22048 22049 if (legacy_fpu) 22050 { 22051 if (mfpu_opt) 22052 as_bad (_("use of old and new-style options to set FPU type")); 22053 22054 mfpu_opt = legacy_fpu; 22055 } 22056 else if (!mfpu_opt) 22057 { 22058#if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ 22059 || defined (TE_NetBSD) || defined (TE_VXWORKS)) 22060 /* Some environments specify a default FPU. If they don't, infer it 22061 from the processor. */ 22062 if (mcpu_fpu_opt) 22063 mfpu_opt = mcpu_fpu_opt; 22064 else 22065 mfpu_opt = march_fpu_opt; 22066#else 22067 mfpu_opt = &fpu_default; 22068#endif 22069 } 22070 22071 if (!mfpu_opt) 22072 { 22073 if (mcpu_cpu_opt != NULL) 22074 mfpu_opt = &fpu_default; 22075 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) 22076 mfpu_opt = &fpu_arch_vfp_v2; 22077 else 22078 mfpu_opt = &fpu_arch_fpa; 22079 } 22080 22081#ifdef CPU_DEFAULT 22082 if (!mcpu_cpu_opt) 22083 { 22084 mcpu_cpu_opt = &cpu_default; 22085 selected_cpu = cpu_default; 22086 } 22087#else 22088 if (mcpu_cpu_opt) 22089 selected_cpu = *mcpu_cpu_opt; 22090 else 22091 mcpu_cpu_opt = &arm_arch_any; 22092#endif 22093 22094 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 22095 22096 autoselect_thumb_from_cpu_variant (); 22097 22098 arm_arch_used = thumb_arch_used = arm_arch_none; 22099 22100#if defined OBJ_COFF || defined OBJ_ELF 22101 { 22102 unsigned int flags = 0; 22103 22104#if defined OBJ_ELF 22105 flags = meabi_flags; 22106 22107 switch (meabi_flags) 22108 { 22109 case EF_ARM_EABI_UNKNOWN: 22110#endif 22111 /* Set the flags in the private structure. */ 22112 if (uses_apcs_26) flags |= F_APCS26; 22113 if (support_interwork) flags |= F_INTERWORK; 22114 if (uses_apcs_float) flags |= F_APCS_FLOAT; 22115 if (pic_code) flags |= F_PIC; 22116 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) 22117 flags |= F_SOFT_FLOAT; 22118 22119 switch (mfloat_abi_opt) 22120 { 22121 case ARM_FLOAT_ABI_SOFT: 22122 case ARM_FLOAT_ABI_SOFTFP: 22123 flags |= F_SOFT_FLOAT; 22124 break; 22125 22126 case ARM_FLOAT_ABI_HARD: 22127 if (flags & F_SOFT_FLOAT) 22128 as_bad (_("hard-float conflicts with specified fpu")); 22129 break; 22130 } 22131 22132 /* Using pure-endian doubles (even if soft-float). */ 22133 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) 22134 flags |= F_VFP_FLOAT; 22135 22136#if defined OBJ_ELF 22137 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) 22138 flags |= EF_ARM_MAVERICK_FLOAT; 22139 break; 22140 22141 case EF_ARM_EABI_VER4: 22142 case EF_ARM_EABI_VER5: 22143 /* No additional flags to set. */ 22144 break; 22145 22146 default: 22147 abort (); 22148 } 22149#endif 22150 bfd_set_private_flags (stdoutput, flags); 22151 22152 /* We have run out flags in the COFF header to encode the 22153 status of ATPCS support, so instead we create a dummy, 22154 empty, debug section called .arm.atpcs. */ 22155 if (atpcs) 22156 { 22157 asection * sec; 22158 22159 sec = bfd_make_section (stdoutput, ".arm.atpcs"); 22160 22161 if (sec != NULL) 22162 { 22163 bfd_set_section_flags 22164 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); 22165 bfd_set_section_size (stdoutput, sec, 0); 22166 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); 22167 } 22168 } 22169 } 22170#endif 22171 22172 /* Record the CPU type as well. */ 22173 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) 22174 mach = bfd_mach_arm_iWMMXt2; 22175 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) 22176 mach = bfd_mach_arm_iWMMXt; 22177 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) 22178 mach = bfd_mach_arm_XScale; 22179 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) 22180 mach = bfd_mach_arm_ep9312; 22181 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) 22182 mach = bfd_mach_arm_5TE; 22183 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) 22184 { 22185 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 22186 mach = bfd_mach_arm_5T; 22187 else 22188 mach = bfd_mach_arm_5; 22189 } 22190 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) 22191 { 22192 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 22193 mach = bfd_mach_arm_4T; 22194 else 22195 mach = bfd_mach_arm_4; 22196 } 22197 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) 22198 mach = bfd_mach_arm_3M; 22199 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) 22200 mach = bfd_mach_arm_3; 22201 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) 22202 mach = bfd_mach_arm_2a; 22203 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) 22204 mach = bfd_mach_arm_2; 22205 else 22206 mach = bfd_mach_arm_unknown; 22207 22208 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); 22209} 22210 22211/* Command line processing. */ 22212 22213/* md_parse_option 22214 Invocation line includes a switch not recognized by the base assembler. 22215 See if it's a processor-specific option. 22216 22217 This routine is somewhat complicated by the need for backwards 22218 compatibility (since older releases of gcc can't be changed). 22219 The new options try to make the interface as compatible as 22220 possible with GCC. 22221 22222 New options (supported) are: 22223 22224 -mcpu=<cpu name> Assemble for selected processor 22225 -march=<architecture name> Assemble for selected architecture 22226 -mfpu=<fpu architecture> Assemble for selected FPU. 22227 -EB/-mbig-endian Big-endian 22228 -EL/-mlittle-endian Little-endian 22229 -k Generate PIC code 22230 -mthumb Start in Thumb mode 22231 -mthumb-interwork Code supports ARM/Thumb interworking 22232 22233 -m[no-]warn-deprecated Warn about deprecated features 22234 22235 For now we will also provide support for: 22236 22237 -mapcs-32 32-bit Program counter 22238 -mapcs-26 26-bit Program counter 22239 -macps-float Floats passed in FP registers 22240 -mapcs-reentrant Reentrant code 22241 -matpcs 22242 (sometime these will probably be replaced with -mapcs=<list of options> 22243 and -matpcs=<list of options>) 22244 22245 The remaining options are only supported for back-wards compatibility. 22246 Cpu variants, the arm part is optional: 22247 -m[arm]1 Currently not supported. 22248 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor 22249 -m[arm]3 Arm 3 processor 22250 -m[arm]6[xx], Arm 6 processors 22251 -m[arm]7[xx][t][[d]m] Arm 7 processors 22252 -m[arm]8[10] Arm 8 processors 22253 -m[arm]9[20][tdmi] Arm 9 processors 22254 -mstrongarm[110[0]] StrongARM processors 22255 -mxscale XScale processors 22256 -m[arm]v[2345[t[e]]] Arm architectures 22257 -mall All (except the ARM1) 22258 FP variants: 22259 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions 22260 -mfpe-old (No float load/store multiples) 22261 -mvfpxd VFP Single precision 22262 -mvfp All VFP 22263 -mno-fpu Disable all floating point instructions 22264 22265 The following CPU names are recognized: 22266 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, 22267 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, 22268 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, 22269 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, 22270 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, 22271 arm10t arm10e, arm1020t, arm1020e, arm10200e, 22272 strongarm, strongarm110, strongarm1100, strongarm1110, xscale. 22273 22274 */ 22275 22276const char * md_shortopts = "m:k"; 22277 22278#ifdef ARM_BI_ENDIAN 22279#define OPTION_EB (OPTION_MD_BASE + 0) 22280#define OPTION_EL (OPTION_MD_BASE + 1) 22281#else 22282#if TARGET_BYTES_BIG_ENDIAN 22283#define OPTION_EB (OPTION_MD_BASE + 0) 22284#else 22285#define OPTION_EL (OPTION_MD_BASE + 1) 22286#endif 22287#endif 22288#define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) 22289 22290struct option md_longopts[] = 22291{ 22292#ifdef OPTION_EB 22293 {"EB", no_argument, NULL, OPTION_EB}, 22294#endif 22295#ifdef OPTION_EL 22296 {"EL", no_argument, NULL, OPTION_EL}, 22297#endif 22298 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, 22299 {NULL, no_argument, NULL, 0} 22300}; 22301 22302size_t md_longopts_size = sizeof (md_longopts); 22303 22304struct arm_option_table 22305{ 22306 char *option; /* Option name to match. */ 22307 char *help; /* Help information. */ 22308 int *var; /* Variable to change. */ 22309 int value; /* What to change it to. */ 22310 char *deprecated; /* If non-null, print this message. */ 22311}; 22312 22313struct arm_option_table arm_opts[] = 22314{ 22315 {"k", N_("generate PIC code"), &pic_code, 1, NULL}, 22316 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, 22317 {"mthumb-interwork", N_("support ARM/Thumb interworking"), 22318 &support_interwork, 1, NULL}, 22319 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, 22320 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, 22321 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, 22322 1, NULL}, 22323 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, 22324 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, 22325 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, 22326 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, 22327 NULL}, 22328 22329 /* These are recognized by the assembler, but have no affect on code. */ 22330 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, 22331 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, 22332 22333 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, 22334 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), 22335 &warn_on_deprecated, 0, NULL}, 22336 {NULL, NULL, NULL, 0, NULL} 22337}; 22338 22339struct arm_legacy_option_table 22340{ 22341 char *option; /* Option name to match. */ 22342 const arm_feature_set **var; /* Variable to change. */ 22343 const arm_feature_set value; /* What to change it to. */ 22344 char *deprecated; /* If non-null, print this message. */ 22345}; 22346 22347const struct arm_legacy_option_table arm_legacy_opts[] = 22348{ 22349 /* DON'T add any new processors to this list -- we want the whole list 22350 to go away... Add them to the processors table instead. */ 22351 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, 22352 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, 22353 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, 22354 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, 22355 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, 22356 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, 22357 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, 22358 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, 22359 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, 22360 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, 22361 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, 22362 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, 22363 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, 22364 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, 22365 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, 22366 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, 22367 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, 22368 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, 22369 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, 22370 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, 22371 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, 22372 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, 22373 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, 22374 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, 22375 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, 22376 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, 22377 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, 22378 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, 22379 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, 22380 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, 22381 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, 22382 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, 22383 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, 22384 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, 22385 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, 22386 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, 22387 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, 22388 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, 22389 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, 22390 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, 22391 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, 22392 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, 22393 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, 22394 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, 22395 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, 22396 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, 22397 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 22398 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 22399 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 22400 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 22401 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, 22402 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, 22403 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, 22404 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, 22405 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, 22406 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, 22407 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, 22408 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, 22409 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, 22410 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, 22411 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, 22412 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, 22413 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, 22414 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, 22415 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, 22416 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, 22417 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, 22418 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, 22419 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, 22420 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, 22421 N_("use -mcpu=strongarm110")}, 22422 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, 22423 N_("use -mcpu=strongarm1100")}, 22424 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, 22425 N_("use -mcpu=strongarm1110")}, 22426 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, 22427 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, 22428 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, 22429 22430 /* Architecture variants -- don't add any more to this list either. */ 22431 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, 22432 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, 22433 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, 22434 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, 22435 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, 22436 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, 22437 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, 22438 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, 22439 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, 22440 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, 22441 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, 22442 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, 22443 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, 22444 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, 22445 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, 22446 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, 22447 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, 22448 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, 22449 22450 /* Floating point variants -- don't add any more to this list either. */ 22451 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, 22452 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, 22453 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, 22454 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, 22455 N_("use either -mfpu=softfpa or -mfpu=softvfp")}, 22456 22457 {NULL, NULL, ARM_ARCH_NONE, NULL} 22458}; 22459 22460struct arm_cpu_option_table 22461{ 22462 char *name; 22463 const arm_feature_set value; 22464 /* For some CPUs we assume an FPU unless the user explicitly sets 22465 -mfpu=... */ 22466 const arm_feature_set default_fpu; 22467 /* The canonical name of the CPU, or NULL to use NAME converted to upper 22468 case. */ 22469 const char *canonical_name; 22470}; 22471 22472/* This list should, at a minimum, contain all the cpu names 22473 recognized by GCC. */ 22474static const struct arm_cpu_option_table arm_cpus[] = 22475{ 22476 {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, 22477 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, 22478 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, 22479 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, 22480 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, 22481 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22482 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22483 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22484 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22485 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22486 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22487 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 22488 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22489 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 22490 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22491 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 22492 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22493 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22494 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22495 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22496 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 22497 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22498 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 22499 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 22500 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22501 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22502 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22503 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 22504 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 22505 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 22506 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 22507 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 22508 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 22509 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 22510 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 22511 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 22512 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 22513 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 22514 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 22515 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, 22516 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 22517 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 22518 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 22519 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 22520 {"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 22521 {"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 22522 /* For V5 or later processors we default to using VFP; but the user 22523 should really set the FPU type explicitly. */ 22524 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 22525 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 22526 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, 22527 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, 22528 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, 22529 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 22530 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, 22531 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 22532 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 22533 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, 22534 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 22535 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 22536 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 22537 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 22538 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 22539 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, 22540 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 22541 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 22542 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 22543 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, 22544 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, 22545 {"fa626te", ARM_ARCH_V5TE, FPU_NONE, NULL}, 22546 {"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 22547 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, 22548 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, 22549 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, 22550 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, 22551 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"}, 22552 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"}, 22553 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, 22554 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, 22555 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, 22556 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, 22557 {"cortex-a5", ARM_ARCH_V7A_MP_SEC, 22558 FPU_NONE, "Cortex-A5"}, 22559 {"cortex-a8", ARM_ARCH_V7A_SEC, 22560 ARM_FEATURE (0, FPU_VFP_V3 22561 | FPU_NEON_EXT_V1), 22562 "Cortex-A8"}, 22563 {"cortex-a9", ARM_ARCH_V7A_MP_SEC, 22564 ARM_FEATURE (0, FPU_VFP_V3 22565 | FPU_NEON_EXT_V1), 22566 "Cortex-A9"}, 22567 {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT, 22568 FPU_ARCH_NEON_VFP_V4, 22569 "Cortex-A15"}, 22570 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"}, 22571 {"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16, 22572 "Cortex-R4F"}, 22573 {"cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"}, 22574 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"}, 22575 {"cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"}, 22576 {"cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"}, 22577 /* ??? XSCALE is really an architecture. */ 22578 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, 22579 /* ??? iwmmxt is not a processor. */ 22580 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, 22581 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL}, 22582 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, 22583 /* Maverick */ 22584 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, 22585 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} 22586}; 22587 22588struct arm_arch_option_table 22589{ 22590 char *name; 22591 const arm_feature_set value; 22592 const arm_feature_set default_fpu; 22593}; 22594 22595/* This list should, at a minimum, contain all the architecture names 22596 recognized by GCC. */ 22597static const struct arm_arch_option_table arm_archs[] = 22598{ 22599 {"all", ARM_ANY, FPU_ARCH_FPA}, 22600 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, 22601 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, 22602 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, 22603 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, 22604 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, 22605 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, 22606 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, 22607 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, 22608 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, 22609 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, 22610 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, 22611 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, 22612 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, 22613 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, 22614 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, 22615 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, 22616 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, 22617 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, 22618 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, 22619 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, 22620 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, 22621 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, 22622 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, 22623 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, 22624 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, 22625 {"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP}, 22626 {"armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP}, 22627 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP}, 22628 /* The official spelling of the ARMv7 profile variants is the dashed form. 22629 Accept the non-dashed form for compatibility with old toolchains. */ 22630 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP}, 22631 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP}, 22632 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP}, 22633 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP}, 22634 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP}, 22635 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP}, 22636 {"armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP}, 22637 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, 22638 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, 22639 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP}, 22640 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} 22641}; 22642 22643/* ISA extensions in the co-processor and main instruction set space. */ 22644struct arm_option_extension_value_table 22645{ 22646 char *name; 22647 const arm_feature_set value; 22648 const arm_feature_set allowed_archs; 22649}; 22650 22651/* The following table must be in alphabetical order with a NULL last entry. 22652 */ 22653static const struct arm_option_extension_value_table arm_extensions[] = 22654{ 22655 {"idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0), 22656 ARM_FEATURE (ARM_EXT_V7A, 0)}, 22657 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY}, 22658 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY}, 22659 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY}, 22660 {"mp", ARM_FEATURE (ARM_EXT_MP, 0), 22661 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)}, 22662 {"os", ARM_FEATURE (ARM_EXT_OS, 0), 22663 ARM_FEATURE (ARM_EXT_V6M, 0)}, 22664 {"sec", ARM_FEATURE (ARM_EXT_SEC, 0), 22665 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)}, 22666 {"virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV | ARM_EXT_DIV, 0), 22667 ARM_FEATURE (ARM_EXT_V7A, 0)}, 22668 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY}, 22669 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} 22670}; 22671 22672/* ISA floating-point and Advanced SIMD extensions. */ 22673struct arm_option_fpu_value_table 22674{ 22675 char *name; 22676 const arm_feature_set value; 22677}; 22678 22679/* This list should, at a minimum, contain all the fpu names 22680 recognized by GCC. */ 22681static const struct arm_option_fpu_value_table arm_fpus[] = 22682{ 22683 {"softfpa", FPU_NONE}, 22684 {"fpe", FPU_ARCH_FPE}, 22685 {"fpe2", FPU_ARCH_FPE}, 22686 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ 22687 {"fpa", FPU_ARCH_FPA}, 22688 {"fpa10", FPU_ARCH_FPA}, 22689 {"fpa11", FPU_ARCH_FPA}, 22690 {"arm7500fe", FPU_ARCH_FPA}, 22691 {"softvfp", FPU_ARCH_VFP}, 22692 {"softvfp+vfp", FPU_ARCH_VFP_V2}, 22693 {"vfp", FPU_ARCH_VFP_V2}, 22694 {"vfp9", FPU_ARCH_VFP_V2}, 22695 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */ 22696 {"vfp10", FPU_ARCH_VFP_V2}, 22697 {"vfp10-r0", FPU_ARCH_VFP_V1}, 22698 {"vfpxd", FPU_ARCH_VFP_V1xD}, 22699 {"vfpv2", FPU_ARCH_VFP_V2}, 22700 {"vfpv3", FPU_ARCH_VFP_V3}, 22701 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, 22702 {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, 22703 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, 22704 {"vfpv3xd", FPU_ARCH_VFP_V3xD}, 22705 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, 22706 {"arm1020t", FPU_ARCH_VFP_V1}, 22707 {"arm1020e", FPU_ARCH_VFP_V2}, 22708 {"arm1136jfs", FPU_ARCH_VFP_V2}, 22709 {"arm1136jf-s", FPU_ARCH_VFP_V2}, 22710 {"maverick", FPU_ARCH_MAVERICK}, 22711 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, 22712 {"neon-fp16", FPU_ARCH_NEON_FP16}, 22713 {"vfpv4", FPU_ARCH_VFP_V4}, 22714 {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, 22715 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, 22716 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, 22717 {NULL, ARM_ARCH_NONE} 22718}; 22719 22720struct arm_option_value_table 22721{ 22722 char *name; 22723 long value; 22724}; 22725 22726static const struct arm_option_value_table arm_float_abis[] = 22727{ 22728 {"hard", ARM_FLOAT_ABI_HARD}, 22729 {"softfp", ARM_FLOAT_ABI_SOFTFP}, 22730 {"soft", ARM_FLOAT_ABI_SOFT}, 22731 {NULL, 0} 22732}; 22733 22734#ifdef OBJ_ELF 22735/* We only know how to output GNU and ver 4/5 (AAELF) formats. */ 22736static const struct arm_option_value_table arm_eabis[] = 22737{ 22738 {"gnu", EF_ARM_EABI_UNKNOWN}, 22739 {"4", EF_ARM_EABI_VER4}, 22740 {"5", EF_ARM_EABI_VER5}, 22741 {NULL, 0} 22742}; 22743#endif 22744 22745struct arm_long_option_table 22746{ 22747 char * option; /* Substring to match. */ 22748 char * help; /* Help information. */ 22749 int (* func) (char * subopt); /* Function to decode sub-option. */ 22750 char * deprecated; /* If non-null, print this message. */ 22751}; 22752 22753static bfd_boolean 22754arm_parse_extension (char * str, const arm_feature_set **opt_p) 22755{ 22756 arm_feature_set *ext_set = (arm_feature_set *) 22757 xmalloc (sizeof (arm_feature_set)); 22758 22759 /* We insist on extensions being specified in alphabetical order, and with 22760 extensions being added before being removed. We achieve this by having 22761 the global ARM_EXTENSIONS table in alphabetical order, and using the 22762 ADDING_VALUE variable to indicate whether we are adding an extension (1) 22763 or removing it (0) and only allowing it to change in the order 22764 -1 -> 1 -> 0. */ 22765 const struct arm_option_extension_value_table * opt = NULL; 22766 int adding_value = -1; 22767 22768 /* Copy the feature set, so that we can modify it. */ 22769 *ext_set = **opt_p; 22770 *opt_p = ext_set; 22771 22772 while (str != NULL && *str != 0) 22773 { 22774 char * ext; 22775 size_t optlen; 22776 22777 if (*str != '+') 22778 { 22779 as_bad (_("invalid architectural extension")); 22780 return FALSE; 22781 } 22782 22783 str++; 22784 ext = strchr (str, '+'); 22785 22786 if (ext != NULL) 22787 optlen = ext - str; 22788 else 22789 optlen = strlen (str); 22790 22791 if (optlen >= 2 22792 && strncmp (str, "no", 2) == 0) 22793 { 22794 if (adding_value != 0) 22795 { 22796 adding_value = 0; 22797 opt = arm_extensions; 22798 } 22799 22800 optlen -= 2; 22801 str += 2; 22802 } 22803 else if (optlen > 0) 22804 { 22805 if (adding_value == -1) 22806 { 22807 adding_value = 1; 22808 opt = arm_extensions; 22809 } 22810 else if (adding_value != 1) 22811 { 22812 as_bad (_("must specify extensions to add before specifying " 22813 "those to remove")); 22814 return FALSE; 22815 } 22816 } 22817 22818 if (optlen == 0) 22819 { 22820 as_bad (_("missing architectural extension")); 22821 return FALSE; 22822 } 22823 22824 gas_assert (adding_value != -1); 22825 gas_assert (opt != NULL); 22826 22827 /* Scan over the options table trying to find an exact match. */ 22828 for (; opt->name != NULL; opt++) 22829 if (strncmp (opt->name, str, optlen) == 0 22830 && strlen (opt->name) == optlen) 22831 { 22832 /* Check we can apply the extension to this architecture. */ 22833 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs)) 22834 { 22835 as_bad (_("extension does not apply to the base architecture")); 22836 return FALSE; 22837 } 22838 22839 /* Add or remove the extension. */ 22840 if (adding_value) 22841 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); 22842 else 22843 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value); 22844 22845 break; 22846 } 22847 22848 if (opt->name == NULL) 22849 { 22850 /* Did we fail to find an extension because it wasn't specified in 22851 alphabetical order, or because it does not exist? */ 22852 22853 for (opt = arm_extensions; opt->name != NULL; opt++) 22854 if (strncmp (opt->name, str, optlen) == 0) 22855 break; 22856 22857 if (opt->name == NULL) 22858 as_bad (_("unknown architectural extension `%s'"), str); 22859 else 22860 as_bad (_("architectural extensions must be specified in " 22861 "alphabetical order")); 22862 22863 return FALSE; 22864 } 22865 else 22866 { 22867 /* We should skip the extension we've just matched the next time 22868 round. */ 22869 opt++; 22870 } 22871 22872 str = ext; 22873 }; 22874 22875 return TRUE; 22876} 22877 22878static bfd_boolean 22879arm_parse_cpu (char * str) 22880{ 22881 const struct arm_cpu_option_table * opt; 22882 char * ext = strchr (str, '+'); 22883 int optlen; 22884 22885 if (ext != NULL) 22886 optlen = ext - str; 22887 else 22888 optlen = strlen (str); 22889 22890 if (optlen == 0) 22891 { 22892 as_bad (_("missing cpu name `%s'"), str); 22893 return FALSE; 22894 } 22895 22896 for (opt = arm_cpus; opt->name != NULL; opt++) 22897 if (strncmp (opt->name, str, optlen) == 0) 22898 { 22899 mcpu_cpu_opt = &opt->value; 22900 mcpu_fpu_opt = &opt->default_fpu; 22901 if (opt->canonical_name) 22902 strcpy (selected_cpu_name, opt->canonical_name); 22903 else 22904 { 22905 int i; 22906 22907 for (i = 0; i < optlen; i++) 22908 selected_cpu_name[i] = TOUPPER (opt->name[i]); 22909 selected_cpu_name[i] = 0; 22910 } 22911 22912 if (ext != NULL) 22913 return arm_parse_extension (ext, &mcpu_cpu_opt); 22914 22915 return TRUE; 22916 } 22917 22918 as_bad (_("unknown cpu `%s'"), str); 22919 return FALSE; 22920} 22921 22922static bfd_boolean 22923arm_parse_arch (char * str) 22924{ 22925 const struct arm_arch_option_table *opt; 22926 char *ext = strchr (str, '+'); 22927 int optlen; 22928 22929 if (ext != NULL) 22930 optlen = ext - str; 22931 else 22932 optlen = strlen (str); 22933 22934 if (optlen == 0) 22935 { 22936 as_bad (_("missing architecture name `%s'"), str); 22937 return FALSE; 22938 } 22939 22940 for (opt = arm_archs; opt->name != NULL; opt++) 22941 if (strncmp (opt->name, str, optlen) == 0) 22942 { 22943 march_cpu_opt = &opt->value; 22944 march_fpu_opt = &opt->default_fpu; 22945 strcpy (selected_cpu_name, opt->name); 22946 22947 if (ext != NULL) 22948 return arm_parse_extension (ext, &march_cpu_opt); 22949 22950 return TRUE; 22951 } 22952 22953 as_bad (_("unknown architecture `%s'\n"), str); 22954 return FALSE; 22955} 22956 22957static bfd_boolean 22958arm_parse_fpu (char * str) 22959{ 22960 const struct arm_option_fpu_value_table * opt; 22961 22962 for (opt = arm_fpus; opt->name != NULL; opt++) 22963 if (streq (opt->name, str)) 22964 { 22965 mfpu_opt = &opt->value; 22966 return TRUE; 22967 } 22968 22969 as_bad (_("unknown floating point format `%s'\n"), str); 22970 return FALSE; 22971} 22972 22973static bfd_boolean 22974arm_parse_float_abi (char * str) 22975{ 22976 const struct arm_option_value_table * opt; 22977 22978 for (opt = arm_float_abis; opt->name != NULL; opt++) 22979 if (streq (opt->name, str)) 22980 { 22981 mfloat_abi_opt = opt->value; 22982 return TRUE; 22983 } 22984 22985 as_bad (_("unknown floating point abi `%s'\n"), str); 22986 return FALSE; 22987} 22988 22989#ifdef OBJ_ELF 22990static bfd_boolean 22991arm_parse_eabi (char * str) 22992{ 22993 const struct arm_option_value_table *opt; 22994 22995 for (opt = arm_eabis; opt->name != NULL; opt++) 22996 if (streq (opt->name, str)) 22997 { 22998 meabi_flags = opt->value; 22999 return TRUE; 23000 } 23001 as_bad (_("unknown EABI `%s'\n"), str); 23002 return FALSE; 23003} 23004#endif 23005 23006static bfd_boolean 23007arm_parse_it_mode (char * str) 23008{ 23009 bfd_boolean ret = TRUE; 23010 23011 if (streq ("arm", str)) 23012 implicit_it_mode = IMPLICIT_IT_MODE_ARM; 23013 else if (streq ("thumb", str)) 23014 implicit_it_mode = IMPLICIT_IT_MODE_THUMB; 23015 else if (streq ("always", str)) 23016 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; 23017 else if (streq ("never", str)) 23018 implicit_it_mode = IMPLICIT_IT_MODE_NEVER; 23019 else 23020 { 23021 as_bad (_("unknown implicit IT mode `%s', should be "\ 23022 "arm, thumb, always, or never."), str); 23023 ret = FALSE; 23024 } 23025 23026 return ret; 23027} 23028 23029struct arm_long_option_table arm_long_opts[] = 23030{ 23031 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), 23032 arm_parse_cpu, NULL}, 23033 {"march=", N_("<arch name>\t assemble for architecture <arch name>"), 23034 arm_parse_arch, NULL}, 23035 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), 23036 arm_parse_fpu, NULL}, 23037 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), 23038 arm_parse_float_abi, NULL}, 23039#ifdef OBJ_ELF 23040 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), 23041 arm_parse_eabi, NULL}, 23042#endif 23043 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), 23044 arm_parse_it_mode, NULL}, 23045 {NULL, NULL, 0, NULL} 23046}; 23047 23048int 23049md_parse_option (int c, char * arg) 23050{ 23051 struct arm_option_table *opt; 23052 const struct arm_legacy_option_table *fopt; 23053 struct arm_long_option_table *lopt; 23054 23055 switch (c) 23056 { 23057#ifdef OPTION_EB 23058 case OPTION_EB: 23059 target_big_endian = 1; 23060 break; 23061#endif 23062 23063#ifdef OPTION_EL 23064 case OPTION_EL: 23065 target_big_endian = 0; 23066 break; 23067#endif 23068 23069 case OPTION_FIX_V4BX: 23070 fix_v4bx = TRUE; 23071 break; 23072 23073 case 'a': 23074 /* Listing option. Just ignore these, we don't support additional 23075 ones. */ 23076 return 0; 23077 23078 default: 23079 for (opt = arm_opts; opt->option != NULL; opt++) 23080 { 23081 if (c == opt->option[0] 23082 && ((arg == NULL && opt->option[1] == 0) 23083 || streq (arg, opt->option + 1))) 23084 { 23085 /* If the option is deprecated, tell the user. */ 23086 if (warn_on_deprecated && opt->deprecated != NULL) 23087 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, 23088 arg ? arg : "", _(opt->deprecated)); 23089 23090 if (opt->var != NULL) 23091 *opt->var = opt->value; 23092 23093 return 1; 23094 } 23095 } 23096 23097 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) 23098 { 23099 if (c == fopt->option[0] 23100 && ((arg == NULL && fopt->option[1] == 0) 23101 || streq (arg, fopt->option + 1))) 23102 { 23103 /* If the option is deprecated, tell the user. */ 23104 if (warn_on_deprecated && fopt->deprecated != NULL) 23105 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, 23106 arg ? arg : "", _(fopt->deprecated)); 23107 23108 if (fopt->var != NULL) 23109 *fopt->var = &fopt->value; 23110 23111 return 1; 23112 } 23113 } 23114 23115 for (lopt = arm_long_opts; lopt->option != NULL; lopt++) 23116 { 23117 /* These options are expected to have an argument. */ 23118 if (c == lopt->option[0] 23119 && arg != NULL 23120 && strncmp (arg, lopt->option + 1, 23121 strlen (lopt->option + 1)) == 0) 23122 { 23123 /* If the option is deprecated, tell the user. */ 23124 if (warn_on_deprecated && lopt->deprecated != NULL) 23125 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, 23126 _(lopt->deprecated)); 23127 23128 /* Call the sup-option parser. */ 23129 return lopt->func (arg + strlen (lopt->option) - 1); 23130 } 23131 } 23132 23133 return 0; 23134 } 23135 23136 return 1; 23137} 23138 23139void 23140md_show_usage (FILE * fp) 23141{ 23142 struct arm_option_table *opt; 23143 struct arm_long_option_table *lopt; 23144 23145 fprintf (fp, _(" ARM-specific assembler options:\n")); 23146 23147 for (opt = arm_opts; opt->option != NULL; opt++) 23148 if (opt->help != NULL) 23149 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); 23150 23151 for (lopt = arm_long_opts; lopt->option != NULL; lopt++) 23152 if (lopt->help != NULL) 23153 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); 23154 23155#ifdef OPTION_EB 23156 fprintf (fp, _("\ 23157 -EB assemble code for a big-endian cpu\n")); 23158#endif 23159 23160#ifdef OPTION_EL 23161 fprintf (fp, _("\ 23162 -EL assemble code for a little-endian cpu\n")); 23163#endif 23164 23165 fprintf (fp, _("\ 23166 --fix-v4bx Allow BX in ARMv4 code\n")); 23167} 23168 23169 23170#ifdef OBJ_ELF 23171typedef struct 23172{ 23173 int val; 23174 arm_feature_set flags; 23175} cpu_arch_ver_table; 23176 23177/* Mapping from CPU features to EABI CPU arch values. Table must be sorted 23178 least features first. */ 23179static const cpu_arch_ver_table cpu_arch_ver[] = 23180{ 23181 {1, ARM_ARCH_V4}, 23182 {2, ARM_ARCH_V4T}, 23183 {3, ARM_ARCH_V5}, 23184 {3, ARM_ARCH_V5T}, 23185 {4, ARM_ARCH_V5TE}, 23186 {5, ARM_ARCH_V5TEJ}, 23187 {6, ARM_ARCH_V6}, 23188 {9, ARM_ARCH_V6K}, 23189 {7, ARM_ARCH_V6Z}, 23190 {11, ARM_ARCH_V6M}, 23191 {12, ARM_ARCH_V6SM}, 23192 {8, ARM_ARCH_V6T2}, 23193 {10, ARM_ARCH_V7A}, 23194 {10, ARM_ARCH_V7R}, 23195 {10, ARM_ARCH_V7M}, 23196 {0, ARM_ARCH_NONE} 23197}; 23198 23199/* Set an attribute if it has not already been set by the user. */ 23200static void 23201aeabi_set_attribute_int (int tag, int value) 23202{ 23203 if (tag < 1 23204 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES 23205 || !attributes_set_explicitly[tag]) 23206 bfd_elf_add_proc_attr_int (stdoutput, tag, value); 23207} 23208 23209static void 23210aeabi_set_attribute_string (int tag, const char *value) 23211{ 23212 if (tag < 1 23213 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES 23214 || !attributes_set_explicitly[tag]) 23215 bfd_elf_add_proc_attr_string (stdoutput, tag, value); 23216} 23217 23218/* Set the public EABI object attributes. */ 23219static void 23220aeabi_set_public_attributes (void) 23221{ 23222 int arch; 23223 int virt_sec = 0; 23224 arm_feature_set flags; 23225 arm_feature_set tmp; 23226 const cpu_arch_ver_table *p; 23227 23228 /* Choose the architecture based on the capabilities of the requested cpu 23229 (if any) and/or the instructions actually used. */ 23230 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); 23231 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); 23232 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); 23233 /*Allow the user to override the reported architecture. */ 23234 if (object_arch) 23235 { 23236 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); 23237 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); 23238 } 23239 23240 /* We need to make sure that the attributes do not identify us as v6S-M 23241 when the only v6S-M feature in use is the Operating System Extensions. */ 23242 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os)) 23243 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only)) 23244 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os); 23245 23246 tmp = flags; 23247 arch = 0; 23248 for (p = cpu_arch_ver; p->val; p++) 23249 { 23250 if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) 23251 { 23252 arch = p->val; 23253 ARM_CLEAR_FEATURE (tmp, tmp, p->flags); 23254 } 23255 } 23256 23257 /* The table lookup above finds the last architecture to contribute 23258 a new feature. Unfortunately, Tag13 is a subset of the union of 23259 v6T2 and v7-M, so it is never seen as contributing a new feature. 23260 We can not search for the last entry which is entirely used, 23261 because if no CPU is specified we build up only those flags 23262 actually used. Perhaps we should separate out the specified 23263 and implicit cases. Avoid taking this path for -march=all by 23264 checking for contradictory v7-A / v7-M features. */ 23265 if (arch == 10 23266 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a) 23267 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m) 23268 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp)) 23269 arch = 13; 23270 23271 /* Tag_CPU_name. */ 23272 if (selected_cpu_name[0]) 23273 { 23274 char *q; 23275 23276 q = selected_cpu_name; 23277 if (strncmp (q, "armv", 4) == 0) 23278 { 23279 int i; 23280 23281 q += 4; 23282 for (i = 0; q[i]; i++) 23283 q[i] = TOUPPER (q[i]); 23284 } 23285 aeabi_set_attribute_string (Tag_CPU_name, q); 23286 } 23287 23288 /* Tag_CPU_arch. */ 23289 aeabi_set_attribute_int (Tag_CPU_arch, arch); 23290 23291 /* Tag_CPU_arch_profile. */ 23292 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) 23293 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A'); 23294 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) 23295 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R'); 23296 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m)) 23297 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M'); 23298 23299 /* Tag_ARM_ISA_use. */ 23300 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) 23301 || arch == 0) 23302 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); 23303 23304 /* Tag_THUMB_ISA_use. */ 23305 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) 23306 || arch == 0) 23307 aeabi_set_attribute_int (Tag_THUMB_ISA_use, 23308 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1); 23309 23310 /* Tag_VFP_arch. */ 23311 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) 23312 aeabi_set_attribute_int (Tag_VFP_arch, 23313 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) 23314 ? 5 : 6); 23315 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) 23316 aeabi_set_attribute_int (Tag_VFP_arch, 3); 23317 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) 23318 aeabi_set_attribute_int (Tag_VFP_arch, 4); 23319 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) 23320 aeabi_set_attribute_int (Tag_VFP_arch, 2); 23321 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) 23322 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) 23323 aeabi_set_attribute_int (Tag_VFP_arch, 1); 23324 23325 /* Tag_ABI_HardFP_use. */ 23326 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) 23327 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) 23328 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); 23329 23330 /* Tag_WMMX_arch. */ 23331 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) 23332 aeabi_set_attribute_int (Tag_WMMX_arch, 2); 23333 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) 23334 aeabi_set_attribute_int (Tag_WMMX_arch, 1); 23335 23336 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ 23337 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) 23338 aeabi_set_attribute_int 23339 (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma) 23340 ? 2 : 1)); 23341 23342 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ 23343 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16)) 23344 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); 23345 23346 /* Tag_DIV_use. */ 23347 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)) 23348 aeabi_set_attribute_int (Tag_DIV_use, 2); 23349 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div)) 23350 aeabi_set_attribute_int (Tag_DIV_use, 0); 23351 else 23352 aeabi_set_attribute_int (Tag_DIV_use, 1); 23353 23354 /* Tag_MP_extension_use. */ 23355 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp)) 23356 aeabi_set_attribute_int (Tag_MPextension_use, 1); 23357 23358 /* Tag Virtualization_use. */ 23359 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec)) 23360 virt_sec |= 1; 23361 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt)) 23362 virt_sec |= 2; 23363 if (virt_sec != 0) 23364 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec); 23365} 23366 23367/* Add the default contents for the .ARM.attributes section. */ 23368void 23369arm_md_end (void) 23370{ 23371 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) 23372 return; 23373 23374 aeabi_set_public_attributes (); 23375} 23376#endif /* OBJ_ELF */ 23377 23378 23379/* Parse a .cpu directive. */ 23380 23381static void 23382s_arm_cpu (int ignored ATTRIBUTE_UNUSED) 23383{ 23384 const struct arm_cpu_option_table *opt; 23385 char *name; 23386 char saved_char; 23387 23388 name = input_line_pointer; 23389 while (*input_line_pointer && !ISSPACE (*input_line_pointer)) 23390 input_line_pointer++; 23391 saved_char = *input_line_pointer; 23392 *input_line_pointer = 0; 23393 23394 /* Skip the first "all" entry. */ 23395 for (opt = arm_cpus + 1; opt->name != NULL; opt++) 23396 if (streq (opt->name, name)) 23397 { 23398 mcpu_cpu_opt = &opt->value; 23399 selected_cpu = opt->value; 23400 if (opt->canonical_name) 23401 strcpy (selected_cpu_name, opt->canonical_name); 23402 else 23403 { 23404 int i; 23405 for (i = 0; opt->name[i]; i++) 23406 selected_cpu_name[i] = TOUPPER (opt->name[i]); 23407 selected_cpu_name[i] = 0; 23408 } 23409 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 23410 *input_line_pointer = saved_char; 23411 demand_empty_rest_of_line (); 23412 return; 23413 } 23414 as_bad (_("unknown cpu `%s'"), name); 23415 *input_line_pointer = saved_char; 23416 ignore_rest_of_line (); 23417} 23418 23419 23420/* Parse a .arch directive. */ 23421 23422static void 23423s_arm_arch (int ignored ATTRIBUTE_UNUSED) 23424{ 23425 const struct arm_arch_option_table *opt; 23426 char saved_char; 23427 char *name; 23428 23429 name = input_line_pointer; 23430 while (*input_line_pointer && !ISSPACE (*input_line_pointer)) 23431 input_line_pointer++; 23432 saved_char = *input_line_pointer; 23433 *input_line_pointer = 0; 23434 23435 /* Skip the first "all" entry. */ 23436 for (opt = arm_archs + 1; opt->name != NULL; opt++) 23437 if (streq (opt->name, name)) 23438 { 23439 mcpu_cpu_opt = &opt->value; 23440 selected_cpu = opt->value; 23441 strcpy (selected_cpu_name, opt->name); 23442 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 23443 *input_line_pointer = saved_char; 23444 demand_empty_rest_of_line (); 23445 return; 23446 } 23447 23448 as_bad (_("unknown architecture `%s'\n"), name); 23449 *input_line_pointer = saved_char; 23450 ignore_rest_of_line (); 23451} 23452 23453 23454/* Parse a .object_arch directive. */ 23455 23456static void 23457s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) 23458{ 23459 const struct arm_arch_option_table *opt; 23460 char saved_char; 23461 char *name; 23462 23463 name = input_line_pointer; 23464 while (*input_line_pointer && !ISSPACE (*input_line_pointer)) 23465 input_line_pointer++; 23466 saved_char = *input_line_pointer; 23467 *input_line_pointer = 0; 23468 23469 /* Skip the first "all" entry. */ 23470 for (opt = arm_archs + 1; opt->name != NULL; opt++) 23471 if (streq (opt->name, name)) 23472 { 23473 object_arch = &opt->value; 23474 *input_line_pointer = saved_char; 23475 demand_empty_rest_of_line (); 23476 return; 23477 } 23478 23479 as_bad (_("unknown architecture `%s'\n"), name); 23480 *input_line_pointer = saved_char; 23481 ignore_rest_of_line (); 23482} 23483 23484/* Parse a .arch_extension directive. */ 23485 23486static void 23487s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) 23488{ 23489 const struct arm_option_extension_value_table *opt; 23490 char saved_char; 23491 char *name; 23492 int adding_value = 1; 23493 23494 name = input_line_pointer; 23495 while (*input_line_pointer && !ISSPACE (*input_line_pointer)) 23496 input_line_pointer++; 23497 saved_char = *input_line_pointer; 23498 *input_line_pointer = 0; 23499 23500 if (strlen (name) >= 2 23501 && strncmp (name, "no", 2) == 0) 23502 { 23503 adding_value = 0; 23504 name += 2; 23505 } 23506 23507 for (opt = arm_extensions; opt->name != NULL; opt++) 23508 if (streq (opt->name, name)) 23509 { 23510 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs)) 23511 { 23512 as_bad (_("architectural extension `%s' is not allowed for the " 23513 "current base architecture"), name); 23514 break; 23515 } 23516 23517 if (adding_value) 23518 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value); 23519 else 23520 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value); 23521 23522 mcpu_cpu_opt = &selected_cpu; 23523 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 23524 *input_line_pointer = saved_char; 23525 demand_empty_rest_of_line (); 23526 return; 23527 } 23528 23529 if (opt->name == NULL) 23530 as_bad (_("unknown architecture `%s'\n"), name); 23531 23532 *input_line_pointer = saved_char; 23533 ignore_rest_of_line (); 23534} 23535 23536/* Parse a .fpu directive. */ 23537 23538static void 23539s_arm_fpu (int ignored ATTRIBUTE_UNUSED) 23540{ 23541 const struct arm_option_fpu_value_table *opt; 23542 char saved_char; 23543 char *name; 23544 23545 name = input_line_pointer; 23546 while (*input_line_pointer && !ISSPACE (*input_line_pointer)) 23547 input_line_pointer++; 23548 saved_char = *input_line_pointer; 23549 *input_line_pointer = 0; 23550 23551 for (opt = arm_fpus; opt->name != NULL; opt++) 23552 if (streq (opt->name, name)) 23553 { 23554 mfpu_opt = &opt->value; 23555 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 23556 *input_line_pointer = saved_char; 23557 demand_empty_rest_of_line (); 23558 return; 23559 } 23560 23561 as_bad (_("unknown floating point format `%s'\n"), name); 23562 *input_line_pointer = saved_char; 23563 ignore_rest_of_line (); 23564} 23565 23566/* Copy symbol information. */ 23567 23568void 23569arm_copy_symbol_attributes (symbolS *dest, symbolS *src) 23570{ 23571 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); 23572} 23573 23574#ifdef OBJ_ELF 23575/* Given a symbolic attribute NAME, return the proper integer value. 23576 Returns -1 if the attribute is not known. */ 23577 23578int 23579arm_convert_symbolic_attribute (const char *name) 23580{ 23581 static const struct 23582 { 23583 const char * name; 23584 const int tag; 23585 } 23586 attribute_table[] = 23587 { 23588 /* When you modify this table you should 23589 also modify the list in doc/c-arm.texi. */ 23590#define T(tag) {#tag, tag} 23591 T (Tag_CPU_raw_name), 23592 T (Tag_CPU_name), 23593 T (Tag_CPU_arch), 23594 T (Tag_CPU_arch_profile), 23595 T (Tag_ARM_ISA_use), 23596 T (Tag_THUMB_ISA_use), 23597 T (Tag_FP_arch), 23598 T (Tag_VFP_arch), 23599 T (Tag_WMMX_arch), 23600 T (Tag_Advanced_SIMD_arch), 23601 T (Tag_PCS_config), 23602 T (Tag_ABI_PCS_R9_use), 23603 T (Tag_ABI_PCS_RW_data), 23604 T (Tag_ABI_PCS_RO_data), 23605 T (Tag_ABI_PCS_GOT_use), 23606 T (Tag_ABI_PCS_wchar_t), 23607 T (Tag_ABI_FP_rounding), 23608 T (Tag_ABI_FP_denormal), 23609 T (Tag_ABI_FP_exceptions), 23610 T (Tag_ABI_FP_user_exceptions), 23611 T (Tag_ABI_FP_number_model), 23612 T (Tag_ABI_align_needed), 23613 T (Tag_ABI_align8_needed), 23614 T (Tag_ABI_align_preserved), 23615 T (Tag_ABI_align8_preserved), 23616 T (Tag_ABI_enum_size), 23617 T (Tag_ABI_HardFP_use), 23618 T (Tag_ABI_VFP_args), 23619 T (Tag_ABI_WMMX_args), 23620 T (Tag_ABI_optimization_goals), 23621 T (Tag_ABI_FP_optimization_goals), 23622 T (Tag_compatibility), 23623 T (Tag_CPU_unaligned_access), 23624 T (Tag_FP_HP_extension), 23625 T (Tag_VFP_HP_extension), 23626 T (Tag_ABI_FP_16bit_format), 23627 T (Tag_MPextension_use), 23628 T (Tag_DIV_use), 23629 T (Tag_nodefaults), 23630 T (Tag_also_compatible_with), 23631 T (Tag_conformance), 23632 T (Tag_T2EE_use), 23633 T (Tag_Virtualization_use), 23634 /* We deliberately do not include Tag_MPextension_use_legacy. */ 23635#undef T 23636 }; 23637 unsigned int i; 23638 23639 if (name == NULL) 23640 return -1; 23641 23642 for (i = 0; i < ARRAY_SIZE (attribute_table); i++) 23643 if (streq (name, attribute_table[i].name)) 23644 return attribute_table[i].tag; 23645 23646 return -1; 23647} 23648 23649 23650/* Apply sym value for relocations only in the case that 23651 they are for local symbols and you have the respective 23652 architectural feature for blx and simple switches. */ 23653int 23654arm_apply_sym_value (struct fix * fixP) 23655{ 23656 if (fixP->fx_addsy 23657 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) 23658 && !S_IS_EXTERNAL (fixP->fx_addsy)) 23659 { 23660 switch (fixP->fx_r_type) 23661 { 23662 case BFD_RELOC_ARM_PCREL_BLX: 23663 case BFD_RELOC_THUMB_PCREL_BRANCH23: 23664 if (ARM_IS_FUNC (fixP->fx_addsy)) 23665 return 1; 23666 break; 23667 23668 case BFD_RELOC_ARM_PCREL_CALL: 23669 case BFD_RELOC_THUMB_PCREL_BLX: 23670 if (THUMB_IS_FUNC (fixP->fx_addsy)) 23671 return 1; 23672 break; 23673 23674 default: 23675 break; 23676 } 23677 23678 } 23679 return 0; 23680} 23681#endif /* OBJ_ELF */ 23682