1/* 2 * Copyright (c) 1999 Apple Computer, Inc. All rights reserved. 3 * 4 * @APPLE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. Please obtain a copy of the License at 10 * http://www.opensource.apple.com/apsl/ and read it before using this 11 * file. 12 * 13 * The Original Code and all software distributed under the License are 14 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 15 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 16 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 18 * Please see the License for the specific language governing rights and 19 * limitations under the License. 20 * 21 * @APPLE_LICENSE_HEADER_END@ 22 */ 23#ifndef RLD 24#include <string.h> 25#import <mach-o/sparc/swap.h> 26#import <architecture/nrw/reg_help.h> 27 28void 29swap_sparc_thread_state_regs( 30struct sparc_thread_state_regs *cpu, 31enum NXByteOrder target_byte_sex) 32{ 33 struct swapped_psr { 34 union { 35 struct { 36 unsigned int 37 cwp:BITS_WIDTH(4,0), 38 et:BIT_WIDTH(5), 39 ps:BIT_WIDTH(6), 40 s:BIT_WIDTH(7), 41 pil:BITS_WIDTH(11,8), 42 ef:BIT_WIDTH(12), 43 ec:BIT_WIDTH(13), 44 reserved:BITS_WIDTH(19,14), 45 icc:BITS_WIDTH(23,20), 46 ver:BITS_WIDTH(27,24), 47 impl:BITS_WIDTH(31,28); 48 } fields; 49 unsigned int word; 50 } u; 51 } spsr; 52 struct p_status *pr_status; 53 enum NXByteOrder host_byte_sex; 54 55 host_byte_sex = NXHostByteOrder(); 56 57 cpu->regs.r_pc = OSSwapInt32(cpu->regs.r_pc); 58 cpu->regs.r_npc = OSSwapInt32(cpu->regs.r_npc); 59 cpu->regs.r_y = OSSwapInt32(cpu->regs.r_y); 60 cpu->regs.r_g1 = OSSwapInt32(cpu->regs.r_g1); 61 cpu->regs.r_g2 = OSSwapInt32(cpu->regs.r_g2); 62 cpu->regs.r_g3 = OSSwapInt32(cpu->regs.r_g3); 63 cpu->regs.r_g4 = OSSwapInt32(cpu->regs.r_g4); 64 cpu->regs.r_g5 = OSSwapInt32(cpu->regs.r_g5); 65 cpu->regs.r_g6 = OSSwapInt32(cpu->regs.r_g6); 66 cpu->regs.r_g7 = OSSwapInt32(cpu->regs.r_g7); 67 cpu->regs.r_o0 = OSSwapInt32(cpu->regs.r_o0); 68 cpu->regs.r_o1 = OSSwapInt32(cpu->regs.r_o1); 69 cpu->regs.r_o2 = OSSwapInt32(cpu->regs.r_o2); 70 cpu->regs.r_o3 = OSSwapInt32(cpu->regs.r_o3); 71 cpu->regs.r_o4 = OSSwapInt32(cpu->regs.r_o4); 72 cpu->regs.r_o5 = OSSwapInt32(cpu->regs.r_o5); 73 cpu->regs.r_o6 = OSSwapInt32(cpu->regs.r_o6); 74 cpu->regs.r_o7 = OSSwapInt32(cpu->regs.r_o7); 75 76 pr_status = (struct p_status *) &(cpu->regs.r_psr); 77 if(target_byte_sex == host_byte_sex){ 78 memcpy(&spsr, &(cpu->regs.r_psr), sizeof(struct swapped_psr)); 79 spsr.u.word = OSSwapInt32(spsr.u.word); 80 pr_status->PSRREG.psr_bits.cwp = spsr.u.fields.cwp; 81 pr_status->PSRREG.psr_bits.ps = spsr.u.fields.ps; 82 pr_status->PSRREG.psr_bits.s = spsr.u.fields.s; 83 pr_status->PSRREG.psr_bits.pil = spsr.u.fields.pil; 84 pr_status->PSRREG.psr_bits.ef = spsr.u.fields.ef; 85 pr_status->PSRREG.psr_bits.ec = spsr.u.fields.ec; 86 pr_status->PSRREG.psr_bits.reserved = spsr.u.fields.reserved; 87 pr_status->PSRREG.psr_bits.icc = spsr.u.fields.icc; 88 pr_status->PSRREG.psr_bits.et = spsr.u.fields.ver; 89 pr_status->PSRREG.psr_bits.impl = spsr.u.fields.impl; 90 } 91 else{ 92 spsr.u.fields.cwp = pr_status->PSRREG.psr_bits.cwp; 93 spsr.u.fields.ps = pr_status->PSRREG.psr_bits.ps; 94 spsr.u.fields.s = pr_status->PSRREG.psr_bits.s; 95 spsr.u.fields.pil = pr_status->PSRREG.psr_bits.pil; 96 spsr.u.fields.ef = pr_status->PSRREG.psr_bits.ef; 97 spsr.u.fields.ec = pr_status->PSRREG.psr_bits.ec; 98 spsr.u.fields.reserved = pr_status->PSRREG.psr_bits.reserved; 99 spsr.u.fields.icc = pr_status->PSRREG.psr_bits.icc; 100 spsr.u.fields.ver = pr_status->PSRREG.psr_bits.et; 101 spsr.u.fields.impl = pr_status->PSRREG.psr_bits.impl; 102 spsr.u.word = OSSwapInt32(spsr.u.word); 103 memcpy(&(cpu->regs.r_psr), &spsr, sizeof(struct swapped_psr)); 104 } 105} 106 107void 108swap_sparc_thread_state_fpu( 109struct sparc_thread_state_fpu *fpu, 110enum NXByteOrder target_byte_sex) 111{ 112 struct swapped_fsr { 113 union { 114 struct { 115 unsigned int 116 cexc:BITS_WIDTH(4,0), 117 aexc:BITS_WIDTH(9,5), 118 fcc:BITS_WIDTH(11,10), 119 pr:BIT_WIDTH(12), 120 qne:BIT_WIDTH(13), 121 ftt:BITS_WIDTH(16,14), 122 res:BITS_WIDTH(22,17), 123 tem:BITS_WIDTH(27,23), 124 rp:BITS_WIDTH(29,28), 125 rd:BITS_WIDTH(31,30); 126 } fields; 127 unsigned int word; 128 } u; 129 } sfsr; 130 uint32_t i; 131 struct f_status *fpu_status; 132 enum NXByteOrder host_byte_sex; 133 134 host_byte_sex = NXHostByteOrder(); 135 136 137 /* floating point registers */ 138 for(i = 0; i < 16; i++) /* 16 doubles */ 139 fpu->fpu.fpu_fr.Fpu_dregs[i] = 140 OSSwapInt64(fpu->fpu.fpu_fr.Fpu_dregs[i]); 141 142 fpu->fpu.Fpu_q[0].FQu.whole = OSSwapInt64(fpu->fpu.Fpu_q[0].FQu.whole); 143 fpu->fpu.Fpu_q[1].FQu.whole = OSSwapInt64(fpu->fpu.Fpu_q[1].FQu.whole); 144 fpu->fpu.Fpu_flags = OSSwapInt32(fpu->fpu.Fpu_flags); 145 fpu->fpu.Fpu_extra = OSSwapInt32(fpu->fpu.Fpu_extra); 146 fpu->fpu.Fpu_qcnt = OSSwapInt32(fpu->fpu.Fpu_qcnt); 147 148 fpu_status = (struct f_status *) &(fpu->fpu.Fpu_fsr); 149 if(target_byte_sex == host_byte_sex){ 150 memcpy(&sfsr, &(fpu->fpu.Fpu_fsr), sizeof(unsigned int)); 151 sfsr.u.word = OSSwapInt32(sfsr.u.word); 152 fpu_status->FPUREG.Fpu_fsr_bits.rd = sfsr.u.fields.rd; 153 fpu_status->FPUREG.Fpu_fsr_bits.rp = sfsr.u.fields.rp; 154 fpu_status->FPUREG.Fpu_fsr_bits.tem = sfsr.u.fields.tem; 155 fpu_status->FPUREG.Fpu_fsr_bits.res = sfsr.u.fields.res; 156 fpu_status->FPUREG.Fpu_fsr_bits.ftt = sfsr.u.fields.ftt; 157 fpu_status->FPUREG.Fpu_fsr_bits.qne = sfsr.u.fields.qne; 158 fpu_status->FPUREG.Fpu_fsr_bits.pr = sfsr.u.fields.pr; 159 fpu_status->FPUREG.Fpu_fsr_bits.fcc = sfsr.u.fields.fcc; 160 fpu_status->FPUREG.Fpu_fsr_bits.aexc = sfsr.u.fields.aexc; 161 fpu_status->FPUREG.Fpu_fsr_bits.cexc = sfsr.u.fields.cexc; 162 } 163 else{ 164 sfsr.u.fields.rd = fpu_status->FPUREG.Fpu_fsr_bits.rd; 165 sfsr.u.fields.rp = fpu_status->FPUREG.Fpu_fsr_bits.rp; 166 sfsr.u.fields.tem = fpu_status->FPUREG.Fpu_fsr_bits.tem; 167 sfsr.u.fields.res = fpu_status->FPUREG.Fpu_fsr_bits.res; 168 sfsr.u.fields.ftt = fpu_status->FPUREG.Fpu_fsr_bits.ftt; 169 sfsr.u.fields.qne = fpu_status->FPUREG.Fpu_fsr_bits.qne; 170 sfsr.u.fields.pr = fpu_status->FPUREG.Fpu_fsr_bits.pr; 171 sfsr.u.fields.fcc = fpu_status->FPUREG.Fpu_fsr_bits.fcc; 172 sfsr.u.fields.aexc = fpu_status->FPUREG.Fpu_fsr_bits.aexc; 173 sfsr.u.fields.cexc = fpu_status->FPUREG.Fpu_fsr_bits.cexc; 174 sfsr.u.word = OSSwapInt32(sfsr.u.word); 175 memcpy(&(fpu->fpu.Fpu_fsr), &sfsr, sizeof(struct swapped_fsr)); 176 } 177} 178#endif /* !defined(RLD) */ 179