1/* SPDX-License-Identifier: GPL-2.0-or-later 2 * 3 * Copyright (C) 2005 David Brownell 4 */ 5 6#ifndef __LINUX_SPI_H 7#define __LINUX_SPI_H 8 9#include <linux/acpi.h> 10#include <linux/bits.h> 11#include <linux/completion.h> 12#include <linux/device.h> 13#include <linux/gpio/consumer.h> 14#include <linux/kthread.h> 15#include <linux/mod_devicetable.h> 16#include <linux/overflow.h> 17#include <linux/scatterlist.h> 18#include <linux/slab.h> 19#include <linux/u64_stats_sync.h> 20 21#include <uapi/linux/spi/spi.h> 22 23/* Max no. of CS supported per spi device */ 24#define SPI_CS_CNT_MAX 16 25 26struct dma_chan; 27struct software_node; 28struct ptp_system_timestamp; 29struct spi_controller; 30struct spi_transfer; 31struct spi_controller_mem_ops; 32struct spi_controller_mem_caps; 33struct spi_message; 34 35/* 36 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers, 37 * and SPI infrastructure. 38 */ 39extern const struct bus_type spi_bus_type; 40 41/** 42 * struct spi_statistics - statistics for spi transfers 43 * @syncp: seqcount to protect members in this struct for per-cpu update 44 * on 32-bit systems 45 * 46 * @messages: number of spi-messages handled 47 * @transfers: number of spi_transfers handled 48 * @errors: number of errors during spi_transfer 49 * @timedout: number of timeouts during spi_transfer 50 * 51 * @spi_sync: number of times spi_sync is used 52 * @spi_sync_immediate: 53 * number of times spi_sync is executed immediately 54 * in calling context without queuing and scheduling 55 * @spi_async: number of times spi_async is used 56 * 57 * @bytes: number of bytes transferred to/from device 58 * @bytes_tx: number of bytes sent to device 59 * @bytes_rx: number of bytes received from device 60 * 61 * @transfer_bytes_histo: 62 * transfer bytes histogram 63 * 64 * @transfers_split_maxsize: 65 * number of transfers that have been split because of 66 * maxsize limit 67 */ 68struct spi_statistics { 69 struct u64_stats_sync syncp; 70 71 u64_stats_t messages; 72 u64_stats_t transfers; 73 u64_stats_t errors; 74 u64_stats_t timedout; 75 76 u64_stats_t spi_sync; 77 u64_stats_t spi_sync_immediate; 78 u64_stats_t spi_async; 79 80 u64_stats_t bytes; 81 u64_stats_t bytes_rx; 82 u64_stats_t bytes_tx; 83 84#define SPI_STATISTICS_HISTO_SIZE 17 85 u64_stats_t transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE]; 86 87 u64_stats_t transfers_split_maxsize; 88}; 89 90#define SPI_STATISTICS_ADD_TO_FIELD(pcpu_stats, field, count) \ 91 do { \ 92 struct spi_statistics *__lstats; \ 93 get_cpu(); \ 94 __lstats = this_cpu_ptr(pcpu_stats); \ 95 u64_stats_update_begin(&__lstats->syncp); \ 96 u64_stats_add(&__lstats->field, count); \ 97 u64_stats_update_end(&__lstats->syncp); \ 98 put_cpu(); \ 99 } while (0) 100 101#define SPI_STATISTICS_INCREMENT_FIELD(pcpu_stats, field) \ 102 do { \ 103 struct spi_statistics *__lstats; \ 104 get_cpu(); \ 105 __lstats = this_cpu_ptr(pcpu_stats); \ 106 u64_stats_update_begin(&__lstats->syncp); \ 107 u64_stats_inc(&__lstats->field); \ 108 u64_stats_update_end(&__lstats->syncp); \ 109 put_cpu(); \ 110 } while (0) 111 112/** 113 * struct spi_delay - SPI delay information 114 * @value: Value for the delay 115 * @unit: Unit for the delay 116 */ 117struct spi_delay { 118#define SPI_DELAY_UNIT_USECS 0 119#define SPI_DELAY_UNIT_NSECS 1 120#define SPI_DELAY_UNIT_SCK 2 121 u16 value; 122 u8 unit; 123}; 124 125extern int spi_delay_to_ns(struct spi_delay *_delay, struct spi_transfer *xfer); 126extern int spi_delay_exec(struct spi_delay *_delay, struct spi_transfer *xfer); 127extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg, 128 struct spi_transfer *xfer); 129 130/** 131 * struct spi_device - Controller side proxy for an SPI slave device 132 * @dev: Driver model representation of the device. 133 * @controller: SPI controller used with the device. 134 * @max_speed_hz: Maximum clock rate to be used with this chip 135 * (on this board); may be changed by the device's driver. 136 * The spi_transfer.speed_hz can override this for each transfer. 137 * @chip_select: Array of physical chipselect, spi->chipselect[i] gives 138 * the corresponding physical CS for logical CS i. 139 * @mode: The spi mode defines how data is clocked out and in. 140 * This may be changed by the device's driver. 141 * The "active low" default for chipselect mode can be overridden 142 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for 143 * each word in a transfer (by specifying SPI_LSB_FIRST). 144 * @bits_per_word: Data transfers involve one or more words; word sizes 145 * like eight or 12 bits are common. In-memory wordsizes are 146 * powers of two bytes (e.g. 20 bit samples use 32 bits). 147 * This may be changed by the device's driver, or left at the 148 * default (0) indicating protocol words are eight bit bytes. 149 * The spi_transfer.bits_per_word can override this for each transfer. 150 * @rt: Make the pump thread real time priority. 151 * @irq: Negative, or the number passed to request_irq() to receive 152 * interrupts from this device. 153 * @controller_state: Controller's runtime state 154 * @controller_data: Board-specific definitions for controller, such as 155 * FIFO initialization parameters; from board_info.controller_data 156 * @modalias: Name of the driver to use with this device, or an alias 157 * for that name. This appears in the sysfs "modalias" attribute 158 * for driver coldplugging, and in uevents used for hotplugging 159 * @driver_override: If the name of a driver is written to this attribute, then 160 * the device will bind to the named driver and only the named driver. 161 * Do not set directly, because core frees it; use driver_set_override() to 162 * set or clear it. 163 * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect lines 164 * (optional, NULL when not using a GPIO line) 165 * @word_delay: delay to be inserted between consecutive 166 * words of a transfer 167 * @cs_setup: delay to be introduced by the controller after CS is asserted 168 * @cs_hold: delay to be introduced by the controller before CS is deasserted 169 * @cs_inactive: delay to be introduced by the controller after CS is 170 * deasserted. If @cs_change_delay is used from @spi_transfer, then the 171 * two delays will be added up. 172 * @pcpu_statistics: statistics for the spi_device 173 * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array 174 * 175 * A @spi_device is used to interchange data between an SPI slave 176 * (usually a discrete chip) and CPU memory. 177 * 178 * In @dev, the platform_data is used to hold information about this 179 * device that's meaningful to the device's protocol driver, but not 180 * to its controller. One example might be an identifier for a chip 181 * variant with slightly different functionality; another might be 182 * information about how this particular board wires the chip's pins. 183 */ 184struct spi_device { 185 struct device dev; 186 struct spi_controller *controller; 187 u32 max_speed_hz; 188 u8 chip_select[SPI_CS_CNT_MAX]; 189 u8 bits_per_word; 190 bool rt; 191#define SPI_NO_TX BIT(31) /* No transmit wire */ 192#define SPI_NO_RX BIT(30) /* No receive wire */ 193 /* 194 * TPM specification defines flow control over SPI. Client device 195 * can insert a wait state on MISO when address is transmitted by 196 * controller on MOSI. Detecting the wait state in software is only 197 * possible for full duplex controllers. For controllers that support 198 * only half-duplex, the wait state detection needs to be implemented 199 * in hardware. TPM devices would set this flag when hardware flow 200 * control is expected from SPI controller. 201 */ 202#define SPI_TPM_HW_FLOW BIT(29) /* TPM HW flow control */ 203 /* 204 * All bits defined above should be covered by SPI_MODE_KERNEL_MASK. 205 * The SPI_MODE_KERNEL_MASK has the SPI_MODE_USER_MASK counterpart, 206 * which is defined in 'include/uapi/linux/spi/spi.h'. 207 * The bits defined here are from bit 31 downwards, while in 208 * SPI_MODE_USER_MASK are from 0 upwards. 209 * These bits must not overlap. A static assert check should make sure of that. 210 * If adding extra bits, make sure to decrease the bit index below as well. 211 */ 212#define SPI_MODE_KERNEL_MASK (~(BIT(29) - 1)) 213 u32 mode; 214 int irq; 215 void *controller_state; 216 void *controller_data; 217 char modalias[SPI_NAME_SIZE]; 218 const char *driver_override; 219 struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /* Chip select gpio desc */ 220 struct spi_delay word_delay; /* Inter-word delay */ 221 /* CS delays */ 222 struct spi_delay cs_setup; 223 struct spi_delay cs_hold; 224 struct spi_delay cs_inactive; 225 226 /* The statistics */ 227 struct spi_statistics __percpu *pcpu_statistics; 228 229 /* Bit mask of the chipselect(s) that the driver need to use from 230 * the chipselect array.When the controller is capable to handle 231 * multiple chip selects & memories are connected in parallel 232 * then more than one bit need to be set in cs_index_mask. 233 */ 234 u32 cs_index_mask : SPI_CS_CNT_MAX; 235 236 /* 237 * Likely need more hooks for more protocol options affecting how 238 * the controller talks to each chip, like: 239 * - memory packing (12 bit samples into low bits, others zeroed) 240 * - priority 241 * - chipselect delays 242 * - ... 243 */ 244}; 245 246/* Make sure that SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK don't overlap */ 247static_assert((SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK) == 0, 248 "SPI_MODE_USER_MASK & SPI_MODE_KERNEL_MASK must not overlap"); 249 250static inline struct spi_device *to_spi_device(const struct device *dev) 251{ 252 return dev ? container_of(dev, struct spi_device, dev) : NULL; 253} 254 255/* Most drivers won't need to care about device refcounting */ 256static inline struct spi_device *spi_dev_get(struct spi_device *spi) 257{ 258 return (spi && get_device(&spi->dev)) ? spi : NULL; 259} 260 261static inline void spi_dev_put(struct spi_device *spi) 262{ 263 if (spi) 264 put_device(&spi->dev); 265} 266 267/* ctldata is for the bus_controller driver's runtime state */ 268static inline void *spi_get_ctldata(const struct spi_device *spi) 269{ 270 return spi->controller_state; 271} 272 273static inline void spi_set_ctldata(struct spi_device *spi, void *state) 274{ 275 spi->controller_state = state; 276} 277 278/* Device driver data */ 279 280static inline void spi_set_drvdata(struct spi_device *spi, void *data) 281{ 282 dev_set_drvdata(&spi->dev, data); 283} 284 285static inline void *spi_get_drvdata(const struct spi_device *spi) 286{ 287 return dev_get_drvdata(&spi->dev); 288} 289 290static inline u8 spi_get_chipselect(const struct spi_device *spi, u8 idx) 291{ 292 return spi->chip_select[idx]; 293} 294 295static inline void spi_set_chipselect(struct spi_device *spi, u8 idx, u8 chipselect) 296{ 297 spi->chip_select[idx] = chipselect; 298} 299 300static inline struct gpio_desc *spi_get_csgpiod(const struct spi_device *spi, u8 idx) 301{ 302 return spi->cs_gpiod[idx]; 303} 304 305static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx, struct gpio_desc *csgpiod) 306{ 307 spi->cs_gpiod[idx] = csgpiod; 308} 309 310static inline bool spi_is_csgpiod(struct spi_device *spi) 311{ 312 u8 idx; 313 314 for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) { 315 if (spi_get_csgpiod(spi, idx)) 316 return true; 317 } 318 return false; 319} 320 321/** 322 * struct spi_driver - Host side "protocol" driver 323 * @id_table: List of SPI devices supported by this driver 324 * @probe: Binds this driver to the SPI device. Drivers can verify 325 * that the device is actually present, and may need to configure 326 * characteristics (such as bits_per_word) which weren't needed for 327 * the initial configuration done during system setup. 328 * @remove: Unbinds this driver from the SPI device 329 * @shutdown: Standard shutdown callback used during system state 330 * transitions such as powerdown/halt and kexec 331 * @driver: SPI device drivers should initialize the name and owner 332 * field of this structure. 333 * 334 * This represents the kind of device driver that uses SPI messages to 335 * interact with the hardware at the other end of a SPI link. It's called 336 * a "protocol" driver because it works through messages rather than talking 337 * directly to SPI hardware (which is what the underlying SPI controller 338 * driver does to pass those messages). These protocols are defined in the 339 * specification for the device(s) supported by the driver. 340 * 341 * As a rule, those device protocols represent the lowest level interface 342 * supported by a driver, and it will support upper level interfaces too. 343 * Examples of such upper levels include frameworks like MTD, networking, 344 * MMC, RTC, filesystem character device nodes, and hardware monitoring. 345 */ 346struct spi_driver { 347 const struct spi_device_id *id_table; 348 int (*probe)(struct spi_device *spi); 349 void (*remove)(struct spi_device *spi); 350 void (*shutdown)(struct spi_device *spi); 351 struct device_driver driver; 352}; 353 354static inline struct spi_driver *to_spi_driver(struct device_driver *drv) 355{ 356 return drv ? container_of(drv, struct spi_driver, driver) : NULL; 357} 358 359extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv); 360 361/** 362 * spi_unregister_driver - reverse effect of spi_register_driver 363 * @sdrv: the driver to unregister 364 * Context: can sleep 365 */ 366static inline void spi_unregister_driver(struct spi_driver *sdrv) 367{ 368 if (sdrv) 369 driver_unregister(&sdrv->driver); 370} 371 372extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 chip_select); 373 374/* Use a define to avoid include chaining to get THIS_MODULE */ 375#define spi_register_driver(driver) \ 376 __spi_register_driver(THIS_MODULE, driver) 377 378/** 379 * module_spi_driver() - Helper macro for registering a SPI driver 380 * @__spi_driver: spi_driver struct 381 * 382 * Helper macro for SPI drivers which do not do anything special in module 383 * init/exit. This eliminates a lot of boilerplate. Each module may only 384 * use this macro once, and calling it replaces module_init() and module_exit() 385 */ 386#define module_spi_driver(__spi_driver) \ 387 module_driver(__spi_driver, spi_register_driver, \ 388 spi_unregister_driver) 389 390/** 391 * struct spi_controller - interface to SPI master or slave controller 392 * @dev: device interface to this driver 393 * @list: link with the global spi_controller list 394 * @bus_num: board-specific (and often SOC-specific) identifier for a 395 * given SPI controller. 396 * @num_chipselect: chipselects are used to distinguish individual 397 * SPI slaves, and are numbered from zero to num_chipselects. 398 * each slave has a chipselect signal, but it's common that not 399 * every chipselect is connected to a slave. 400 * @dma_alignment: SPI controller constraint on DMA buffers alignment. 401 * @mode_bits: flags understood by this controller driver 402 * @buswidth_override_bits: flags to override for this controller driver 403 * @bits_per_word_mask: A mask indicating which values of bits_per_word are 404 * supported by the driver. Bit n indicates that a bits_per_word n+1 is 405 * supported. If set, the SPI core will reject any transfer with an 406 * unsupported bits_per_word. If not set, this value is simply ignored, 407 * and it's up to the individual driver to perform any validation. 408 * @min_speed_hz: Lowest supported transfer speed 409 * @max_speed_hz: Highest supported transfer speed 410 * @flags: other constraints relevant to this driver 411 * @slave: indicates that this is an SPI slave controller 412 * @target: indicates that this is an SPI target controller 413 * @devm_allocated: whether the allocation of this struct is devres-managed 414 * @max_transfer_size: function that returns the max transfer size for 415 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 416 * @max_message_size: function that returns the max message size for 417 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 418 * @io_mutex: mutex for physical bus access 419 * @add_lock: mutex to avoid adding devices to the same chipselect 420 * @bus_lock_spinlock: spinlock for SPI bus locking 421 * @bus_lock_mutex: mutex for exclusion of multiple callers 422 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use 423 * @setup: updates the device mode and clocking records used by a 424 * device's SPI controller; protocol code may call this. This 425 * must fail if an unrecognized or unsupported mode is requested. 426 * It's always safe to call this unless transfers are pending on 427 * the device whose settings are being modified. 428 * @set_cs_timing: optional hook for SPI devices to request SPI master 429 * controller for configuring specific CS setup time, hold time and inactive 430 * delay interms of clock counts 431 * @transfer: adds a message to the controller's transfer queue. 432 * @cleanup: frees controller-specific state 433 * @can_dma: determine whether this controller supports DMA 434 * @dma_map_dev: device which can be used for DMA mapping 435 * @cur_rx_dma_dev: device which is currently used for RX DMA mapping 436 * @cur_tx_dma_dev: device which is currently used for TX DMA mapping 437 * @queued: whether this controller is providing an internal message queue 438 * @kworker: pointer to thread struct for message pump 439 * @pump_messages: work struct for scheduling work to the message pump 440 * @queue_lock: spinlock to synchronise access to message queue 441 * @queue: message queue 442 * @cur_msg: the currently in-flight message 443 * @cur_msg_completion: a completion for the current in-flight message 444 * @cur_msg_incomplete: Flag used internally to opportunistically skip 445 * the @cur_msg_completion. This flag is used to check if the driver has 446 * already called spi_finalize_current_message(). 447 * @cur_msg_need_completion: Flag used internally to opportunistically skip 448 * the @cur_msg_completion. This flag is used to signal the context that 449 * is running spi_finalize_current_message() that it needs to complete() 450 * @cur_msg_mapped: message has been mapped for DMA 451 * @fallback: fallback to PIO if DMA transfer return failure with 452 * SPI_TRANS_FAIL_NO_START. 453 * @last_cs_mode_high: was (mode & SPI_CS_HIGH) true on the last call to set_cs. 454 * @last_cs: the last chip_select that is recorded by set_cs, -1 on non chip 455 * selected 456 * @last_cs_index_mask: bit mask the last chip selects that were used 457 * @xfer_completion: used by core transfer_one_message() 458 * @busy: message pump is busy 459 * @running: message pump is running 460 * @rt: whether this queue is set to run as a realtime task 461 * @auto_runtime_pm: the core should ensure a runtime PM reference is held 462 * while the hardware is prepared, using the parent 463 * device for the spidev 464 * @max_dma_len: Maximum length of a DMA transfer for the device. 465 * @prepare_transfer_hardware: a message will soon arrive from the queue 466 * so the subsystem requests the driver to prepare the transfer hardware 467 * by issuing this call 468 * @transfer_one_message: the subsystem calls the driver to transfer a single 469 * message while queuing transfers that arrive in the meantime. When the 470 * driver is finished with this message, it must call 471 * spi_finalize_current_message() so the subsystem can issue the next 472 * message 473 * @unprepare_transfer_hardware: there are currently no more messages on the 474 * queue so the subsystem notifies the driver that it may relax the 475 * hardware by issuing this call 476 * 477 * @set_cs: set the logic level of the chip select line. May be called 478 * from interrupt context. 479 * @optimize_message: optimize the message for reuse 480 * @unoptimize_message: release resources allocated by optimize_message 481 * @prepare_message: set up the controller to transfer a single message, 482 * for example doing DMA mapping. Called from threaded 483 * context. 484 * @transfer_one: transfer a single spi_transfer. 485 * 486 * - return 0 if the transfer is finished, 487 * - return 1 if the transfer is still in progress. When 488 * the driver is finished with this transfer it must 489 * call spi_finalize_current_transfer() so the subsystem 490 * can issue the next transfer. If the transfer fails, the 491 * driver must set the flag SPI_TRANS_FAIL_IO to 492 * spi_transfer->error first, before calling 493 * spi_finalize_current_transfer(). 494 * Note: transfer_one and transfer_one_message are mutually 495 * exclusive; when both are set, the generic subsystem does 496 * not call your transfer_one callback. 497 * @handle_err: the subsystem calls the driver to handle an error that occurs 498 * in the generic implementation of transfer_one_message(). 499 * @mem_ops: optimized/dedicated operations for interactions with SPI memory. 500 * This field is optional and should only be implemented if the 501 * controller has native support for memory like operations. 502 * @mem_caps: controller capabilities for the handling of memory operations. 503 * @unprepare_message: undo any work done by prepare_message(). 504 * @slave_abort: abort the ongoing transfer request on an SPI slave controller 505 * @target_abort: abort the ongoing transfer request on an SPI target controller 506 * @cs_gpiods: Array of GPIO descriptors to use as chip select lines; one per CS 507 * number. Any individual value may be NULL for CS lines that 508 * are not GPIOs (driven by the SPI controller itself). 509 * @use_gpio_descriptors: Turns on the code in the SPI core to parse and grab 510 * GPIO descriptors. This will fill in @cs_gpiods and SPI devices will have 511 * the cs_gpiod assigned if a GPIO line is found for the chipselect. 512 * @unused_native_cs: When cs_gpiods is used, spi_register_controller() will 513 * fill in this field with the first unused native CS, to be used by SPI 514 * controller drivers that need to drive a native CS when using GPIO CS. 515 * @max_native_cs: When cs_gpiods is used, and this field is filled in, 516 * spi_register_controller() will validate all native CS (including the 517 * unused native CS) against this value. 518 * @pcpu_statistics: statistics for the spi_controller 519 * @dma_tx: DMA transmit channel 520 * @dma_rx: DMA receive channel 521 * @dummy_rx: dummy receive buffer for full-duplex devices 522 * @dummy_tx: dummy transmit buffer for full-duplex devices 523 * @fw_translate_cs: If the boot firmware uses different numbering scheme 524 * what Linux expects, this optional hook can be used to translate 525 * between the two. 526 * @ptp_sts_supported: If the driver sets this to true, it must provide a 527 * time snapshot in @spi_transfer->ptp_sts as close as possible to the 528 * moment in time when @spi_transfer->ptp_sts_word_pre and 529 * @spi_transfer->ptp_sts_word_post were transmitted. 530 * If the driver does not set this, the SPI core takes the snapshot as 531 * close to the driver hand-over as possible. 532 * @irq_flags: Interrupt enable state during PTP system timestamping 533 * @queue_empty: signal green light for opportunistically skipping the queue 534 * for spi_sync transfers. 535 * @must_async: disable all fast paths in the core 536 * 537 * Each SPI controller can communicate with one or more @spi_device 538 * children. These make a small bus, sharing MOSI, MISO and SCK signals 539 * but not chip select signals. Each device may be configured to use a 540 * different clock rate, since those shared signals are ignored unless 541 * the chip is selected. 542 * 543 * The driver for an SPI controller manages access to those devices through 544 * a queue of spi_message transactions, copying data between CPU memory and 545 * an SPI slave device. For each such message it queues, it calls the 546 * message's completion function when the transaction completes. 547 */ 548struct spi_controller { 549 struct device dev; 550 551 struct list_head list; 552 553 /* 554 * Other than negative (== assign one dynamically), bus_num is fully 555 * board-specific. Usually that simplifies to being SoC-specific. 556 * example: one SoC has three SPI controllers, numbered 0..2, 557 * and one board's schematics might show it using SPI-2. Software 558 * would normally use bus_num=2 for that controller. 559 */ 560 s16 bus_num; 561 562 /* 563 * Chipselects will be integral to many controllers; some others 564 * might use board-specific GPIOs. 565 */ 566 u16 num_chipselect; 567 568 /* Some SPI controllers pose alignment requirements on DMAable 569 * buffers; let protocol drivers know about these requirements. 570 */ 571 u16 dma_alignment; 572 573 /* spi_device.mode flags understood by this controller driver */ 574 u32 mode_bits; 575 576 /* spi_device.mode flags override flags for this controller */ 577 u32 buswidth_override_bits; 578 579 /* Bitmask of supported bits_per_word for transfers */ 580 u32 bits_per_word_mask; 581#define SPI_BPW_MASK(bits) BIT((bits) - 1) 582#define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1) 583 584 /* Limits on transfer speed */ 585 u32 min_speed_hz; 586 u32 max_speed_hz; 587 588 /* Other constraints relevant to this driver */ 589 u16 flags; 590#define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* Can't do full duplex */ 591#define SPI_CONTROLLER_NO_RX BIT(1) /* Can't do buffer read */ 592#define SPI_CONTROLLER_NO_TX BIT(2) /* Can't do buffer write */ 593#define SPI_CONTROLLER_MUST_RX BIT(3) /* Requires rx */ 594#define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx */ 595#define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS must select slave */ 596#define SPI_CONTROLLER_SUSPENDED BIT(6) /* Currently suspended */ 597 /* 598 * The spi-controller has multi chip select capability and can 599 * assert/de-assert more than one chip select at once. 600 */ 601#define SPI_CONTROLLER_MULTI_CS BIT(7) 602 603 /* Flag indicating if the allocation of this struct is devres-managed */ 604 bool devm_allocated; 605 606 union { 607 /* Flag indicating this is an SPI slave controller */ 608 bool slave; 609 /* Flag indicating this is an SPI target controller */ 610 bool target; 611 }; 612 613 /* 614 * On some hardware transfer / message size may be constrained 615 * the limit may depend on device transfer settings. 616 */ 617 size_t (*max_transfer_size)(struct spi_device *spi); 618 size_t (*max_message_size)(struct spi_device *spi); 619 620 /* I/O mutex */ 621 struct mutex io_mutex; 622 623 /* Used to avoid adding the same CS twice */ 624 struct mutex add_lock; 625 626 /* Lock and mutex for SPI bus locking */ 627 spinlock_t bus_lock_spinlock; 628 struct mutex bus_lock_mutex; 629 630 /* Flag indicating that the SPI bus is locked for exclusive use */ 631 bool bus_lock_flag; 632 633 /* 634 * Setup mode and clock, etc (SPI driver may call many times). 635 * 636 * IMPORTANT: this may be called when transfers to another 637 * device are active. DO NOT UPDATE SHARED REGISTERS in ways 638 * which could break those transfers. 639 */ 640 int (*setup)(struct spi_device *spi); 641 642 /* 643 * set_cs_timing() method is for SPI controllers that supports 644 * configuring CS timing. 645 * 646 * This hook allows SPI client drivers to request SPI controllers 647 * to configure specific CS timing through spi_set_cs_timing() after 648 * spi_setup(). 649 */ 650 int (*set_cs_timing)(struct spi_device *spi); 651 652 /* 653 * Bidirectional bulk transfers 654 * 655 * + The transfer() method may not sleep; its main role is 656 * just to add the message to the queue. 657 * + For now there's no remove-from-queue operation, or 658 * any other request management 659 * + To a given spi_device, message queueing is pure FIFO 660 * 661 * + The controller's main job is to process its message queue, 662 * selecting a chip (for masters), then transferring data 663 * + If there are multiple spi_device children, the i/o queue 664 * arbitration algorithm is unspecified (round robin, FIFO, 665 * priority, reservations, preemption, etc) 666 * 667 * + Chipselect stays active during the entire message 668 * (unless modified by spi_transfer.cs_change != 0). 669 * + The message transfers use clock and SPI mode parameters 670 * previously established by setup() for this device 671 */ 672 int (*transfer)(struct spi_device *spi, 673 struct spi_message *mesg); 674 675 /* Called on release() to free memory provided by spi_controller */ 676 void (*cleanup)(struct spi_device *spi); 677 678 /* 679 * Used to enable core support for DMA handling, if can_dma() 680 * exists and returns true then the transfer will be mapped 681 * prior to transfer_one() being called. The driver should 682 * not modify or store xfer and dma_tx and dma_rx must be set 683 * while the device is prepared. 684 */ 685 bool (*can_dma)(struct spi_controller *ctlr, 686 struct spi_device *spi, 687 struct spi_transfer *xfer); 688 struct device *dma_map_dev; 689 struct device *cur_rx_dma_dev; 690 struct device *cur_tx_dma_dev; 691 692 /* 693 * These hooks are for drivers that want to use the generic 694 * controller transfer queueing mechanism. If these are used, the 695 * transfer() function above must NOT be specified by the driver. 696 * Over time we expect SPI drivers to be phased over to this API. 697 */ 698 bool queued; 699 struct kthread_worker *kworker; 700 struct kthread_work pump_messages; 701 spinlock_t queue_lock; 702 struct list_head queue; 703 struct spi_message *cur_msg; 704 struct completion cur_msg_completion; 705 bool cur_msg_incomplete; 706 bool cur_msg_need_completion; 707 bool busy; 708 bool running; 709 bool rt; 710 bool auto_runtime_pm; 711 bool cur_msg_mapped; 712 bool fallback; 713 bool last_cs_mode_high; 714 s8 last_cs[SPI_CS_CNT_MAX]; 715 u32 last_cs_index_mask : SPI_CS_CNT_MAX; 716 struct completion xfer_completion; 717 size_t max_dma_len; 718 719 int (*optimize_message)(struct spi_message *msg); 720 int (*unoptimize_message)(struct spi_message *msg); 721 int (*prepare_transfer_hardware)(struct spi_controller *ctlr); 722 int (*transfer_one_message)(struct spi_controller *ctlr, 723 struct spi_message *mesg); 724 int (*unprepare_transfer_hardware)(struct spi_controller *ctlr); 725 int (*prepare_message)(struct spi_controller *ctlr, 726 struct spi_message *message); 727 int (*unprepare_message)(struct spi_controller *ctlr, 728 struct spi_message *message); 729 union { 730 int (*slave_abort)(struct spi_controller *ctlr); 731 int (*target_abort)(struct spi_controller *ctlr); 732 }; 733 734 /* 735 * These hooks are for drivers that use a generic implementation 736 * of transfer_one_message() provided by the core. 737 */ 738 void (*set_cs)(struct spi_device *spi, bool enable); 739 int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi, 740 struct spi_transfer *transfer); 741 void (*handle_err)(struct spi_controller *ctlr, 742 struct spi_message *message); 743 744 /* Optimized handlers for SPI memory-like operations. */ 745 const struct spi_controller_mem_ops *mem_ops; 746 const struct spi_controller_mem_caps *mem_caps; 747 748 /* GPIO chip select */ 749 struct gpio_desc **cs_gpiods; 750 bool use_gpio_descriptors; 751 s8 unused_native_cs; 752 s8 max_native_cs; 753 754 /* Statistics */ 755 struct spi_statistics __percpu *pcpu_statistics; 756 757 /* DMA channels for use with core dmaengine helpers */ 758 struct dma_chan *dma_tx; 759 struct dma_chan *dma_rx; 760 761 /* Dummy data for full duplex devices */ 762 void *dummy_rx; 763 void *dummy_tx; 764 765 int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); 766 767 /* 768 * Driver sets this field to indicate it is able to snapshot SPI 769 * transfers (needed e.g. for reading the time of POSIX clocks) 770 */ 771 bool ptp_sts_supported; 772 773 /* Interrupt enable state during PTP system timestamping */ 774 unsigned long irq_flags; 775 776 /* Flag for enabling opportunistic skipping of the queue in spi_sync */ 777 bool queue_empty; 778 bool must_async; 779}; 780 781static inline void *spi_controller_get_devdata(struct spi_controller *ctlr) 782{ 783 return dev_get_drvdata(&ctlr->dev); 784} 785 786static inline void spi_controller_set_devdata(struct spi_controller *ctlr, 787 void *data) 788{ 789 dev_set_drvdata(&ctlr->dev, data); 790} 791 792static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr) 793{ 794 if (!ctlr || !get_device(&ctlr->dev)) 795 return NULL; 796 return ctlr; 797} 798 799static inline void spi_controller_put(struct spi_controller *ctlr) 800{ 801 if (ctlr) 802 put_device(&ctlr->dev); 803} 804 805static inline bool spi_controller_is_slave(struct spi_controller *ctlr) 806{ 807 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave; 808} 809 810static inline bool spi_controller_is_target(struct spi_controller *ctlr) 811{ 812 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->target; 813} 814 815/* PM calls that need to be issued by the driver */ 816extern int spi_controller_suspend(struct spi_controller *ctlr); 817extern int spi_controller_resume(struct spi_controller *ctlr); 818 819/* Calls the driver make to interact with the message queue */ 820extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr); 821extern void spi_finalize_current_message(struct spi_controller *ctlr); 822extern void spi_finalize_current_transfer(struct spi_controller *ctlr); 823 824/* Helper calls for driver to timestamp transfer */ 825void spi_take_timestamp_pre(struct spi_controller *ctlr, 826 struct spi_transfer *xfer, 827 size_t progress, bool irqs_off); 828void spi_take_timestamp_post(struct spi_controller *ctlr, 829 struct spi_transfer *xfer, 830 size_t progress, bool irqs_off); 831 832/* The SPI driver core manages memory for the spi_controller classdev */ 833extern struct spi_controller *__spi_alloc_controller(struct device *host, 834 unsigned int size, bool slave); 835 836static inline struct spi_controller *spi_alloc_master(struct device *host, 837 unsigned int size) 838{ 839 return __spi_alloc_controller(host, size, false); 840} 841 842static inline struct spi_controller *spi_alloc_slave(struct device *host, 843 unsigned int size) 844{ 845 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 846 return NULL; 847 848 return __spi_alloc_controller(host, size, true); 849} 850 851static inline struct spi_controller *spi_alloc_host(struct device *dev, 852 unsigned int size) 853{ 854 return __spi_alloc_controller(dev, size, false); 855} 856 857static inline struct spi_controller *spi_alloc_target(struct device *dev, 858 unsigned int size) 859{ 860 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 861 return NULL; 862 863 return __spi_alloc_controller(dev, size, true); 864} 865 866struct spi_controller *__devm_spi_alloc_controller(struct device *dev, 867 unsigned int size, 868 bool slave); 869 870static inline struct spi_controller *devm_spi_alloc_master(struct device *dev, 871 unsigned int size) 872{ 873 return __devm_spi_alloc_controller(dev, size, false); 874} 875 876static inline struct spi_controller *devm_spi_alloc_slave(struct device *dev, 877 unsigned int size) 878{ 879 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 880 return NULL; 881 882 return __devm_spi_alloc_controller(dev, size, true); 883} 884 885static inline struct spi_controller *devm_spi_alloc_host(struct device *dev, 886 unsigned int size) 887{ 888 return __devm_spi_alloc_controller(dev, size, false); 889} 890 891static inline struct spi_controller *devm_spi_alloc_target(struct device *dev, 892 unsigned int size) 893{ 894 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 895 return NULL; 896 897 return __devm_spi_alloc_controller(dev, size, true); 898} 899 900extern int spi_register_controller(struct spi_controller *ctlr); 901extern int devm_spi_register_controller(struct device *dev, 902 struct spi_controller *ctlr); 903extern void spi_unregister_controller(struct spi_controller *ctlr); 904 905#if IS_ENABLED(CONFIG_ACPI) 906extern struct spi_controller *acpi_spi_find_controller_by_adev(struct acpi_device *adev); 907extern struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr, 908 struct acpi_device *adev, 909 int index); 910int acpi_spi_count_resources(struct acpi_device *adev); 911#endif 912 913/* 914 * SPI resource management while processing a SPI message 915 */ 916 917typedef void (*spi_res_release_t)(struct spi_controller *ctlr, 918 struct spi_message *msg, 919 void *res); 920 921/** 922 * struct spi_res - SPI resource management structure 923 * @entry: list entry 924 * @release: release code called prior to freeing this resource 925 * @data: extra data allocated for the specific use-case 926 * 927 * This is based on ideas from devres, but focused on life-cycle 928 * management during spi_message processing. 929 */ 930struct spi_res { 931 struct list_head entry; 932 spi_res_release_t release; 933 unsigned long long data[]; /* Guarantee ull alignment */ 934}; 935 936/*---------------------------------------------------------------------------*/ 937 938/* 939 * I/O INTERFACE between SPI controller and protocol drivers 940 * 941 * Protocol drivers use a queue of spi_messages, each transferring data 942 * between the controller and memory buffers. 943 * 944 * The spi_messages themselves consist of a series of read+write transfer 945 * segments. Those segments always read the same number of bits as they 946 * write; but one or the other is easily ignored by passing a NULL buffer 947 * pointer. (This is unlike most types of I/O API, because SPI hardware 948 * is full duplex.) 949 * 950 * NOTE: Allocation of spi_transfer and spi_message memory is entirely 951 * up to the protocol driver, which guarantees the integrity of both (as 952 * well as the data buffers) for as long as the message is queued. 953 */ 954 955/** 956 * struct spi_transfer - a read/write buffer pair 957 * @tx_buf: data to be written (DMA-safe memory), or NULL 958 * @rx_buf: data to be read (DMA-safe memory), or NULL 959 * @tx_dma: DMA address of tx_buf, currently not for client use 960 * @rx_dma: DMA address of rx_buf, currently not for client use 961 * @tx_nbits: number of bits used for writing. If 0 the default 962 * (SPI_NBITS_SINGLE) is used. 963 * @rx_nbits: number of bits used for reading. If 0 the default 964 * (SPI_NBITS_SINGLE) is used. 965 * @len: size of rx and tx buffers (in bytes) 966 * @speed_hz: Select a speed other than the device default for this 967 * transfer. If 0 the default (from @spi_device) is used. 968 * @bits_per_word: select a bits_per_word other than the device default 969 * for this transfer. If 0 the default (from @spi_device) is used. 970 * @dummy_data: indicates transfer is dummy bytes transfer. 971 * @cs_off: performs the transfer with chipselect off. 972 * @cs_change: affects chipselect after this transfer completes 973 * @cs_change_delay: delay between cs deassert and assert when 974 * @cs_change is set and @spi_transfer is not the last in @spi_message 975 * @delay: delay to be introduced after this transfer before 976 * (optionally) changing the chipselect status, then starting 977 * the next transfer or completing this @spi_message. 978 * @word_delay: inter word delay to be introduced after each word size 979 * (set by bits_per_word) transmission. 980 * @effective_speed_hz: the effective SCK-speed that was used to 981 * transfer this transfer. Set to 0 if the SPI bus driver does 982 * not support it. 983 * @transfer_list: transfers are sequenced through @spi_message.transfers 984 * @tx_sg: Scatterlist for transmit, currently not for client use 985 * @rx_sg: Scatterlist for receive, currently not for client use 986 * @ptp_sts_word_pre: The word (subject to bits_per_word semantics) offset 987 * within @tx_buf for which the SPI device is requesting that the time 988 * snapshot for this transfer begins. Upon completing the SPI transfer, 989 * this value may have changed compared to what was requested, depending 990 * on the available snapshotting resolution (DMA transfer, 991 * @ptp_sts_supported is false, etc). 992 * @ptp_sts_word_post: See @ptp_sts_word_post. The two can be equal (meaning 993 * that a single byte should be snapshotted). 994 * If the core takes care of the timestamp (if @ptp_sts_supported is false 995 * for this controller), it will set @ptp_sts_word_pre to 0, and 996 * @ptp_sts_word_post to the length of the transfer. This is done 997 * purposefully (instead of setting to spi_transfer->len - 1) to denote 998 * that a transfer-level snapshot taken from within the driver may still 999 * be of higher quality. 1000 * @ptp_sts: Pointer to a memory location held by the SPI slave device where a 1001 * PTP system timestamp structure may lie. If drivers use PIO or their 1002 * hardware has some sort of assist for retrieving exact transfer timing, 1003 * they can (and should) assert @ptp_sts_supported and populate this 1004 * structure using the ptp_read_system_*ts helper functions. 1005 * The timestamp must represent the time at which the SPI slave device has 1006 * processed the word, i.e. the "pre" timestamp should be taken before 1007 * transmitting the "pre" word, and the "post" timestamp after receiving 1008 * transmit confirmation from the controller for the "post" word. 1009 * @timestamped: true if the transfer has been timestamped 1010 * @error: Error status logged by SPI controller driver. 1011 * 1012 * SPI transfers always write the same number of bytes as they read. 1013 * Protocol drivers should always provide @rx_buf and/or @tx_buf. 1014 * In some cases, they may also want to provide DMA addresses for 1015 * the data being transferred; that may reduce overhead, when the 1016 * underlying driver uses DMA. 1017 * 1018 * If the transmit buffer is NULL, zeroes will be shifted out 1019 * while filling @rx_buf. If the receive buffer is NULL, the data 1020 * shifted in will be discarded. Only "len" bytes shift out (or in). 1021 * It's an error to try to shift out a partial word. (For example, by 1022 * shifting out three bytes with word size of sixteen or twenty bits; 1023 * the former uses two bytes per word, the latter uses four bytes.) 1024 * 1025 * In-memory data values are always in native CPU byte order, translated 1026 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So 1027 * for example when bits_per_word is sixteen, buffers are 2N bytes long 1028 * (@len = 2N) and hold N sixteen bit words in CPU byte order. 1029 * 1030 * When the word size of the SPI transfer is not a power-of-two multiple 1031 * of eight bits, those in-memory words include extra bits. In-memory 1032 * words are always seen by protocol drivers as right-justified, so the 1033 * undefined (rx) or unused (tx) bits are always the most significant bits. 1034 * 1035 * All SPI transfers start with the relevant chipselect active. Normally 1036 * it stays selected until after the last transfer in a message. Drivers 1037 * can affect the chipselect signal using cs_change. 1038 * 1039 * (i) If the transfer isn't the last one in the message, this flag is 1040 * used to make the chipselect briefly go inactive in the middle of the 1041 * message. Toggling chipselect in this way may be needed to terminate 1042 * a chip command, letting a single spi_message perform all of group of 1043 * chip transactions together. 1044 * 1045 * (ii) When the transfer is the last one in the message, the chip may 1046 * stay selected until the next transfer. On multi-device SPI busses 1047 * with nothing blocking messages going to other devices, this is just 1048 * a performance hint; starting a message to another device deselects 1049 * this one. But in other cases, this can be used to ensure correctness. 1050 * Some devices need protocol transactions to be built from a series of 1051 * spi_message submissions, where the content of one message is determined 1052 * by the results of previous messages and where the whole transaction 1053 * ends when the chipselect goes inactive. 1054 * 1055 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information 1056 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these 1057 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x) 1058 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer. 1059 * 1060 * The code that submits an spi_message (and its spi_transfers) 1061 * to the lower layers is responsible for managing its memory. 1062 * Zero-initialize every field you don't set up explicitly, to 1063 * insulate against future API updates. After you submit a message 1064 * and its transfers, ignore them until its completion callback. 1065 */ 1066struct spi_transfer { 1067 /* 1068 * It's okay if tx_buf == rx_buf (right?). 1069 * For MicroWire, one buffer must be NULL. 1070 * Buffers must work with dma_*map_single() calls. 1071 */ 1072 const void *tx_buf; 1073 void *rx_buf; 1074 unsigned len; 1075 1076#define SPI_TRANS_FAIL_NO_START BIT(0) 1077#define SPI_TRANS_FAIL_IO BIT(1) 1078 u16 error; 1079 1080 dma_addr_t tx_dma; 1081 dma_addr_t rx_dma; 1082 struct sg_table tx_sg; 1083 struct sg_table rx_sg; 1084 1085 unsigned dummy_data:1; 1086 unsigned cs_off:1; 1087 unsigned cs_change:1; 1088 unsigned tx_nbits:3; 1089 unsigned rx_nbits:3; 1090 unsigned timestamped:1; 1091#define SPI_NBITS_SINGLE 0x01 /* 1-bit transfer */ 1092#define SPI_NBITS_DUAL 0x02 /* 2-bit transfer */ 1093#define SPI_NBITS_QUAD 0x04 /* 4-bit transfer */ 1094 u8 bits_per_word; 1095 struct spi_delay delay; 1096 struct spi_delay cs_change_delay; 1097 struct spi_delay word_delay; 1098 u32 speed_hz; 1099 1100 u32 effective_speed_hz; 1101 1102 unsigned int ptp_sts_word_pre; 1103 unsigned int ptp_sts_word_post; 1104 1105 struct ptp_system_timestamp *ptp_sts; 1106 1107 struct list_head transfer_list; 1108}; 1109 1110/** 1111 * struct spi_message - one multi-segment SPI transaction 1112 * @transfers: list of transfer segments in this transaction 1113 * @spi: SPI device to which the transaction is queued 1114 * @pre_optimized: peripheral driver pre-optimized the message 1115 * @optimized: the message is in the optimized state 1116 * @prepared: spi_prepare_message was called for the this message 1117 * @status: zero for success, else negative errno 1118 * @complete: called to report transaction completions 1119 * @context: the argument to complete() when it's called 1120 * @frame_length: the total number of bytes in the message 1121 * @actual_length: the total number of bytes that were transferred in all 1122 * successful segments 1123 * @queue: for use by whichever driver currently owns the message 1124 * @state: for use by whichever driver currently owns the message 1125 * @opt_state: for use by whichever driver currently owns the message 1126 * @resources: for resource management when the SPI message is processed 1127 * 1128 * A @spi_message is used to execute an atomic sequence of data transfers, 1129 * each represented by a struct spi_transfer. The sequence is "atomic" 1130 * in the sense that no other spi_message may use that SPI bus until that 1131 * sequence completes. On some systems, many such sequences can execute as 1132 * a single programmed DMA transfer. On all systems, these messages are 1133 * queued, and might complete after transactions to other devices. Messages 1134 * sent to a given spi_device are always executed in FIFO order. 1135 * 1136 * The code that submits an spi_message (and its spi_transfers) 1137 * to the lower layers is responsible for managing its memory. 1138 * Zero-initialize every field you don't set up explicitly, to 1139 * insulate against future API updates. After you submit a message 1140 * and its transfers, ignore them until its completion callback. 1141 */ 1142struct spi_message { 1143 struct list_head transfers; 1144 1145 struct spi_device *spi; 1146 1147 /* spi_optimize_message() was called for this message */ 1148 bool pre_optimized; 1149 /* __spi_optimize_message() was called for this message */ 1150 bool optimized; 1151 1152 /* spi_prepare_message() was called for this message */ 1153 bool prepared; 1154 1155 /* 1156 * REVISIT: we might want a flag affecting the behavior of the 1157 * last transfer ... allowing things like "read 16 bit length L" 1158 * immediately followed by "read L bytes". Basically imposing 1159 * a specific message scheduling algorithm. 1160 * 1161 * Some controller drivers (message-at-a-time queue processing) 1162 * could provide that as their default scheduling algorithm. But 1163 * others (with multi-message pipelines) could need a flag to 1164 * tell them about such special cases. 1165 */ 1166 1167 /* Completion is reported through a callback */ 1168 int status; 1169 void (*complete)(void *context); 1170 void *context; 1171 unsigned frame_length; 1172 unsigned actual_length; 1173 1174 /* 1175 * For optional use by whatever driver currently owns the 1176 * spi_message ... between calls to spi_async and then later 1177 * complete(), that's the spi_controller controller driver. 1178 */ 1179 struct list_head queue; 1180 void *state; 1181 /* 1182 * Optional state for use by controller driver between calls to 1183 * __spi_optimize_message() and __spi_unoptimize_message(). 1184 */ 1185 void *opt_state; 1186 1187 /* List of spi_res resources when the SPI message is processed */ 1188 struct list_head resources; 1189}; 1190 1191static inline void spi_message_init_no_memset(struct spi_message *m) 1192{ 1193 INIT_LIST_HEAD(&m->transfers); 1194 INIT_LIST_HEAD(&m->resources); 1195} 1196 1197static inline void spi_message_init(struct spi_message *m) 1198{ 1199 memset(m, 0, sizeof *m); 1200 spi_message_init_no_memset(m); 1201} 1202 1203static inline void 1204spi_message_add_tail(struct spi_transfer *t, struct spi_message *m) 1205{ 1206 list_add_tail(&t->transfer_list, &m->transfers); 1207} 1208 1209static inline void 1210spi_transfer_del(struct spi_transfer *t) 1211{ 1212 list_del(&t->transfer_list); 1213} 1214 1215static inline int 1216spi_transfer_delay_exec(struct spi_transfer *t) 1217{ 1218 return spi_delay_exec(&t->delay, t); 1219} 1220 1221/** 1222 * spi_message_init_with_transfers - Initialize spi_message and append transfers 1223 * @m: spi_message to be initialized 1224 * @xfers: An array of SPI transfers 1225 * @num_xfers: Number of items in the xfer array 1226 * 1227 * This function initializes the given spi_message and adds each spi_transfer in 1228 * the given array to the message. 1229 */ 1230static inline void 1231spi_message_init_with_transfers(struct spi_message *m, 1232struct spi_transfer *xfers, unsigned int num_xfers) 1233{ 1234 unsigned int i; 1235 1236 spi_message_init(m); 1237 for (i = 0; i < num_xfers; ++i) 1238 spi_message_add_tail(&xfers[i], m); 1239} 1240 1241/* 1242 * It's fine to embed message and transaction structures in other data 1243 * structures so long as you don't free them while they're in use. 1244 */ 1245static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags) 1246{ 1247 struct spi_message_with_transfers { 1248 struct spi_message m; 1249 struct spi_transfer t[]; 1250 } *mwt; 1251 unsigned i; 1252 1253 mwt = kzalloc(struct_size(mwt, t, ntrans), flags); 1254 if (!mwt) 1255 return NULL; 1256 1257 spi_message_init_no_memset(&mwt->m); 1258 for (i = 0; i < ntrans; i++) 1259 spi_message_add_tail(&mwt->t[i], &mwt->m); 1260 1261 return &mwt->m; 1262} 1263 1264static inline void spi_message_free(struct spi_message *m) 1265{ 1266 kfree(m); 1267} 1268 1269extern int spi_optimize_message(struct spi_device *spi, struct spi_message *msg); 1270extern void spi_unoptimize_message(struct spi_message *msg); 1271 1272extern int spi_setup(struct spi_device *spi); 1273extern int spi_async(struct spi_device *spi, struct spi_message *message); 1274extern int spi_slave_abort(struct spi_device *spi); 1275extern int spi_target_abort(struct spi_device *spi); 1276 1277static inline size_t 1278spi_max_message_size(struct spi_device *spi) 1279{ 1280 struct spi_controller *ctlr = spi->controller; 1281 1282 if (!ctlr->max_message_size) 1283 return SIZE_MAX; 1284 return ctlr->max_message_size(spi); 1285} 1286 1287static inline size_t 1288spi_max_transfer_size(struct spi_device *spi) 1289{ 1290 struct spi_controller *ctlr = spi->controller; 1291 size_t tr_max = SIZE_MAX; 1292 size_t msg_max = spi_max_message_size(spi); 1293 1294 if (ctlr->max_transfer_size) 1295 tr_max = ctlr->max_transfer_size(spi); 1296 1297 /* Transfer size limit must not be greater than message size limit */ 1298 return min(tr_max, msg_max); 1299} 1300 1301/** 1302 * spi_is_bpw_supported - Check if bits per word is supported 1303 * @spi: SPI device 1304 * @bpw: Bits per word 1305 * 1306 * This function checks to see if the SPI controller supports @bpw. 1307 * 1308 * Returns: 1309 * True if @bpw is supported, false otherwise. 1310 */ 1311static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw) 1312{ 1313 u32 bpw_mask = spi->controller->bits_per_word_mask; 1314 1315 if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw))) 1316 return true; 1317 1318 return false; 1319} 1320 1321/** 1322 * spi_controller_xfer_timeout - Compute a suitable timeout value 1323 * @ctlr: SPI device 1324 * @xfer: Transfer descriptor 1325 * 1326 * Compute a relevant timeout value for the given transfer. We derive the time 1327 * that it would take on a single data line and take twice this amount of time 1328 * with a minimum of 500ms to avoid false positives on loaded systems. 1329 * 1330 * Returns: Transfer timeout value in milliseconds. 1331 */ 1332static inline unsigned int spi_controller_xfer_timeout(struct spi_controller *ctlr, 1333 struct spi_transfer *xfer) 1334{ 1335 return max(xfer->len * 8 * 2 / (xfer->speed_hz / 1000), 500U); 1336} 1337 1338/*---------------------------------------------------------------------------*/ 1339 1340/* SPI transfer replacement methods which make use of spi_res */ 1341 1342struct spi_replaced_transfers; 1343typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr, 1344 struct spi_message *msg, 1345 struct spi_replaced_transfers *res); 1346/** 1347 * struct spi_replaced_transfers - structure describing the spi_transfer 1348 * replacements that have occurred 1349 * so that they can get reverted 1350 * @release: some extra release code to get executed prior to 1351 * releasing this structure 1352 * @extradata: pointer to some extra data if requested or NULL 1353 * @replaced_transfers: transfers that have been replaced and which need 1354 * to get restored 1355 * @replaced_after: the transfer after which the @replaced_transfers 1356 * are to get re-inserted 1357 * @inserted: number of transfers inserted 1358 * @inserted_transfers: array of spi_transfers of array-size @inserted, 1359 * that have been replacing replaced_transfers 1360 * 1361 * Note: that @extradata will point to @inserted_transfers[@inserted] 1362 * if some extra allocation is requested, so alignment will be the same 1363 * as for spi_transfers. 1364 */ 1365struct spi_replaced_transfers { 1366 spi_replaced_release_t release; 1367 void *extradata; 1368 struct list_head replaced_transfers; 1369 struct list_head *replaced_after; 1370 size_t inserted; 1371 struct spi_transfer inserted_transfers[]; 1372}; 1373 1374/*---------------------------------------------------------------------------*/ 1375 1376/* SPI transfer transformation methods */ 1377 1378extern int spi_split_transfers_maxsize(struct spi_controller *ctlr, 1379 struct spi_message *msg, 1380 size_t maxsize); 1381extern int spi_split_transfers_maxwords(struct spi_controller *ctlr, 1382 struct spi_message *msg, 1383 size_t maxwords); 1384 1385/*---------------------------------------------------------------------------*/ 1386 1387/* 1388 * All these synchronous SPI transfer routines are utilities layered 1389 * over the core async transfer primitive. Here, "synchronous" means 1390 * they will sleep uninterruptibly until the async transfer completes. 1391 */ 1392 1393extern int spi_sync(struct spi_device *spi, struct spi_message *message); 1394extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message); 1395extern int spi_bus_lock(struct spi_controller *ctlr); 1396extern int spi_bus_unlock(struct spi_controller *ctlr); 1397 1398/** 1399 * spi_sync_transfer - synchronous SPI data transfer 1400 * @spi: device with which data will be exchanged 1401 * @xfers: An array of spi_transfers 1402 * @num_xfers: Number of items in the xfer array 1403 * Context: can sleep 1404 * 1405 * Does a synchronous SPI data transfer of the given spi_transfer array. 1406 * 1407 * For more specific semantics see spi_sync(). 1408 * 1409 * Return: zero on success, else a negative error code. 1410 */ 1411static inline int 1412spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers, 1413 unsigned int num_xfers) 1414{ 1415 struct spi_message msg; 1416 1417 spi_message_init_with_transfers(&msg, xfers, num_xfers); 1418 1419 return spi_sync(spi, &msg); 1420} 1421 1422/** 1423 * spi_write - SPI synchronous write 1424 * @spi: device to which data will be written 1425 * @buf: data buffer 1426 * @len: data buffer size 1427 * Context: can sleep 1428 * 1429 * This function writes the buffer @buf. 1430 * Callable only from contexts that can sleep. 1431 * 1432 * Return: zero on success, else a negative error code. 1433 */ 1434static inline int 1435spi_write(struct spi_device *spi, const void *buf, size_t len) 1436{ 1437 struct spi_transfer t = { 1438 .tx_buf = buf, 1439 .len = len, 1440 }; 1441 1442 return spi_sync_transfer(spi, &t, 1); 1443} 1444 1445/** 1446 * spi_read - SPI synchronous read 1447 * @spi: device from which data will be read 1448 * @buf: data buffer 1449 * @len: data buffer size 1450 * Context: can sleep 1451 * 1452 * This function reads the buffer @buf. 1453 * Callable only from contexts that can sleep. 1454 * 1455 * Return: zero on success, else a negative error code. 1456 */ 1457static inline int 1458spi_read(struct spi_device *spi, void *buf, size_t len) 1459{ 1460 struct spi_transfer t = { 1461 .rx_buf = buf, 1462 .len = len, 1463 }; 1464 1465 return spi_sync_transfer(spi, &t, 1); 1466} 1467 1468/* This copies txbuf and rxbuf data; for small transfers only! */ 1469extern int spi_write_then_read(struct spi_device *spi, 1470 const void *txbuf, unsigned n_tx, 1471 void *rxbuf, unsigned n_rx); 1472 1473/** 1474 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read 1475 * @spi: device with which data will be exchanged 1476 * @cmd: command to be written before data is read back 1477 * Context: can sleep 1478 * 1479 * Callable only from contexts that can sleep. 1480 * 1481 * Return: the (unsigned) eight bit number returned by the 1482 * device, or else a negative error code. 1483 */ 1484static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd) 1485{ 1486 ssize_t status; 1487 u8 result; 1488 1489 status = spi_write_then_read(spi, &cmd, 1, &result, 1); 1490 1491 /* Return negative errno or unsigned value */ 1492 return (status < 0) ? status : result; 1493} 1494 1495/** 1496 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read 1497 * @spi: device with which data will be exchanged 1498 * @cmd: command to be written before data is read back 1499 * Context: can sleep 1500 * 1501 * The number is returned in wire-order, which is at least sometimes 1502 * big-endian. 1503 * 1504 * Callable only from contexts that can sleep. 1505 * 1506 * Return: the (unsigned) sixteen bit number returned by the 1507 * device, or else a negative error code. 1508 */ 1509static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) 1510{ 1511 ssize_t status; 1512 u16 result; 1513 1514 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1515 1516 /* Return negative errno or unsigned value */ 1517 return (status < 0) ? status : result; 1518} 1519 1520/** 1521 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read 1522 * @spi: device with which data will be exchanged 1523 * @cmd: command to be written before data is read back 1524 * Context: can sleep 1525 * 1526 * This function is similar to spi_w8r16, with the exception that it will 1527 * convert the read 16 bit data word from big-endian to native endianness. 1528 * 1529 * Callable only from contexts that can sleep. 1530 * 1531 * Return: the (unsigned) sixteen bit number returned by the device in CPU 1532 * endianness, or else a negative error code. 1533 */ 1534static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd) 1535 1536{ 1537 ssize_t status; 1538 __be16 result; 1539 1540 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1541 if (status < 0) 1542 return status; 1543 1544 return be16_to_cpu(result); 1545} 1546 1547/*---------------------------------------------------------------------------*/ 1548 1549/* 1550 * INTERFACE between board init code and SPI infrastructure. 1551 * 1552 * No SPI driver ever sees these SPI device table segments, but 1553 * it's how the SPI core (or adapters that get hotplugged) grows 1554 * the driver model tree. 1555 * 1556 * As a rule, SPI devices can't be probed. Instead, board init code 1557 * provides a table listing the devices which are present, with enough 1558 * information to bind and set up the device's driver. There's basic 1559 * support for non-static configurations too; enough to handle adding 1560 * parport adapters, or microcontrollers acting as USB-to-SPI bridges. 1561 */ 1562 1563/** 1564 * struct spi_board_info - board-specific template for a SPI device 1565 * @modalias: Initializes spi_device.modalias; identifies the driver. 1566 * @platform_data: Initializes spi_device.platform_data; the particular 1567 * data stored there is driver-specific. 1568 * @swnode: Software node for the device. 1569 * @controller_data: Initializes spi_device.controller_data; some 1570 * controllers need hints about hardware setup, e.g. for DMA. 1571 * @irq: Initializes spi_device.irq; depends on how the board is wired. 1572 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits 1573 * from the chip datasheet and board-specific signal quality issues. 1574 * @bus_num: Identifies which spi_controller parents the spi_device; unused 1575 * by spi_new_device(), and otherwise depends on board wiring. 1576 * @chip_select: Initializes spi_device.chip_select; depends on how 1577 * the board is wired. 1578 * @mode: Initializes spi_device.mode; based on the chip datasheet, board 1579 * wiring (some devices support both 3WIRE and standard modes), and 1580 * possibly presence of an inverter in the chipselect path. 1581 * 1582 * When adding new SPI devices to the device tree, these structures serve 1583 * as a partial device template. They hold information which can't always 1584 * be determined by drivers. Information that probe() can establish (such 1585 * as the default transfer wordsize) is not included here. 1586 * 1587 * These structures are used in two places. Their primary role is to 1588 * be stored in tables of board-specific device descriptors, which are 1589 * declared early in board initialization and then used (much later) to 1590 * populate a controller's device tree after the that controller's driver 1591 * initializes. A secondary (and atypical) role is as a parameter to 1592 * spi_new_device() call, which happens after those controller drivers 1593 * are active in some dynamic board configuration models. 1594 */ 1595struct spi_board_info { 1596 /* 1597 * The device name and module name are coupled, like platform_bus; 1598 * "modalias" is normally the driver name. 1599 * 1600 * platform_data goes to spi_device.dev.platform_data, 1601 * controller_data goes to spi_device.controller_data, 1602 * IRQ is copied too. 1603 */ 1604 char modalias[SPI_NAME_SIZE]; 1605 const void *platform_data; 1606 const struct software_node *swnode; 1607 void *controller_data; 1608 int irq; 1609 1610 /* Slower signaling on noisy or low voltage boards */ 1611 u32 max_speed_hz; 1612 1613 1614 /* 1615 * bus_num is board specific and matches the bus_num of some 1616 * spi_controller that will probably be registered later. 1617 * 1618 * chip_select reflects how this chip is wired to that master; 1619 * it's less than num_chipselect. 1620 */ 1621 u16 bus_num; 1622 u16 chip_select; 1623 1624 /* 1625 * mode becomes spi_device.mode, and is essential for chips 1626 * where the default of SPI_CS_HIGH = 0 is wrong. 1627 */ 1628 u32 mode; 1629 1630 /* 1631 * ... may need additional spi_device chip config data here. 1632 * avoid stuff protocol drivers can set; but include stuff 1633 * needed to behave without being bound to a driver: 1634 * - quirks like clock rate mattering when not selected 1635 */ 1636}; 1637 1638#ifdef CONFIG_SPI 1639extern int 1640spi_register_board_info(struct spi_board_info const *info, unsigned n); 1641#else 1642/* Board init code may ignore whether SPI is configured or not */ 1643static inline int 1644spi_register_board_info(struct spi_board_info const *info, unsigned n) 1645 { return 0; } 1646#endif 1647 1648/* 1649 * If you're hotplugging an adapter with devices (parport, USB, etc) 1650 * use spi_new_device() to describe each device. You can also call 1651 * spi_unregister_device() to start making that device vanish, but 1652 * normally that would be handled by spi_unregister_controller(). 1653 * 1654 * You can also use spi_alloc_device() and spi_add_device() to use a two 1655 * stage registration sequence for each spi_device. This gives the caller 1656 * some more control over the spi_device structure before it is registered, 1657 * but requires that caller to initialize fields that would otherwise 1658 * be defined using the board info. 1659 */ 1660extern struct spi_device * 1661spi_alloc_device(struct spi_controller *ctlr); 1662 1663extern int 1664spi_add_device(struct spi_device *spi); 1665 1666extern struct spi_device * 1667spi_new_device(struct spi_controller *, struct spi_board_info *); 1668 1669extern void spi_unregister_device(struct spi_device *spi); 1670 1671extern const struct spi_device_id * 1672spi_get_device_id(const struct spi_device *sdev); 1673 1674extern const void * 1675spi_get_device_match_data(const struct spi_device *sdev); 1676 1677static inline bool 1678spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer) 1679{ 1680 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers); 1681} 1682 1683#endif /* __LINUX_SPI_H */ 1684