1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Author: Chao Hao <chao.hao@mediatek.com> 5 */ 6 7#ifndef _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_ 8#define _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_ 9 10#include <dt-bindings/memory/mtk-memory-port.h> 11 12#define M4U_LARB0_ID 0 13#define M4U_LARB1_ID 1 14#define M4U_LARB2_ID 2 15#define M4U_LARB3_ID 3 16#define M4U_LARB4_ID 4 17#define M4U_LARB5_ID 5 18#define M4U_LARB6_ID 6 19#define M4U_LARB7_ID 7 20#define M4U_LARB8_ID 8 21#define M4U_LARB9_ID 9 22#define M4U_LARB10_ID 10 23#define M4U_LARB11_ID 11 24 25/* larb0 */ 26#define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0) 27#define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1) 28#define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2) 29#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3) 30#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) 31#define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5) 32#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) 33#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7) 34#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8) 35 36/* larb1 */ 37#define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0) 38#define M4U_PORT_DISP_OVL1_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 1) 39#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB1_ID, 2) 40#define M4U_PORT_DISP_OVL1_2L MTK_M4U_ID(M4U_LARB1_ID, 3) 41#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 4) 42#define M4U_PORT_MDP_PVRIC0 MTK_M4U_ID(M4U_LARB1_ID, 5) 43#define M4U_PORT_MDP_PVRIC1 MTK_M4U_ID(M4U_LARB1_ID, 6) 44#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB1_ID, 7) 45#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 8) 46#define M4U_PORT_MDP_WROT0_R MTK_M4U_ID(M4U_LARB1_ID, 9) 47#define M4U_PORT_MDP_WROT0_W MTK_M4U_ID(M4U_LARB1_ID, 10) 48#define M4U_PORT_MDP_WROT1_R MTK_M4U_ID(M4U_LARB1_ID, 11) 49#define M4U_PORT_MDP_WROT1_W MTK_M4U_ID(M4U_LARB1_ID, 12) 50#define M4U_PORT_DISP_FAKE1 MTK_M4U_ID(M4U_LARB1_ID, 13) 51 52/* larb2-VDEC */ 53#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) 54#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) 55#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) 56#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) 57#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) 58#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) 59#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) 60#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 7) 61#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB2_ID, 8) 62#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 9) 63#define M4U_PORT_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(M4U_LARB2_ID, 10) 64#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11) 65 66/* larb3-VENC */ 67#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) 68#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) 69#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) 70#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) 71#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) 72#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) 73#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 6) 74#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB3_ID, 7) 75#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) 76#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB3_ID, 9) 77#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 10) 78#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 11) 79#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 12) 80#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 13) 81#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 14) 82#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 15) 83#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 16) 84#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 17) 85#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 18) 86 87/* larb4-dummy */ 88 89/* larb5-IMG */ 90#define M4U_PORT_IMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 0) 91#define M4U_PORT_IMGBI_D1 MTK_M4U_ID(M4U_LARB5_ID, 1) 92#define M4U_PORT_DMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 2) 93#define M4U_PORT_DEPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 3) 94#define M4U_PORT_LCEI_D1 MTK_M4U_ID(M4U_LARB5_ID, 4) 95#define M4U_PORT_SMTI_D1 MTK_M4U_ID(M4U_LARB5_ID, 5) 96#define M4U_PORT_SMTO_D2 MTK_M4U_ID(M4U_LARB5_ID, 6) 97#define M4U_PORT_SMTO_D1 MTK_M4U_ID(M4U_LARB5_ID, 7) 98#define M4U_PORT_CRZO_D1 MTK_M4U_ID(M4U_LARB5_ID, 8) 99#define M4U_PORT_IMG3O_D1 MTK_M4U_ID(M4U_LARB5_ID, 9) 100#define M4U_PORT_VIPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 10) 101#define M4U_PORT_WPE_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 11) 102#define M4U_PORT_WPE_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 12) 103#define M4U_PORT_WPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 13) 104#define M4U_PORT_TIMGO_D1 MTK_M4U_ID(M4U_LARB5_ID, 14) 105#define M4U_PORT_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 15) 106#define M4U_PORT_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 16) 107#define M4U_PORT_MFB_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 17) 108#define M4U_PORT_MFB_RDMA3 MTK_M4U_ID(M4U_LARB5_ID, 18) 109#define M4U_PORT_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 19) 110#define M4U_PORT_RESERVE1 MTK_M4U_ID(M4U_LARB5_ID, 20) 111#define M4U_PORT_RESERVE2 MTK_M4U_ID(M4U_LARB5_ID, 21) 112#define M4U_PORT_RESERVE3 MTK_M4U_ID(M4U_LARB5_ID, 22) 113#define M4U_PORT_RESERVE4 MTK_M4U_ID(M4U_LARB5_ID, 23) 114#define M4U_PORT_RESERVE5 MTK_M4U_ID(M4U_LARB5_ID, 24) 115#define M4U_PORT_RESERVE6 MTK_M4U_ID(M4U_LARB5_ID, 25) 116 117/* larb6-IMG-VPU */ 118#define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB6_ID, 0) 119#define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB6_ID, 1) 120#define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB6_ID, 2) 121 122/* larb7-DVS */ 123#define M4U_PORT_DVS_RDMA MTK_M4U_ID(M4U_LARB7_ID, 0) 124#define M4U_PORT_DVS_WDMA MTK_M4U_ID(M4U_LARB7_ID, 1) 125#define M4U_PORT_DVP_RDMA MTK_M4U_ID(M4U_LARB7_ID, 2) 126#define M4U_PORT_DVP_WDMA MTK_M4U_ID(M4U_LARB7_ID, 3) 127 128/* larb8-IPESYS */ 129#define M4U_PORT_FDVT_RDA MTK_M4U_ID(M4U_LARB8_ID, 0) 130#define M4U_PORT_FDVT_RDB MTK_M4U_ID(M4U_LARB8_ID, 1) 131#define M4U_PORT_FDVT_WRA MTK_M4U_ID(M4U_LARB8_ID, 2) 132#define M4U_PORT_FDVT_WRB MTK_M4U_ID(M4U_LARB8_ID, 3) 133#define M4U_PORT_FE_RD0 MTK_M4U_ID(M4U_LARB8_ID, 4) 134#define M4U_PORT_FE_RD1 MTK_M4U_ID(M4U_LARB8_ID, 5) 135#define M4U_PORT_FE_WR0 MTK_M4U_ID(M4U_LARB8_ID, 6) 136#define M4U_PORT_FE_WR1 MTK_M4U_ID(M4U_LARB8_ID, 7) 137#define M4U_PORT_RSC_RDMA0 MTK_M4U_ID(M4U_LARB8_ID, 8) 138#define M4U_PORT_RSC_WDMA MTK_M4U_ID(M4U_LARB8_ID, 9) 139 140/* larb9-CAM */ 141#define M4U_PORT_CAM_IMGO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 0) 142#define M4U_PORT_CAM_RRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 1) 143#define M4U_PORT_CAM_LSCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 2) 144#define M4U_PORT_CAM_BPCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 3) 145#define M4U_PORT_CAM_YUVO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 4) 146#define M4U_PORT_CAM_UFDI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 5) 147#define M4U_PORT_CAM_RAWI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 6) 148#define M4U_PORT_CAM_RAWI_R5_C MTK_M4U_ID(M4U_LARB9_ID, 7) 149#define M4U_PORT_CAM_CAMSV_1 MTK_M4U_ID(M4U_LARB9_ID, 8) 150#define M4U_PORT_CAM_CAMSV_2 MTK_M4U_ID(M4U_LARB9_ID, 9) 151#define M4U_PORT_CAM_CAMSV_3 MTK_M4U_ID(M4U_LARB9_ID, 10) 152#define M4U_PORT_CAM_CAMSV_4 MTK_M4U_ID(M4U_LARB9_ID, 11) 153#define M4U_PORT_CAM_CAMSV_5 MTK_M4U_ID(M4U_LARB9_ID, 12) 154#define M4U_PORT_CAM_CAMSV_6 MTK_M4U_ID(M4U_LARB9_ID, 13) 155#define M4U_PORT_CAM_AAO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 14) 156#define M4U_PORT_CAM_AFO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 15) 157#define M4U_PORT_CAM_FLKO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 16) 158#define M4U_PORT_CAM_LCESO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 17) 159#define M4U_PORT_CAM_CRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 18) 160#define M4U_PORT_CAM_LTMSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 19) 161#define M4U_PORT_CAM_RSSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 20) 162#define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB9_ID, 21) 163#define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB9_ID, 22) 164#define M4U_PORT_CAM_FAKE MTK_M4U_ID(M4U_LARB9_ID, 23) 165 166/* larb10-CAM_A */ 167#define M4U_PORT_CAM_IMGO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 0) 168#define M4U_PORT_CAM_RRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 1) 169#define M4U_PORT_CAM_LSCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 2) 170#define M4U_PORT_CAM_BPCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 3) 171#define M4U_PORT_CAM_YUVO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 4) 172#define M4U_PORT_CAM_UFDI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 5) 173#define M4U_PORT_CAM_RAWI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 6) 174#define M4U_PORT_CAM_RAWI_R5_A MTK_M4U_ID(M4U_LARB10_ID, 7) 175#define M4U_PORT_CAM_IMGO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 8) 176#define M4U_PORT_CAM_RRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 9) 177#define M4U_PORT_CAM_LSCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 10) 178#define M4U_PORT_CAM_BPCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 11) 179#define M4U_PORT_CAM_YUVO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 12) 180#define M4U_PORT_CAM_UFDI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 13) 181#define M4U_PORT_CAM_RAWI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 14) 182#define M4U_PORT_CAM_RAWI_R5_B MTK_M4U_ID(M4U_LARB10_ID, 15) 183#define M4U_PORT_CAM_CAMSV_0 MTK_M4U_ID(M4U_LARB10_ID, 16) 184#define M4U_PORT_CAM_AAO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 17) 185#define M4U_PORT_CAM_AFO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 18) 186#define M4U_PORT_CAM_FLKO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 19) 187#define M4U_PORT_CAM_LCESO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 20) 188#define M4U_PORT_CAM_CRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 21) 189#define M4U_PORT_CAM_AAO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 22) 190#define M4U_PORT_CAM_AFO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 23) 191#define M4U_PORT_CAM_FLKO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 24) 192#define M4U_PORT_CAM_LCESO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 25) 193#define M4U_PORT_CAM_CRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 26) 194#define M4U_PORT_CAM_LTMSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 27) 195#define M4U_PORT_CAM_RSSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 28) 196#define M4U_PORT_CAM_LTMSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 29) 197#define M4U_PORT_CAM_RSSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 30) 198 199/* larb11-CAM-VPU */ 200#define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB11_ID, 0) 201#define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB11_ID, 1) 202#define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB11_ID, 2) 203#define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB11_ID, 3) 204#define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB11_ID, 4) 205 206#endif 207