1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Tegra20-specific VI implementation 4 * 5 * Copyright (C) 2023 SKIDATA GmbH 6 * Author: Luca Ceresoli <luca.ceresoli@bootlin.com> 7 */ 8 9/* 10 * This source file contains Tegra20 supported video formats, 11 * VI and VIP SoC specific data, operations and registers accessors. 12 */ 13 14#include <linux/bitfield.h> 15#include <linux/delay.h> 16#include <linux/host1x.h> 17#include <linux/kernel.h> 18#include <linux/kthread.h> 19#include <linux/v4l2-mediabus.h> 20 21#include "vip.h" 22#include "vi.h" 23 24#define TEGRA_VI_SYNCPT_WAIT_TIMEOUT msecs_to_jiffies(200) 25 26/* This are just good-sense numbers. The actual min/max is not documented. */ 27#define TEGRA20_MIN_WIDTH 32U 28#define TEGRA20_MIN_HEIGHT 32U 29#define TEGRA20_MAX_WIDTH 2048U 30#define TEGRA20_MAX_HEIGHT 2048U 31 32/* -------------------------------------------------------------------------- 33 * Registers 34 */ 35 36#define TEGRA_VI_CONT_SYNCPT_OUT_1 0x0060 37#define VI_CONT_SYNCPT_OUT_1_CONTINUOUS_SYNCPT BIT(8) 38#define VI_CONT_SYNCPT_OUT_1_SYNCPT_IDX_SFT 0 39 40#define TEGRA_VI_VI_INPUT_CONTROL 0x0088 41#define VI_INPUT_FIELD_DETECT BIT(27) 42#define VI_INPUT_BT656 BIT(25) 43#define VI_INPUT_YUV_INPUT_FORMAT_SFT 8 /* bits [9:8] */ 44#define VI_INPUT_YUV_INPUT_FORMAT_UYVY (0 << VI_INPUT_YUV_INPUT_FORMAT_SFT) 45#define VI_INPUT_YUV_INPUT_FORMAT_VYUY (1 << VI_INPUT_YUV_INPUT_FORMAT_SFT) 46#define VI_INPUT_YUV_INPUT_FORMAT_YUYV (2 << VI_INPUT_YUV_INPUT_FORMAT_SFT) 47#define VI_INPUT_YUV_INPUT_FORMAT_YVYU (3 << VI_INPUT_YUV_INPUT_FORMAT_SFT) 48#define VI_INPUT_INPUT_FORMAT_SFT 2 /* bits [5:2] */ 49#define VI_INPUT_INPUT_FORMAT_YUV422 (0 << VI_INPUT_INPUT_FORMAT_SFT) 50#define VI_INPUT_VIP_INPUT_ENABLE BIT(1) 51 52#define TEGRA_VI_VI_CORE_CONTROL 0x008c 53#define VI_VI_CORE_CONTROL_PLANAR_CONV_IN_SEL_EXT BIT(31) 54#define VI_VI_CORE_CONTROL_CSC_INPUT_SEL_EXT BIT(30) 55#define VI_VI_CORE_CONTROL_INPUT_TO_ALT_MUX_SFT 27 56#define VI_VI_CORE_CONTROL_INPUT_TO_CORE_EXT_SFT 24 57#define VI_VI_CORE_CONTROL_OUTPUT_TO_ISP_EXT_SFT 21 58#define VI_VI_CORE_CONTROL_ISP_HOST_STALL_OFF BIT(20) 59#define VI_VI_CORE_CONTROL_V_DOWNSCALING BIT(19) 60#define VI_VI_CORE_CONTROL_V_AVERAGING BIT(18) 61#define VI_VI_CORE_CONTROL_H_DOWNSCALING BIT(17) 62#define VI_VI_CORE_CONTROL_H_AVERAGING BIT(16) 63#define VI_VI_CORE_CONTROL_CSC_INPUT_SEL BIT(11) 64#define VI_VI_CORE_CONTROL_PLANAR_CONV_INPUT_SEL BIT(10) 65#define VI_VI_CORE_CONTROL_INPUT_TO_CORE_SFT 8 66#define VI_VI_CORE_CONTROL_ISP_DOWNSAMPLE_SFT 5 67#define VI_VI_CORE_CONTROL_OUTPUT_TO_EPP_SFT 2 68#define VI_VI_CORE_CONTROL_OUTPUT_TO_ISP_SFT 0 69 70#define TEGRA_VI_VI_FIRST_OUTPUT_CONTROL 0x0090 71#define VI_OUTPUT_FORMAT_EXT BIT(22) 72#define VI_OUTPUT_V_DIRECTION BIT(20) 73#define VI_OUTPUT_H_DIRECTION BIT(19) 74#define VI_OUTPUT_YUV_OUTPUT_FORMAT_SFT 17 75#define VI_OUTPUT_YUV_OUTPUT_FORMAT_UYVY (0 << VI_OUTPUT_YUV_OUTPUT_FORMAT_SFT) 76#define VI_OUTPUT_YUV_OUTPUT_FORMAT_VYUY (1 << VI_OUTPUT_YUV_OUTPUT_FORMAT_SFT) 77#define VI_OUTPUT_YUV_OUTPUT_FORMAT_YUYV (2 << VI_OUTPUT_YUV_OUTPUT_FORMAT_SFT) 78#define VI_OUTPUT_YUV_OUTPUT_FORMAT_YVYU (3 << VI_OUTPUT_YUV_OUTPUT_FORMAT_SFT) 79#define VI_OUTPUT_OUTPUT_BYTE_SWAP BIT(16) 80#define VI_OUTPUT_LAST_PIXEL_DUPLICATION BIT(8) 81#define VI_OUTPUT_OUTPUT_FORMAT_SFT 0 82#define VI_OUTPUT_OUTPUT_FORMAT_YUV422POST (3 << VI_OUTPUT_OUTPUT_FORMAT_SFT) 83#define VI_OUTPUT_OUTPUT_FORMAT_YUV420PLANAR (6 << VI_OUTPUT_OUTPUT_FORMAT_SFT) 84 85#define TEGRA_VI_VIP_H_ACTIVE 0x00a4 86#define VI_VIP_H_ACTIVE_PERIOD_SFT 16 /* active pixels/line, must be even */ 87#define VI_VIP_H_ACTIVE_START_SFT 0 88 89#define TEGRA_VI_VIP_V_ACTIVE 0x00a8 90#define VI_VIP_V_ACTIVE_PERIOD_SFT 16 /* active lines */ 91#define VI_VIP_V_ACTIVE_START_SFT 0 92 93#define TEGRA_VI_VB0_START_ADDRESS_FIRST 0x00c4 94#define TEGRA_VI_VB0_BASE_ADDRESS_FIRST 0x00c8 95#define TEGRA_VI_VB0_START_ADDRESS_U 0x00cc 96#define TEGRA_VI_VB0_BASE_ADDRESS_U 0x00d0 97#define TEGRA_VI_VB0_START_ADDRESS_V 0x00d4 98#define TEGRA_VI_VB0_BASE_ADDRESS_V 0x00d8 99 100#define TEGRA_VI_FIRST_OUTPUT_FRAME_SIZE 0x00e0 101#define VI_FIRST_OUTPUT_FRAME_HEIGHT_SFT 16 102#define VI_FIRST_OUTPUT_FRAME_WIDTH_SFT 0 103 104#define TEGRA_VI_VB0_COUNT_FIRST 0x00e4 105 106#define TEGRA_VI_VB0_SIZE_FIRST 0x00e8 107#define VI_VB0_SIZE_FIRST_V_SFT 16 108#define VI_VB0_SIZE_FIRST_H_SFT 0 109 110#define TEGRA_VI_VB0_BUFFER_STRIDE_FIRST 0x00ec 111#define VI_VB0_BUFFER_STRIDE_FIRST_CHROMA_SFT 30 112#define VI_VB0_BUFFER_STRIDE_FIRST_LUMA_SFT 0 113 114#define TEGRA_VI_H_LPF_CONTROL 0x0108 115#define VI_H_LPF_CONTROL_CHROMA_SFT 16 116#define VI_H_LPF_CONTROL_LUMA_SFT 0 117 118#define TEGRA_VI_H_DOWNSCALE_CONTROL 0x010c 119#define TEGRA_VI_V_DOWNSCALE_CONTROL 0x0110 120 121#define TEGRA_VI_VIP_INPUT_STATUS 0x0144 122 123#define TEGRA_VI_VI_DATA_INPUT_CONTROL 0x0168 124#define VI_DATA_INPUT_SFT 0 /* [11:0] = mask pin inputs to VI core */ 125 126#define TEGRA_VI_PIN_INPUT_ENABLE 0x016c 127#define VI_PIN_INPUT_VSYNC BIT(14) 128#define VI_PIN_INPUT_HSYNC BIT(13) 129#define VI_PIN_INPUT_VD_SFT 0 /* [11:0] = data bin N input enable */ 130 131#define TEGRA_VI_PIN_INVERSION 0x0174 132#define VI_PIN_INVERSION_VSYNC_ACTIVE_HIGH BIT(1) 133#define VI_PIN_INVERSION_HSYNC_ACTIVE_HIGH BIT(0) 134 135#define TEGRA_VI_CAMERA_CONTROL 0x01a0 136#define VI_CAMERA_CONTROL_STOP_CAPTURE BIT(2) 137#define VI_CAMERA_CONTROL_TEST_MODE BIT(1) 138#define VI_CAMERA_CONTROL_VIP_ENABLE BIT(0) 139 140#define TEGRA_VI_VI_ENABLE 0x01a4 141#define VI_VI_ENABLE_SW_FLOW_CONTROL_OUT1 BIT(1) 142#define VI_VI_ENABLE_FIRST_OUTPUT_TO_MEM_DISABLE BIT(0) 143 144#define TEGRA_VI_VI_RAISE 0x01ac 145#define VI_VI_RAISE_ON_EDGE BIT(0) 146 147/* -------------------------------------------------------------------------- 148 * VI 149 */ 150 151static void tegra20_vi_write(struct tegra_vi_channel *chan, unsigned int addr, u32 val) 152{ 153 writel(val, chan->vi->iomem + addr); 154} 155 156/* 157 * Get the main input format (YUV/RGB...) and the YUV variant as values to 158 * be written into registers for the current VI input mbus code. 159 */ 160static void tegra20_vi_get_input_formats(struct tegra_vi_channel *chan, 161 unsigned int *main_input_format, 162 unsigned int *yuv_input_format) 163{ 164 unsigned int input_mbus_code = chan->fmtinfo->code; 165 166 (*main_input_format) = VI_INPUT_INPUT_FORMAT_YUV422; 167 (*yuv_input_format) = VI_INPUT_YUV_INPUT_FORMAT_UYVY; 168 169 switch (input_mbus_code) { 170 case MEDIA_BUS_FMT_UYVY8_2X8: 171 (*yuv_input_format) = VI_INPUT_YUV_INPUT_FORMAT_UYVY; 172 break; 173 case MEDIA_BUS_FMT_VYUY8_2X8: 174 (*yuv_input_format) = VI_INPUT_YUV_INPUT_FORMAT_VYUY; 175 break; 176 case MEDIA_BUS_FMT_YUYV8_2X8: 177 (*yuv_input_format) = VI_INPUT_YUV_INPUT_FORMAT_YUYV; 178 break; 179 case MEDIA_BUS_FMT_YVYU8_2X8: 180 (*yuv_input_format) = VI_INPUT_YUV_INPUT_FORMAT_YVYU; 181 break; 182 } 183} 184 185/* 186 * Get the main output format (YUV/RGB...) and the YUV variant as values to 187 * be written into registers for the current VI output pixel format. 188 */ 189static void tegra20_vi_get_output_formats(struct tegra_vi_channel *chan, 190 unsigned int *main_output_format, 191 unsigned int *yuv_output_format) 192{ 193 u32 output_fourcc = chan->format.pixelformat; 194 195 /* Default to YUV422 non-planar (U8Y8V8Y8) after downscaling */ 196 (*main_output_format) = VI_OUTPUT_OUTPUT_FORMAT_YUV422POST; 197 (*yuv_output_format) = VI_OUTPUT_YUV_OUTPUT_FORMAT_UYVY; 198 199 switch (output_fourcc) { 200 case V4L2_PIX_FMT_UYVY: 201 (*yuv_output_format) = VI_OUTPUT_YUV_OUTPUT_FORMAT_UYVY; 202 break; 203 case V4L2_PIX_FMT_VYUY: 204 (*yuv_output_format) = VI_OUTPUT_YUV_OUTPUT_FORMAT_VYUY; 205 break; 206 case V4L2_PIX_FMT_YUYV: 207 (*yuv_output_format) = VI_OUTPUT_YUV_OUTPUT_FORMAT_YUYV; 208 break; 209 case V4L2_PIX_FMT_YVYU: 210 (*yuv_output_format) = VI_OUTPUT_YUV_OUTPUT_FORMAT_YVYU; 211 break; 212 case V4L2_PIX_FMT_YUV420: 213 case V4L2_PIX_FMT_YVU420: 214 (*main_output_format) = VI_OUTPUT_OUTPUT_FORMAT_YUV420PLANAR; 215 break; 216 } 217} 218 219/* 220 * Make the VI accessible (needed on Tegra20). 221 * 222 * This function writes an unknown bit into an unknown register. The code 223 * comes from a downstream 3.1 kernel that has a working VIP driver for 224 * Tegra20, and removing it makes the VI completely unaccessible. It should 225 * be rewritten and possibly moved elsewhere, but the appropriate location 226 * and implementation is unknown due to a total lack of documentation. 227 */ 228static int tegra20_vi_enable(struct tegra_vi *vi, bool on) 229{ 230 /* from arch/arm/mach-tegra/iomap.h */ 231 const phys_addr_t TEGRA_APB_MISC_BASE = 0x70000000; 232 const unsigned long reg_offset = 0x42c; 233 void __iomem *apb_misc; 234 u32 val; 235 236 apb_misc = ioremap(TEGRA_APB_MISC_BASE, PAGE_SIZE); 237 if (!apb_misc) 238 apb_misc = ERR_PTR(-ENOENT); 239 if (IS_ERR(apb_misc)) 240 return dev_err_probe(vi->dev, PTR_ERR(apb_misc), "cannot access APB_MISC"); 241 242 val = readl(apb_misc + reg_offset); 243 val &= ~BIT(0); 244 val |= on ? BIT(0) : 0; 245 writel(val, apb_misc + reg_offset); 246 iounmap(apb_misc); 247 248 return 0; 249} 250 251static int tegra20_channel_host1x_syncpt_init(struct tegra_vi_channel *chan) 252{ 253 struct tegra_vi *vi = chan->vi; 254 struct host1x_syncpt *out_sp; 255 256 out_sp = host1x_syncpt_request(&vi->client, HOST1X_SYNCPT_CLIENT_MANAGED); 257 if (!out_sp) 258 return dev_err_probe(vi->dev, -ENOMEM, "failed to request syncpoint\n"); 259 260 chan->mw_ack_sp[0] = out_sp; 261 262 return 0; 263} 264 265static void tegra20_channel_host1x_syncpt_free(struct tegra_vi_channel *chan) 266{ 267 host1x_syncpt_put(chan->mw_ack_sp[0]); 268} 269 270static void tegra20_fmt_align(struct v4l2_pix_format *pix, unsigned int bpp) 271{ 272 pix->width = clamp(pix->width, TEGRA20_MIN_WIDTH, TEGRA20_MAX_WIDTH); 273 pix->height = clamp(pix->height, TEGRA20_MIN_HEIGHT, TEGRA20_MAX_HEIGHT); 274 275 switch (pix->pixelformat) { 276 case V4L2_PIX_FMT_UYVY: 277 case V4L2_PIX_FMT_VYUY: 278 case V4L2_PIX_FMT_YUYV: 279 case V4L2_PIX_FMT_YVYU: 280 pix->bytesperline = roundup(pix->width, 2) * 2; 281 pix->sizeimage = roundup(pix->width, 2) * 2 * pix->height; 282 break; 283 case V4L2_PIX_FMT_YUV420: 284 case V4L2_PIX_FMT_YVU420: 285 pix->bytesperline = roundup(pix->width, 8); 286 pix->sizeimage = roundup(pix->width, 8) * pix->height * 3 / 2; 287 break; 288 } 289} 290 291/* 292 * Compute buffer offsets once per stream so that 293 * tegra20_channel_vi_buffer_setup() only has to do very simple maths for 294 * each buffer. 295 */ 296static void tegra20_channel_queue_setup(struct tegra_vi_channel *chan) 297{ 298 unsigned int stride = chan->format.bytesperline; 299 unsigned int height = chan->format.height; 300 301 chan->start_offset = 0; 302 303 switch (chan->format.pixelformat) { 304 case V4L2_PIX_FMT_UYVY: 305 case V4L2_PIX_FMT_VYUY: 306 case V4L2_PIX_FMT_YUYV: 307 case V4L2_PIX_FMT_YVYU: 308 if (chan->vflip) 309 chan->start_offset += stride * (height - 1); 310 if (chan->hflip) 311 chan->start_offset += stride - 1; 312 break; 313 314 case V4L2_PIX_FMT_YUV420: 315 case V4L2_PIX_FMT_YVU420: 316 chan->addr_offset_u = stride * height; 317 chan->addr_offset_v = chan->addr_offset_u + stride * height / 4; 318 319 /* For YVU420, we swap the locations of the U and V planes. */ 320 if (chan->format.pixelformat == V4L2_PIX_FMT_YVU420) 321 swap(chan->addr_offset_u, chan->addr_offset_v); 322 323 chan->start_offset_u = chan->addr_offset_u; 324 chan->start_offset_v = chan->addr_offset_v; 325 326 if (chan->vflip) { 327 chan->start_offset += stride * (height - 1); 328 chan->start_offset_u += (stride / 2) * ((height / 2) - 1); 329 chan->start_offset_v += (stride / 2) * ((height / 2) - 1); 330 } 331 if (chan->hflip) { 332 chan->start_offset += stride - 1; 333 chan->start_offset_u += (stride / 2) - 1; 334 chan->start_offset_v += (stride / 2) - 1; 335 } 336 break; 337 } 338} 339 340static void release_buffer(struct tegra_vi_channel *chan, 341 struct tegra_channel_buffer *buf, 342 enum vb2_buffer_state state) 343{ 344 struct vb2_v4l2_buffer *vb = &buf->buf; 345 346 vb->sequence = chan->sequence++; 347 vb->field = V4L2_FIELD_NONE; 348 vb->vb2_buf.timestamp = ktime_get_ns(); 349 vb2_buffer_done(&vb->vb2_buf, state); 350} 351 352static void tegra20_channel_vi_buffer_setup(struct tegra_vi_channel *chan, 353 struct tegra_channel_buffer *buf) 354{ 355 dma_addr_t base = buf->addr; 356 357 switch (chan->fmtinfo->fourcc) { 358 case V4L2_PIX_FMT_YUV420: 359 case V4L2_PIX_FMT_YVU420: 360 tegra20_vi_write(chan, TEGRA_VI_VB0_BASE_ADDRESS_U, base + chan->addr_offset_u); 361 tegra20_vi_write(chan, TEGRA_VI_VB0_START_ADDRESS_U, base + chan->start_offset_u); 362 tegra20_vi_write(chan, TEGRA_VI_VB0_BASE_ADDRESS_V, base + chan->addr_offset_v); 363 tegra20_vi_write(chan, TEGRA_VI_VB0_START_ADDRESS_V, base + chan->start_offset_v); 364 fallthrough; 365 366 case V4L2_PIX_FMT_UYVY: 367 case V4L2_PIX_FMT_VYUY: 368 case V4L2_PIX_FMT_YUYV: 369 case V4L2_PIX_FMT_YVYU: 370 tegra20_vi_write(chan, TEGRA_VI_VB0_BASE_ADDRESS_FIRST, base); 371 tegra20_vi_write(chan, TEGRA_VI_VB0_START_ADDRESS_FIRST, base + chan->start_offset); 372 break; 373 } 374} 375 376static int tegra20_channel_capture_frame(struct tegra_vi_channel *chan, 377 struct tegra_channel_buffer *buf) 378{ 379 int err; 380 381 chan->next_out_sp_idx++; 382 383 tegra20_channel_vi_buffer_setup(chan, buf); 384 385 tegra20_vi_write(chan, TEGRA_VI_CAMERA_CONTROL, VI_CAMERA_CONTROL_VIP_ENABLE); 386 387 /* Wait for syncpt counter to reach frame start event threshold */ 388 err = host1x_syncpt_wait(chan->mw_ack_sp[0], chan->next_out_sp_idx, 389 TEGRA_VI_SYNCPT_WAIT_TIMEOUT, NULL); 390 if (err) { 391 host1x_syncpt_incr(chan->mw_ack_sp[0]); 392 dev_err_ratelimited(&chan->video.dev, "frame start syncpt timeout: %d\n", err); 393 release_buffer(chan, buf, VB2_BUF_STATE_ERROR); 394 return err; 395 } 396 397 tegra20_vi_write(chan, TEGRA_VI_CAMERA_CONTROL, 398 VI_CAMERA_CONTROL_STOP_CAPTURE | VI_CAMERA_CONTROL_VIP_ENABLE); 399 400 release_buffer(chan, buf, VB2_BUF_STATE_DONE); 401 402 return 0; 403} 404 405static int tegra20_chan_capture_kthread_start(void *data) 406{ 407 struct tegra_vi_channel *chan = data; 408 struct tegra_channel_buffer *buf; 409 unsigned int retries = 0; 410 int err = 0; 411 412 while (1) { 413 /* 414 * Source is not streaming if error is non-zero. 415 * So, do not dequeue buffers on error and let the thread sleep 416 * till kthread stop signal is received. 417 */ 418 wait_event_interruptible(chan->start_wait, 419 kthread_should_stop() || 420 (!list_empty(&chan->capture) && !err)); 421 422 if (kthread_should_stop()) 423 break; 424 425 /* dequeue the buffer and start capture */ 426 spin_lock(&chan->start_lock); 427 if (list_empty(&chan->capture)) { 428 spin_unlock(&chan->start_lock); 429 continue; 430 } 431 432 buf = list_first_entry(&chan->capture, struct tegra_channel_buffer, queue); 433 list_del_init(&buf->queue); 434 spin_unlock(&chan->start_lock); 435 436 err = tegra20_channel_capture_frame(chan, buf); 437 if (!err) { 438 retries = 0; 439 continue; 440 } 441 442 if (retries++ > chan->syncpt_timeout_retry) 443 vb2_queue_error(&chan->queue); 444 else 445 err = 0; 446 } 447 448 return 0; 449} 450 451static void tegra20_camera_capture_setup(struct tegra_vi_channel *chan) 452{ 453 u32 output_fourcc = chan->format.pixelformat; 454 int width = chan->format.width; 455 int height = chan->format.height; 456 int stride_l = chan->format.bytesperline; 457 int stride_c = (output_fourcc == V4L2_PIX_FMT_YUV420 || 458 output_fourcc == V4L2_PIX_FMT_YVU420) ? 1 : 0; 459 int main_output_format; 460 int yuv_output_format; 461 462 tegra20_vi_get_output_formats(chan, &main_output_format, &yuv_output_format); 463 464 /* 465 * Set up low pass filter. Use 0x240 for chromaticity and 0x240 466 * for luminance, which is the default and means not to touch 467 * anything. 468 */ 469 tegra20_vi_write(chan, TEGRA_VI_H_LPF_CONTROL, 470 0x0240 << VI_H_LPF_CONTROL_LUMA_SFT | 471 0x0240 << VI_H_LPF_CONTROL_CHROMA_SFT); 472 473 /* Set up raise-on-edge, so we get an interrupt on end of frame. */ 474 tegra20_vi_write(chan, TEGRA_VI_VI_RAISE, VI_VI_RAISE_ON_EDGE); 475 476 tegra20_vi_write(chan, TEGRA_VI_VI_FIRST_OUTPUT_CONTROL, 477 (chan->vflip ? VI_OUTPUT_V_DIRECTION : 0) | 478 (chan->hflip ? VI_OUTPUT_H_DIRECTION : 0) | 479 yuv_output_format << VI_OUTPUT_YUV_OUTPUT_FORMAT_SFT | 480 main_output_format << VI_OUTPUT_OUTPUT_FORMAT_SFT); 481 482 /* Set up frame size */ 483 tegra20_vi_write(chan, TEGRA_VI_FIRST_OUTPUT_FRAME_SIZE, 484 height << VI_FIRST_OUTPUT_FRAME_HEIGHT_SFT | 485 width << VI_FIRST_OUTPUT_FRAME_WIDTH_SFT); 486 487 /* First output memory enabled */ 488 tegra20_vi_write(chan, TEGRA_VI_VI_ENABLE, 0); 489 490 /* Set the number of frames in the buffer */ 491 tegra20_vi_write(chan, TEGRA_VI_VB0_COUNT_FIRST, 1); 492 493 /* Set up buffer frame size */ 494 tegra20_vi_write(chan, TEGRA_VI_VB0_SIZE_FIRST, 495 height << VI_VB0_SIZE_FIRST_V_SFT | 496 width << VI_VB0_SIZE_FIRST_H_SFT); 497 498 tegra20_vi_write(chan, TEGRA_VI_VB0_BUFFER_STRIDE_FIRST, 499 stride_l << VI_VB0_BUFFER_STRIDE_FIRST_LUMA_SFT | 500 stride_c << VI_VB0_BUFFER_STRIDE_FIRST_CHROMA_SFT); 501 502 tegra20_vi_write(chan, TEGRA_VI_VI_ENABLE, 0); 503} 504 505static int tegra20_vi_start_streaming(struct vb2_queue *vq, u32 count) 506{ 507 struct tegra_vi_channel *chan = vb2_get_drv_priv(vq); 508 struct media_pipeline *pipe = &chan->video.pipe; 509 int err; 510 511 chan->next_out_sp_idx = host1x_syncpt_read(chan->mw_ack_sp[0]); 512 513 err = video_device_pipeline_start(&chan->video, pipe); 514 if (err) 515 goto error_pipeline_start; 516 517 tegra20_camera_capture_setup(chan); 518 519 err = tegra_channel_set_stream(chan, true); 520 if (err) 521 goto error_set_stream; 522 523 chan->sequence = 0; 524 525 chan->kthread_start_capture = kthread_run(tegra20_chan_capture_kthread_start, 526 chan, "%s:0", chan->video.name); 527 if (IS_ERR(chan->kthread_start_capture)) { 528 err = PTR_ERR(chan->kthread_start_capture); 529 chan->kthread_start_capture = NULL; 530 dev_err_probe(&chan->video.dev, err, "failed to run capture kthread\n"); 531 goto error_kthread_start; 532 } 533 534 return 0; 535 536error_kthread_start: 537 tegra_channel_set_stream(chan, false); 538error_set_stream: 539 video_device_pipeline_stop(&chan->video); 540error_pipeline_start: 541 tegra_channel_release_buffers(chan, VB2_BUF_STATE_QUEUED); 542 543 return err; 544} 545 546static void tegra20_vi_stop_streaming(struct vb2_queue *vq) 547{ 548 struct tegra_vi_channel *chan = vb2_get_drv_priv(vq); 549 550 if (chan->kthread_start_capture) { 551 kthread_stop(chan->kthread_start_capture); 552 chan->kthread_start_capture = NULL; 553 } 554 555 tegra_channel_release_buffers(chan, VB2_BUF_STATE_ERROR); 556 tegra_channel_set_stream(chan, false); 557 video_device_pipeline_stop(&chan->video); 558} 559 560static const struct tegra_vi_ops tegra20_vi_ops = { 561 .vi_enable = tegra20_vi_enable, 562 .channel_host1x_syncpt_init = tegra20_channel_host1x_syncpt_init, 563 .channel_host1x_syncpt_free = tegra20_channel_host1x_syncpt_free, 564 .vi_fmt_align = tegra20_fmt_align, 565 .channel_queue_setup = tegra20_channel_queue_setup, 566 .vi_start_streaming = tegra20_vi_start_streaming, 567 .vi_stop_streaming = tegra20_vi_stop_streaming, 568}; 569 570#define TEGRA20_VIDEO_FMT(MBUS_CODE, BPP, FOURCC) \ 571{ \ 572 .code = MEDIA_BUS_FMT_##MBUS_CODE, \ 573 .bpp = BPP, \ 574 .fourcc = V4L2_PIX_FMT_##FOURCC, \ 575} 576 577static const struct tegra_video_format tegra20_video_formats[] = { 578 TEGRA20_VIDEO_FMT(UYVY8_2X8, 2, UYVY), 579 TEGRA20_VIDEO_FMT(VYUY8_2X8, 2, VYUY), 580 TEGRA20_VIDEO_FMT(YUYV8_2X8, 2, YUYV), 581 TEGRA20_VIDEO_FMT(YVYU8_2X8, 2, YVYU), 582 TEGRA20_VIDEO_FMT(UYVY8_2X8, 1, YUV420), 583 TEGRA20_VIDEO_FMT(UYVY8_2X8, 1, YVU420), 584}; 585 586const struct tegra_vi_soc tegra20_vi_soc = { 587 .video_formats = tegra20_video_formats, 588 .nformats = ARRAY_SIZE(tegra20_video_formats), 589 .default_video_format = &tegra20_video_formats[0], 590 .ops = &tegra20_vi_ops, 591 .vi_max_channels = 1, /* parallel input (VIP) */ 592 .vi_max_clk_hz = 150000000, 593 .has_h_v_flip = true, 594}; 595 596/* -------------------------------------------------------------------------- 597 * VIP 598 */ 599 600/* 601 * VIP-specific configuration for stream start. 602 * 603 * Whatever is common among VIP and CSI is done by the VI component (see 604 * tegra20_vi_start_streaming()). Here we do what is VIP-specific. 605 */ 606static int tegra20_vip_start_streaming(struct tegra_vip_channel *vip_chan) 607{ 608 struct tegra_vi_channel *vi_chan = v4l2_get_subdev_hostdata(&vip_chan->subdev); 609 int width = vi_chan->format.width; 610 int height = vi_chan->format.height; 611 612 unsigned int main_input_format; 613 unsigned int yuv_input_format; 614 615 tegra20_vi_get_input_formats(vi_chan, &main_input_format, &yuv_input_format); 616 617 tegra20_vi_write(vi_chan, TEGRA_VI_VI_CORE_CONTROL, 0); 618 619 tegra20_vi_write(vi_chan, TEGRA_VI_VI_INPUT_CONTROL, 620 VI_INPUT_VIP_INPUT_ENABLE | main_input_format | yuv_input_format); 621 622 tegra20_vi_write(vi_chan, TEGRA_VI_V_DOWNSCALE_CONTROL, 0); 623 tegra20_vi_write(vi_chan, TEGRA_VI_H_DOWNSCALE_CONTROL, 0); 624 625 tegra20_vi_write(vi_chan, TEGRA_VI_VIP_V_ACTIVE, height << VI_VIP_V_ACTIVE_PERIOD_SFT); 626 tegra20_vi_write(vi_chan, TEGRA_VI_VIP_H_ACTIVE, 627 roundup(width, 2) << VI_VIP_H_ACTIVE_PERIOD_SFT); 628 629 /* 630 * For VIP, D9..D2 is mapped to the video decoder's P7..P0. 631 * Disable/mask out the other Dn wires. When not in BT656 632 * mode we also need the V/H sync. 633 */ 634 tegra20_vi_write(vi_chan, TEGRA_VI_PIN_INPUT_ENABLE, 635 GENMASK(9, 2) << VI_PIN_INPUT_VD_SFT | 636 VI_PIN_INPUT_HSYNC | VI_PIN_INPUT_VSYNC); 637 tegra20_vi_write(vi_chan, TEGRA_VI_VI_DATA_INPUT_CONTROL, 638 GENMASK(9, 2) << VI_DATA_INPUT_SFT); 639 tegra20_vi_write(vi_chan, TEGRA_VI_PIN_INVERSION, 0); 640 641 tegra20_vi_write(vi_chan, TEGRA_VI_CONT_SYNCPT_OUT_1, 642 VI_CONT_SYNCPT_OUT_1_CONTINUOUS_SYNCPT | 643 host1x_syncpt_id(vi_chan->mw_ack_sp[0]) 644 << VI_CONT_SYNCPT_OUT_1_SYNCPT_IDX_SFT); 645 646 tegra20_vi_write(vi_chan, TEGRA_VI_CAMERA_CONTROL, VI_CAMERA_CONTROL_STOP_CAPTURE); 647 648 return 0; 649} 650 651static const struct tegra_vip_ops tegra20_vip_ops = { 652 .vip_start_streaming = tegra20_vip_start_streaming, 653}; 654 655const struct tegra_vip_soc tegra20_vip_soc = { 656 .ops = &tegra20_vip_ops, 657}; 658