1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Intel Meteor Point PCH pinctrl/GPIO driver 4 * 5 * Copyright (C) 2022-2023, Intel Corporation 6 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 7 */ 8 9#include <linux/mod_devicetable.h> 10#include <linux/module.h> 11#include <linux/platform_device.h> 12#include <linux/pm.h> 13 14#include <linux/pinctrl/pinctrl.h> 15 16#include "pinctrl-intel.h" 17 18#define MTP_PAD_OWN 0x0b0 19#define MTP_PADCFGLOCK 0x110 20#define MTP_HOSTSW_OWN 0x150 21#define MTP_GPI_IS 0x200 22#define MTP_GPI_IE 0x220 23 24#define MTP_GPP(r, s, e, g) \ 25 { \ 26 .reg_num = (r), \ 27 .base = (s), \ 28 .size = ((e) - (s) + 1), \ 29 .gpio_base = (g), \ 30 } 31 32#define MTP_COMMUNITY(b, s, e, g) \ 33 INTEL_COMMUNITY_GPPS(b, s, e, g, MTP) 34 35/* Meteor Point-S */ 36static const struct pinctrl_pin_desc mtps_pins[] = { 37 /* GPP_D */ 38 PINCTRL_PIN(0, "GPP_D_0"), 39 PINCTRL_PIN(1, "GPP_D_1"), 40 PINCTRL_PIN(2, "GPP_D_2"), 41 PINCTRL_PIN(3, "GPP_D_3"), 42 PINCTRL_PIN(4, "GPP_D_4"), 43 PINCTRL_PIN(5, "CNV_RF_RESET_B"), 44 PINCTRL_PIN(6, "CRF_CLKREQ"), 45 PINCTRL_PIN(7, "GPP_D_7"), 46 PINCTRL_PIN(8, "GPP_D_8"), 47 PINCTRL_PIN(9, "SML0CLK"), 48 PINCTRL_PIN(10, "SML0DATA"), 49 PINCTRL_PIN(11, "GPP_D_11"), 50 PINCTRL_PIN(12, "GPP_D_12"), 51 PINCTRL_PIN(13, "GPP_D_13"), 52 PINCTRL_PIN(14, "GPP_D_14"), 53 PINCTRL_PIN(15, "GPP_D_15"), 54 PINCTRL_PIN(16, "GPP_D_16"), 55 PINCTRL_PIN(17, "GPP_D_17"), 56 PINCTRL_PIN(18, "GPP_D_18"), 57 PINCTRL_PIN(19, "GPP_D_19"), 58 PINCTRL_PIN(20, "GPP_D_20"), 59 PINCTRL_PIN(21, "GPP_D_21"), 60 PINCTRL_PIN(22, "GPP_D_22"), 61 PINCTRL_PIN(23, "GPP_D_23"), 62 PINCTRL_PIN(24, "GSPI3_CLK_LOOPBK"), 63 /* GPP_R */ 64 PINCTRL_PIN(25, "HDA_BCLK"), 65 PINCTRL_PIN(26, "HDA_SYNC"), 66 PINCTRL_PIN(27, "HDA_SDO"), 67 PINCTRL_PIN(28, "HDA_SDI_0"), 68 PINCTRL_PIN(29, "HDA_RSTB"), 69 PINCTRL_PIN(30, "GPP_R_5"), 70 PINCTRL_PIN(31, "GPP_R_6"), 71 PINCTRL_PIN(32, "GPP_R_7"), 72 PINCTRL_PIN(33, "GPP_R_8"), 73 PINCTRL_PIN(34, "GPP_R_9"), 74 PINCTRL_PIN(35, "GPP_R_10"), 75 PINCTRL_PIN(36, "GPP_R_11"), 76 PINCTRL_PIN(37, "GPP_R_12"), 77 PINCTRL_PIN(38, "GSPI2_CLK_LOOPBK"), 78 /* GPP_J */ 79 PINCTRL_PIN(39, "GPP_J_0"), 80 PINCTRL_PIN(40, "CNV_BRI_DT"), 81 PINCTRL_PIN(41, "CNV_BRI_RSP"), 82 PINCTRL_PIN(42, "CNV_RGI_DT"), 83 PINCTRL_PIN(43, "CNV_RGI_RSP"), 84 PINCTRL_PIN(44, "GPP_J_5"), 85 PINCTRL_PIN(45, "GPP_J_6"), 86 PINCTRL_PIN(46, "BOOTHALT_B"), 87 PINCTRL_PIN(47, "RTCCLKOUT"), 88 PINCTRL_PIN(48, "BPKI3C_SDA"), 89 PINCTRL_PIN(49, "BPKI3C_SCL"), 90 PINCTRL_PIN(50, "DAM"), 91 PINCTRL_PIN(51, "HDACPU_SDI"), 92 PINCTRL_PIN(52, "HDACPU_SDO"), 93 PINCTRL_PIN(53, "HDACPU_BCLK"), 94 PINCTRL_PIN(54, "AUX_PWRGD"), 95 PINCTRL_PIN(55, "GLB_RST_WARN_B"), 96 PINCTRL_PIN(56, "RESET_SYNCB"), 97 /* vGPIO */ 98 PINCTRL_PIN(57, "CNV_BTEN"), 99 PINCTRL_PIN(58, "CNV_BT_HOST_WAKEB"), 100 PINCTRL_PIN(59, "CNV_BT_IF_SELECT"), 101 PINCTRL_PIN(60, "vCNV_BT_UART_TXD"), 102 PINCTRL_PIN(61, "vCNV_BT_UART_RXD"), 103 PINCTRL_PIN(62, "vCNV_BT_UART_CTS_B"), 104 PINCTRL_PIN(63, "vCNV_BT_UART_RTS_B"), 105 PINCTRL_PIN(64, "vCNV_MFUART1_TXD"), 106 PINCTRL_PIN(65, "vCNV_MFUART1_RXD"), 107 PINCTRL_PIN(66, "vCNV_MFUART1_CTS_B"), 108 PINCTRL_PIN(67, "vCNV_MFUART1_RTS_B"), 109 PINCTRL_PIN(68, "vUART0_TXD"), 110 PINCTRL_PIN(69, "vUART0_RXD"), 111 PINCTRL_PIN(70, "vUART0_CTS_B"), 112 PINCTRL_PIN(71, "vUART0_RTS_B"), 113 PINCTRL_PIN(72, "vISH_UART0_TXD"), 114 PINCTRL_PIN(73, "vISH_UART0_RXD"), 115 PINCTRL_PIN(74, "vISH_UART0_CTS_B"), 116 PINCTRL_PIN(75, "vISH_UART0_RTS_B"), 117 PINCTRL_PIN(76, "vCNV_BT_I2S_BCLK"), 118 PINCTRL_PIN(77, "vCNV_BT_I2S_WS_SYNC"), 119 PINCTRL_PIN(78, "vCNV_BT_I2S_SDO"), 120 PINCTRL_PIN(79, "vCNV_BT_I2S_SDI"), 121 PINCTRL_PIN(80, "vI2S2_SCLK"), 122 PINCTRL_PIN(81, "vI2S2_SFRM"), 123 PINCTRL_PIN(82, "vI2S2_TXD"), 124 PINCTRL_PIN(83, "vI2S2_RXD"), 125 PINCTRL_PIN(84, "THC0_WOT_INT"), 126 PINCTRL_PIN(85, "THC1_WOT_INT"), 127 PINCTRL_PIN(86, "THC0_WHC_INT"), 128 PINCTRL_PIN(87, "THC1_WHC_INT"), 129 /* GPP_A */ 130 PINCTRL_PIN(88, "ESPI_IO_0"), 131 PINCTRL_PIN(89, "ESPI_IO_1"), 132 PINCTRL_PIN(90, "ESPI_IO_2"), 133 PINCTRL_PIN(91, "ESPI_IO_3"), 134 PINCTRL_PIN(92, "ESPI_CS0B"), 135 PINCTRL_PIN(93, "ESPI_CLK"), 136 PINCTRL_PIN(94, "ESPI_RESETB"), 137 PINCTRL_PIN(95, "ESPI_CS1B"), 138 PINCTRL_PIN(96, "ESPI_CS2B"), 139 PINCTRL_PIN(97, "ESPI_CS3B"), 140 PINCTRL_PIN(98, "ESPI_ALERT0B"), 141 PINCTRL_PIN(99, "ESPI_ALERT1B"), 142 PINCTRL_PIN(100, "ESPI_ALERT2B"), 143 PINCTRL_PIN(101, "ESPI_ALERT3B"), 144 PINCTRL_PIN(102, "ESPI_CLK_LOOPBK"), 145 /* DIR_ESPI */ 146 PINCTRL_PIN(103, "PWRBTNB_OUT"), 147 PINCTRL_PIN(104, "DMI_PERSTB"), 148 PINCTRL_PIN(105, "DMI_CLKREQB"), 149 PINCTRL_PIN(106, "DIR_ESPI_IO_0"), 150 PINCTRL_PIN(107, "DIR_ESPI_IO_1"), 151 PINCTRL_PIN(108, "DIR_ESPI_IO_2"), 152 PINCTRL_PIN(109, "DIR_ESPI_IO_3"), 153 PINCTRL_PIN(110, "DIR_ESPI_CSB"), 154 PINCTRL_PIN(111, "DIR_ESPI_RESETB"), 155 PINCTRL_PIN(112, "DIR_ESPI_CLK"), 156 PINCTRL_PIN(113, "DIR_ESPI_RCLK"), 157 PINCTRL_PIN(114, "DIR_ESPI_ALERTB"), 158 /* GPP_B */ 159 PINCTRL_PIN(115, "GPP_B_0"), 160 PINCTRL_PIN(116, "GPP_B_1"), 161 PINCTRL_PIN(117, "GPP_B_2"), 162 PINCTRL_PIN(118, "GPP_B_3"), 163 PINCTRL_PIN(119, "GPP_B_4"), 164 PINCTRL_PIN(120, "GPP_B_5"), 165 PINCTRL_PIN(121, "CLKOUT_48"), 166 PINCTRL_PIN(122, "GPP_B_7"), 167 PINCTRL_PIN(123, "GPP_B_8"), 168 PINCTRL_PIN(124, "GPP_B_9"), 169 PINCTRL_PIN(125, "GPP_B_10"), 170 PINCTRL_PIN(126, "GPP_B_11"), 171 PINCTRL_PIN(127, "SLP_S0B"), 172 PINCTRL_PIN(128, "PLTRSTB"), 173 PINCTRL_PIN(129, "GPP_B_14"), 174 PINCTRL_PIN(130, "GPP_B_15"), 175 PINCTRL_PIN(131, "GPP_B_16"), 176 PINCTRL_PIN(132, "GPP_B_17"), 177 PINCTRL_PIN(133, "GPP_B_18"), 178 PINCTRL_PIN(134, "FUSA_DIAGTEST_EN"), 179 PINCTRL_PIN(135, "FUSA_DIAGTEST_MODE"), 180 PINCTRL_PIN(136, "GPP_B_21"), 181 /* SPI0 */ 182 PINCTRL_PIN(137, "SPI0_IO_2"), 183 PINCTRL_PIN(138, "SPI0_IO_3"), 184 PINCTRL_PIN(139, "SPI0_MOSI_IO_0"), 185 PINCTRL_PIN(140, "SPI0_MISO_IO_1"), 186 PINCTRL_PIN(141, "SPI0_TPM_CSB"), 187 PINCTRL_PIN(142, "SPI0_FLASH_0_CSB"), 188 PINCTRL_PIN(143, "SPI0_FLASH_1_CSB"), 189 PINCTRL_PIN(144, "SPI0_CLK"), 190 PINCTRL_PIN(145, "SPI0_CLK_LOOPBK"), 191 /* GPP_C */ 192 PINCTRL_PIN(146, "SMBCLK"), 193 PINCTRL_PIN(147, "SMBDATA"), 194 PINCTRL_PIN(148, "SMBALERTB"), 195 PINCTRL_PIN(149, "GPP_C_3"), 196 PINCTRL_PIN(150, "GPP_C_4"), 197 PINCTRL_PIN(151, "GPP_C_5"), 198 PINCTRL_PIN(152, "GPP_C_6"), 199 PINCTRL_PIN(153, "GPP_C_7"), 200 PINCTRL_PIN(154, "GPP_C_8"), 201 PINCTRL_PIN(155, "GPP_C_9"), 202 PINCTRL_PIN(156, "GPP_C_10"), 203 PINCTRL_PIN(157, "GPP_C_11"), 204 PINCTRL_PIN(158, "GPP_C_12"), 205 PINCTRL_PIN(159, "GPP_C_13"), 206 PINCTRL_PIN(160, "GPP_C_14"), 207 PINCTRL_PIN(161, "GPP_C_15"), 208 PINCTRL_PIN(162, "GPP_C_16"), 209 PINCTRL_PIN(163, "GPP_C_17"), 210 PINCTRL_PIN(164, "GPP_C_18"), 211 PINCTRL_PIN(165, "GPP_C_19"), 212 PINCTRL_PIN(166, "GPP_C_20"), 213 PINCTRL_PIN(167, "GPP_C_21"), 214 PINCTRL_PIN(168, "GPP_C_22"), 215 PINCTRL_PIN(169, "GPP_C_23"), 216 /* GPP_H */ 217 PINCTRL_PIN(170, "GPP_H_0"), 218 PINCTRL_PIN(171, "GPP_H_1"), 219 PINCTRL_PIN(172, "GPP_H_2"), 220 PINCTRL_PIN(173, "GPP_H_3"), 221 PINCTRL_PIN(174, "GPP_H_4"), 222 PINCTRL_PIN(175, "GPP_H_5"), 223 PINCTRL_PIN(176, "GPP_H_6"), 224 PINCTRL_PIN(177, "GPP_H_7"), 225 PINCTRL_PIN(178, "GPP_H_8"), 226 PINCTRL_PIN(179, "GPP_H_9"), 227 PINCTRL_PIN(180, "GPP_H_10"), 228 PINCTRL_PIN(181, "GPP_H_11"), 229 PINCTRL_PIN(182, "GPP_H_12"), 230 PINCTRL_PIN(183, "GPP_H_13"), 231 PINCTRL_PIN(184, "GPP_H_14"), 232 PINCTRL_PIN(185, "GPP_H_15"), 233 PINCTRL_PIN(186, "GPP_H_16"), 234 PINCTRL_PIN(187, "GPP_H_17"), 235 PINCTRL_PIN(188, "GPP_H_18"), 236 PINCTRL_PIN(189, "GPP_H_19"), 237 /* vGPIO_3 */ 238 PINCTRL_PIN(190, "CPU_PCIE_LNK_DN_0"), 239 PINCTRL_PIN(191, "CPU_PCIE_LNK_DN_1"), 240 PINCTRL_PIN(192, "CPU_PCIE_LNK_DN_2"), 241 PINCTRL_PIN(193, "CPU_PCIE_LNK_DN_3"), 242 /* vGPIO_0 */ 243 PINCTRL_PIN(194, "ESPI_USB_OCB_0"), 244 PINCTRL_PIN(195, "ESPI_USB_OCB_1"), 245 PINCTRL_PIN(196, "ESPI_USB_OCB_2"), 246 PINCTRL_PIN(197, "ESPI_USB_OCB_3"), 247 PINCTRL_PIN(198, "USB_CPU_OCB_0"), 248 PINCTRL_PIN(199, "USB_CPU_OCB_1"), 249 PINCTRL_PIN(200, "USB_CPU_OCB_2"), 250 PINCTRL_PIN(201, "USB_CPU_OCB_3"), 251 /* vGPIO_4 */ 252 PINCTRL_PIN(202, "ESPI_ISCLK_XTAL_CLKREQ"), 253 PINCTRL_PIN(203, "ISCLK_ESPI_XTAL_CLKACK"), 254 PINCTRL_PIN(204, "ME_SLPC_FTPM_ENABLE"), 255 PINCTRL_PIN(205, "GP_SLPC_DTFUS_CORE_SPITPM_DIS"), 256 PINCTRL_PIN(206, "GP_SLPC_SPI_STRAP_TOS"), 257 PINCTRL_PIN(207, "GP_SLPC_DTFUS_CORE_SPITPM_DIS_L01"), 258 PINCTRL_PIN(208, "GP_SLPC_SPI_STRAP_TOS_L01"), 259 PINCTRL_PIN(209, "LPC_PRR_TS_OVR"), 260 PINCTRL_PIN(210, "ITSS_KU1_SHTDWN"), 261 PINCTRL_PIN(211, "vGPIO_SPARE_0"), 262 PINCTRL_PIN(212, "vGPIO_SPARE_1"), 263 PINCTRL_PIN(213, "vGPIO_SPARE_2"), 264 PINCTRL_PIN(214, "vGPIO_SPARE_3"), 265 PINCTRL_PIN(215, "vGPIO_SPARE_4"), 266 PINCTRL_PIN(216, "vGPIO_SPARE_5"), 267 PINCTRL_PIN(217, "vGPIO_SPARE_6"), 268 PINCTRL_PIN(218, "vGPIO_SPARE_7"), 269 PINCTRL_PIN(219, "vGPIO_SPARE_8"), 270 PINCTRL_PIN(220, "vGPIO_SPARE_9"), 271 PINCTRL_PIN(221, "vGPIO_SPARE_10"), 272 PINCTRL_PIN(222, "vGPIO_SPARE_11"), 273 PINCTRL_PIN(223, "vGPIO_SPARE_12"), 274 PINCTRL_PIN(224, "vGPIO_SPARE_13"), 275 PINCTRL_PIN(225, "vGPIO_SPARE_14"), 276 PINCTRL_PIN(226, "vGPIO_SPARE_15"), 277 PINCTRL_PIN(227, "vGPIO_SPARE_16"), 278 PINCTRL_PIN(228, "vGPIO_SPARE_17"), 279 PINCTRL_PIN(229, "vGPIO_SPARE_18"), 280 PINCTRL_PIN(230, "vGPIO_SPARE_19"), 281 PINCTRL_PIN(231, "vGPIO_SPARE_20"), 282 PINCTRL_PIN(232, "vGPIO_SPARE_21"), 283 /* GPP_S */ 284 PINCTRL_PIN(233, "GPP_S_0"), 285 PINCTRL_PIN(234, "GPP_S_1"), 286 PINCTRL_PIN(235, "GPP_S_2"), 287 PINCTRL_PIN(236, "GPP_S_3"), 288 PINCTRL_PIN(237, "GPP_S_4"), 289 PINCTRL_PIN(238, "GPP_S_5"), 290 PINCTRL_PIN(239, "GPP_S_6"), 291 PINCTRL_PIN(240, "GPP_S_7"), 292 /* GPP_E */ 293 PINCTRL_PIN(241, "GPP_E_0"), 294 PINCTRL_PIN(242, "GPP_E_1"), 295 PINCTRL_PIN(243, "GPP_E_2"), 296 PINCTRL_PIN(244, "GPP_E_3"), 297 PINCTRL_PIN(245, "GPP_E_4"), 298 PINCTRL_PIN(246, "GPP_E_5"), 299 PINCTRL_PIN(247, "GPP_E_6"), 300 PINCTRL_PIN(248, "GPP_E_7"), 301 PINCTRL_PIN(249, "GPP_E_8"), 302 PINCTRL_PIN(250, "GPP_E_9"), 303 PINCTRL_PIN(251, "GPP_E_10"), 304 PINCTRL_PIN(252, "GPP_E_11"), 305 PINCTRL_PIN(253, "GPP_E_12"), 306 PINCTRL_PIN(254, "GPP_E_13"), 307 PINCTRL_PIN(255, "GPP_E_14"), 308 PINCTRL_PIN(256, "GPP_E_15"), 309 PINCTRL_PIN(257, "GPP_E_16"), 310 PINCTRL_PIN(258, "GPP_E_17"), 311 PINCTRL_PIN(259, "GPP_E_18"), 312 PINCTRL_PIN(260, "GPP_E_19"), 313 PINCTRL_PIN(261, "GPP_E_20"), 314 PINCTRL_PIN(262, "GPP_E_21"), 315 PINCTRL_PIN(263, "SPI1_CLK_LOOPBK"), 316 /* GPP_K */ 317 PINCTRL_PIN(264, "GPP_K_0"), 318 PINCTRL_PIN(265, "GPP_K_1"), 319 PINCTRL_PIN(266, "GPP_K_2"), 320 PINCTRL_PIN(267, "GPP_K_3"), 321 PINCTRL_PIN(268, "GPP_K_4"), 322 PINCTRL_PIN(269, "GPP_K_5"), 323 PINCTRL_PIN(270, "FUSE_SORT_BUMP_0"), 324 PINCTRL_PIN(271, "FUSE_SORT_BUMP_1"), 325 PINCTRL_PIN(272, "CORE_VID_0"), 326 PINCTRL_PIN(273, "CORE_VID_1"), 327 PINCTRL_PIN(274, "FUSE_SORT_BUMP_2"), 328 PINCTRL_PIN(275, "MISC_SPARE"), 329 PINCTRL_PIN(276, "SYS_RESETB"), 330 PINCTRL_PIN(277, "MLK_RSTB"), 331 /* GPP_F */ 332 PINCTRL_PIN(278, "SATAXPCIE_3"), 333 PINCTRL_PIN(279, "SATAXPCIE_4"), 334 PINCTRL_PIN(280, "SATAXPCIE_5"), 335 PINCTRL_PIN(281, "SATAXPCIE_6"), 336 PINCTRL_PIN(282, "SATAXPCIE_7"), 337 PINCTRL_PIN(283, "SATA_DEVSLP_3"), 338 PINCTRL_PIN(284, "SATA_DEVSLP_4"), 339 PINCTRL_PIN(285, "SATA_DEVSLP_5"), 340 PINCTRL_PIN(286, "SATA_DEVSLP_6"), 341 PINCTRL_PIN(287, "GPP_F_9"), 342 PINCTRL_PIN(288, "GPP_F_10"), 343 PINCTRL_PIN(289, "GPP_F_11"), 344 PINCTRL_PIN(290, "GPP_F_12"), 345 PINCTRL_PIN(291, "GPP_F_13"), 346 PINCTRL_PIN(292, "GPP_F_14"), 347 PINCTRL_PIN(293, "GPP_F_15"), 348 PINCTRL_PIN(294, "GPP_F_16"), 349 PINCTRL_PIN(295, "GPP_F_17"), 350 PINCTRL_PIN(296, "GPP_F_18"), 351 PINCTRL_PIN(297, "DNX_FORCE_RELOAD"), 352 PINCTRL_PIN(298, "GPP_F_20"), 353 PINCTRL_PIN(299, "GPP_F_21"), 354 PINCTRL_PIN(300, "GPP_F_22"), 355 PINCTRL_PIN(301, "GPP_F_23"), 356 /* GPP_I */ 357 PINCTRL_PIN(302, "GPP_I_0"), 358 PINCTRL_PIN(303, "GPP_I_1"), 359 PINCTRL_PIN(304, "GPP_I_2"), 360 PINCTRL_PIN(305, "GPP_I_3"), 361 PINCTRL_PIN(306, "GPP_I_4"), 362 PINCTRL_PIN(307, "GPP_I_5"), 363 PINCTRL_PIN(308, "GPP_I_6"), 364 PINCTRL_PIN(309, "GPP_I_7"), 365 PINCTRL_PIN(310, "GPP_I_8"), 366 PINCTRL_PIN(311, "GPP_I_9"), 367 PINCTRL_PIN(312, "GPP_I_10"), 368 PINCTRL_PIN(313, "GPP_I_11"), 369 PINCTRL_PIN(314, "GPP_I_12"), 370 PINCTRL_PIN(315, "GPP_I_13"), 371 PINCTRL_PIN(316, "GPP_I_14"), 372 PINCTRL_PIN(317, "GPP_I_15"), 373 PINCTRL_PIN(318, "GPP_I_16"), 374 PINCTRL_PIN(319, "GSPI0_CLK_LOOPBK"), 375 PINCTRL_PIN(320, "GSPI1_CLK_LOOPBK"), 376 PINCTRL_PIN(321, "ISH_I3C0_CLK_LOOPBK"), 377 PINCTRL_PIN(322, "I3C0_CLK_LOOPBK"), 378 /* JTAG_CPU */ 379 PINCTRL_PIN(323, "JTAG_TDO"), 380 PINCTRL_PIN(324, "JTAGX"), 381 PINCTRL_PIN(325, "PRDYB"), 382 PINCTRL_PIN(326, "PREQB"), 383 PINCTRL_PIN(327, "JTAG_TDI"), 384 PINCTRL_PIN(328, "JTAG_TMS"), 385 PINCTRL_PIN(329, "JTAG_TCK"), 386 PINCTRL_PIN(330, "DBG_PMODE"), 387 PINCTRL_PIN(331, "CPU_TRSTB"), 388 PINCTRL_PIN(332, "CPUPWRGD"), 389 PINCTRL_PIN(333, "PM_SPARE0"), 390 PINCTRL_PIN(334, "PM_SPARE1"), 391 PINCTRL_PIN(335, "CRASHLOG_TRIG_N"), 392 PINCTRL_PIN(336, "TRIGGER_IN"), 393 PINCTRL_PIN(337, "TRIGGER_OUT"), 394 PINCTRL_PIN(338, "FBRK_OUT_N"), 395}; 396 397static const struct intel_padgroup mtps_community0_gpps[] = { 398 MTP_GPP(0, 0, 24, 0), /* GPP_D */ 399 MTP_GPP(1, 25, 38, 32), /* GPP_R */ 400 MTP_GPP(2, 39, 56, 64), /* GPP_J */ 401 MTP_GPP(3, 57, 87, 96), /* vGPIO */ 402}; 403 404static const struct intel_padgroup mtps_community1_gpps[] = { 405 MTP_GPP(0, 88, 102, 128), /* GPP_A */ 406 MTP_GPP(1, 103, 114, 160), /* DIR_ESPI */ 407 MTP_GPP(2, 115, 136, 192), /* GPP_B */ 408}; 409 410static const struct intel_padgroup mtps_community3_gpps[] = { 411 MTP_GPP(0, 137, 145, 224), /* SPI0 */ 412 MTP_GPP(1, 146, 169, 256), /* GPP_C */ 413 MTP_GPP(2, 170, 189, 288), /* GPP_H */ 414 MTP_GPP(3, 190, 193, 320), /* vGPIO_3 */ 415 MTP_GPP(4, 194, 201, 352), /* vGPIO_0 */ 416 MTP_GPP(5, 202, 232, 384), /* vGPIO_4 */ 417}; 418 419static const struct intel_padgroup mtps_community4_gpps[] = { 420 MTP_GPP(0, 233, 240, 416), /* GPP_S */ 421 MTP_GPP(1, 241, 263, 448), /* GPP_E */ 422 MTP_GPP(2, 264, 277, 480), /* GPP_K */ 423 MTP_GPP(3, 278, 301, 512), /* GPP_F */ 424}; 425 426static const struct intel_padgroup mtps_community5_gpps[] = { 427 MTP_GPP(0, 302, 322, 544), /* GPP_I */ 428 MTP_GPP(1, 323, 338, 576), /* JTAG_CPU */ 429}; 430 431static const struct intel_community mtps_communities[] = { 432 MTP_COMMUNITY(0, 0, 87, mtps_community0_gpps), 433 MTP_COMMUNITY(1, 88, 136, mtps_community1_gpps), 434 MTP_COMMUNITY(2, 137, 232, mtps_community3_gpps), 435 MTP_COMMUNITY(3, 233, 301, mtps_community4_gpps), 436 MTP_COMMUNITY(4, 302, 338, mtps_community5_gpps), 437}; 438 439static const struct intel_pinctrl_soc_data mtps_soc_data = { 440 .pins = mtps_pins, 441 .npins = ARRAY_SIZE(mtps_pins), 442 .communities = mtps_communities, 443 .ncommunities = ARRAY_SIZE(mtps_communities), 444}; 445 446static const struct acpi_device_id mtp_pinctrl_acpi_match[] = { 447 { "INTC1084", (kernel_ulong_t)&mtps_soc_data }, 448 { } 449}; 450MODULE_DEVICE_TABLE(acpi, mtp_pinctrl_acpi_match); 451 452static struct platform_driver mtp_pinctrl_driver = { 453 .probe = intel_pinctrl_probe_by_hid, 454 .driver = { 455 .name = "meteorpoint-pinctrl", 456 .acpi_match_table = mtp_pinctrl_acpi_match, 457 .pm = pm_sleep_ptr(&intel_pinctrl_pm_ops), 458 }, 459}; 460module_platform_driver(mtp_pinctrl_driver); 461 462MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 463MODULE_DESCRIPTION("Intel Meteor Point PCH pinctrl/GPIO driver"); 464MODULE_LICENSE("GPL v2"); 465MODULE_IMPORT_NS(PINCTRL_INTEL); 466