1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel Cedar Fork PCH pinctrl/GPIO driver
4 *
5 * Copyright (C) 2017, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 */
8
9#include <linux/mod_devicetable.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/pm.h>
13
14#include <linux/pinctrl/pinctrl.h>
15
16#include "pinctrl-intel.h"
17
18#define CDF_PAD_OWN	0x020
19#define CDF_PADCFGLOCK	0x0c0
20#define CDF_HOSTSW_OWN	0x120
21#define CDF_GPI_IS	0x200
22#define CDF_GPI_IE	0x230
23
24#define CDF_GPP(r, s, e)				\
25	{						\
26		.reg_num = (r),				\
27		.base = (s),				\
28		.size = ((e) - (s) + 1),		\
29	}
30
31#define CDF_COMMUNITY(b, s, e, g)			\
32	INTEL_COMMUNITY_GPPS(b, s, e, g, CDF)
33
34/* Cedar Fork PCH */
35static const struct pinctrl_pin_desc cdf_pins[] = {
36	/* WEST2 */
37	PINCTRL_PIN(0, "GBE_SDP_TIMESYNC0_S2N"),
38	PINCTRL_PIN(1, "GBE_SDP_TIMESYNC1_S2N"),
39	PINCTRL_PIN(2, "GBE_SDP_TIMESYNC2_S2N"),
40	PINCTRL_PIN(3, "GBE_SDP_TIMESYNC3_S2N"),
41	PINCTRL_PIN(4, "GBE0_I2C_CLK"),
42	PINCTRL_PIN(5, "GBE0_I2C_DATA"),
43	PINCTRL_PIN(6, "GBE1_I2C_CLK"),
44	PINCTRL_PIN(7, "GBE1_I2C_DATA"),
45	PINCTRL_PIN(8, "GBE2_I2C_CLK"),
46	PINCTRL_PIN(9, "GBE2_I2C_DATA"),
47	PINCTRL_PIN(10, "GBE3_I2C_CLK"),
48	PINCTRL_PIN(11, "GBE3_I2C_DATA"),
49	PINCTRL_PIN(12, "GBE0_LED0"),
50	PINCTRL_PIN(13, "GBE0_LED1"),
51	PINCTRL_PIN(14, "GBE0_LED2"),
52	PINCTRL_PIN(15, "GBE1_LED0"),
53	PINCTRL_PIN(16, "GBE1_LED1"),
54	PINCTRL_PIN(17, "GBE1_LED2"),
55	PINCTRL_PIN(18, "GBE2_LED0"),
56	PINCTRL_PIN(19, "GBE2_LED1"),
57	PINCTRL_PIN(20, "GBE2_LED2"),
58	PINCTRL_PIN(21, "GBE3_LED0"),
59	PINCTRL_PIN(22, "GBE3_LED1"),
60	PINCTRL_PIN(23, "GBE3_LED2"),
61	/* WEST3 */
62	PINCTRL_PIN(24, "NCSI_RXD0"),
63	PINCTRL_PIN(25, "NCSI_CLK_IN"),
64	PINCTRL_PIN(26, "NCSI_RXD1"),
65	PINCTRL_PIN(27, "NCSI_CRS_DV"),
66	PINCTRL_PIN(28, "NCSI_ARB_IN"),
67	PINCTRL_PIN(29, "NCSI_TX_EN"),
68	PINCTRL_PIN(30, "NCSI_TXD0"),
69	PINCTRL_PIN(31, "NCSI_TXD1"),
70	PINCTRL_PIN(32, "NCSI_ARB_OUT"),
71	PINCTRL_PIN(33, "GBE_SMB_CLK"),
72	PINCTRL_PIN(34, "GBE_SMB_DATA"),
73	PINCTRL_PIN(35, "GBE_SMB_ALRT_N"),
74	PINCTRL_PIN(36, "THERMTRIP_N"),
75	PINCTRL_PIN(37, "PCHHOT_N"),
76	PINCTRL_PIN(38, "ERROR0_N"),
77	PINCTRL_PIN(39, "ERROR1_N"),
78	PINCTRL_PIN(40, "ERROR2_N"),
79	PINCTRL_PIN(41, "MSMI_N"),
80	PINCTRL_PIN(42, "CATERR_N"),
81	PINCTRL_PIN(43, "MEMTRIP_N"),
82	PINCTRL_PIN(44, "UART0_RXD"),
83	PINCTRL_PIN(45, "UART0_TXD"),
84	PINCTRL_PIN(46, "GBE_UART_RXD"),
85	PINCTRL_PIN(47, "GBE_UART_TXD"),
86	/* WEST01 */
87	PINCTRL_PIN(48, "GBE_GPIO13"),
88	PINCTRL_PIN(49, "AUX_PWR"),
89	PINCTRL_PIN(50, "UART0_RTS"),
90	PINCTRL_PIN(51, "UART0_CTS"),
91	PINCTRL_PIN(52, "FAN_PWM_0"),
92	PINCTRL_PIN(53, "FAN_PWM_1"),
93	PINCTRL_PIN(54, "FAN_PWM_2"),
94	PINCTRL_PIN(55, "FAN_PWM_3"),
95	PINCTRL_PIN(56, "FAN_TACH_0"),
96	PINCTRL_PIN(57, "FAN_TACH_1"),
97	PINCTRL_PIN(58, "FAN_TACH_2"),
98	PINCTRL_PIN(59, "FAN_TACH_3"),
99	PINCTRL_PIN(60, "ME_SMB0_CLK"),
100	PINCTRL_PIN(61, "ME_SMB0_DATA"),
101	PINCTRL_PIN(62, "ME_SMB0_ALRT_N"),
102	PINCTRL_PIN(63, "ME_SMB1_CLK"),
103	PINCTRL_PIN(64, "ME_SMB1_DATA"),
104	PINCTRL_PIN(65, "ME_SMB1_ALRT_N"),
105	PINCTRL_PIN(66, "ME_SMB2_CLK"),
106	PINCTRL_PIN(67, "ME_SMB2_DATA"),
107	PINCTRL_PIN(68, "ME_SMB2_ALRT_N"),
108	PINCTRL_PIN(69, "GBE_MNG_I2C_CLK"),
109	PINCTRL_PIN(70, "GBE_MNG_I2C_DATA"),
110	/* WEST5 */
111	PINCTRL_PIN(71, "IE_UART_RXD"),
112	PINCTRL_PIN(72, "IE_UART_TXD"),
113	PINCTRL_PIN(73, "VPP_SMB_CLK"),
114	PINCTRL_PIN(74, "VPP_SMB_DATA"),
115	PINCTRL_PIN(75, "VPP_SMB_ALRT_N"),
116	PINCTRL_PIN(76, "PCIE_CLKREQ0_N"),
117	PINCTRL_PIN(77, "PCIE_CLKREQ1_N"),
118	PINCTRL_PIN(78, "PCIE_CLKREQ2_N"),
119	PINCTRL_PIN(79, "PCIE_CLKREQ3_N"),
120	PINCTRL_PIN(80, "PCIE_CLKREQ4_N"),
121	PINCTRL_PIN(81, "PCIE_CLKREQ5_N"),
122	PINCTRL_PIN(82, "PCIE_CLKREQ6_N"),
123	PINCTRL_PIN(83, "PCIE_CLKREQ7_N"),
124	PINCTRL_PIN(84, "PCIE_CLKREQ8_N"),
125	PINCTRL_PIN(85, "PCIE_CLKREQ9_N"),
126	PINCTRL_PIN(86, "FLEX_CLK_SE0"),
127	PINCTRL_PIN(87, "FLEX_CLK_SE1"),
128	PINCTRL_PIN(88, "FLEX_CLK1_50"),
129	PINCTRL_PIN(89, "FLEX_CLK2_50"),
130	PINCTRL_PIN(90, "FLEX_CLK_125"),
131	/* WESTC */
132	PINCTRL_PIN(91, "TCK_PCH"),
133	PINCTRL_PIN(92, "JTAGX_PCH"),
134	PINCTRL_PIN(93, "TRST_N_PCH"),
135	PINCTRL_PIN(94, "TMS_PCH"),
136	PINCTRL_PIN(95, "TDI_PCH"),
137	PINCTRL_PIN(96, "TDO_PCH"),
138	/* WESTC_DFX */
139	PINCTRL_PIN(97, "CX_PRDY_N"),
140	PINCTRL_PIN(98, "CX_PREQ_N"),
141	PINCTRL_PIN(99, "CPU_FBREAK_OUT_N"),
142	PINCTRL_PIN(100, "TRIGGER0_N"),
143	PINCTRL_PIN(101, "TRIGGER1_N"),
144	/* WESTA */
145	PINCTRL_PIN(102, "DBG_PTI_CLK0"),
146	PINCTRL_PIN(103, "DBG_PTI_CLK3"),
147	PINCTRL_PIN(104, "DBG_PTI_DATA0"),
148	PINCTRL_PIN(105, "DBG_PTI_DATA1"),
149	PINCTRL_PIN(106, "DBG_PTI_DATA2"),
150	PINCTRL_PIN(107, "DBG_PTI_DATA3"),
151	PINCTRL_PIN(108, "DBG_PTI_DATA4"),
152	PINCTRL_PIN(109, "DBG_PTI_DATA5"),
153	PINCTRL_PIN(110, "DBG_PTI_DATA6"),
154	PINCTRL_PIN(111, "DBG_PTI_DATA7"),
155	/* WESTB */
156	PINCTRL_PIN(112, "DBG_PTI_DATA8"),
157	PINCTRL_PIN(113, "DBG_PTI_DATA9"),
158	PINCTRL_PIN(114, "DBG_PTI_DATA10"),
159	PINCTRL_PIN(115, "DBG_PTI_DATA11"),
160	PINCTRL_PIN(116, "DBG_PTI_DATA12"),
161	PINCTRL_PIN(117, "DBG_PTI_DATA13"),
162	PINCTRL_PIN(118, "DBG_PTI_DATA14"),
163	PINCTRL_PIN(119, "DBG_PTI_DATA15"),
164	PINCTRL_PIN(120, "DBG_SPARE0"),
165	PINCTRL_PIN(121, "DBG_SPARE1"),
166	PINCTRL_PIN(122, "DBG_SPARE2"),
167	PINCTRL_PIN(123, "DBG_SPARE3"),
168	/* WESTD */
169	PINCTRL_PIN(124, "CPU_PWR_GOOD"),
170	PINCTRL_PIN(125, "PLTRST_CPU_N"),
171	PINCTRL_PIN(126, "NAC_RESET_NAC_N"),
172	PINCTRL_PIN(127, "PCH_SBLINK_RX"),
173	PINCTRL_PIN(128, "PCH_SBLINK_TX"),
174	PINCTRL_PIN(129, "PMSYNC_CLK"),
175	PINCTRL_PIN(130, "CPU_ERR0_N"),
176	PINCTRL_PIN(131, "CPU_ERR1_N"),
177	PINCTRL_PIN(132, "CPU_ERR2_N"),
178	PINCTRL_PIN(133, "CPU_THERMTRIP_N"),
179	PINCTRL_PIN(134, "CPU_MSMI_N"),
180	PINCTRL_PIN(135, "CPU_CATERR_N"),
181	PINCTRL_PIN(136, "CPU_MEMTRIP_N"),
182	PINCTRL_PIN(137, "NAC_GR_N"),
183	PINCTRL_PIN(138, "NAC_XTAL_VALID"),
184	PINCTRL_PIN(139, "NAC_WAKE_N"),
185	PINCTRL_PIN(140, "NAC_SBLINK_CLK_S2N"),
186	PINCTRL_PIN(141, "NAC_SBLINK_N2S"),
187	PINCTRL_PIN(142, "NAC_SBLINK_S2N"),
188	PINCTRL_PIN(143, "NAC_SBLINK_CLK_N2S"),
189	/* WESTD_PECI */
190	PINCTRL_PIN(144, "ME_PECI"),
191	/* WESTF */
192	PINCTRL_PIN(145, "NAC_RMII_CLK"),
193	PINCTRL_PIN(146, "NAC_RGMII_CLK"),
194	PINCTRL_PIN(147, "NAC_GBE_SMB_CLK_TX_N2S"),
195	PINCTRL_PIN(148, "NAC_GBE_SMB_DATA_TX_N2S"),
196	PINCTRL_PIN(149, "NAC_SPARE2"),
197	PINCTRL_PIN(150, "NAC_INIT_SX_WAKE_N"),
198	PINCTRL_PIN(151, "NAC_GBE_GPIO0_S2N"),
199	PINCTRL_PIN(152, "NAC_GBE_GPIO1_S2N"),
200	PINCTRL_PIN(153, "NAC_GBE_GPIO2_S2N"),
201	PINCTRL_PIN(154, "NAC_GBE_GPIO3_S2N"),
202	PINCTRL_PIN(155, "NAC_NCSI_RXD0"),
203	PINCTRL_PIN(156, "NAC_NCSI_CLK_IN"),
204	PINCTRL_PIN(157, "NAC_NCSI_RXD1"),
205	PINCTRL_PIN(158, "NAC_NCSI_CRS_DV"),
206	PINCTRL_PIN(159, "NAC_NCSI_ARB_IN"),
207	PINCTRL_PIN(160, "NAC_NCSI_TX_EN"),
208	PINCTRL_PIN(161, "NAC_NCSI_TXD0"),
209	PINCTRL_PIN(162, "NAC_NCSI_TXD1"),
210	PINCTRL_PIN(163, "NAC_NCSI_ARB_OUT"),
211	PINCTRL_PIN(164, "NAC_NCSI_OE_N"),
212	PINCTRL_PIN(165, "NAC_GBE_SMB_CLK_RX_S2N"),
213	PINCTRL_PIN(166, "NAC_GBE_SMB_DATA_RX_S2N"),
214	PINCTRL_PIN(167, "NAC_GBE_SMB_ALRT_N"),
215	/* EAST2 */
216	PINCTRL_PIN(168, "USB_OC0_N"),
217	PINCTRL_PIN(169, "GBE_GPIO0"),
218	PINCTRL_PIN(170, "GBE_GPIO1"),
219	PINCTRL_PIN(171, "GBE_GPIO2"),
220	PINCTRL_PIN(172, "GBE_GPIO3"),
221	PINCTRL_PIN(173, "GBE_GPIO4"),
222	PINCTRL_PIN(174, "GBE_GPIO5"),
223	PINCTRL_PIN(175, "GBE_GPIO6"),
224	PINCTRL_PIN(176, "GBE_GPIO7"),
225	PINCTRL_PIN(177, "SPI_TPM_CS_N"),
226	PINCTRL_PIN(178, "GBE_GPIO9"),
227	PINCTRL_PIN(179, "GBE_GPIO10"),
228	PINCTRL_PIN(180, "GBE_GPIO11"),
229	PINCTRL_PIN(181, "GBE_GPIO12"),
230	PINCTRL_PIN(182, "PECI_SMB_DATA"),
231	PINCTRL_PIN(183, "SATA0_LED_N"),
232	PINCTRL_PIN(184, "SATA1_LED_N"),
233	PINCTRL_PIN(185, "SATA_PDETECT0"),
234	PINCTRL_PIN(186, "SATA_PDETECT1"),
235	PINCTRL_PIN(187, "SATA0_SDOUT"),
236	PINCTRL_PIN(188, "SATA1_SDOUT"),
237	PINCTRL_PIN(189, "SATA2_LED_N"),
238	PINCTRL_PIN(190, "SATA_PDETECT2"),
239	PINCTRL_PIN(191, "SATA2_SDOUT"),
240	/* EAST3 */
241	PINCTRL_PIN(192, "ESPI_IO0"),
242	PINCTRL_PIN(193, "ESPI_IO1"),
243	PINCTRL_PIN(194, "ESPI_IO2"),
244	PINCTRL_PIN(195, "ESPI_IO3"),
245	PINCTRL_PIN(196, "ESPI_CLK"),
246	PINCTRL_PIN(197, "ESPI_RST_N"),
247	PINCTRL_PIN(198, "ESPI_CS0_N"),
248	PINCTRL_PIN(199, "ESPI_ALRT0_N"),
249	PINCTRL_PIN(200, "ESPI_CS1_N"),
250	PINCTRL_PIN(201, "ESPI_ALRT1_N"),
251	PINCTRL_PIN(202, "ESPI_CLK_LOOPBK"),
252	/* EAST0 */
253	PINCTRL_PIN(203, "SPI_CS0_N"),
254	PINCTRL_PIN(204, "SPI_CS1_N"),
255	PINCTRL_PIN(205, "SPI_MOSI_IO0"),
256	PINCTRL_PIN(206, "SPI_MISO_IO1"),
257	PINCTRL_PIN(207, "SPI_IO2"),
258	PINCTRL_PIN(208, "SPI_IO3"),
259	PINCTRL_PIN(209, "SPI_CLK"),
260	PINCTRL_PIN(210, "SPI_CLK_LOOPBK"),
261	PINCTRL_PIN(211, "SUSPWRDNACK"),
262	PINCTRL_PIN(212, "PMU_SUSCLK"),
263	PINCTRL_PIN(213, "ADR_COMPLETE"),
264	PINCTRL_PIN(214, "ADR_TRIGGER_N"),
265	PINCTRL_PIN(215, "PMU_SLP_S45_N"),
266	PINCTRL_PIN(216, "PMU_SLP_S3_N"),
267	PINCTRL_PIN(217, "PMU_WAKE_N"),
268	PINCTRL_PIN(218, "PMU_PWRBTN_N"),
269	PINCTRL_PIN(219, "PMU_RESETBUTTON_N"),
270	PINCTRL_PIN(220, "PMU_PLTRST_N"),
271	PINCTRL_PIN(221, "SUS_STAT_N"),
272	PINCTRL_PIN(222, "PMU_I2C_CLK"),
273	PINCTRL_PIN(223, "PMU_I2C_DATA"),
274	PINCTRL_PIN(224, "PECI_SMB_CLK"),
275	PINCTRL_PIN(225, "PECI_SMB_ALRT_N"),
276	/* EMMC */
277	PINCTRL_PIN(226, "EMMC_CMD"),
278	PINCTRL_PIN(227, "EMMC_STROBE"),
279	PINCTRL_PIN(228, "EMMC_CLK"),
280	PINCTRL_PIN(229, "EMMC_D0"),
281	PINCTRL_PIN(230, "EMMC_D1"),
282	PINCTRL_PIN(231, "EMMC_D2"),
283	PINCTRL_PIN(232, "EMMC_D3"),
284	PINCTRL_PIN(233, "EMMC_D4"),
285	PINCTRL_PIN(234, "EMMC_D5"),
286	PINCTRL_PIN(235, "EMMC_D6"),
287	PINCTRL_PIN(236, "EMMC_D7"),
288};
289
290static const struct intel_padgroup cdf_community0_gpps[] = {
291	CDF_GPP(0, 0, 23),	/* WEST2 */
292	CDF_GPP(1, 24, 47),	/* WEST3 */
293	CDF_GPP(2, 48, 70),	/* WEST01 */
294	CDF_GPP(3, 71, 90),	/* WEST5 */
295	CDF_GPP(4, 91, 96),	/* WESTC */
296	CDF_GPP(5, 97, 101),	/* WESTC_DFX */
297	CDF_GPP(6, 102, 111),	/* WESTA */
298	CDF_GPP(7, 112, 123),	/* WESTB */
299	CDF_GPP(8, 124, 143),	/* WESTD */
300	CDF_GPP(9, 144, 144),	/* WESTD_PECI */
301	CDF_GPP(10, 145, 167),	/* WESTF */
302};
303
304static const struct intel_padgroup cdf_community1_gpps[] = {
305	CDF_GPP(0, 168, 191),	/* EAST2 */
306	CDF_GPP(1, 192, 202),	/* EAST3 */
307	CDF_GPP(2, 203, 225),	/* EAST0 */
308	CDF_GPP(3, 226, 236),	/* EMMC */
309};
310
311static const struct intel_community cdf_communities[] = {
312	CDF_COMMUNITY(0, 0, 167, cdf_community0_gpps),		/* West */
313	CDF_COMMUNITY(1, 168, 236, cdf_community1_gpps),	/* East */
314};
315
316static const struct intel_pinctrl_soc_data cdf_soc_data = {
317	.pins = cdf_pins,
318	.npins = ARRAY_SIZE(cdf_pins),
319	.communities = cdf_communities,
320	.ncommunities = ARRAY_SIZE(cdf_communities),
321};
322
323static const struct acpi_device_id cdf_pinctrl_acpi_match[] = {
324	{ "INTC3001", (kernel_ulong_t)&cdf_soc_data },
325	{ }
326};
327MODULE_DEVICE_TABLE(acpi, cdf_pinctrl_acpi_match);
328
329static struct platform_driver cdf_pinctrl_driver = {
330	.probe = intel_pinctrl_probe_by_hid,
331	.driver = {
332		.name = "cedarfork-pinctrl",
333		.acpi_match_table = cdf_pinctrl_acpi_match,
334		.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
335	},
336};
337
338static int __init cdf_pinctrl_init(void)
339{
340	return platform_driver_register(&cdf_pinctrl_driver);
341}
342subsys_initcall(cdf_pinctrl_init);
343
344static void __exit cdf_pinctrl_exit(void)
345{
346	platform_driver_unregister(&cdf_pinctrl_driver);
347}
348module_exit(cdf_pinctrl_exit);
349
350MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
351MODULE_DESCRIPTION("Intel Cedar Fork PCH pinctrl/GPIO driver");
352MODULE_LICENSE("GPL v2");
353MODULE_IMPORT_NS(PINCTRL_INTEL);
354