1/* SPDX-License-Identifier: GPL-2.0-only
2 *
3 * Copyright (c) 2021, MediaTek Inc.
4 * Copyright (c) 2021-2022, Intel Corporation.
5 *
6 * Authors:
7 *  Haijun Liu <haijun.liu@mediatek.com>
8 *  Ricardo Martinez <ricardo.martinez@linux.intel.com>
9 *  Sreehari Kancharla <sreehari.kancharla@intel.com>
10 *
11 * Contributors:
12 *  Amir Hanania <amir.hanania@intel.com>
13 *  Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
14 *  Moises Veleta <moises.veleta@intel.com>
15 */
16
17#ifndef __T7XX_PCI_H__
18#define __T7XX_PCI_H__
19
20#include <linux/completion.h>
21#include <linux/irqreturn.h>
22#include <linux/mutex.h>
23#include <linux/pci.h>
24#include <linux/spinlock.h>
25#include <linux/types.h>
26
27#include "t7xx_reg.h"
28
29/* struct t7xx_addr_base - holds base addresses
30 * @pcie_mac_ireg_base: PCIe MAC register base
31 * @pcie_ext_reg_base: used to calculate base addresses for CLDMA, DPMA and MHCCIF registers
32 * @pcie_dev_reg_trsl_addr: used to calculate the register base address
33 * @infracfg_ao_base: base address used in CLDMA reset operations
34 * @mhccif_rc_base: host view of MHCCIF rc base addr
35 */
36struct t7xx_addr_base {
37	void __iomem		*pcie_mac_ireg_base;
38	void __iomem		*pcie_ext_reg_base;
39	u32			pcie_dev_reg_trsl_addr;
40	void __iomem		*infracfg_ao_base;
41	void __iomem		*mhccif_rc_base;
42};
43
44typedef irqreturn_t (*t7xx_intr_callback)(int irq, void *param);
45
46enum t7xx_mode {
47	T7XX_UNKNOWN,
48	T7XX_READY,
49	T7XX_RESET,
50	T7XX_FASTBOOT_SWITCHING,
51	T7XX_FASTBOOT_DOWNLOAD,
52	T7XX_FASTBOOT_DUMP,
53	T7XX_MODE_LAST, /* must always be last */
54};
55
56/* struct t7xx_pci_dev - MTK device context structure
57 * @intr_handler: array of handler function for request_threaded_irq
58 * @intr_thread: array of thread_fn for request_threaded_irq
59 * @callback_param: array of cookie passed back to interrupt functions
60 * @pdev: PCI device
61 * @base_addr: memory base addresses of HW components
62 * @md: modem interface
63 * @ccmni_ctlb: context structure used to control the network data path
64 * @rgu_pci_irq_en: RGU callback ISR registered and active
65 * @md_pm_entities: list of pm entities
66 * @md_pm_entity_mtx: protects md_pm_entities list
67 * @pm_sr_ack: ack from the device when went to sleep or woke up
68 * @md_pm_state: state for resume/suspend
69 * @md_pm_lock: protects PCIe sleep lock
70 * @sleep_disable_count: PCIe L1.2 lock counter
71 * @sleep_lock_acquire: indicates that sleep has been disabled
72 * @mode: indicates the device mode
73 */
74struct t7xx_pci_dev {
75	t7xx_intr_callback	intr_handler[EXT_INT_NUM];
76	t7xx_intr_callback	intr_thread[EXT_INT_NUM];
77	void			*callback_param[EXT_INT_NUM];
78	struct pci_dev		*pdev;
79	struct t7xx_addr_base	base_addr;
80	struct t7xx_modem	*md;
81	struct t7xx_ccmni_ctrl	*ccmni_ctlb;
82	bool			rgu_pci_irq_en;
83	struct completion	init_done;
84
85	/* Low Power Items */
86	struct list_head	md_pm_entities;
87	struct mutex		md_pm_entity_mtx;	/* Protects MD PM entities list */
88	struct completion	pm_sr_ack;
89	atomic_t		md_pm_state;
90	spinlock_t		md_pm_lock;		/* Protects PCI resource lock */
91	unsigned int		sleep_disable_count;
92	struct completion	sleep_lock_acquire;
93#ifdef CONFIG_WWAN_DEBUGFS
94	struct dentry		*debugfs_dir;
95#endif
96	u32			mode;
97};
98
99enum t7xx_pm_id {
100	PM_ENTITY_ID_CTRL1,
101	PM_ENTITY_ID_CTRL2,
102	PM_ENTITY_ID_DATA,
103	PM_ENTITY_ID_INVALID
104};
105
106/* struct md_pm_entity - device power management entity
107 * @entity: list of PM Entities
108 * @suspend: callback invoked before sending D3 request to device
109 * @suspend_late: callback invoked after getting D3 ACK from device
110 * @resume_early: callback invoked before sending the resume request to device
111 * @resume: callback invoked after getting resume ACK from device
112 * @id: unique PM entity identifier
113 * @entity_param: parameter passed to the registered callbacks
114 *
115 *  This structure is used to indicate PM operations required by internal
116 *  HW modules such as CLDMA and DPMA.
117 */
118struct md_pm_entity {
119	struct list_head	entity;
120	int (*suspend)(struct t7xx_pci_dev *t7xx_dev, void *entity_param);
121	void (*suspend_late)(struct t7xx_pci_dev *t7xx_dev, void *entity_param);
122	void (*resume_early)(struct t7xx_pci_dev *t7xx_dev, void *entity_param);
123	int (*resume)(struct t7xx_pci_dev *t7xx_dev, void *entity_param);
124	enum t7xx_pm_id		id;
125	void			*entity_param;
126};
127
128void t7xx_pci_disable_sleep(struct t7xx_pci_dev *t7xx_dev);
129void t7xx_pci_enable_sleep(struct t7xx_pci_dev *t7xx_dev);
130int t7xx_pci_sleep_disable_complete(struct t7xx_pci_dev *t7xx_dev);
131int t7xx_pci_pm_entity_register(struct t7xx_pci_dev *t7xx_dev, struct md_pm_entity *pm_entity);
132int t7xx_pci_pm_entity_unregister(struct t7xx_pci_dev *t7xx_dev, struct md_pm_entity *pm_entity);
133void t7xx_pci_pm_init_late(struct t7xx_pci_dev *t7xx_dev);
134void t7xx_pci_pm_exp_detected(struct t7xx_pci_dev *t7xx_dev);
135void t7xx_mode_update(struct t7xx_pci_dev *t7xx_dev, enum t7xx_mode mode);
136#endif /* __T7XX_PCI_H__ */
137