1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 */ 6 7#ifndef __SPARX5_MAIN_H__ 8#define __SPARX5_MAIN_H__ 9 10#include <linux/types.h> 11#include <linux/phy/phy.h> 12#include <linux/netdevice.h> 13#include <linux/phy.h> 14#include <linux/if_vlan.h> 15#include <linux/bitmap.h> 16#include <linux/phylink.h> 17#include <linux/net_tstamp.h> 18#include <linux/ptp_clock_kernel.h> 19#include <linux/hrtimer.h> 20#include <linux/debugfs.h> 21#include <net/flow_offload.h> 22 23#include "sparx5_main_regs.h" 24 25/* Target chip type */ 26enum spx5_target_chiptype { 27 SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */ 28 SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */ 29 SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */ 30 SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */ 31 SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */ 32 SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */ 33 SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */ 34 SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */ 35 SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */ 36 SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */ 37}; 38 39enum sparx5_port_max_tags { 40 SPX5_PORT_MAX_TAGS_NONE, /* No extra tags allowed */ 41 SPX5_PORT_MAX_TAGS_ONE, /* Single tag allowed */ 42 SPX5_PORT_MAX_TAGS_TWO /* Single and double tag allowed */ 43}; 44 45enum sparx5_vlan_port_type { 46 SPX5_VLAN_PORT_TYPE_UNAWARE, /* VLAN unaware port */ 47 SPX5_VLAN_PORT_TYPE_C, /* C-port */ 48 SPX5_VLAN_PORT_TYPE_S, /* S-port */ 49 SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */ 50}; 51 52#define SPX5_PORTS 65 53#define SPX5_PORT_CPU (SPX5_PORTS) /* Next port is CPU port */ 54#define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */ 55#define SPX5_PORT_CPU_1 (SPX5_PORT_CPU + 1) /* CPU Port 66 */ 56#define SPX5_PORT_VD0 (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */ 57#define SPX5_PORT_VD1 (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */ 58#define SPX5_PORT_VD2 (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/ 59#define SPX5_PORTS_ALL (SPX5_PORT_CPU + 5) /* Total number of ports */ 60 61#define PGID_BASE SPX5_PORTS /* Starts after port PGIDs */ 62#define PGID_UC_FLOOD (PGID_BASE + 0) 63#define PGID_MC_FLOOD (PGID_BASE + 1) 64#define PGID_IPV4_MC_DATA (PGID_BASE + 2) 65#define PGID_IPV4_MC_CTRL (PGID_BASE + 3) 66#define PGID_IPV6_MC_DATA (PGID_BASE + 4) 67#define PGID_IPV6_MC_CTRL (PGID_BASE + 5) 68#define PGID_BCAST (PGID_BASE + 6) 69#define PGID_CPU (PGID_BASE + 7) 70#define PGID_MCAST_START (PGID_BASE + 8) 71 72#define PGID_TABLE_SIZE 3290 73 74#define IFH_LEN 9 /* 36 bytes */ 75#define NULL_VID 0 76#define SPX5_MACT_PULL_DELAY (2 * HZ) 77#define SPX5_STATS_CHECK_DELAY (1 * HZ) 78#define SPX5_PRIOS 8 /* Number of priority queues */ 79#define SPX5_BUFFER_CELL_SZ 184 /* Cell size */ 80#define SPX5_BUFFER_MEMORY 4194280 /* 22795 words * 184 bytes */ 81 82#define XTR_QUEUE 0 83#define INJ_QUEUE 0 84 85#define FDMA_DCB_MAX 64 86#define FDMA_RX_DCB_MAX_DBS 15 87#define FDMA_TX_DCB_MAX_DBS 1 88 89#define SPARX5_PHC_COUNT 3 90#define SPARX5_PHC_PORT 0 91 92#define IFH_REW_OP_NOOP 0x0 93#define IFH_REW_OP_ONE_STEP_PTP 0x3 94#define IFH_REW_OP_TWO_STEP_PTP 0x4 95 96#define IFH_PDU_TYPE_NONE 0x0 97#define IFH_PDU_TYPE_PTP 0x5 98#define IFH_PDU_TYPE_IPV4_UDP_PTP 0x6 99#define IFH_PDU_TYPE_IPV6_UDP_PTP 0x7 100 101struct sparx5; 102 103struct sparx5_db_hw { 104 u64 dataptr; 105 u64 status; 106}; 107 108struct sparx5_rx_dcb_hw { 109 u64 nextptr; 110 u64 info; 111 struct sparx5_db_hw db[FDMA_RX_DCB_MAX_DBS]; 112}; 113 114struct sparx5_tx_dcb_hw { 115 u64 nextptr; 116 u64 info; 117 struct sparx5_db_hw db[FDMA_TX_DCB_MAX_DBS]; 118}; 119 120/* Frame DMA receive state: 121 * For each DB, there is a SKB, and the skb data pointer is mapped in 122 * the DB. Once a frame is received the skb is given to the upper layers 123 * and a new skb is added to the dcb. 124 * When the db_index reached FDMA_RX_DCB_MAX_DBS the DB is reused. 125 */ 126struct sparx5_rx { 127 struct sparx5_rx_dcb_hw *dcb_entries; 128 struct sparx5_rx_dcb_hw *last_entry; 129 struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS]; 130 int db_index; 131 int dcb_index; 132 dma_addr_t dma; 133 struct napi_struct napi; 134 u32 channel_id; 135 struct net_device *ndev; 136 u64 packets; 137}; 138 139/* Frame DMA transmit state: 140 * DCBs are chained using the DCBs nextptr field. 141 */ 142struct sparx5_tx { 143 struct sparx5_tx_dcb_hw *curr_entry; 144 struct sparx5_tx_dcb_hw *first_entry; 145 struct list_head db_list; 146 dma_addr_t dma; 147 u32 channel_id; 148 u64 packets; 149 u64 dropped; 150}; 151 152struct sparx5_port_config { 153 phy_interface_t portmode; 154 u32 bandwidth; 155 int speed; 156 int duplex; 157 enum phy_media media; 158 bool inband; 159 bool power_down; 160 bool autoneg; 161 bool serdes_reset; 162 u32 pause; 163 u32 pause_adv; 164 phy_interface_t phy_mode; 165 u32 sd_sgpio; 166}; 167 168struct sparx5_port { 169 struct net_device *ndev; 170 struct sparx5 *sparx5; 171 struct device_node *of_node; 172 struct phy *serdes; 173 struct sparx5_port_config conf; 174 struct phylink_config phylink_config; 175 struct phylink *phylink; 176 struct phylink_pcs phylink_pcs; 177 struct flow_stats mirror_stats; 178 u16 portno; 179 /* Ingress default VLAN (pvid) */ 180 u16 pvid; 181 /* Egress default VLAN (vid) */ 182 u16 vid; 183 bool signd_internal; 184 bool signd_active_high; 185 bool signd_enable; 186 bool flow_control; 187 enum sparx5_port_max_tags max_vlan_tags; 188 enum sparx5_vlan_port_type vlan_type; 189 u32 custom_etype; 190 bool vlan_aware; 191 struct hrtimer inj_timer; 192 /* ptp */ 193 u8 ptp_cmd; 194 u16 ts_id; 195 struct sk_buff_head tx_skbs; 196 bool is_mrouter; 197 struct list_head tc_templates; /* list of TC templates on this port */ 198}; 199 200enum sparx5_core_clockfreq { 201 SPX5_CORE_CLOCK_DEFAULT, /* Defaults to the highest supported frequency */ 202 SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */ 203 SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */ 204 SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */ 205}; 206 207struct sparx5_phc { 208 struct ptp_clock *clock; 209 struct ptp_clock_info info; 210 struct kernel_hwtstamp_config hwtstamp_config; 211 struct sparx5 *sparx5; 212 u8 index; 213}; 214 215struct sparx5_skb_cb { 216 u8 rew_op; 217 u8 pdu_type; 218 u8 pdu_w16_offset; 219 u16 ts_id; 220 unsigned long jiffies; 221}; 222 223struct sparx5_mdb_entry { 224 struct list_head list; 225 DECLARE_BITMAP(port_mask, SPX5_PORTS); 226 unsigned char addr[ETH_ALEN]; 227 bool cpu_copy; 228 u16 vid; 229 u16 pgid_idx; 230}; 231 232struct sparx5_mall_mirror_entry { 233 u32 idx; 234 struct sparx5_port *port; 235}; 236 237struct sparx5_mall_entry { 238 struct list_head list; 239 struct sparx5_port *port; 240 unsigned long cookie; 241 enum flow_action_id type; 242 bool ingress; 243 union { 244 struct sparx5_mall_mirror_entry mirror; 245 }; 246}; 247 248#define SPARX5_PTP_TIMEOUT msecs_to_jiffies(10) 249#define SPARX5_SKB_CB(skb) \ 250 ((struct sparx5_skb_cb *)((skb)->cb)) 251 252struct sparx5 { 253 struct platform_device *pdev; 254 struct device *dev; 255 u32 chip_id; 256 enum spx5_target_chiptype target_ct; 257 void __iomem *regs[NUM_TARGETS]; 258 int port_count; 259 struct mutex lock; /* MAC reg lock */ 260 /* port structures are in net device */ 261 struct sparx5_port *ports[SPX5_PORTS]; 262 enum sparx5_core_clockfreq coreclock; 263 /* Statistics */ 264 u32 num_stats; 265 u32 num_ethtool_stats; 266 const char * const *stats_layout; 267 u64 *stats; 268 /* Workqueue for reading stats */ 269 struct mutex queue_stats_lock; 270 struct delayed_work stats_work; 271 struct workqueue_struct *stats_queue; 272 /* Notifiers */ 273 struct notifier_block netdevice_nb; 274 struct notifier_block switchdev_nb; 275 struct notifier_block switchdev_blocking_nb; 276 /* Switch state */ 277 u8 base_mac[ETH_ALEN]; 278 /* Associated bridge device (when bridged) */ 279 struct net_device *hw_bridge_dev; 280 /* Bridged interfaces */ 281 DECLARE_BITMAP(bridge_mask, SPX5_PORTS); 282 DECLARE_BITMAP(bridge_fwd_mask, SPX5_PORTS); 283 DECLARE_BITMAP(bridge_lrn_mask, SPX5_PORTS); 284 DECLARE_BITMAP(vlan_mask[VLAN_N_VID], SPX5_PORTS); 285 /* SW MAC table */ 286 struct list_head mact_entries; 287 /* mac table list (mact_entries) mutex */ 288 struct mutex mact_lock; 289 /* SW MDB table */ 290 struct list_head mdb_entries; 291 /* mdb list mutex */ 292 struct mutex mdb_lock; 293 struct delayed_work mact_work; 294 struct workqueue_struct *mact_queue; 295 /* Board specifics */ 296 bool sd_sgpio_remapping; 297 /* Register based inj/xtr */ 298 int xtr_irq; 299 /* Frame DMA */ 300 int fdma_irq; 301 spinlock_t tx_lock; /* lock for frame transmission */ 302 struct sparx5_rx rx; 303 struct sparx5_tx tx; 304 /* PTP */ 305 bool ptp; 306 struct sparx5_phc phc[SPARX5_PHC_COUNT]; 307 spinlock_t ptp_clock_lock; /* lock for phc */ 308 spinlock_t ptp_ts_id_lock; /* lock for ts_id */ 309 struct mutex ptp_lock; /* lock for ptp interface state */ 310 u16 ptp_skbs; 311 int ptp_irq; 312 /* VCAP */ 313 struct vcap_control *vcap_ctrl; 314 /* PGID allocation map */ 315 u8 pgid_map[PGID_TABLE_SIZE]; 316 struct list_head mall_entries; 317 /* Common root for debugfs */ 318 struct dentry *debugfs_root; 319}; 320 321/* sparx5_switchdev.c */ 322int sparx5_register_notifier_blocks(struct sparx5 *sparx5); 323void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5); 324 325/* sparx5_packet.c */ 326struct frame_info { 327 int src_port; 328 u32 timestamp; 329}; 330 331void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp); 332void sparx5_ifh_parse(u32 *ifh, struct frame_info *info); 333irqreturn_t sparx5_xtr_handler(int irq, void *_priv); 334netdev_tx_t sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev); 335int sparx5_manual_injection_mode(struct sparx5 *sparx5); 336void sparx5_port_inj_timer_setup(struct sparx5_port *port); 337 338/* sparx5_fdma.c */ 339int sparx5_fdma_start(struct sparx5 *sparx5); 340int sparx5_fdma_stop(struct sparx5 *sparx5); 341int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb); 342irqreturn_t sparx5_fdma_handler(int irq, void *args); 343 344/* sparx5_mactable.c */ 345void sparx5_mact_pull_work(struct work_struct *work); 346int sparx5_mact_learn(struct sparx5 *sparx5, int port, 347 const unsigned char mac[ETH_ALEN], u16 vid); 348bool sparx5_mact_getnext(struct sparx5 *sparx5, 349 unsigned char mac[ETH_ALEN], u16 *vid, u32 *pcfg2); 350int sparx5_mact_find(struct sparx5 *sparx5, 351 const unsigned char mac[ETH_ALEN], u16 vid, u32 *pcfg2); 352int sparx5_mact_forget(struct sparx5 *sparx5, 353 const unsigned char mac[ETH_ALEN], u16 vid); 354int sparx5_add_mact_entry(struct sparx5 *sparx5, 355 struct net_device *dev, 356 u16 portno, 357 const unsigned char *addr, u16 vid); 358int sparx5_del_mact_entry(struct sparx5 *sparx5, 359 const unsigned char *addr, 360 u16 vid); 361int sparx5_mc_sync(struct net_device *dev, const unsigned char *addr); 362int sparx5_mc_unsync(struct net_device *dev, const unsigned char *addr); 363void sparx5_set_ageing(struct sparx5 *sparx5, int msecs); 364void sparx5_mact_init(struct sparx5 *sparx5); 365 366/* sparx5_vlan.c */ 367void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable); 368void sparx5_pgid_clear(struct sparx5 *spx5, int pgid); 369void sparx5_pgid_read_mask(struct sparx5 *sparx5, int pgid, u32 portmask[3]); 370void sparx5_update_fwd(struct sparx5 *sparx5); 371void sparx5_vlan_init(struct sparx5 *sparx5); 372void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno); 373int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid, 374 bool untagged); 375int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid); 376void sparx5_vlan_port_apply(struct sparx5 *sparx5, struct sparx5_port *port); 377 378/* sparx5_calendar.c */ 379int sparx5_config_auto_calendar(struct sparx5 *sparx5); 380int sparx5_config_dsm_calendar(struct sparx5 *sparx5); 381 382/* sparx5_ethtool.c */ 383void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats); 384int sparx_stats_init(struct sparx5 *sparx5); 385 386/* sparx5_dcb.c */ 387#ifdef CONFIG_SPARX5_DCB 388int sparx5_dcb_init(struct sparx5 *sparx5); 389#else 390static inline int sparx5_dcb_init(struct sparx5 *sparx5) 391{ 392 return 0; 393} 394#endif 395 396/* sparx5_netdev.c */ 397void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp); 398void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op); 399void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type); 400void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset); 401void sparx5_set_port_ifh(void *ifh_hdr, u16 portno); 402bool sparx5_netdevice_check(const struct net_device *dev); 403struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno); 404int sparx5_register_netdevs(struct sparx5 *sparx5); 405void sparx5_destroy_netdevs(struct sparx5 *sparx5); 406void sparx5_unregister_netdevs(struct sparx5 *sparx5); 407 408/* sparx5_ptp.c */ 409int sparx5_ptp_init(struct sparx5 *sparx5); 410void sparx5_ptp_deinit(struct sparx5 *sparx5); 411int sparx5_ptp_hwtstamp_set(struct sparx5_port *port, 412 struct kernel_hwtstamp_config *cfg, 413 struct netlink_ext_ack *extack); 414void sparx5_ptp_hwtstamp_get(struct sparx5_port *port, 415 struct kernel_hwtstamp_config *cfg); 416void sparx5_ptp_rxtstamp(struct sparx5 *sparx5, struct sk_buff *skb, 417 u64 timestamp); 418int sparx5_ptp_txtstamp_request(struct sparx5_port *port, 419 struct sk_buff *skb); 420void sparx5_ptp_txtstamp_release(struct sparx5_port *port, 421 struct sk_buff *skb); 422irqreturn_t sparx5_ptp_irq_handler(int irq, void *args); 423int sparx5_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts); 424 425/* sparx5_vcap_impl.c */ 426int sparx5_vcap_init(struct sparx5 *sparx5); 427void sparx5_vcap_destroy(struct sparx5 *sparx5); 428 429/* sparx5_pgid.c */ 430enum sparx5_pgid_type { 431 SPX5_PGID_FREE, 432 SPX5_PGID_RESERVED, 433 SPX5_PGID_MULTICAST, 434}; 435 436void sparx5_pgid_init(struct sparx5 *spx5); 437int sparx5_pgid_alloc_mcast(struct sparx5 *spx5, u16 *idx); 438int sparx5_pgid_free(struct sparx5 *spx5, u16 idx); 439 440/* sparx5_pool.c */ 441struct sparx5_pool_entry { 442 u16 ref_cnt; 443 u32 idx; /* tc index */ 444}; 445 446u32 sparx5_pool_idx_to_id(u32 idx); 447int sparx5_pool_put(struct sparx5_pool_entry *pool, int size, u32 id); 448int sparx5_pool_get(struct sparx5_pool_entry *pool, int size, u32 *id); 449int sparx5_pool_get_with_idx(struct sparx5_pool_entry *pool, int size, u32 idx, 450 u32 *id); 451 452/* sparx5_sdlb.c */ 453#define SPX5_SDLB_PUP_TOKEN_DISABLE 0x1FFF 454#define SPX5_SDLB_PUP_TOKEN_MAX (SPX5_SDLB_PUP_TOKEN_DISABLE - 1) 455#define SPX5_SDLB_GROUP_RATE_MAX 25000000000ULL 456#define SPX5_SDLB_2CYCLES_TYPE2_THRES_OFFSET 13 457#define SPX5_SDLB_CNT 4096 458#define SPX5_SDLB_GROUP_CNT 10 459#define SPX5_CLK_PER_100PS_DEFAULT 16 460 461struct sparx5_sdlb_group { 462 u64 max_rate; 463 u32 min_burst; 464 u32 frame_size; 465 u32 pup_interval; 466 u32 nsets; 467}; 468 469extern struct sparx5_sdlb_group sdlb_groups[SPX5_SDLB_GROUP_CNT]; 470int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, 471 u64 rate); 472 473int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5); 474int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst); 475int sparx5_sdlb_group_get_by_index(struct sparx5 *sparx5, u32 idx, u32 *group); 476 477int sparx5_sdlb_group_add(struct sparx5 *sparx5, u32 group, u32 idx); 478int sparx5_sdlb_group_del(struct sparx5 *sparx5, u32 group, u32 idx); 479 480void sparx5_sdlb_group_init(struct sparx5 *sparx5, u64 max_rate, u32 min_burst, 481 u32 frame_size, u32 idx); 482 483/* sparx5_police.c */ 484enum { 485 /* More policer types will be added later */ 486 SPX5_POL_SERVICE 487}; 488 489struct sparx5_policer { 490 u32 type; 491 u32 idx; 492 u64 rate; 493 u32 burst; 494 u32 group; 495 u8 event_mask; 496}; 497 498int sparx5_policer_conf_set(struct sparx5 *sparx5, struct sparx5_policer *pol); 499 500/* sparx5_psfp.c */ 501#define SPX5_PSFP_GCE_CNT 4 502#define SPX5_PSFP_SG_CNT 1024 503#define SPX5_PSFP_SG_MIN_CYCLE_TIME_NS (1 * NSEC_PER_USEC) 504#define SPX5_PSFP_SG_MAX_CYCLE_TIME_NS ((1 * NSEC_PER_SEC) - 1) 505#define SPX5_PSFP_SG_MAX_IPV (SPX5_PRIOS - 1) 506#define SPX5_PSFP_SG_OPEN (SPX5_PSFP_SG_CNT - 1) 507#define SPX5_PSFP_SG_CYCLE_TIME_DEFAULT 1000000 508#define SPX5_PSFP_SF_MAX_SDU 16383 509 510struct sparx5_psfp_fm { 511 struct sparx5_policer pol; 512}; 513 514struct sparx5_psfp_gce { 515 bool gate_state; /* StreamGateState */ 516 u32 interval; /* TimeInterval */ 517 u32 ipv; /* InternalPriorityValue */ 518 u32 maxoctets; /* IntervalOctetMax */ 519}; 520 521struct sparx5_psfp_sg { 522 bool gate_state; /* PSFPAdminGateStates */ 523 bool gate_enabled; /* PSFPGateEnabled */ 524 u32 ipv; /* PSFPAdminIPV */ 525 struct timespec64 basetime; /* PSFPAdminBaseTime */ 526 u32 cycletime; /* PSFPAdminCycleTime */ 527 u32 cycletimeext; /* PSFPAdminCycleTimeExtension */ 528 u32 num_entries; /* PSFPAdminControlListLength */ 529 struct sparx5_psfp_gce gce[SPX5_PSFP_GCE_CNT]; 530}; 531 532struct sparx5_psfp_sf { 533 bool sblock_osize_ena; 534 bool sblock_osize; 535 u32 max_sdu; 536 u32 sgid; /* Gate id */ 537 u32 fmid; /* Flow meter id */ 538}; 539 540int sparx5_psfp_fm_add(struct sparx5 *sparx5, u32 uidx, 541 struct sparx5_psfp_fm *fm, u32 *id); 542int sparx5_psfp_fm_del(struct sparx5 *sparx5, u32 id); 543 544int sparx5_psfp_sg_add(struct sparx5 *sparx5, u32 uidx, 545 struct sparx5_psfp_sg *sg, u32 *id); 546int sparx5_psfp_sg_del(struct sparx5 *sparx5, u32 id); 547 548int sparx5_psfp_sf_add(struct sparx5 *sparx5, const struct sparx5_psfp_sf *sf, 549 u32 *id); 550int sparx5_psfp_sf_del(struct sparx5 *sparx5, u32 id); 551 552u32 sparx5_psfp_isdx_get_sf(struct sparx5 *sparx5, u32 isdx); 553u32 sparx5_psfp_isdx_get_fm(struct sparx5 *sparx5, u32 isdx); 554u32 sparx5_psfp_sf_get_sg(struct sparx5 *sparx5, u32 sfid); 555void sparx5_isdx_conf_set(struct sparx5 *sparx5, u32 isdx, u32 sfid, u32 fmid); 556 557void sparx5_psfp_init(struct sparx5 *sparx5); 558 559/* sparx5_qos.c */ 560void sparx5_new_base_time(struct sparx5 *sparx5, const u32 cycle_time, 561 const ktime_t org_base_time, ktime_t *new_base_time); 562 563/* sparx5_mirror.c */ 564int sparx5_mirror_add(struct sparx5_mall_entry *entry); 565void sparx5_mirror_del(struct sparx5_mall_entry *entry); 566void sparx5_mirror_stats(struct sparx5_mall_entry *entry, 567 struct flow_stats *fstats); 568 569/* Clock period in picoseconds */ 570static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock) 571{ 572 switch (cclock) { 573 case SPX5_CORE_CLOCK_250MHZ: 574 return 4000; 575 case SPX5_CORE_CLOCK_500MHZ: 576 return 2000; 577 case SPX5_CORE_CLOCK_625MHZ: 578 default: 579 return 1600; 580 } 581} 582 583static inline bool sparx5_is_baser(phy_interface_t interface) 584{ 585 return interface == PHY_INTERFACE_MODE_5GBASER || 586 interface == PHY_INTERFACE_MODE_10GBASER || 587 interface == PHY_INTERFACE_MODE_25GBASER; 588} 589 590extern const struct phylink_mac_ops sparx5_phylink_mac_ops; 591extern const struct phylink_pcs_ops sparx5_phylink_pcs_ops; 592extern const struct ethtool_ops sparx5_ethtool_ops; 593extern const struct dcbnl_rtnl_ops sparx5_dcbnl_ops; 594 595/* Calculate raw offset */ 596static inline __pure int spx5_offset(int id, int tinst, int tcnt, 597 int gbase, int ginst, 598 int gcnt, int gwidth, 599 int raddr, int rinst, 600 int rcnt, int rwidth) 601{ 602 WARN_ON((tinst) >= tcnt); 603 WARN_ON((ginst) >= gcnt); 604 WARN_ON((rinst) >= rcnt); 605 return gbase + ((ginst) * gwidth) + 606 raddr + ((rinst) * rwidth); 607} 608 609/* Read, Write and modify registers content. 610 * The register definition macros start at the id 611 */ 612static inline void __iomem *spx5_addr(void __iomem *base[], 613 int id, int tinst, int tcnt, 614 int gbase, int ginst, 615 int gcnt, int gwidth, 616 int raddr, int rinst, 617 int rcnt, int rwidth) 618{ 619 WARN_ON((tinst) >= tcnt); 620 WARN_ON((ginst) >= gcnt); 621 WARN_ON((rinst) >= rcnt); 622 return base[id + (tinst)] + 623 gbase + ((ginst) * gwidth) + 624 raddr + ((rinst) * rwidth); 625} 626 627static inline void __iomem *spx5_inst_addr(void __iomem *base, 628 int gbase, int ginst, 629 int gcnt, int gwidth, 630 int raddr, int rinst, 631 int rcnt, int rwidth) 632{ 633 WARN_ON((ginst) >= gcnt); 634 WARN_ON((rinst) >= rcnt); 635 return base + 636 gbase + ((ginst) * gwidth) + 637 raddr + ((rinst) * rwidth); 638} 639 640static inline u32 spx5_rd(struct sparx5 *sparx5, int id, int tinst, int tcnt, 641 int gbase, int ginst, int gcnt, int gwidth, 642 int raddr, int rinst, int rcnt, int rwidth) 643{ 644 return readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 645 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 646} 647 648static inline u32 spx5_inst_rd(void __iomem *iomem, int id, int tinst, int tcnt, 649 int gbase, int ginst, int gcnt, int gwidth, 650 int raddr, int rinst, int rcnt, int rwidth) 651{ 652 return readl(spx5_inst_addr(iomem, gbase, ginst, 653 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 654} 655 656static inline void spx5_wr(u32 val, struct sparx5 *sparx5, 657 int id, int tinst, int tcnt, 658 int gbase, int ginst, int gcnt, int gwidth, 659 int raddr, int rinst, int rcnt, int rwidth) 660{ 661 writel(val, spx5_addr(sparx5->regs, id, tinst, tcnt, 662 gbase, ginst, gcnt, gwidth, 663 raddr, rinst, rcnt, rwidth)); 664} 665 666static inline void spx5_inst_wr(u32 val, void __iomem *iomem, 667 int id, int tinst, int tcnt, 668 int gbase, int ginst, int gcnt, int gwidth, 669 int raddr, int rinst, int rcnt, int rwidth) 670{ 671 writel(val, spx5_inst_addr(iomem, 672 gbase, ginst, gcnt, gwidth, 673 raddr, rinst, rcnt, rwidth)); 674} 675 676static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5, 677 int id, int tinst, int tcnt, 678 int gbase, int ginst, int gcnt, int gwidth, 679 int raddr, int rinst, int rcnt, int rwidth) 680{ 681 u32 nval; 682 683 nval = readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 684 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 685 nval = (nval & ~mask) | (val & mask); 686 writel(nval, spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 687 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 688} 689 690static inline void spx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem, 691 int id, int tinst, int tcnt, 692 int gbase, int ginst, int gcnt, int gwidth, 693 int raddr, int rinst, int rcnt, int rwidth) 694{ 695 u32 nval; 696 697 nval = readl(spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr, 698 rinst, rcnt, rwidth)); 699 nval = (nval & ~mask) | (val & mask); 700 writel(nval, spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr, 701 rinst, rcnt, rwidth)); 702} 703 704static inline void __iomem *spx5_inst_get(struct sparx5 *sparx5, int id, int tinst) 705{ 706 return sparx5->regs[id + tinst]; 707} 708 709static inline void __iomem *spx5_reg_get(struct sparx5 *sparx5, 710 int id, int tinst, int tcnt, 711 int gbase, int ginst, int gcnt, int gwidth, 712 int raddr, int rinst, int rcnt, int rwidth) 713{ 714 return spx5_addr(sparx5->regs, id, tinst, tcnt, 715 gbase, ginst, gcnt, gwidth, 716 raddr, rinst, rcnt, rwidth); 717} 718 719#endif /* __SPARX5_MAIN_H__ */ 720