1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#define SWSMU_CODE_LAYER_L2 25 26#include "amdgpu.h" 27#include "amdgpu_smu.h" 28#include "smu_v13_0.h" 29#include "smu13_driver_if_v13_0_5.h" 30#include "smu_v13_0_5_ppt.h" 31#include "smu_v13_0_5_ppsmc.h" 32#include "smu_v13_0_5_pmfw.h" 33#include "smu_cmn.h" 34 35/* 36 * DO NOT use these for err/warn/info/debug messages. 37 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 38 * They are more MGPU friendly. 39 */ 40#undef pr_err 41#undef pr_warn 42#undef pr_info 43#undef pr_debug 44 45#define mmMP1_C2PMSG_2 (0xbee142 + 0xb00000 / 4) 46#define mmMP1_C2PMSG_2_BASE_IDX 0 47 48#define mmMP1_C2PMSG_34 (0xbee262 + 0xb00000 / 4) 49#define mmMP1_C2PMSG_34_BASE_IDX 0 50 51#define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4) 52#define mmMP1_C2PMSG_33_BASE_IDX 0 53 54#define FEATURE_MASK(feature) (1ULL << feature) 55#define SMC_DPM_FEATURE ( \ 56 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 57 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 58 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 59 FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \ 60 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 61 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \ 62 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)| \ 63 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)| \ 64 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)) 65 66static struct cmn2asic_msg_mapping smu_v13_0_5_message_map[SMU_MSG_MAX_COUNT] = { 67 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 68 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 69 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), 70 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), 71 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1), 72 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 1), 73 MSG_MAP(Spare0, PPSMC_MSG_Spare0, 1), 74 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1), 75 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 76 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 77 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 78 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1), 79 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1), 80 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1), 81 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1), 82 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), 83 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), 84 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), 85 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1), 86 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1), 87 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1), 88 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1), 89 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 90 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 91}; 92 93static struct cmn2asic_mapping smu_v13_0_5_feature_mask_map[SMU_FEATURE_COUNT] = { 94 FEA_MAP(DATA_CALCULATION), 95 FEA_MAP(PPT), 96 FEA_MAP(TDC), 97 FEA_MAP(THERMAL), 98 FEA_MAP(PROCHOT), 99 FEA_MAP(CCLK_DPM), 100 FEA_MAP_REVERSE(FCLK), 101 FEA_MAP(LCLK_DPM), 102 FEA_MAP(DF_CSTATES), 103 FEA_MAP(FAN_CONTROLLER), 104 FEA_MAP(CPPC), 105 FEA_MAP_HALF_REVERSE(GFX), 106 FEA_MAP(DS_GFXCLK), 107 FEA_MAP(S0I3), 108 FEA_MAP(VCN_DPM), 109 FEA_MAP(DS_VCN), 110 FEA_MAP(DCFCLK_DPM), 111 FEA_MAP(ATHUB_PG), 112 FEA_MAP_REVERSE(SOCCLK), 113 FEA_MAP(SHUBCLK_DPM), 114 FEA_MAP(GFXOFF), 115}; 116 117static struct cmn2asic_mapping smu_v13_0_5_table_map[SMU_TABLE_COUNT] = { 118 TAB_MAP_VALID(WATERMARKS), 119 TAB_MAP_VALID(SMU_METRICS), 120 TAB_MAP_VALID(CUSTOM_DPM), 121 TAB_MAP_VALID(DPMCLOCKS), 122}; 123 124static int smu_v13_0_5_init_smc_tables(struct smu_context *smu) 125{ 126 struct smu_table_context *smu_table = &smu->smu_table; 127 struct smu_table *tables = smu_table->tables; 128 129 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 130 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 131 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 132 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 133 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 134 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 135 136 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 137 if (!smu_table->clocks_table) 138 goto err0_out; 139 140 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 141 if (!smu_table->metrics_table) 142 goto err1_out; 143 smu_table->metrics_time = 0; 144 145 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 146 if (!smu_table->watermarks_table) 147 goto err2_out; 148 149 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1); 150 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 151 if (!smu_table->gpu_metrics_table) 152 goto err3_out; 153 154 return 0; 155 156err3_out: 157 kfree(smu_table->watermarks_table); 158err2_out: 159 kfree(smu_table->metrics_table); 160err1_out: 161 kfree(smu_table->clocks_table); 162err0_out: 163 return -ENOMEM; 164} 165 166static int smu_v13_0_5_fini_smc_tables(struct smu_context *smu) 167{ 168 struct smu_table_context *smu_table = &smu->smu_table; 169 170 kfree(smu_table->clocks_table); 171 smu_table->clocks_table = NULL; 172 173 kfree(smu_table->metrics_table); 174 smu_table->metrics_table = NULL; 175 176 kfree(smu_table->watermarks_table); 177 smu_table->watermarks_table = NULL; 178 179 kfree(smu_table->gpu_metrics_table); 180 smu_table->gpu_metrics_table = NULL; 181 182 return 0; 183} 184 185static int smu_v13_0_5_system_features_control(struct smu_context *smu, bool en) 186{ 187 struct amdgpu_device *adev = smu->adev; 188 int ret = 0; 189 190 if (!en && !adev->in_s0ix) 191 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL); 192 193 return ret; 194} 195 196static int smu_v13_0_5_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 197{ 198 int ret = 0; 199 200 /* vcn dpm on is a prerequisite for vcn power gate messages */ 201 if (enable) 202 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 203 0, NULL); 204 else 205 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 206 0, NULL); 207 208 return ret; 209} 210 211static int smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 212{ 213 int ret = 0; 214 215 if (enable) 216 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 217 0, NULL); 218 else 219 ret = smu_cmn_send_smc_msg_with_param(smu, 220 SMU_MSG_PowerDownJpeg, 0, 221 NULL); 222 223 return ret; 224} 225 226 227static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu) 228{ 229 int ret = 0; 230 uint64_t feature_enabled; 231 232 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 233 234 if (ret) 235 return false; 236 237 return !!(feature_enabled & SMC_DPM_FEATURE); 238} 239 240static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type) 241{ 242 int ret = 0; 243 244 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, type, NULL); 245 if (ret) 246 dev_err(smu->adev->dev, "Failed to mode reset!\n"); 247 248 return ret; 249} 250 251static int smu_v13_0_5_mode2_reset(struct smu_context *smu) 252{ 253 return smu_v13_0_5_mode_reset(smu, SMU_RESET_MODE_2); 254} 255 256static int smu_v13_0_5_get_smu_metrics_data(struct smu_context *smu, 257 MetricsMember_t member, 258 uint32_t *value) 259{ 260 struct smu_table_context *smu_table = &smu->smu_table; 261 262 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 263 int ret = 0; 264 265 ret = smu_cmn_get_metrics_table(smu, NULL, false); 266 if (ret) 267 return ret; 268 269 switch (member) { 270 case METRICS_AVERAGE_GFXCLK: 271 *value = metrics->GfxclkFrequency; 272 break; 273 case METRICS_AVERAGE_SOCCLK: 274 *value = metrics->SocclkFrequency; 275 break; 276 case METRICS_AVERAGE_VCLK: 277 *value = metrics->VclkFrequency; 278 break; 279 case METRICS_AVERAGE_DCLK: 280 *value = metrics->DclkFrequency; 281 break; 282 case METRICS_AVERAGE_UCLK: 283 *value = metrics->MemclkFrequency; 284 break; 285 case METRICS_AVERAGE_GFXACTIVITY: 286 *value = metrics->GfxActivity / 100; 287 break; 288 case METRICS_AVERAGE_VCNACTIVITY: 289 *value = metrics->UvdActivity / 100; 290 break; 291 case METRICS_CURR_SOCKETPOWER: 292 *value = (metrics->CurrentSocketPower << 8) / 1000; 293 break; 294 case METRICS_TEMPERATURE_EDGE: 295 *value = metrics->GfxTemperature / 100 * 296 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 297 break; 298 case METRICS_TEMPERATURE_HOTSPOT: 299 *value = metrics->SocTemperature / 100 * 300 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 301 break; 302 case METRICS_THROTTLER_STATUS: 303 *value = metrics->ThrottlerStatus; 304 break; 305 case METRICS_VOLTAGE_VDDGFX: 306 *value = metrics->Voltage[0]; 307 break; 308 case METRICS_VOLTAGE_VDDSOC: 309 *value = metrics->Voltage[1]; 310 break; 311 default: 312 *value = UINT_MAX; 313 break; 314 } 315 316 return ret; 317} 318 319static int smu_v13_0_5_read_sensor(struct smu_context *smu, 320 enum amd_pp_sensors sensor, 321 void *data, uint32_t *size) 322{ 323 int ret = 0; 324 325 if (!data || !size) 326 return -EINVAL; 327 328 switch (sensor) { 329 case AMDGPU_PP_SENSOR_GPU_LOAD: 330 ret = smu_v13_0_5_get_smu_metrics_data(smu, 331 METRICS_AVERAGE_GFXACTIVITY, 332 (uint32_t *)data); 333 *size = 4; 334 break; 335 case AMDGPU_PP_SENSOR_VCN_LOAD: 336 ret = smu_v13_0_5_get_smu_metrics_data(smu, 337 METRICS_AVERAGE_VCNACTIVITY, 338 (uint32_t *)data); 339 *size = 4; 340 break; 341 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 342 ret = smu_v13_0_5_get_smu_metrics_data(smu, 343 METRICS_CURR_SOCKETPOWER, 344 (uint32_t *)data); 345 *size = 4; 346 break; 347 case AMDGPU_PP_SENSOR_EDGE_TEMP: 348 ret = smu_v13_0_5_get_smu_metrics_data(smu, 349 METRICS_TEMPERATURE_EDGE, 350 (uint32_t *)data); 351 *size = 4; 352 break; 353 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 354 ret = smu_v13_0_5_get_smu_metrics_data(smu, 355 METRICS_TEMPERATURE_HOTSPOT, 356 (uint32_t *)data); 357 *size = 4; 358 break; 359 case AMDGPU_PP_SENSOR_GFX_MCLK: 360 ret = smu_v13_0_5_get_smu_metrics_data(smu, 361 METRICS_AVERAGE_UCLK, 362 (uint32_t *)data); 363 *(uint32_t *)data *= 100; 364 *size = 4; 365 break; 366 case AMDGPU_PP_SENSOR_GFX_SCLK: 367 ret = smu_v13_0_5_get_smu_metrics_data(smu, 368 METRICS_AVERAGE_GFXCLK, 369 (uint32_t *)data); 370 *(uint32_t *)data *= 100; 371 *size = 4; 372 break; 373 case AMDGPU_PP_SENSOR_VDDGFX: 374 ret = smu_v13_0_5_get_smu_metrics_data(smu, 375 METRICS_VOLTAGE_VDDGFX, 376 (uint32_t *)data); 377 *size = 4; 378 break; 379 case AMDGPU_PP_SENSOR_VDDNB: 380 ret = smu_v13_0_5_get_smu_metrics_data(smu, 381 METRICS_VOLTAGE_VDDSOC, 382 (uint32_t *)data); 383 *size = 4; 384 break; 385 case AMDGPU_PP_SENSOR_SS_APU_SHARE: 386 ret = smu_v13_0_5_get_smu_metrics_data(smu, 387 METRICS_SS_APU_SHARE, 388 (uint32_t *)data); 389 *size = 4; 390 break; 391 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE: 392 ret = smu_v13_0_5_get_smu_metrics_data(smu, 393 METRICS_SS_DGPU_SHARE, 394 (uint32_t *)data); 395 *size = 4; 396 break; 397 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 398 default: 399 ret = -EOPNOTSUPP; 400 break; 401 } 402 403 return ret; 404} 405 406static int smu_v13_0_5_set_watermarks_table(struct smu_context *smu, 407 struct pp_smu_wm_range_sets *clock_ranges) 408{ 409 int i; 410 int ret = 0; 411 Watermarks_t *table = smu->smu_table.watermarks_table; 412 413 if (!table || !clock_ranges) 414 return -EINVAL; 415 416 if (clock_ranges) { 417 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 418 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 419 return -EINVAL; 420 421 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 422 table->WatermarkRow[WM_DCFCLK][i].MinClock = 423 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 424 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 425 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 426 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 427 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 428 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 429 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 430 431 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 432 clock_ranges->reader_wm_sets[i].wm_inst; 433 } 434 435 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 436 table->WatermarkRow[WM_SOCCLK][i].MinClock = 437 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 438 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 439 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 440 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 441 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 442 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 443 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 444 445 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 446 clock_ranges->writer_wm_sets[i].wm_inst; 447 } 448 449 smu->watermarks_bitmap |= WATERMARKS_EXIST; 450 } 451 452 /* pass data to smu controller */ 453 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 454 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 455 ret = smu_cmn_write_watermarks_table(smu); 456 if (ret) { 457 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 458 return ret; 459 } 460 smu->watermarks_bitmap |= WATERMARKS_LOADED; 461 } 462 463 return 0; 464} 465 466static ssize_t smu_v13_0_5_get_gpu_metrics(struct smu_context *smu, 467 void **table) 468{ 469 struct smu_table_context *smu_table = &smu->smu_table; 470 struct gpu_metrics_v2_1 *gpu_metrics = 471 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; 472 SmuMetrics_t metrics; 473 int ret = 0; 474 475 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 476 if (ret) 477 return ret; 478 479 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1); 480 481 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 482 gpu_metrics->temperature_soc = metrics.SocTemperature; 483 484 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 485 gpu_metrics->average_mm_activity = metrics.UvdActivity; 486 487 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 488 gpu_metrics->average_gfx_power = metrics.Power[0]; 489 gpu_metrics->average_soc_power = metrics.Power[1]; 490 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 491 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 492 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 493 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 494 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 495 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 496 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 497 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 498 499 *table = (void *)gpu_metrics; 500 501 return sizeof(struct gpu_metrics_v2_1); 502} 503 504static int smu_v13_0_5_set_default_dpm_tables(struct smu_context *smu) 505{ 506 struct smu_table_context *smu_table = &smu->smu_table; 507 508 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false); 509} 510 511static int smu_v13_0_5_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, 512 long input[], uint32_t size) 513{ 514 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 515 int ret = 0; 516 517 /* Only allowed in manual mode */ 518 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 519 return -EINVAL; 520 521 switch (type) { 522 case PP_OD_EDIT_SCLK_VDDC_TABLE: 523 if (size != 2) { 524 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 525 return -EINVAL; 526 } 527 528 if (input[0] == 0) { 529 if (input[1] < smu->gfx_default_hard_min_freq) { 530 dev_warn(smu->adev->dev, 531 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 532 input[1], smu->gfx_default_hard_min_freq); 533 return -EINVAL; 534 } 535 smu->gfx_actual_hard_min_freq = input[1]; 536 } else if (input[0] == 1) { 537 if (input[1] > smu->gfx_default_soft_max_freq) { 538 dev_warn(smu->adev->dev, 539 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 540 input[1], smu->gfx_default_soft_max_freq); 541 return -EINVAL; 542 } 543 smu->gfx_actual_soft_max_freq = input[1]; 544 } else { 545 return -EINVAL; 546 } 547 break; 548 case PP_OD_RESTORE_DEFAULT_TABLE: 549 if (size != 0) { 550 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 551 return -EINVAL; 552 } else { 553 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 554 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 555 } 556 break; 557 case PP_OD_COMMIT_DPM_TABLE: 558 if (size != 0) { 559 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 560 return -EINVAL; 561 } else { 562 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 563 dev_err(smu->adev->dev, 564 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 565 smu->gfx_actual_hard_min_freq, 566 smu->gfx_actual_soft_max_freq); 567 return -EINVAL; 568 } 569 570 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 571 smu->gfx_actual_hard_min_freq, NULL); 572 if (ret) { 573 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 574 return ret; 575 } 576 577 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 578 smu->gfx_actual_soft_max_freq, NULL); 579 if (ret) { 580 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 581 return ret; 582 } 583 } 584 break; 585 default: 586 return -ENOSYS; 587 } 588 589 return ret; 590} 591 592static int smu_v13_0_5_get_current_clk_freq(struct smu_context *smu, 593 enum smu_clk_type clk_type, 594 uint32_t *value) 595{ 596 MetricsMember_t member_type; 597 598 switch (clk_type) { 599 case SMU_SOCCLK: 600 member_type = METRICS_AVERAGE_SOCCLK; 601 break; 602 case SMU_VCLK: 603 member_type = METRICS_AVERAGE_VCLK; 604 break; 605 case SMU_DCLK: 606 member_type = METRICS_AVERAGE_DCLK; 607 break; 608 case SMU_MCLK: 609 member_type = METRICS_AVERAGE_UCLK; 610 break; 611 case SMU_GFXCLK: 612 case SMU_SCLK: 613 return smu_cmn_send_smc_msg_with_param(smu, 614 SMU_MSG_GetGfxclkFrequency, 0, value); 615 break; 616 default: 617 return -EINVAL; 618 } 619 620 return smu_v13_0_5_get_smu_metrics_data(smu, member_type, value); 621} 622 623static int smu_v13_0_5_get_dpm_level_count(struct smu_context *smu, 624 enum smu_clk_type clk_type, 625 uint32_t *count) 626{ 627 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 628 629 switch (clk_type) { 630 case SMU_SOCCLK: 631 *count = clk_table->NumSocClkLevelsEnabled; 632 break; 633 case SMU_VCLK: 634 *count = clk_table->VcnClkLevelsEnabled; 635 break; 636 case SMU_DCLK: 637 *count = clk_table->VcnClkLevelsEnabled; 638 break; 639 case SMU_MCLK: 640 *count = clk_table->NumDfPstatesEnabled; 641 break; 642 case SMU_FCLK: 643 *count = clk_table->NumDfPstatesEnabled; 644 break; 645 default: 646 break; 647 } 648 649 return 0; 650} 651 652static int smu_v13_0_5_get_dpm_freq_by_index(struct smu_context *smu, 653 enum smu_clk_type clk_type, 654 uint32_t dpm_level, 655 uint32_t *freq) 656{ 657 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 658 659 if (!clk_table || clk_type >= SMU_CLK_COUNT) 660 return -EINVAL; 661 662 switch (clk_type) { 663 case SMU_SOCCLK: 664 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 665 return -EINVAL; 666 *freq = clk_table->SocClocks[dpm_level]; 667 break; 668 case SMU_VCLK: 669 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 670 return -EINVAL; 671 *freq = clk_table->VClocks[dpm_level]; 672 break; 673 case SMU_DCLK: 674 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 675 return -EINVAL; 676 *freq = clk_table->DClocks[dpm_level]; 677 break; 678 case SMU_UCLK: 679 case SMU_MCLK: 680 if (dpm_level >= clk_table->NumDfPstatesEnabled) 681 return -EINVAL; 682 *freq = clk_table->DfPstateTable[dpm_level].MemClk; 683 break; 684 case SMU_FCLK: 685 if (dpm_level >= clk_table->NumDfPstatesEnabled) 686 return -EINVAL; 687 *freq = clk_table->DfPstateTable[dpm_level].FClk; 688 break; 689 default: 690 return -EINVAL; 691 } 692 693 return 0; 694} 695 696static bool smu_v13_0_5_clk_dpm_is_enabled(struct smu_context *smu, 697 enum smu_clk_type clk_type) 698{ 699 enum smu_feature_mask feature_id = 0; 700 701 switch (clk_type) { 702 case SMU_MCLK: 703 case SMU_UCLK: 704 case SMU_FCLK: 705 feature_id = SMU_FEATURE_DPM_FCLK_BIT; 706 break; 707 case SMU_GFXCLK: 708 case SMU_SCLK: 709 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 710 break; 711 case SMU_SOCCLK: 712 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 713 break; 714 case SMU_VCLK: 715 case SMU_DCLK: 716 feature_id = SMU_FEATURE_VCN_DPM_BIT; 717 break; 718 default: 719 return true; 720 } 721 722 return smu_cmn_feature_is_enabled(smu, feature_id); 723} 724 725static int smu_v13_0_5_get_dpm_ultimate_freq(struct smu_context *smu, 726 enum smu_clk_type clk_type, 727 uint32_t *min, 728 uint32_t *max) 729{ 730 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 731 uint32_t clock_limit; 732 uint32_t max_dpm_level, min_dpm_level; 733 int ret = 0; 734 735 if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type)) { 736 switch (clk_type) { 737 case SMU_MCLK: 738 case SMU_UCLK: 739 clock_limit = smu->smu_table.boot_values.uclk; 740 break; 741 case SMU_FCLK: 742 clock_limit = smu->smu_table.boot_values.fclk; 743 break; 744 case SMU_GFXCLK: 745 case SMU_SCLK: 746 clock_limit = smu->smu_table.boot_values.gfxclk; 747 break; 748 case SMU_SOCCLK: 749 clock_limit = smu->smu_table.boot_values.socclk; 750 break; 751 case SMU_VCLK: 752 clock_limit = smu->smu_table.boot_values.vclk; 753 break; 754 case SMU_DCLK: 755 clock_limit = smu->smu_table.boot_values.dclk; 756 break; 757 default: 758 clock_limit = 0; 759 break; 760 } 761 762 /* clock in Mhz unit */ 763 if (min) 764 *min = clock_limit / 100; 765 if (max) 766 *max = clock_limit / 100; 767 768 return 0; 769 } 770 771 if (max) { 772 switch (clk_type) { 773 case SMU_GFXCLK: 774 case SMU_SCLK: 775 *max = clk_table->MaxGfxClk; 776 break; 777 case SMU_MCLK: 778 case SMU_UCLK: 779 case SMU_FCLK: 780 max_dpm_level = 0; 781 break; 782 case SMU_SOCCLK: 783 max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1; 784 break; 785 case SMU_VCLK: 786 case SMU_DCLK: 787 max_dpm_level = clk_table->VcnClkLevelsEnabled - 1; 788 break; 789 default: 790 ret = -EINVAL; 791 goto failed; 792 } 793 794 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { 795 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max); 796 if (ret) 797 goto failed; 798 } 799 } 800 801 if (min) { 802 switch (clk_type) { 803 case SMU_GFXCLK: 804 case SMU_SCLK: 805 *min = clk_table->MinGfxClk; 806 break; 807 case SMU_MCLK: 808 case SMU_UCLK: 809 case SMU_FCLK: 810 min_dpm_level = clk_table->NumDfPstatesEnabled - 1; 811 break; 812 case SMU_SOCCLK: 813 min_dpm_level = 0; 814 break; 815 case SMU_VCLK: 816 case SMU_DCLK: 817 min_dpm_level = 0; 818 break; 819 default: 820 ret = -EINVAL; 821 goto failed; 822 } 823 824 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { 825 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min); 826 if (ret) 827 goto failed; 828 } 829 } 830 831failed: 832 return ret; 833} 834 835static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu, 836 enum smu_clk_type clk_type, 837 uint32_t min, 838 uint32_t max) 839{ 840 enum smu_message_type msg_set_min, msg_set_max; 841 uint32_t min_clk = min; 842 uint32_t max_clk = max; 843 int ret = 0; 844 845 if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type)) 846 return -EINVAL; 847 848 switch (clk_type) { 849 case SMU_GFXCLK: 850 case SMU_SCLK: 851 msg_set_min = SMU_MSG_SetHardMinGfxClk; 852 msg_set_max = SMU_MSG_SetSoftMaxGfxClk; 853 break; 854 case SMU_VCLK: 855 case SMU_DCLK: 856 msg_set_min = SMU_MSG_SetHardMinVcn; 857 msg_set_max = SMU_MSG_SetSoftMaxVcn; 858 break; 859 default: 860 return -EINVAL; 861 } 862 863 if (clk_type == SMU_VCLK) { 864 min_clk = min << SMU_13_VCLK_SHIFT; 865 max_clk = max << SMU_13_VCLK_SHIFT; 866 } 867 868 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL); 869 if (ret) 870 goto out; 871 872 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL); 873 if (ret) 874 goto out; 875 876out: 877 return ret; 878} 879 880static int smu_v13_0_5_print_clk_levels(struct smu_context *smu, 881 enum smu_clk_type clk_type, char *buf) 882{ 883 int i, idx, size = 0, ret = 0; 884 uint32_t cur_value = 0, value = 0, count = 0; 885 uint32_t min = 0, max = 0; 886 887 smu_cmn_get_sysfs_buf(&buf, &size); 888 889 switch (clk_type) { 890 case SMU_OD_SCLK: 891 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 892 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 893 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 894 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 895 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 896 break; 897 case SMU_OD_RANGE: 898 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 899 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 900 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq); 901 break; 902 case SMU_SOCCLK: 903 case SMU_VCLK: 904 case SMU_DCLK: 905 case SMU_MCLK: 906 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value); 907 if (ret) 908 goto print_clk_out; 909 910 ret = smu_v13_0_5_get_dpm_level_count(smu, clk_type, &count); 911 if (ret) 912 goto print_clk_out; 913 914 for (i = 0; i < count; i++) { 915 idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i; 916 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, idx, &value); 917 if (ret) 918 goto print_clk_out; 919 920 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 921 cur_value == value ? "*" : ""); 922 } 923 break; 924 case SMU_GFXCLK: 925 case SMU_SCLK: 926 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value); 927 if (ret) 928 goto print_clk_out; 929 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; 930 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; 931 if (cur_value == max) 932 i = 2; 933 else if (cur_value == min) 934 i = 0; 935 else 936 i = 1; 937 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min, 938 i == 0 ? "*" : ""); 939 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 940 i == 1 ? cur_value : SMU_13_0_5_UMD_PSTATE_GFXCLK, 941 i == 1 ? "*" : ""); 942 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, 943 i == 2 ? "*" : ""); 944 break; 945 default: 946 break; 947 } 948 949print_clk_out: 950 return size; 951} 952 953 954static int smu_v13_0_5_force_clk_levels(struct smu_context *smu, 955 enum smu_clk_type clk_type, uint32_t mask) 956{ 957 uint32_t soft_min_level = 0, soft_max_level = 0; 958 uint32_t min_freq = 0, max_freq = 0; 959 int ret = 0; 960 961 soft_min_level = mask ? (ffs(mask) - 1) : 0; 962 soft_max_level = mask ? (fls(mask) - 1) : 0; 963 964 switch (clk_type) { 965 case SMU_VCLK: 966 case SMU_DCLK: 967 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 968 if (ret) 969 goto force_level_out; 970 971 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 972 if (ret) 973 goto force_level_out; 974 975 ret = smu_v13_0_5_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 976 if (ret) 977 goto force_level_out; 978 break; 979 default: 980 ret = -EINVAL; 981 break; 982 } 983 984force_level_out: 985 return ret; 986} 987 988static int smu_v13_0_5_get_dpm_profile_freq(struct smu_context *smu, 989 enum amd_dpm_forced_level level, 990 enum smu_clk_type clk_type, 991 uint32_t *min_clk, 992 uint32_t *max_clk) 993{ 994 int ret = 0; 995 uint32_t clk_limit = 0; 996 997 switch (clk_type) { 998 case SMU_GFXCLK: 999 case SMU_SCLK: 1000 clk_limit = SMU_13_0_5_UMD_PSTATE_GFXCLK; 1001 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 1002 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit); 1003 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) 1004 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL); 1005 break; 1006 case SMU_VCLK: 1007 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit); 1008 break; 1009 case SMU_DCLK: 1010 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit); 1011 break; 1012 default: 1013 ret = -EINVAL; 1014 break; 1015 } 1016 *min_clk = *max_clk = clk_limit; 1017 return ret; 1018} 1019 1020static int smu_v13_0_5_set_performance_level(struct smu_context *smu, 1021 enum amd_dpm_forced_level level) 1022{ 1023 struct amdgpu_device *adev = smu->adev; 1024 uint32_t sclk_min = 0, sclk_max = 0; 1025 uint32_t vclk_min = 0, vclk_max = 0; 1026 uint32_t dclk_min = 0, dclk_max = 0; 1027 int ret = 0; 1028 1029 switch (level) { 1030 case AMD_DPM_FORCED_LEVEL_HIGH: 1031 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max); 1032 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max); 1033 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max); 1034 sclk_min = sclk_max; 1035 vclk_min = vclk_max; 1036 dclk_min = dclk_max; 1037 break; 1038 case AMD_DPM_FORCED_LEVEL_LOW: 1039 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL); 1040 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL); 1041 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL); 1042 sclk_max = sclk_min; 1043 vclk_max = vclk_min; 1044 dclk_max = dclk_min; 1045 break; 1046 case AMD_DPM_FORCED_LEVEL_AUTO: 1047 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max); 1048 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max); 1049 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max); 1050 break; 1051 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1052 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1053 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1054 smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max); 1055 smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max); 1056 smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max); 1057 break; 1058 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1059 dev_err(adev->dev, "The performance level profile_min_mclk is not supported."); 1060 return -EOPNOTSUPP; 1061 case AMD_DPM_FORCED_LEVEL_MANUAL: 1062 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1063 return 0; 1064 default: 1065 dev_err(adev->dev, "Invalid performance level %d\n", level); 1066 return -EINVAL; 1067 } 1068 1069 if (sclk_min && sclk_max) { 1070 ret = smu_v13_0_5_set_soft_freq_limited_range(smu, 1071 SMU_SCLK, 1072 sclk_min, 1073 sclk_max); 1074 if (ret) 1075 return ret; 1076 1077 smu->gfx_actual_hard_min_freq = sclk_min; 1078 smu->gfx_actual_soft_max_freq = sclk_max; 1079 } 1080 1081 if (vclk_min && vclk_max) { 1082 ret = smu_v13_0_5_set_soft_freq_limited_range(smu, 1083 SMU_VCLK, 1084 vclk_min, 1085 vclk_max); 1086 if (ret) 1087 return ret; 1088 } 1089 1090 if (dclk_min && dclk_max) { 1091 ret = smu_v13_0_5_set_soft_freq_limited_range(smu, 1092 SMU_DCLK, 1093 dclk_min, 1094 dclk_max); 1095 if (ret) 1096 return ret; 1097 } 1098 return ret; 1099} 1100 1101static int smu_v13_0_5_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 1102{ 1103 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 1104 1105 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 1106 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 1107 smu->gfx_actual_hard_min_freq = 0; 1108 smu->gfx_actual_soft_max_freq = 0; 1109 1110 return 0; 1111} 1112 1113static const struct pptable_funcs smu_v13_0_5_ppt_funcs = { 1114 .check_fw_status = smu_v13_0_check_fw_status, 1115 .check_fw_version = smu_v13_0_check_fw_version, 1116 .init_smc_tables = smu_v13_0_5_init_smc_tables, 1117 .fini_smc_tables = smu_v13_0_5_fini_smc_tables, 1118 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1119 .system_features_control = smu_v13_0_5_system_features_control, 1120 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1121 .send_smc_msg = smu_cmn_send_smc_msg, 1122 .dpm_set_vcn_enable = smu_v13_0_5_dpm_set_vcn_enable, 1123 .dpm_set_jpeg_enable = smu_v13_0_5_dpm_set_jpeg_enable, 1124 .set_default_dpm_table = smu_v13_0_5_set_default_dpm_tables, 1125 .read_sensor = smu_v13_0_5_read_sensor, 1126 .is_dpm_running = smu_v13_0_5_is_dpm_running, 1127 .set_watermarks_table = smu_v13_0_5_set_watermarks_table, 1128 .get_gpu_metrics = smu_v13_0_5_get_gpu_metrics, 1129 .get_enabled_mask = smu_cmn_get_enabled_mask, 1130 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1131 .set_driver_table_location = smu_v13_0_set_driver_table_location, 1132 .gfx_off_control = smu_v13_0_gfx_off_control, 1133 .mode2_reset = smu_v13_0_5_mode2_reset, 1134 .get_dpm_ultimate_freq = smu_v13_0_5_get_dpm_ultimate_freq, 1135 .od_edit_dpm_table = smu_v13_0_5_od_edit_dpm_table, 1136 .print_clk_levels = smu_v13_0_5_print_clk_levels, 1137 .force_clk_levels = smu_v13_0_5_force_clk_levels, 1138 .set_performance_level = smu_v13_0_5_set_performance_level, 1139 .set_fine_grain_gfx_freq_parameters = smu_v13_0_5_set_fine_grain_gfx_freq_parameters, 1140}; 1141 1142void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu) 1143{ 1144 struct amdgpu_device *adev = smu->adev; 1145 1146 smu->ppt_funcs = &smu_v13_0_5_ppt_funcs; 1147 smu->message_map = smu_v13_0_5_message_map; 1148 smu->feature_map = smu_v13_0_5_feature_mask_map; 1149 smu->table_map = smu_v13_0_5_table_map; 1150 smu->is_apu = true; 1151 smu->smc_driver_if_version = SMU13_0_5_DRIVER_IF_VERSION; 1152 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34); 1153 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2); 1154 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33); 1155} 1156