1/* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include <linux/firmware.h> 25#include "amdgpu.h" 26#include "amdgpu_vcn.h" 27#include "amdgpu_pm.h" 28#include "amdgpu_cs.h" 29#include "soc15.h" 30#include "soc15d.h" 31#include "vcn_v2_0.h" 32#include "mmsch_v3_0.h" 33#include "vcn_sw_ring.h" 34 35#include "vcn/vcn_3_0_0_offset.h" 36#include "vcn/vcn_3_0_0_sh_mask.h" 37#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 38 39#include <drm/drm_drv.h> 40 41#define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 42#define VCN1_VID_SOC_ADDRESS_3_0 0x48200 43 44#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 45#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 46#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 47#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 48#define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 49#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 50#define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 51 52#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 53#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 54#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 55#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 56 57#define VCN_INSTANCES_SIENNA_CICHLID 2 58#define DEC_SW_RING_ENABLED FALSE 59 60#define RDECODE_MSG_CREATE 0x00000000 61#define RDECODE_MESSAGE_CREATE 0x00000001 62 63static int amdgpu_ih_clientid_vcns[] = { 64 SOC15_IH_CLIENTID_VCN, 65 SOC15_IH_CLIENTID_VCN1 66}; 67 68static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); 69static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 70static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); 71static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); 72static int vcn_v3_0_set_powergating_state(void *handle, 73 enum amd_powergating_state state); 74static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 75 int inst_idx, struct dpg_pause_state *new_state); 76 77static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 78static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 79 80/** 81 * vcn_v3_0_early_init - set function pointers and load microcode 82 * 83 * @handle: amdgpu_device pointer 84 * 85 * Set ring and irq function pointers 86 * Load microcode from filesystem 87 */ 88static int vcn_v3_0_early_init(void *handle) 89{ 90 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 91 92 if (amdgpu_sriov_vf(adev)) { 93 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 94 adev->vcn.harvest_config = 0; 95 adev->vcn.num_enc_rings = 1; 96 97 } else { 98 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 99 AMDGPU_VCN_HARVEST_VCN1)) 100 /* both instances are harvested, disable the block */ 101 return -ENOENT; 102 103 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == 104 IP_VERSION(3, 0, 33)) 105 adev->vcn.num_enc_rings = 0; 106 else 107 adev->vcn.num_enc_rings = 2; 108 } 109 110 vcn_v3_0_set_dec_ring_funcs(adev); 111 vcn_v3_0_set_enc_ring_funcs(adev); 112 vcn_v3_0_set_irq_funcs(adev); 113 114 return amdgpu_vcn_early_init(adev); 115} 116 117/** 118 * vcn_v3_0_sw_init - sw init for VCN block 119 * 120 * @handle: amdgpu_device pointer 121 * 122 * Load firmware and sw initialization 123 */ 124static int vcn_v3_0_sw_init(void *handle) 125{ 126 struct amdgpu_ring *ring; 127 int i, j, r; 128 int vcn_doorbell_index = 0; 129 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 130 131 r = amdgpu_vcn_sw_init(adev); 132 if (r) 133 return r; 134 135 amdgpu_vcn_setup_ucode(adev); 136 137 r = amdgpu_vcn_resume(adev); 138 if (r) 139 return r; 140 141 /* 142 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines 143 * Formula: 144 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 145 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) 146 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j 147 */ 148 if (amdgpu_sriov_vf(adev)) { 149 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; 150 /* get DWORD offset */ 151 vcn_doorbell_index = vcn_doorbell_index << 1; 152 } 153 154 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 155 volatile struct amdgpu_fw_shared *fw_shared; 156 157 if (adev->vcn.harvest_config & (1 << i)) 158 continue; 159 160 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 161 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 162 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 163 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 164 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 165 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 166 167 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 168 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 169 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 170 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 171 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 172 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 173 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 174 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 175 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 176 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 177 178 /* VCN DEC TRAP */ 179 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 180 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 181 if (r) 182 return r; 183 184 atomic_set(&adev->vcn.inst[i].sched_score, 0); 185 186 ring = &adev->vcn.inst[i].ring_dec; 187 ring->use_doorbell = true; 188 if (amdgpu_sriov_vf(adev)) { 189 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1); 190 } else { 191 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 192 } 193 ring->vm_hub = AMDGPU_MMHUB0(0); 194 sprintf(ring->name, "vcn_dec_%d", i); 195 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 196 AMDGPU_RING_PRIO_DEFAULT, 197 &adev->vcn.inst[i].sched_score); 198 if (r) 199 return r; 200 201 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 202 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(j); 203 204 /* VCN ENC TRAP */ 205 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 206 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 207 if (r) 208 return r; 209 210 ring = &adev->vcn.inst[i].ring_enc[j]; 211 ring->use_doorbell = true; 212 if (amdgpu_sriov_vf(adev)) { 213 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j; 214 } else { 215 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 216 } 217 ring->vm_hub = AMDGPU_MMHUB0(0); 218 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 219 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 220 hw_prio, &adev->vcn.inst[i].sched_score); 221 if (r) 222 return r; 223 } 224 225 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 226 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) | 227 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) | 228 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB); 229 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); 230 fw_shared->present_flag_0 |= AMDGPU_VCN_SMU_VERSION_INFO_FLAG; 231 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 1, 2)) 232 fw_shared->smu_interface_info.smu_interface_type = 2; 233 else if (amdgpu_ip_version(adev, UVD_HWIP, 0) == 234 IP_VERSION(3, 1, 1)) 235 fw_shared->smu_interface_info.smu_interface_type = 1; 236 237 if (amdgpu_vcnfw_log) 238 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 239 } 240 241 if (amdgpu_sriov_vf(adev)) { 242 r = amdgpu_virt_alloc_mm_table(adev); 243 if (r) 244 return r; 245 } 246 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 247 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode; 248 249 return 0; 250} 251 252/** 253 * vcn_v3_0_sw_fini - sw fini for VCN block 254 * 255 * @handle: amdgpu_device pointer 256 * 257 * VCN suspend and free up sw allocation 258 */ 259static int vcn_v3_0_sw_fini(void *handle) 260{ 261 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 262 int i, r, idx; 263 264 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 265 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 266 volatile struct amdgpu_fw_shared *fw_shared; 267 268 if (adev->vcn.harvest_config & (1 << i)) 269 continue; 270 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 271 fw_shared->present_flag_0 = 0; 272 fw_shared->sw_ring.is_enabled = false; 273 } 274 275 drm_dev_exit(idx); 276 } 277 278 if (amdgpu_sriov_vf(adev)) 279 amdgpu_virt_free_mm_table(adev); 280 281 r = amdgpu_vcn_suspend(adev); 282 if (r) 283 return r; 284 285 r = amdgpu_vcn_sw_fini(adev); 286 287 return r; 288} 289 290/** 291 * vcn_v3_0_hw_init - start and test VCN block 292 * 293 * @handle: amdgpu_device pointer 294 * 295 * Initialize the hardware, boot up the VCPU and do some testing 296 */ 297static int vcn_v3_0_hw_init(void *handle) 298{ 299 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 300 struct amdgpu_ring *ring; 301 int i, j, r; 302 303 if (amdgpu_sriov_vf(adev)) { 304 r = vcn_v3_0_start_sriov(adev); 305 if (r) 306 goto done; 307 308 /* initialize VCN dec and enc ring buffers */ 309 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 310 if (adev->vcn.harvest_config & (1 << i)) 311 continue; 312 313 ring = &adev->vcn.inst[i].ring_dec; 314 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i)) { 315 ring->sched.ready = false; 316 ring->no_scheduler = true; 317 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 318 } else { 319 ring->wptr = 0; 320 ring->wptr_old = 0; 321 vcn_v3_0_dec_ring_set_wptr(ring); 322 ring->sched.ready = true; 323 } 324 325 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 326 ring = &adev->vcn.inst[i].ring_enc[j]; 327 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { 328 ring->sched.ready = false; 329 ring->no_scheduler = true; 330 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 331 } else { 332 ring->wptr = 0; 333 ring->wptr_old = 0; 334 vcn_v3_0_enc_ring_set_wptr(ring); 335 ring->sched.ready = true; 336 } 337 } 338 } 339 } else { 340 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 341 if (adev->vcn.harvest_config & (1 << i)) 342 continue; 343 344 ring = &adev->vcn.inst[i].ring_dec; 345 346 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 347 ring->doorbell_index, i); 348 349 r = amdgpu_ring_test_helper(ring); 350 if (r) 351 goto done; 352 353 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 354 ring = &adev->vcn.inst[i].ring_enc[j]; 355 r = amdgpu_ring_test_helper(ring); 356 if (r) 357 goto done; 358 } 359 } 360 } 361 362 return 0; 363done: 364 if (!r) 365 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 366 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 367 368 return r; 369} 370 371/** 372 * vcn_v3_0_hw_fini - stop the hardware block 373 * 374 * @handle: amdgpu_device pointer 375 * 376 * Stop the VCN block, mark ring as not ready any more 377 */ 378static int vcn_v3_0_hw_fini(void *handle) 379{ 380 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 381 int i; 382 383 cancel_delayed_work_sync(&adev->vcn.idle_work); 384 385 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 386 if (adev->vcn.harvest_config & (1 << i)) 387 continue; 388 389 if (!amdgpu_sriov_vf(adev)) { 390 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 391 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 392 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { 393 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 394 } 395 } 396 } 397 398 return 0; 399} 400 401/** 402 * vcn_v3_0_suspend - suspend VCN block 403 * 404 * @handle: amdgpu_device pointer 405 * 406 * HW fini and suspend VCN block 407 */ 408static int vcn_v3_0_suspend(void *handle) 409{ 410 int r; 411 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 412 413 r = vcn_v3_0_hw_fini(adev); 414 if (r) 415 return r; 416 417 r = amdgpu_vcn_suspend(adev); 418 419 return r; 420} 421 422/** 423 * vcn_v3_0_resume - resume VCN block 424 * 425 * @handle: amdgpu_device pointer 426 * 427 * Resume firmware and hw init VCN block 428 */ 429static int vcn_v3_0_resume(void *handle) 430{ 431 int r; 432 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 433 434 r = amdgpu_vcn_resume(adev); 435 if (r) 436 return r; 437 438 r = vcn_v3_0_hw_init(adev); 439 440 return r; 441} 442 443/** 444 * vcn_v3_0_mc_resume - memory controller programming 445 * 446 * @adev: amdgpu_device pointer 447 * @inst: instance number 448 * 449 * Let the VCN memory controller know it's offsets 450 */ 451static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) 452{ 453 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst]->size + 4); 454 uint32_t offset; 455 456 /* cache window 0: fw */ 457 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 458 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 459 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 460 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 461 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 462 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); 463 offset = 0; 464 } else { 465 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 466 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 467 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 468 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 469 offset = size; 470 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 471 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 472 } 473 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); 474 475 /* cache window 1: stack */ 476 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 477 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 478 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 479 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 480 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); 481 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 482 483 /* cache window 2: context */ 484 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 485 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 486 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 487 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 488 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); 489 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 490 491 /* non-cache window */ 492 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 493 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 494 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 495 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 496 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 497 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, 498 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 499} 500 501static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 502{ 503 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst_idx]->size + 4); 504 uint32_t offset; 505 506 /* cache window 0: fw */ 507 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 508 if (!indirect) { 509 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 510 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 511 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 512 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 513 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 514 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 515 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 516 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 517 } else { 518 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 519 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 520 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 521 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 522 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 523 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 524 } 525 offset = 0; 526 } else { 527 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 528 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 529 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 530 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 531 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 532 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 533 offset = size; 534 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 535 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 536 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 537 } 538 539 if (!indirect) 540 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 541 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 542 else 543 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 544 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 545 546 /* cache window 1: stack */ 547 if (!indirect) { 548 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 549 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 550 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 552 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 553 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 554 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 555 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 556 } else { 557 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 558 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 559 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 560 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 561 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 562 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 563 } 564 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 565 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 566 567 /* cache window 2: context */ 568 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 569 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 570 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 571 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 572 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 573 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 574 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 575 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 576 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 577 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 578 579 /* non-cache window */ 580 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 581 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 582 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 583 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 584 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 585 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 586 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 587 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 588 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 589 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 590 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 591 592 /* VCN global tiling registers */ 593 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 594 UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 595} 596 597static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 598{ 599 uint32_t data = 0; 600 601 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 602 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 603 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 604 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 605 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 606 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 607 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 608 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 609 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 610 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 611 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 612 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 613 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 614 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 615 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 616 617 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 618 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 619 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 620 } else { 621 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 622 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 623 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 624 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 625 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 626 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 627 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 628 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 629 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 630 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 631 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 632 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 633 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 634 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 635 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 636 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); 637 } 638 639 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 640 data &= ~0x103; 641 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 642 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 643 UVD_POWER_STATUS__UVD_PG_EN_MASK; 644 645 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 646} 647 648static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 649{ 650 uint32_t data; 651 652 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 653 /* Before power off, this indicator has to be turned on */ 654 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 655 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 656 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 657 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 658 659 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 660 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 661 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 662 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 663 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 664 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 665 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 666 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 667 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 668 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 669 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 670 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 671 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 672 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 673 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 674 675 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 676 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 677 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 678 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 679 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 680 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 681 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 682 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 683 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 684 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 685 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 686 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 687 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 688 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 689 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 690 } 691} 692 693/** 694 * vcn_v3_0_disable_clock_gating - disable VCN clock gating 695 * 696 * @adev: amdgpu_device pointer 697 * @inst: instance number 698 * 699 * Disable clock gating for VCN block 700 */ 701static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 702{ 703 uint32_t data; 704 705 /* VCN disable CGC */ 706 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 707 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 708 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 709 else 710 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 711 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 712 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 713 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 714 715 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); 716 data &= ~(UVD_CGC_GATE__SYS_MASK 717 | UVD_CGC_GATE__UDEC_MASK 718 | UVD_CGC_GATE__MPEG2_MASK 719 | UVD_CGC_GATE__REGS_MASK 720 | UVD_CGC_GATE__RBC_MASK 721 | UVD_CGC_GATE__LMI_MC_MASK 722 | UVD_CGC_GATE__LMI_UMC_MASK 723 | UVD_CGC_GATE__IDCT_MASK 724 | UVD_CGC_GATE__MPRD_MASK 725 | UVD_CGC_GATE__MPC_MASK 726 | UVD_CGC_GATE__LBSI_MASK 727 | UVD_CGC_GATE__LRBBM_MASK 728 | UVD_CGC_GATE__UDEC_RE_MASK 729 | UVD_CGC_GATE__UDEC_CM_MASK 730 | UVD_CGC_GATE__UDEC_IT_MASK 731 | UVD_CGC_GATE__UDEC_DB_MASK 732 | UVD_CGC_GATE__UDEC_MP_MASK 733 | UVD_CGC_GATE__WCB_MASK 734 | UVD_CGC_GATE__VCPU_MASK 735 | UVD_CGC_GATE__MMSCH_MASK); 736 737 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); 738 739 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 740 741 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 742 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 743 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 744 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 745 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 746 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 747 | UVD_CGC_CTRL__SYS_MODE_MASK 748 | UVD_CGC_CTRL__UDEC_MODE_MASK 749 | UVD_CGC_CTRL__MPEG2_MODE_MASK 750 | UVD_CGC_CTRL__REGS_MODE_MASK 751 | UVD_CGC_CTRL__RBC_MODE_MASK 752 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 753 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 754 | UVD_CGC_CTRL__IDCT_MODE_MASK 755 | UVD_CGC_CTRL__MPRD_MODE_MASK 756 | UVD_CGC_CTRL__MPC_MODE_MASK 757 | UVD_CGC_CTRL__LBSI_MODE_MASK 758 | UVD_CGC_CTRL__LRBBM_MODE_MASK 759 | UVD_CGC_CTRL__WCB_MODE_MASK 760 | UVD_CGC_CTRL__VCPU_MODE_MASK 761 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 762 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 763 764 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); 765 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 766 | UVD_SUVD_CGC_GATE__SIT_MASK 767 | UVD_SUVD_CGC_GATE__SMP_MASK 768 | UVD_SUVD_CGC_GATE__SCM_MASK 769 | UVD_SUVD_CGC_GATE__SDB_MASK 770 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 771 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 772 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 773 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 774 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 775 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 776 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 777 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 778 | UVD_SUVD_CGC_GATE__SCLR_MASK 779 | UVD_SUVD_CGC_GATE__ENT_MASK 780 | UVD_SUVD_CGC_GATE__IME_MASK 781 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 782 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 783 | UVD_SUVD_CGC_GATE__SITE_MASK 784 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 785 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 786 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 787 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 788 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK 789 | UVD_SUVD_CGC_GATE__EFC_MASK 790 | UVD_SUVD_CGC_GATE__SAOE_MASK 791 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK 792 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 793 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 794 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK 795 | UVD_SUVD_CGC_GATE__SMPA_MASK); 796 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); 797 798 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); 799 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK 800 | UVD_SUVD_CGC_GATE2__MPBE1_MASK 801 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 802 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 803 | UVD_SUVD_CGC_GATE2__MPC1_MASK); 804 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); 805 806 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 807 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 808 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 809 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 810 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 811 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 812 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 813 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 814 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 815 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 816 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 817 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 818 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 819 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 820 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 821 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 822 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 823 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 824 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 825 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 826 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 827} 828 829static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 830 uint8_t sram_sel, int inst_idx, uint8_t indirect) 831{ 832 uint32_t reg_data = 0; 833 834 /* enable sw clock gating control */ 835 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 836 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 837 else 838 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 839 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 840 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 841 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 842 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 843 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 844 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 845 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 846 UVD_CGC_CTRL__SYS_MODE_MASK | 847 UVD_CGC_CTRL__UDEC_MODE_MASK | 848 UVD_CGC_CTRL__MPEG2_MODE_MASK | 849 UVD_CGC_CTRL__REGS_MODE_MASK | 850 UVD_CGC_CTRL__RBC_MODE_MASK | 851 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 852 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 853 UVD_CGC_CTRL__IDCT_MODE_MASK | 854 UVD_CGC_CTRL__MPRD_MODE_MASK | 855 UVD_CGC_CTRL__MPC_MODE_MASK | 856 UVD_CGC_CTRL__LBSI_MODE_MASK | 857 UVD_CGC_CTRL__LRBBM_MODE_MASK | 858 UVD_CGC_CTRL__WCB_MODE_MASK | 859 UVD_CGC_CTRL__VCPU_MODE_MASK | 860 UVD_CGC_CTRL__MMSCH_MODE_MASK); 861 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 862 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 863 864 /* turn off clock gating */ 865 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 866 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); 867 868 /* turn on SUVD clock gating */ 869 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 870 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 871 872 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 873 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 874 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 875} 876 877/** 878 * vcn_v3_0_enable_clock_gating - enable VCN clock gating 879 * 880 * @adev: amdgpu_device pointer 881 * @inst: instance number 882 * 883 * Enable clock gating for VCN block 884 */ 885static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 886{ 887 uint32_t data; 888 889 /* enable VCN CGC */ 890 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 891 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 892 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 893 else 894 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 895 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 896 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 897 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 898 899 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 900 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 901 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 902 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 903 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 904 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 905 | UVD_CGC_CTRL__SYS_MODE_MASK 906 | UVD_CGC_CTRL__UDEC_MODE_MASK 907 | UVD_CGC_CTRL__MPEG2_MODE_MASK 908 | UVD_CGC_CTRL__REGS_MODE_MASK 909 | UVD_CGC_CTRL__RBC_MODE_MASK 910 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 911 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 912 | UVD_CGC_CTRL__IDCT_MODE_MASK 913 | UVD_CGC_CTRL__MPRD_MODE_MASK 914 | UVD_CGC_CTRL__MPC_MODE_MASK 915 | UVD_CGC_CTRL__LBSI_MODE_MASK 916 | UVD_CGC_CTRL__LRBBM_MODE_MASK 917 | UVD_CGC_CTRL__WCB_MODE_MASK 918 | UVD_CGC_CTRL__VCPU_MODE_MASK 919 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 920 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 921 922 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 923 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 924 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 925 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 926 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 927 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 928 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 929 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 930 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 931 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 932 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 933 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 934 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 935 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 936 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 937 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 938 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 939 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 940 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 941 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 942 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 943} 944 945static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 946{ 947 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 948 struct amdgpu_ring *ring; 949 uint32_t rb_bufsz, tmp; 950 951 /* disable register anti-hang mechanism */ 952 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 953 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 954 /* enable dynamic power gating mode */ 955 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 956 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 957 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 958 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 959 960 if (indirect) 961 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 962 963 /* enable clock gating */ 964 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 965 966 /* enable VCPU clock */ 967 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 968 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 969 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 970 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 971 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 972 973 /* disable master interupt */ 974 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 975 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); 976 977 /* setup mmUVD_LMI_CTRL */ 978 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 979 UVD_LMI_CTRL__REQ_MODE_MASK | 980 UVD_LMI_CTRL__CRC_RESET_MASK | 981 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 982 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 983 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 984 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 985 0x00100000L); 986 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 987 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); 988 989 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 990 VCN, inst_idx, mmUVD_MPC_CNTL), 991 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 992 993 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 994 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), 995 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 996 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 997 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 998 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 999 1000 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1001 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), 1002 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1003 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1004 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1005 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 1006 1007 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1008 VCN, inst_idx, mmUVD_MPC_SET_MUX), 1009 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1010 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1011 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1012 1013 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 1014 1015 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1016 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 1017 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1018 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 1019 1020 /* enable LMI MC and UMC channels */ 1021 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1022 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); 1023 1024 /* unblock VCPU register access */ 1025 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1026 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 1027 1028 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1029 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1030 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1031 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1032 1033 /* enable master interrupt */ 1034 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1035 VCN, inst_idx, mmUVD_MASTINT_EN), 1036 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1037 1038 /* add nop to workaround PSP size check */ 1039 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1040 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1041 1042 if (indirect) 1043 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 1044 1045 ring = &adev->vcn.inst[inst_idx].ring_dec; 1046 /* force RBC into idle state */ 1047 rb_bufsz = order_base_2(ring->ring_size); 1048 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1049 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1050 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1051 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1052 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1053 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1054 1055 /* Stall DPG before WPTR/RPTR reset */ 1056 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1057 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1058 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1059 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1060 1061 /* set the write pointer delay */ 1062 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1063 1064 /* set the wb address */ 1065 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1066 (upper_32_bits(ring->gpu_addr) >> 2)); 1067 1068 /* programm the RB_BASE for ring buffer */ 1069 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1070 lower_32_bits(ring->gpu_addr)); 1071 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1072 upper_32_bits(ring->gpu_addr)); 1073 1074 /* Initialize the ring buffer's read and write pointers */ 1075 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1076 1077 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1078 1079 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1080 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1081 lower_32_bits(ring->wptr)); 1082 1083 /* Reset FW shared memory RBC WPTR/RPTR */ 1084 fw_shared->rb.rptr = 0; 1085 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1086 1087 /*resetting done, fw can check RB ring */ 1088 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1089 1090 /* Unstall DPG */ 1091 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1092 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1093 1094 return 0; 1095} 1096 1097static int vcn_v3_0_start(struct amdgpu_device *adev) 1098{ 1099 volatile struct amdgpu_fw_shared *fw_shared; 1100 struct amdgpu_ring *ring; 1101 uint32_t rb_bufsz, tmp; 1102 int i, j, k, r; 1103 1104 if (adev->pm.dpm_enabled) 1105 amdgpu_dpm_enable_uvd(adev, true); 1106 1107 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1108 if (adev->vcn.harvest_config & (1 << i)) 1109 continue; 1110 1111 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1112 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1113 continue; 1114 } 1115 1116 /* disable VCN power gating */ 1117 vcn_v3_0_disable_static_power_gating(adev, i); 1118 1119 /* set VCN status busy */ 1120 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1121 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1122 1123 /*SW clock gating */ 1124 vcn_v3_0_disable_clock_gating(adev, i); 1125 1126 /* enable VCPU clock */ 1127 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1128 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1129 1130 /* disable master interrupt */ 1131 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1132 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1133 1134 /* enable LMI MC and UMC channels */ 1135 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1136 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1137 1138 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1139 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1140 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1141 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1142 1143 /* setup mmUVD_LMI_CTRL */ 1144 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1145 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 1146 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1147 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1148 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1149 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1150 1151 /* setup mmUVD_MPC_CNTL */ 1152 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1153 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1154 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1155 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1156 1157 /* setup UVD_MPC_SET_MUXA0 */ 1158 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1159 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1160 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1161 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1162 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1163 1164 /* setup UVD_MPC_SET_MUXB0 */ 1165 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1166 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1167 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1168 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1169 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1170 1171 /* setup mmUVD_MPC_SET_MUX */ 1172 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1173 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1174 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1175 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1176 1177 vcn_v3_0_mc_resume(adev, i); 1178 1179 /* VCN global tiling registers */ 1180 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, 1181 adev->gfx.config.gb_addr_config); 1182 1183 /* unblock VCPU register access */ 1184 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1185 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1186 1187 /* release VCPU reset to boot */ 1188 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1189 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1190 1191 for (j = 0; j < 10; ++j) { 1192 uint32_t status; 1193 1194 for (k = 0; k < 100; ++k) { 1195 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1196 if (status & 2) 1197 break; 1198 mdelay(10); 1199 } 1200 r = 0; 1201 if (status & 2) 1202 break; 1203 1204 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); 1205 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1206 UVD_VCPU_CNTL__BLK_RST_MASK, 1207 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1208 mdelay(10); 1209 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1210 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1211 1212 mdelay(10); 1213 r = -1; 1214 } 1215 1216 if (r) { 1217 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); 1218 return r; 1219 } 1220 1221 /* enable master interrupt */ 1222 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1223 UVD_MASTINT_EN__VCPU_EN_MASK, 1224 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1225 1226 /* clear the busy bit of VCN_STATUS */ 1227 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1228 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1229 1230 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1231 1232 ring = &adev->vcn.inst[i].ring_dec; 1233 /* force RBC into idle state */ 1234 rb_bufsz = order_base_2(ring->ring_size); 1235 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1236 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1237 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1238 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1239 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1240 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1241 1242 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1243 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1244 1245 /* programm the RB_BASE for ring buffer */ 1246 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1247 lower_32_bits(ring->gpu_addr)); 1248 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1249 upper_32_bits(ring->gpu_addr)); 1250 1251 /* Initialize the ring buffer's read and write pointers */ 1252 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1253 1254 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); 1255 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1256 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1257 lower_32_bits(ring->wptr)); 1258 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1259 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1260 1261 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != 1262 IP_VERSION(3, 0, 33)) { 1263 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1264 ring = &adev->vcn.inst[i].ring_enc[0]; 1265 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1266 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1267 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1268 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1269 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1270 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1271 1272 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1273 ring = &adev->vcn.inst[i].ring_enc[1]; 1274 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1275 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1276 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1277 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1278 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1279 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1280 } 1281 } 1282 1283 return 0; 1284} 1285 1286static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1287{ 1288 int i, j; 1289 struct amdgpu_ring *ring; 1290 uint64_t cache_addr; 1291 uint64_t rb_addr; 1292 uint64_t ctx_addr; 1293 uint32_t param, resp, expected; 1294 uint32_t offset, cache_size; 1295 uint32_t tmp, timeout; 1296 1297 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1298 uint32_t *table_loc; 1299 uint32_t table_size; 1300 uint32_t size, size_dw; 1301 1302 struct mmsch_v3_0_cmd_direct_write 1303 direct_wt = { {0} }; 1304 struct mmsch_v3_0_cmd_direct_read_modify_write 1305 direct_rd_mod_wt = { {0} }; 1306 struct mmsch_v3_0_cmd_end end = { {0} }; 1307 struct mmsch_v3_0_init_header header; 1308 1309 direct_wt.cmd_header.command_type = 1310 MMSCH_COMMAND__DIRECT_REG_WRITE; 1311 direct_rd_mod_wt.cmd_header.command_type = 1312 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1313 end.cmd_header.command_type = 1314 MMSCH_COMMAND__END; 1315 1316 header.version = MMSCH_VERSION; 1317 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1318 for (i = 0; i < MMSCH_V3_0_VCN_INSTANCES; i++) { 1319 header.inst[i].init_status = 0; 1320 header.inst[i].table_offset = 0; 1321 header.inst[i].table_size = 0; 1322 } 1323 1324 table_loc = (uint32_t *)table->cpu_addr; 1325 table_loc += header.total_size; 1326 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1327 if (adev->vcn.harvest_config & (1 << i)) 1328 continue; 1329 1330 table_size = 0; 1331 1332 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1333 mmUVD_STATUS), 1334 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1335 1336 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4); 1337 1338 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1339 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1340 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1341 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1342 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1343 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1344 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1345 offset = 0; 1346 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1347 mmUVD_VCPU_CACHE_OFFSET0), 1348 0); 1349 } else { 1350 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1351 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1352 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1353 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1354 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1355 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1356 offset = cache_size; 1357 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1358 mmUVD_VCPU_CACHE_OFFSET0), 1359 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1360 } 1361 1362 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1363 mmUVD_VCPU_CACHE_SIZE0), 1364 cache_size); 1365 1366 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1367 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1368 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1369 lower_32_bits(cache_addr)); 1370 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1371 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1372 upper_32_bits(cache_addr)); 1373 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1374 mmUVD_VCPU_CACHE_OFFSET1), 1375 0); 1376 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1377 mmUVD_VCPU_CACHE_SIZE1), 1378 AMDGPU_VCN_STACK_SIZE); 1379 1380 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1381 AMDGPU_VCN_STACK_SIZE; 1382 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1383 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1384 lower_32_bits(cache_addr)); 1385 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1386 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1387 upper_32_bits(cache_addr)); 1388 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1389 mmUVD_VCPU_CACHE_OFFSET2), 1390 0); 1391 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1392 mmUVD_VCPU_CACHE_SIZE2), 1393 AMDGPU_VCN_CONTEXT_SIZE); 1394 1395 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1396 ring = &adev->vcn.inst[i].ring_enc[j]; 1397 ring->wptr = 0; 1398 rb_addr = ring->gpu_addr; 1399 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1400 mmUVD_RB_BASE_LO), 1401 lower_32_bits(rb_addr)); 1402 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1403 mmUVD_RB_BASE_HI), 1404 upper_32_bits(rb_addr)); 1405 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1406 mmUVD_RB_SIZE), 1407 ring->ring_size / 4); 1408 } 1409 1410 ring = &adev->vcn.inst[i].ring_dec; 1411 ring->wptr = 0; 1412 rb_addr = ring->gpu_addr; 1413 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1414 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1415 lower_32_bits(rb_addr)); 1416 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1417 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1418 upper_32_bits(rb_addr)); 1419 /* force RBC into idle state */ 1420 tmp = order_base_2(ring->ring_size); 1421 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1422 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1423 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1424 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1425 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1426 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1427 mmUVD_RBC_RB_CNTL), 1428 tmp); 1429 1430 /* add end packet */ 1431 MMSCH_V3_0_INSERT_END(); 1432 1433 /* refine header */ 1434 header.inst[i].init_status = 0; 1435 header.inst[i].table_offset = header.total_size; 1436 header.inst[i].table_size = table_size; 1437 header.total_size += table_size; 1438 } 1439 1440 /* Update init table header in memory */ 1441 size = sizeof(struct mmsch_v3_0_init_header); 1442 table_loc = (uint32_t *)table->cpu_addr; 1443 memcpy((void *)table_loc, &header, size); 1444 1445 /* message MMSCH (in VCN[0]) to initialize this client 1446 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1447 * of memory descriptor location 1448 */ 1449 ctx_addr = table->gpu_addr; 1450 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1451 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1452 1453 /* 2, update vmid of descriptor */ 1454 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1455 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1456 /* use domain0 for MM scheduler */ 1457 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1458 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1459 1460 /* 3, notify mmsch about the size of this descriptor */ 1461 size = header.total_size; 1462 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1463 1464 /* 4, set resp to zero */ 1465 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1466 1467 /* 5, kick off the initialization and wait until 1468 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1469 */ 1470 param = 0x10000001; 1471 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1472 tmp = 0; 1473 timeout = 1000; 1474 resp = 0; 1475 expected = param + 1; 1476 while (resp != expected) { 1477 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1478 if (resp == expected) 1479 break; 1480 1481 udelay(10); 1482 tmp = tmp + 10; 1483 if (tmp >= timeout) { 1484 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1485 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1486 "(expected=0x%08x, readback=0x%08x)\n", 1487 tmp, expected, resp); 1488 return -EBUSY; 1489 } 1490 } 1491 1492 return 0; 1493} 1494 1495static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1496{ 1497 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1498 uint32_t tmp; 1499 1500 vcn_v3_0_pause_dpg_mode(adev, inst_idx, &state); 1501 1502 /* Wait for power status to be 1 */ 1503 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1504 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1505 1506 /* wait for read ptr to be equal to write ptr */ 1507 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1508 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1509 1510 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1511 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1512 1513 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1514 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1515 1516 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1517 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1518 1519 /* disable dynamic power gating mode */ 1520 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1521 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1522 1523 return 0; 1524} 1525 1526static int vcn_v3_0_stop(struct amdgpu_device *adev) 1527{ 1528 uint32_t tmp; 1529 int i, r = 0; 1530 1531 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1532 if (adev->vcn.harvest_config & (1 << i)) 1533 continue; 1534 1535 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1536 r = vcn_v3_0_stop_dpg_mode(adev, i); 1537 continue; 1538 } 1539 1540 /* wait for vcn idle */ 1541 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1542 if (r) 1543 return r; 1544 1545 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1546 UVD_LMI_STATUS__READ_CLEAN_MASK | 1547 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1548 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1549 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1550 if (r) 1551 return r; 1552 1553 /* disable LMI UMC channel */ 1554 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1555 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1556 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1557 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1558 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1559 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1560 if (r) 1561 return r; 1562 1563 /* block VCPU register access */ 1564 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1565 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1566 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1567 1568 /* reset VCPU */ 1569 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1570 UVD_VCPU_CNTL__BLK_RST_MASK, 1571 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1572 1573 /* disable VCPU clock */ 1574 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1575 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1576 1577 /* apply soft reset */ 1578 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1579 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1580 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1581 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1582 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1583 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1584 1585 /* clear status */ 1586 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1587 1588 /* apply HW clock gating */ 1589 vcn_v3_0_enable_clock_gating(adev, i); 1590 1591 /* enable VCN power gating */ 1592 vcn_v3_0_enable_static_power_gating(adev, i); 1593 } 1594 1595 if (adev->pm.dpm_enabled) 1596 amdgpu_dpm_enable_uvd(adev, false); 1597 1598 return 0; 1599} 1600 1601static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 1602 int inst_idx, struct dpg_pause_state *new_state) 1603{ 1604 volatile struct amdgpu_fw_shared *fw_shared; 1605 struct amdgpu_ring *ring; 1606 uint32_t reg_data = 0; 1607 int ret_code; 1608 1609 /* pause/unpause if state is changed */ 1610 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1611 DRM_DEBUG("dpg pause state changed %d -> %d", 1612 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1613 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1614 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1615 1616 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1617 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1618 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1619 1620 if (!ret_code) { 1621 /* pause DPG */ 1622 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1623 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1624 1625 /* wait for ACK */ 1626 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1627 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1628 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1629 1630 /* Stall DPG before WPTR/RPTR reset */ 1631 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1632 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1633 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1634 1635 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != 1636 IP_VERSION(3, 0, 33)) { 1637 /* Restore */ 1638 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1639 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1640 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1641 ring->wptr = 0; 1642 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1643 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1644 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1645 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1646 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1647 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1648 1649 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1650 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1651 ring->wptr = 0; 1652 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1653 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1654 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1655 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1656 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1657 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1658 1659 /* restore wptr/rptr with pointers saved in FW shared memory*/ 1660 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); 1661 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); 1662 } 1663 1664 /* Unstall DPG */ 1665 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1666 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1667 1668 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1669 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1670 } 1671 } else { 1672 /* unpause dpg, no need to wait */ 1673 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1674 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1675 } 1676 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1677 } 1678 1679 return 0; 1680} 1681 1682/** 1683 * vcn_v3_0_dec_ring_get_rptr - get read pointer 1684 * 1685 * @ring: amdgpu_ring pointer 1686 * 1687 * Returns the current hardware read pointer 1688 */ 1689static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1690{ 1691 struct amdgpu_device *adev = ring->adev; 1692 1693 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1694} 1695 1696/** 1697 * vcn_v3_0_dec_ring_get_wptr - get write pointer 1698 * 1699 * @ring: amdgpu_ring pointer 1700 * 1701 * Returns the current hardware write pointer 1702 */ 1703static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1704{ 1705 struct amdgpu_device *adev = ring->adev; 1706 1707 if (ring->use_doorbell) 1708 return *ring->wptr_cpu_addr; 1709 else 1710 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1711} 1712 1713/** 1714 * vcn_v3_0_dec_ring_set_wptr - set write pointer 1715 * 1716 * @ring: amdgpu_ring pointer 1717 * 1718 * Commits the write pointer to the hardware 1719 */ 1720static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1721{ 1722 struct amdgpu_device *adev = ring->adev; 1723 volatile struct amdgpu_fw_shared *fw_shared; 1724 1725 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1726 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */ 1727 fw_shared = adev->vcn.inst[ring->me].fw_shared.cpu_addr; 1728 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1729 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, 1730 lower_32_bits(ring->wptr)); 1731 } 1732 1733 if (ring->use_doorbell) { 1734 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1735 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1736 } else { 1737 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1738 } 1739} 1740 1741static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { 1742 .type = AMDGPU_RING_TYPE_VCN_DEC, 1743 .align_mask = 0x3f, 1744 .nop = VCN_DEC_SW_CMD_NO_OP, 1745 .secure_submission_supported = true, 1746 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1747 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1748 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1749 .emit_frame_size = 1750 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1751 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1752 VCN_SW_RING_EMIT_FRAME_SIZE, 1753 .emit_ib_size = 5, /* vcn_dec_sw_ring_emit_ib */ 1754 .emit_ib = vcn_dec_sw_ring_emit_ib, 1755 .emit_fence = vcn_dec_sw_ring_emit_fence, 1756 .emit_vm_flush = vcn_dec_sw_ring_emit_vm_flush, 1757 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring, 1758 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib, 1759 .insert_nop = amdgpu_ring_insert_nop, 1760 .insert_end = vcn_dec_sw_ring_insert_end, 1761 .pad_ib = amdgpu_ring_generic_pad_ib, 1762 .begin_use = amdgpu_vcn_ring_begin_use, 1763 .end_use = amdgpu_vcn_ring_end_use, 1764 .emit_wreg = vcn_dec_sw_ring_emit_wreg, 1765 .emit_reg_wait = vcn_dec_sw_ring_emit_reg_wait, 1766 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1767}; 1768 1769static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p, 1770 struct amdgpu_job *job) 1771{ 1772 struct drm_gpu_scheduler **scheds; 1773 1774 /* The create msg must be in the first IB submitted */ 1775 if (atomic_read(&job->base.entity->fence_seq)) 1776 return -EINVAL; 1777 1778 /* if VCN0 is harvested, we can't support AV1 */ 1779 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) 1780 return -EINVAL; 1781 1782 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC] 1783 [AMDGPU_RING_PRIO_DEFAULT].sched; 1784 drm_sched_entity_modify_sched(job->base.entity, scheds, 1); 1785 return 0; 1786} 1787 1788static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, 1789 uint64_t addr) 1790{ 1791 struct ttm_operation_ctx ctx = { false, false }; 1792 struct amdgpu_bo_va_mapping *map; 1793 uint32_t *msg, num_buffers; 1794 struct amdgpu_bo *bo; 1795 uint64_t start, end; 1796 unsigned int i; 1797 void *ptr; 1798 int r; 1799 1800 addr &= AMDGPU_GMC_HOLE_MASK; 1801 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1802 if (r) { 1803 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 1804 return r; 1805 } 1806 1807 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1808 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1809 if (addr & 0x7) { 1810 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1811 return -EINVAL; 1812 } 1813 1814 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1815 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1816 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1817 if (r) { 1818 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1819 return r; 1820 } 1821 1822 r = amdgpu_bo_kmap(bo, &ptr); 1823 if (r) { 1824 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1825 return r; 1826 } 1827 1828 msg = ptr + addr - start; 1829 1830 /* Check length */ 1831 if (msg[1] > end - addr) { 1832 r = -EINVAL; 1833 goto out; 1834 } 1835 1836 if (msg[3] != RDECODE_MSG_CREATE) 1837 goto out; 1838 1839 num_buffers = msg[2]; 1840 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1841 uint32_t offset, size, *create; 1842 1843 if (msg[0] != RDECODE_MESSAGE_CREATE) 1844 continue; 1845 1846 offset = msg[1]; 1847 size = msg[2]; 1848 1849 if (offset + size > end) { 1850 r = -EINVAL; 1851 goto out; 1852 } 1853 1854 create = ptr + addr + offset - start; 1855 1856 /* H246, HEVC and VP9 can run on any instance */ 1857 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1858 continue; 1859 1860 r = vcn_v3_0_limit_sched(p, job); 1861 if (r) 1862 goto out; 1863 } 1864 1865out: 1866 amdgpu_bo_kunmap(bo); 1867 return r; 1868} 1869 1870static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1871 struct amdgpu_job *job, 1872 struct amdgpu_ib *ib) 1873{ 1874 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1875 uint32_t msg_lo = 0, msg_hi = 0; 1876 unsigned i; 1877 int r; 1878 1879 /* The first instance can decode anything */ 1880 if (!ring->me) 1881 return 0; 1882 1883 for (i = 0; i < ib->length_dw; i += 2) { 1884 uint32_t reg = amdgpu_ib_get_value(ib, i); 1885 uint32_t val = amdgpu_ib_get_value(ib, i + 1); 1886 1887 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) { 1888 msg_lo = val; 1889 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) { 1890 msg_hi = val; 1891 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) && 1892 val == 0) { 1893 r = vcn_v3_0_dec_msg(p, job, 1894 ((u64)msg_hi) << 32 | msg_lo); 1895 if (r) 1896 return r; 1897 } 1898 } 1899 return 0; 1900} 1901 1902static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 1903 .type = AMDGPU_RING_TYPE_VCN_DEC, 1904 .align_mask = 0xf, 1905 .secure_submission_supported = true, 1906 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1907 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1908 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1909 .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place, 1910 .emit_frame_size = 1911 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1912 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1913 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1914 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1915 6, 1916 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1917 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1918 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1919 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1920 .test_ring = vcn_v2_0_dec_ring_test_ring, 1921 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1922 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1923 .insert_start = vcn_v2_0_dec_ring_insert_start, 1924 .insert_end = vcn_v2_0_dec_ring_insert_end, 1925 .pad_ib = amdgpu_ring_generic_pad_ib, 1926 .begin_use = amdgpu_vcn_ring_begin_use, 1927 .end_use = amdgpu_vcn_ring_end_use, 1928 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1929 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1930 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1931}; 1932 1933/** 1934 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer 1935 * 1936 * @ring: amdgpu_ring pointer 1937 * 1938 * Returns the current hardware enc read pointer 1939 */ 1940static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1941{ 1942 struct amdgpu_device *adev = ring->adev; 1943 1944 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 1945 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 1946 else 1947 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 1948} 1949 1950/** 1951 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer 1952 * 1953 * @ring: amdgpu_ring pointer 1954 * 1955 * Returns the current hardware enc write pointer 1956 */ 1957static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1958{ 1959 struct amdgpu_device *adev = ring->adev; 1960 1961 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1962 if (ring->use_doorbell) 1963 return *ring->wptr_cpu_addr; 1964 else 1965 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 1966 } else { 1967 if (ring->use_doorbell) 1968 return *ring->wptr_cpu_addr; 1969 else 1970 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 1971 } 1972} 1973 1974/** 1975 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer 1976 * 1977 * @ring: amdgpu_ring pointer 1978 * 1979 * Commits the enc write pointer to the hardware 1980 */ 1981static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1982{ 1983 struct amdgpu_device *adev = ring->adev; 1984 1985 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1986 if (ring->use_doorbell) { 1987 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1988 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1989 } else { 1990 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1991 } 1992 } else { 1993 if (ring->use_doorbell) { 1994 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1995 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1996 } else { 1997 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1998 } 1999 } 2000} 2001 2002static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 2003 .type = AMDGPU_RING_TYPE_VCN_ENC, 2004 .align_mask = 0x3f, 2005 .nop = VCN_ENC_CMD_NO_OP, 2006 .get_rptr = vcn_v3_0_enc_ring_get_rptr, 2007 .get_wptr = vcn_v3_0_enc_ring_get_wptr, 2008 .set_wptr = vcn_v3_0_enc_ring_set_wptr, 2009 .emit_frame_size = 2010 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2011 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2012 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2013 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2014 1, /* vcn_v2_0_enc_ring_insert_end */ 2015 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2016 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2017 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2018 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2019 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2020 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2021 .insert_nop = amdgpu_ring_insert_nop, 2022 .insert_end = vcn_v2_0_enc_ring_insert_end, 2023 .pad_ib = amdgpu_ring_generic_pad_ib, 2024 .begin_use = amdgpu_vcn_ring_begin_use, 2025 .end_use = amdgpu_vcn_ring_end_use, 2026 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2027 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2028 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2029}; 2030 2031static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2032{ 2033 int i; 2034 2035 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2036 if (adev->vcn.harvest_config & (1 << i)) 2037 continue; 2038 2039 if (!DEC_SW_RING_ENABLED) 2040 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; 2041 else 2042 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs; 2043 adev->vcn.inst[i].ring_dec.me = i; 2044 DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i, 2045 DEC_SW_RING_ENABLED?"(Software Ring)":""); 2046 } 2047} 2048 2049static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2050{ 2051 int i, j; 2052 2053 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2054 if (adev->vcn.harvest_config & (1 << i)) 2055 continue; 2056 2057 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 2058 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; 2059 adev->vcn.inst[i].ring_enc[j].me = i; 2060 } 2061 if (adev->vcn.num_enc_rings > 0) 2062 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i); 2063 } 2064} 2065 2066static bool vcn_v3_0_is_idle(void *handle) 2067{ 2068 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2069 int i, ret = 1; 2070 2071 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2072 if (adev->vcn.harvest_config & (1 << i)) 2073 continue; 2074 2075 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 2076 } 2077 2078 return ret; 2079} 2080 2081static int vcn_v3_0_wait_for_idle(void *handle) 2082{ 2083 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2084 int i, ret = 0; 2085 2086 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2087 if (adev->vcn.harvest_config & (1 << i)) 2088 continue; 2089 2090 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 2091 UVD_STATUS__IDLE); 2092 if (ret) 2093 return ret; 2094 } 2095 2096 return ret; 2097} 2098 2099static int vcn_v3_0_set_clockgating_state(void *handle, 2100 enum amd_clockgating_state state) 2101{ 2102 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2103 bool enable = state == AMD_CG_STATE_GATE; 2104 int i; 2105 2106 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2107 if (adev->vcn.harvest_config & (1 << i)) 2108 continue; 2109 2110 if (enable) { 2111 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) 2112 return -EBUSY; 2113 vcn_v3_0_enable_clock_gating(adev, i); 2114 } else { 2115 vcn_v3_0_disable_clock_gating(adev, i); 2116 } 2117 } 2118 2119 return 0; 2120} 2121 2122static int vcn_v3_0_set_powergating_state(void *handle, 2123 enum amd_powergating_state state) 2124{ 2125 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2126 int ret; 2127 2128 /* for SRIOV, guest should not control VCN Power-gating 2129 * MMSCH FW should control Power-gating and clock-gating 2130 * guest should avoid touching CGC and PG 2131 */ 2132 if (amdgpu_sriov_vf(adev)) { 2133 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 2134 return 0; 2135 } 2136 2137 if (state == adev->vcn.cur_state) 2138 return 0; 2139 2140 if (state == AMD_PG_STATE_GATE) 2141 ret = vcn_v3_0_stop(adev); 2142 else 2143 ret = vcn_v3_0_start(adev); 2144 2145 if (!ret) 2146 adev->vcn.cur_state = state; 2147 2148 return ret; 2149} 2150 2151static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, 2152 struct amdgpu_irq_src *source, 2153 unsigned type, 2154 enum amdgpu_interrupt_state state) 2155{ 2156 return 0; 2157} 2158 2159static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, 2160 struct amdgpu_irq_src *source, 2161 struct amdgpu_iv_entry *entry) 2162{ 2163 uint32_t ip_instance; 2164 2165 switch (entry->client_id) { 2166 case SOC15_IH_CLIENTID_VCN: 2167 ip_instance = 0; 2168 break; 2169 case SOC15_IH_CLIENTID_VCN1: 2170 ip_instance = 1; 2171 break; 2172 default: 2173 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2174 return 0; 2175 } 2176 2177 DRM_DEBUG("IH: VCN TRAP\n"); 2178 2179 switch (entry->src_id) { 2180 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2181 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 2182 break; 2183 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2184 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2185 break; 2186 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2187 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 2188 break; 2189 default: 2190 DRM_ERROR("Unhandled interrupt: %d %d\n", 2191 entry->src_id, entry->src_data[0]); 2192 break; 2193 } 2194 2195 return 0; 2196} 2197 2198static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { 2199 .set = vcn_v3_0_set_interrupt_state, 2200 .process = vcn_v3_0_process_interrupt, 2201}; 2202 2203static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) 2204{ 2205 int i; 2206 2207 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2208 if (adev->vcn.harvest_config & (1 << i)) 2209 continue; 2210 2211 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 2212 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; 2213 } 2214} 2215 2216static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 2217 .name = "vcn_v3_0", 2218 .early_init = vcn_v3_0_early_init, 2219 .late_init = NULL, 2220 .sw_init = vcn_v3_0_sw_init, 2221 .sw_fini = vcn_v3_0_sw_fini, 2222 .hw_init = vcn_v3_0_hw_init, 2223 .hw_fini = vcn_v3_0_hw_fini, 2224 .suspend = vcn_v3_0_suspend, 2225 .resume = vcn_v3_0_resume, 2226 .is_idle = vcn_v3_0_is_idle, 2227 .wait_for_idle = vcn_v3_0_wait_for_idle, 2228 .check_soft_reset = NULL, 2229 .pre_soft_reset = NULL, 2230 .soft_reset = NULL, 2231 .post_soft_reset = NULL, 2232 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 2233 .set_powergating_state = vcn_v3_0_set_powergating_state, 2234 .dump_ip_state = NULL, 2235 .print_ip_state = NULL, 2236}; 2237 2238const struct amdgpu_ip_block_version vcn_v3_0_ip_block = { 2239 .type = AMD_IP_BLOCK_TYPE_VCN, 2240 .major = 3, 2241 .minor = 0, 2242 .rev = 0, 2243 .funcs = &vcn_v3_0_ip_funcs, 2244}; 2245