1// SPDX-License-Identifier: GPL-2.0
2//
3// IXP4 GPIO driver
4// Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
5//
6// based on previous work and know-how from:
7// Deepak Saxena <dsaxena@plexity.net>
8
9#include <linux/gpio/driver.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12#include <linux/irqdomain.h>
13#include <linux/irqchip.h>
14#include <linux/of_irq.h>
15#include <linux/platform_device.h>
16#include <linux/bitops.h>
17
18#define IXP4XX_REG_GPOUT	0x00
19#define IXP4XX_REG_GPOE		0x04
20#define IXP4XX_REG_GPIN		0x08
21#define IXP4XX_REG_GPIS		0x0C
22#define IXP4XX_REG_GPIT1	0x10
23#define IXP4XX_REG_GPIT2	0x14
24#define IXP4XX_REG_GPCLK	0x18
25#define IXP4XX_REG_GPDBSEL	0x1C
26
27/*
28 * The hardware uses 3 bits to indicate interrupt "style".
29 * we clear and set these three bits accordingly. The lower 24
30 * bits in two registers (GPIT1 and GPIT2) are used to set up
31 * the style for 8 lines each for a total of 16 GPIO lines.
32 */
33#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH	0x0
34#define IXP4XX_GPIO_STYLE_ACTIVE_LOW	0x1
35#define IXP4XX_GPIO_STYLE_RISING_EDGE	0x2
36#define IXP4XX_GPIO_STYLE_FALLING_EDGE	0x3
37#define IXP4XX_GPIO_STYLE_TRANSITIONAL	0x4
38#define IXP4XX_GPIO_STYLE_MASK		GENMASK(2, 0)
39#define IXP4XX_GPIO_STYLE_SIZE		3
40
41/*
42 * Clock output control register defines.
43 */
44#define IXP4XX_GPCLK_CLK0DC_SHIFT	0
45#define IXP4XX_GPCLK_CLK0TC_SHIFT	4
46#define IXP4XX_GPCLK_CLK0_MASK		GENMASK(7, 0)
47#define IXP4XX_GPCLK_MUX14		BIT(8)
48#define IXP4XX_GPCLK_CLK1DC_SHIFT	16
49#define IXP4XX_GPCLK_CLK1TC_SHIFT	20
50#define IXP4XX_GPCLK_CLK1_MASK		GENMASK(23, 16)
51#define IXP4XX_GPCLK_MUX15		BIT(24)
52
53/**
54 * struct ixp4xx_gpio - IXP4 GPIO state container
55 * @dev: containing device for this instance
56 * @fwnode: the fwnode for this GPIO chip
57 * @gc: gpiochip for this instance
58 * @base: remapped I/O-memory base
59 * @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
60 * 0: level triggered
61 */
62struct ixp4xx_gpio {
63	struct device *dev;
64	struct fwnode_handle *fwnode;
65	struct gpio_chip gc;
66	void __iomem *base;
67	unsigned long long irq_edge;
68};
69
70static void ixp4xx_gpio_irq_ack(struct irq_data *d)
71{
72	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
73	struct ixp4xx_gpio *g = gpiochip_get_data(gc);
74
75	__raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS);
76}
77
78static void ixp4xx_gpio_mask_irq(struct irq_data *d)
79{
80	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
81
82	irq_chip_mask_parent(d);
83	gpiochip_disable_irq(gc, d->hwirq);
84}
85
86static void ixp4xx_gpio_irq_unmask(struct irq_data *d)
87{
88	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
89	struct ixp4xx_gpio *g = gpiochip_get_data(gc);
90
91	/* ACK when unmasking if not edge-triggered */
92	if (!(g->irq_edge & BIT(d->hwirq)))
93		ixp4xx_gpio_irq_ack(d);
94
95	gpiochip_enable_irq(gc, d->hwirq);
96	irq_chip_unmask_parent(d);
97}
98
99static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type)
100{
101	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
102	struct ixp4xx_gpio *g = gpiochip_get_data(gc);
103	int line = d->hwirq;
104	unsigned long flags;
105	u32 int_style;
106	u32 int_reg;
107	u32 val;
108
109	switch (type) {
110	case IRQ_TYPE_EDGE_BOTH:
111		irq_set_handler_locked(d, handle_edge_irq);
112		int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
113		g->irq_edge |= BIT(d->hwirq);
114		break;
115	case IRQ_TYPE_EDGE_RISING:
116		irq_set_handler_locked(d, handle_edge_irq);
117		int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
118		g->irq_edge |= BIT(d->hwirq);
119		break;
120	case IRQ_TYPE_EDGE_FALLING:
121		irq_set_handler_locked(d, handle_edge_irq);
122		int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
123		g->irq_edge |= BIT(d->hwirq);
124		break;
125	case IRQ_TYPE_LEVEL_HIGH:
126		irq_set_handler_locked(d, handle_level_irq);
127		int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
128		g->irq_edge &= ~BIT(d->hwirq);
129		break;
130	case IRQ_TYPE_LEVEL_LOW:
131		irq_set_handler_locked(d, handle_level_irq);
132		int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
133		g->irq_edge &= ~BIT(d->hwirq);
134		break;
135	default:
136		return -EINVAL;
137	}
138
139	if (line >= 8) {
140		/* pins 8-15 */
141		line -= 8;
142		int_reg = IXP4XX_REG_GPIT2;
143	} else {
144		/* pins 0-7 */
145		int_reg = IXP4XX_REG_GPIT1;
146	}
147
148	raw_spin_lock_irqsave(&g->gc.bgpio_lock, flags);
149
150	/* Clear the style for the appropriate pin */
151	val = __raw_readl(g->base + int_reg);
152	val &= ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE));
153	__raw_writel(val, g->base + int_reg);
154
155	__raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS);
156
157	/* Set the new style */
158	val = __raw_readl(g->base + int_reg);
159	val |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
160	__raw_writel(val, g->base + int_reg);
161
162	/* Force-configure this line as an input */
163	val = __raw_readl(g->base + IXP4XX_REG_GPOE);
164	val |= BIT(d->hwirq);
165	__raw_writel(val, g->base + IXP4XX_REG_GPOE);
166
167	raw_spin_unlock_irqrestore(&g->gc.bgpio_lock, flags);
168
169	/* This parent only accept level high (asserted) */
170	return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
171}
172
173static const struct irq_chip ixp4xx_gpio_irqchip = {
174	.name = "IXP4GPIO",
175	.irq_ack = ixp4xx_gpio_irq_ack,
176	.irq_mask = ixp4xx_gpio_mask_irq,
177	.irq_unmask = ixp4xx_gpio_irq_unmask,
178	.irq_set_type = ixp4xx_gpio_irq_set_type,
179	.flags = IRQCHIP_IMMUTABLE,
180	GPIOCHIP_IRQ_RESOURCE_HELPERS,
181};
182
183static int ixp4xx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
184					     unsigned int child,
185					     unsigned int child_type,
186					     unsigned int *parent,
187					     unsigned int *parent_type)
188{
189	/* All these interrupts are level high in the CPU */
190	*parent_type = IRQ_TYPE_LEVEL_HIGH;
191
192	/* GPIO lines 0..12 have dedicated IRQs */
193	if (child == 0) {
194		*parent = 6;
195		return 0;
196	}
197	if (child == 1) {
198		*parent = 7;
199		return 0;
200	}
201	if (child >= 2 && child <= 12) {
202		*parent = child + 17;
203		return 0;
204	}
205	return -EINVAL;
206}
207
208static int ixp4xx_gpio_probe(struct platform_device *pdev)
209{
210	unsigned long flags;
211	struct device *dev = &pdev->dev;
212	struct device_node *np = dev->of_node;
213	struct irq_domain *parent;
214	struct ixp4xx_gpio *g;
215	struct gpio_irq_chip *girq;
216	struct device_node *irq_parent;
217	bool clk_14, clk_15;
218	u32 val;
219	int ret;
220
221	g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
222	if (!g)
223		return -ENOMEM;
224	g->dev = dev;
225
226	g->base = devm_platform_ioremap_resource(pdev, 0);
227	if (IS_ERR(g->base))
228		return PTR_ERR(g->base);
229
230	irq_parent = of_irq_find_parent(np);
231	if (!irq_parent) {
232		dev_err(dev, "no IRQ parent node\n");
233		return -ENODEV;
234	}
235	parent = irq_find_host(irq_parent);
236	if (!parent) {
237		dev_err(dev, "no IRQ parent domain\n");
238		return -ENODEV;
239	}
240	g->fwnode = of_node_to_fwnode(np);
241
242	/*
243	 * If either clock output is enabled explicitly in the device tree
244	 * we take full control of the clock by masking off all bits for
245	 * the clock control and selectively enabling them. Otherwise
246	 * we leave the hardware default settings.
247	 *
248	 * Enable clock outputs with default timings of requested clock.
249	 * If you need control over TC and DC, add these to the device
250	 * tree bindings and use them here.
251	 */
252	clk_14 = of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout");
253	clk_15 = of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout");
254
255	/*
256	 * Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on
257	 * specific machines.
258	 */
259	if (of_machine_is_compatible("dlink,dsm-g600-a") ||
260	    of_machine_is_compatible("iom,nas-100d"))
261		val = 0;
262	else {
263		val = __raw_readl(g->base + IXP4XX_REG_GPCLK);
264
265		if (clk_14 || clk_15) {
266			val &= ~(IXP4XX_GPCLK_MUX14 | IXP4XX_GPCLK_MUX15);
267			val &= ~IXP4XX_GPCLK_CLK0_MASK;
268			val &= ~IXP4XX_GPCLK_CLK1_MASK;
269			if (clk_14) {
270				/* IXP4XX_GPCLK_CLK0DC implicit low */
271				val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT);
272				val |= IXP4XX_GPCLK_MUX14;
273			}
274
275			if (clk_15) {
276				/* IXP4XX_GPCLK_CLK1DC implicit low */
277				val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT);
278				val |= IXP4XX_GPCLK_MUX15;
279			}
280		}
281	}
282
283	__raw_writel(val, g->base + IXP4XX_REG_GPCLK);
284
285	/*
286	 * This is a very special big-endian ARM issue: when the IXP4xx is
287	 * run in big endian mode, all registers in the machine are switched
288	 * around to the CPU-native endianness. As you see mostly in the
289	 * driver we use __raw_readl()/__raw_writel() to access the registers
290	 * in the appropriate order. With the GPIO library we need to specify
291	 * byte order explicitly, so this flag needs to be set when compiling
292	 * for big endian.
293	 */
294#if defined(CONFIG_CPU_BIG_ENDIAN)
295	flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
296#else
297	flags = 0;
298#endif
299
300	/* Populate and register gpio chip */
301	ret = bgpio_init(&g->gc, dev, 4,
302			 g->base + IXP4XX_REG_GPIN,
303			 g->base + IXP4XX_REG_GPOUT,
304			 NULL,
305			 NULL,
306			 g->base + IXP4XX_REG_GPOE,
307			 flags);
308	if (ret) {
309		dev_err(dev, "unable to init generic GPIO\n");
310		return ret;
311	}
312	g->gc.ngpio = 16;
313	g->gc.label = "IXP4XX_GPIO_CHIP";
314	/*
315	 * TODO: when we have migrated to device tree and all GPIOs
316	 * are fetched using phandles, set this to -1 to get rid of
317	 * the fixed gpiochip base.
318	 */
319	g->gc.base = 0;
320	g->gc.parent = &pdev->dev;
321	g->gc.owner = THIS_MODULE;
322
323	girq = &g->gc.irq;
324	gpio_irq_chip_set_chip(girq, &ixp4xx_gpio_irqchip);
325	girq->fwnode = g->fwnode;
326	girq->parent_domain = parent;
327	girq->child_to_parent_hwirq = ixp4xx_gpio_child_to_parent_hwirq;
328	girq->handler = handle_bad_irq;
329	girq->default_type = IRQ_TYPE_NONE;
330
331	ret = devm_gpiochip_add_data(dev, &g->gc, g);
332	if (ret) {
333		dev_err(dev, "failed to add SoC gpiochip\n");
334		return ret;
335	}
336
337	platform_set_drvdata(pdev, g);
338	dev_info(dev, "IXP4 GPIO registered\n");
339
340	return 0;
341}
342
343static const struct of_device_id ixp4xx_gpio_of_match[] = {
344	{
345		.compatible = "intel,ixp4xx-gpio",
346	},
347	{},
348};
349
350
351static struct platform_driver ixp4xx_gpio_driver = {
352	.driver = {
353		.name		= "ixp4xx-gpio",
354		.of_match_table = ixp4xx_gpio_of_match,
355	},
356	.probe = ixp4xx_gpio_probe,
357};
358builtin_platform_driver(ixp4xx_gpio_driver);
359