1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_X86_PGTABLE_H 3#define _ASM_X86_PGTABLE_H 4 5#include <linux/mem_encrypt.h> 6#include <asm/page.h> 7#include <asm/pgtable_types.h> 8 9/* 10 * Macro to mark a page protection value as UC- 11 */ 12#define pgprot_noncached(prot) \ 13 ((boot_cpu_data.x86 > 3) \ 14 ? (__pgprot(pgprot_val(prot) | \ 15 cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS))) \ 16 : (prot)) 17 18#ifndef __ASSEMBLY__ 19#include <linux/spinlock.h> 20#include <asm/x86_init.h> 21#include <asm/pkru.h> 22#include <asm/fpu/api.h> 23#include <asm/coco.h> 24#include <asm-generic/pgtable_uffd.h> 25#include <linux/page_table_check.h> 26 27extern pgd_t early_top_pgt[PTRS_PER_PGD]; 28bool __init __early_make_pgtable(unsigned long address, pmdval_t pmd); 29 30struct seq_file; 31void ptdump_walk_pgd_level(struct seq_file *m, struct mm_struct *mm); 32void ptdump_walk_pgd_level_debugfs(struct seq_file *m, struct mm_struct *mm, 33 bool user); 34bool ptdump_walk_pgd_level_checkwx(void); 35#define ptdump_check_wx ptdump_walk_pgd_level_checkwx 36void ptdump_walk_user_pgd_level_checkwx(void); 37 38/* 39 * Macros to add or remove encryption attribute 40 */ 41#define pgprot_encrypted(prot) __pgprot(cc_mkenc(pgprot_val(prot))) 42#define pgprot_decrypted(prot) __pgprot(cc_mkdec(pgprot_val(prot))) 43 44#ifdef CONFIG_DEBUG_WX 45#define debug_checkwx_user() ptdump_walk_user_pgd_level_checkwx() 46#else 47#define debug_checkwx_user() do { } while (0) 48#endif 49 50/* 51 * ZERO_PAGE is a global shared page that is always zero: used 52 * for zero-mapped memory areas etc.. 53 */ 54extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)] 55 __visible; 56#define ZERO_PAGE(vaddr) ((void)(vaddr),virt_to_page(empty_zero_page)) 57 58extern spinlock_t pgd_lock; 59extern struct list_head pgd_list; 60 61extern struct mm_struct *pgd_page_get_mm(struct page *page); 62 63extern pmdval_t early_pmd_flags; 64 65#ifdef CONFIG_PARAVIRT_XXL 66#include <asm/paravirt.h> 67#else /* !CONFIG_PARAVIRT_XXL */ 68#define set_pte(ptep, pte) native_set_pte(ptep, pte) 69 70#define set_pte_atomic(ptep, pte) \ 71 native_set_pte_atomic(ptep, pte) 72 73#define set_pmd(pmdp, pmd) native_set_pmd(pmdp, pmd) 74 75#ifndef __PAGETABLE_P4D_FOLDED 76#define set_pgd(pgdp, pgd) native_set_pgd(pgdp, pgd) 77#define pgd_clear(pgd) (pgtable_l5_enabled() ? native_pgd_clear(pgd) : 0) 78#endif 79 80#ifndef set_p4d 81# define set_p4d(p4dp, p4d) native_set_p4d(p4dp, p4d) 82#endif 83 84#ifndef __PAGETABLE_PUD_FOLDED 85#define p4d_clear(p4d) native_p4d_clear(p4d) 86#endif 87 88#ifndef set_pud 89# define set_pud(pudp, pud) native_set_pud(pudp, pud) 90#endif 91 92#ifndef __PAGETABLE_PUD_FOLDED 93#define pud_clear(pud) native_pud_clear(pud) 94#endif 95 96#define pte_clear(mm, addr, ptep) native_pte_clear(mm, addr, ptep) 97#define pmd_clear(pmd) native_pmd_clear(pmd) 98 99#define pgd_val(x) native_pgd_val(x) 100#define __pgd(x) native_make_pgd(x) 101 102#ifndef __PAGETABLE_P4D_FOLDED 103#define p4d_val(x) native_p4d_val(x) 104#define __p4d(x) native_make_p4d(x) 105#endif 106 107#ifndef __PAGETABLE_PUD_FOLDED 108#define pud_val(x) native_pud_val(x) 109#define __pud(x) native_make_pud(x) 110#endif 111 112#ifndef __PAGETABLE_PMD_FOLDED 113#define pmd_val(x) native_pmd_val(x) 114#define __pmd(x) native_make_pmd(x) 115#endif 116 117#define pte_val(x) native_pte_val(x) 118#define __pte(x) native_make_pte(x) 119 120#define arch_end_context_switch(prev) do {} while(0) 121#endif /* CONFIG_PARAVIRT_XXL */ 122 123/* 124 * The following only work if pte_present() is true. 125 * Undefined behaviour if not.. 126 */ 127static inline bool pte_dirty(pte_t pte) 128{ 129 return pte_flags(pte) & _PAGE_DIRTY_BITS; 130} 131 132static inline bool pte_shstk(pte_t pte) 133{ 134 return cpu_feature_enabled(X86_FEATURE_SHSTK) && 135 (pte_flags(pte) & (_PAGE_RW | _PAGE_DIRTY)) == _PAGE_DIRTY; 136} 137 138static inline int pte_young(pte_t pte) 139{ 140 return pte_flags(pte) & _PAGE_ACCESSED; 141} 142 143#define pmd_dirty pmd_dirty 144static inline bool pmd_dirty(pmd_t pmd) 145{ 146 return pmd_flags(pmd) & _PAGE_DIRTY_BITS; 147} 148 149static inline bool pmd_shstk(pmd_t pmd) 150{ 151 return cpu_feature_enabled(X86_FEATURE_SHSTK) && 152 (pmd_flags(pmd) & (_PAGE_RW | _PAGE_DIRTY | _PAGE_PSE)) == 153 (_PAGE_DIRTY | _PAGE_PSE); 154} 155 156#define pmd_young pmd_young 157static inline int pmd_young(pmd_t pmd) 158{ 159 return pmd_flags(pmd) & _PAGE_ACCESSED; 160} 161 162static inline bool pud_dirty(pud_t pud) 163{ 164 return pud_flags(pud) & _PAGE_DIRTY_BITS; 165} 166 167static inline int pud_young(pud_t pud) 168{ 169 return pud_flags(pud) & _PAGE_ACCESSED; 170} 171 172static inline int pte_write(pte_t pte) 173{ 174 /* 175 * Shadow stack pages are logically writable, but do not have 176 * _PAGE_RW. Check for them separately from _PAGE_RW itself. 177 */ 178 return (pte_flags(pte) & _PAGE_RW) || pte_shstk(pte); 179} 180 181#define pmd_write pmd_write 182static inline int pmd_write(pmd_t pmd) 183{ 184 /* 185 * Shadow stack pages are logically writable, but do not have 186 * _PAGE_RW. Check for them separately from _PAGE_RW itself. 187 */ 188 return (pmd_flags(pmd) & _PAGE_RW) || pmd_shstk(pmd); 189} 190 191#define pud_write pud_write 192static inline int pud_write(pud_t pud) 193{ 194 return pud_flags(pud) & _PAGE_RW; 195} 196 197static inline int pte_huge(pte_t pte) 198{ 199 return pte_flags(pte) & _PAGE_PSE; 200} 201 202static inline int pte_global(pte_t pte) 203{ 204 return pte_flags(pte) & _PAGE_GLOBAL; 205} 206 207static inline int pte_exec(pte_t pte) 208{ 209 return !(pte_flags(pte) & _PAGE_NX); 210} 211 212static inline int pte_special(pte_t pte) 213{ 214 return pte_flags(pte) & _PAGE_SPECIAL; 215} 216 217/* Entries that were set to PROT_NONE are inverted */ 218 219static inline u64 protnone_mask(u64 val); 220 221#define PFN_PTE_SHIFT PAGE_SHIFT 222 223static inline unsigned long pte_pfn(pte_t pte) 224{ 225 phys_addr_t pfn = pte_val(pte); 226 pfn ^= protnone_mask(pfn); 227 return (pfn & PTE_PFN_MASK) >> PAGE_SHIFT; 228} 229 230static inline unsigned long pmd_pfn(pmd_t pmd) 231{ 232 phys_addr_t pfn = pmd_val(pmd); 233 pfn ^= protnone_mask(pfn); 234 return (pfn & pmd_pfn_mask(pmd)) >> PAGE_SHIFT; 235} 236 237#define pud_pfn pud_pfn 238static inline unsigned long pud_pfn(pud_t pud) 239{ 240 phys_addr_t pfn = pud_val(pud); 241 pfn ^= protnone_mask(pfn); 242 return (pfn & pud_pfn_mask(pud)) >> PAGE_SHIFT; 243} 244 245static inline unsigned long p4d_pfn(p4d_t p4d) 246{ 247 return (p4d_val(p4d) & p4d_pfn_mask(p4d)) >> PAGE_SHIFT; 248} 249 250static inline unsigned long pgd_pfn(pgd_t pgd) 251{ 252 return (pgd_val(pgd) & PTE_PFN_MASK) >> PAGE_SHIFT; 253} 254 255#define p4d_leaf p4d_leaf 256static inline bool p4d_leaf(p4d_t p4d) 257{ 258 /* No 512 GiB pages yet */ 259 return 0; 260} 261 262#define pte_page(pte) pfn_to_page(pte_pfn(pte)) 263 264#define pmd_leaf pmd_leaf 265static inline bool pmd_leaf(pmd_t pte) 266{ 267 return pmd_flags(pte) & _PAGE_PSE; 268} 269 270#ifdef CONFIG_TRANSPARENT_HUGEPAGE 271/* NOTE: when predicate huge page, consider also pmd_devmap, or use pmd_leaf */ 272static inline int pmd_trans_huge(pmd_t pmd) 273{ 274 return (pmd_val(pmd) & (_PAGE_PSE|_PAGE_DEVMAP)) == _PAGE_PSE; 275} 276 277#ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 278static inline int pud_trans_huge(pud_t pud) 279{ 280 return (pud_val(pud) & (_PAGE_PSE|_PAGE_DEVMAP)) == _PAGE_PSE; 281} 282#endif 283 284#define has_transparent_hugepage has_transparent_hugepage 285static inline int has_transparent_hugepage(void) 286{ 287 return boot_cpu_has(X86_FEATURE_PSE); 288} 289 290#ifdef CONFIG_ARCH_HAS_PTE_DEVMAP 291static inline int pmd_devmap(pmd_t pmd) 292{ 293 return !!(pmd_val(pmd) & _PAGE_DEVMAP); 294} 295 296#ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 297static inline int pud_devmap(pud_t pud) 298{ 299 return !!(pud_val(pud) & _PAGE_DEVMAP); 300} 301#else 302static inline int pud_devmap(pud_t pud) 303{ 304 return 0; 305} 306#endif 307 308static inline int pgd_devmap(pgd_t pgd) 309{ 310 return 0; 311} 312#endif 313#endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 314 315static inline pte_t pte_set_flags(pte_t pte, pteval_t set) 316{ 317 pteval_t v = native_pte_val(pte); 318 319 return native_make_pte(v | set); 320} 321 322static inline pte_t pte_clear_flags(pte_t pte, pteval_t clear) 323{ 324 pteval_t v = native_pte_val(pte); 325 326 return native_make_pte(v & ~clear); 327} 328 329/* 330 * Write protection operations can result in Dirty=1,Write=0 PTEs. But in the 331 * case of X86_FEATURE_USER_SHSTK, these PTEs denote shadow stack memory. So 332 * when creating dirty, write-protected memory, a software bit is used: 333 * _PAGE_BIT_SAVED_DIRTY. The following functions take a PTE and transition the 334 * Dirty bit to SavedDirty, and vice-vesra. 335 * 336 * This shifting is only done if needed. In the case of shifting 337 * Dirty->SavedDirty, the condition is if the PTE is Write=0. In the case of 338 * shifting SavedDirty->Dirty, the condition is Write=1. 339 */ 340static inline pgprotval_t mksaveddirty_shift(pgprotval_t v) 341{ 342 pgprotval_t cond = (~v >> _PAGE_BIT_RW) & 1; 343 344 v |= ((v >> _PAGE_BIT_DIRTY) & cond) << _PAGE_BIT_SAVED_DIRTY; 345 v &= ~(cond << _PAGE_BIT_DIRTY); 346 347 return v; 348} 349 350static inline pgprotval_t clear_saveddirty_shift(pgprotval_t v) 351{ 352 pgprotval_t cond = (v >> _PAGE_BIT_RW) & 1; 353 354 v |= ((v >> _PAGE_BIT_SAVED_DIRTY) & cond) << _PAGE_BIT_DIRTY; 355 v &= ~(cond << _PAGE_BIT_SAVED_DIRTY); 356 357 return v; 358} 359 360static inline pte_t pte_mksaveddirty(pte_t pte) 361{ 362 pteval_t v = native_pte_val(pte); 363 364 v = mksaveddirty_shift(v); 365 return native_make_pte(v); 366} 367 368static inline pte_t pte_clear_saveddirty(pte_t pte) 369{ 370 pteval_t v = native_pte_val(pte); 371 372 v = clear_saveddirty_shift(v); 373 return native_make_pte(v); 374} 375 376static inline pte_t pte_wrprotect(pte_t pte) 377{ 378 pte = pte_clear_flags(pte, _PAGE_RW); 379 380 /* 381 * Blindly clearing _PAGE_RW might accidentally create 382 * a shadow stack PTE (Write=0,Dirty=1). Move the hardware 383 * dirty value to the software bit, if present. 384 */ 385 return pte_mksaveddirty(pte); 386} 387 388#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 389static inline int pte_uffd_wp(pte_t pte) 390{ 391 return pte_flags(pte) & _PAGE_UFFD_WP; 392} 393 394static inline pte_t pte_mkuffd_wp(pte_t pte) 395{ 396 return pte_wrprotect(pte_set_flags(pte, _PAGE_UFFD_WP)); 397} 398 399static inline pte_t pte_clear_uffd_wp(pte_t pte) 400{ 401 return pte_clear_flags(pte, _PAGE_UFFD_WP); 402} 403#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 404 405static inline pte_t pte_mkclean(pte_t pte) 406{ 407 return pte_clear_flags(pte, _PAGE_DIRTY_BITS); 408} 409 410static inline pte_t pte_mkold(pte_t pte) 411{ 412 return pte_clear_flags(pte, _PAGE_ACCESSED); 413} 414 415static inline pte_t pte_mkexec(pte_t pte) 416{ 417 return pte_clear_flags(pte, _PAGE_NX); 418} 419 420static inline pte_t pte_mkdirty(pte_t pte) 421{ 422 pte = pte_set_flags(pte, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 423 424 return pte_mksaveddirty(pte); 425} 426 427static inline pte_t pte_mkwrite_shstk(pte_t pte) 428{ 429 pte = pte_clear_flags(pte, _PAGE_RW); 430 431 return pte_set_flags(pte, _PAGE_DIRTY); 432} 433 434static inline pte_t pte_mkyoung(pte_t pte) 435{ 436 return pte_set_flags(pte, _PAGE_ACCESSED); 437} 438 439static inline pte_t pte_mkwrite_novma(pte_t pte) 440{ 441 return pte_set_flags(pte, _PAGE_RW); 442} 443 444struct vm_area_struct; 445pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma); 446#define pte_mkwrite pte_mkwrite 447 448static inline pte_t pte_mkhuge(pte_t pte) 449{ 450 return pte_set_flags(pte, _PAGE_PSE); 451} 452 453static inline pte_t pte_clrhuge(pte_t pte) 454{ 455 return pte_clear_flags(pte, _PAGE_PSE); 456} 457 458static inline pte_t pte_mkglobal(pte_t pte) 459{ 460 return pte_set_flags(pte, _PAGE_GLOBAL); 461} 462 463static inline pte_t pte_clrglobal(pte_t pte) 464{ 465 return pte_clear_flags(pte, _PAGE_GLOBAL); 466} 467 468static inline pte_t pte_mkspecial(pte_t pte) 469{ 470 return pte_set_flags(pte, _PAGE_SPECIAL); 471} 472 473static inline pte_t pte_mkdevmap(pte_t pte) 474{ 475 return pte_set_flags(pte, _PAGE_SPECIAL|_PAGE_DEVMAP); 476} 477 478static inline pmd_t pmd_set_flags(pmd_t pmd, pmdval_t set) 479{ 480 pmdval_t v = native_pmd_val(pmd); 481 482 return native_make_pmd(v | set); 483} 484 485static inline pmd_t pmd_clear_flags(pmd_t pmd, pmdval_t clear) 486{ 487 pmdval_t v = native_pmd_val(pmd); 488 489 return native_make_pmd(v & ~clear); 490} 491 492/* See comments above mksaveddirty_shift() */ 493static inline pmd_t pmd_mksaveddirty(pmd_t pmd) 494{ 495 pmdval_t v = native_pmd_val(pmd); 496 497 v = mksaveddirty_shift(v); 498 return native_make_pmd(v); 499} 500 501/* See comments above mksaveddirty_shift() */ 502static inline pmd_t pmd_clear_saveddirty(pmd_t pmd) 503{ 504 pmdval_t v = native_pmd_val(pmd); 505 506 v = clear_saveddirty_shift(v); 507 return native_make_pmd(v); 508} 509 510static inline pmd_t pmd_wrprotect(pmd_t pmd) 511{ 512 pmd = pmd_clear_flags(pmd, _PAGE_RW); 513 514 /* 515 * Blindly clearing _PAGE_RW might accidentally create 516 * a shadow stack PMD (RW=0, Dirty=1). Move the hardware 517 * dirty value to the software bit. 518 */ 519 return pmd_mksaveddirty(pmd); 520} 521 522#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 523static inline int pmd_uffd_wp(pmd_t pmd) 524{ 525 return pmd_flags(pmd) & _PAGE_UFFD_WP; 526} 527 528static inline pmd_t pmd_mkuffd_wp(pmd_t pmd) 529{ 530 return pmd_wrprotect(pmd_set_flags(pmd, _PAGE_UFFD_WP)); 531} 532 533static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd) 534{ 535 return pmd_clear_flags(pmd, _PAGE_UFFD_WP); 536} 537#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 538 539static inline pmd_t pmd_mkold(pmd_t pmd) 540{ 541 return pmd_clear_flags(pmd, _PAGE_ACCESSED); 542} 543 544static inline pmd_t pmd_mkclean(pmd_t pmd) 545{ 546 return pmd_clear_flags(pmd, _PAGE_DIRTY_BITS); 547} 548 549static inline pmd_t pmd_mkdirty(pmd_t pmd) 550{ 551 pmd = pmd_set_flags(pmd, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 552 553 return pmd_mksaveddirty(pmd); 554} 555 556static inline pmd_t pmd_mkwrite_shstk(pmd_t pmd) 557{ 558 pmd = pmd_clear_flags(pmd, _PAGE_RW); 559 560 return pmd_set_flags(pmd, _PAGE_DIRTY); 561} 562 563static inline pmd_t pmd_mkdevmap(pmd_t pmd) 564{ 565 return pmd_set_flags(pmd, _PAGE_DEVMAP); 566} 567 568static inline pmd_t pmd_mkhuge(pmd_t pmd) 569{ 570 return pmd_set_flags(pmd, _PAGE_PSE); 571} 572 573static inline pmd_t pmd_mkyoung(pmd_t pmd) 574{ 575 return pmd_set_flags(pmd, _PAGE_ACCESSED); 576} 577 578static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 579{ 580 return pmd_set_flags(pmd, _PAGE_RW); 581} 582 583pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma); 584#define pmd_mkwrite pmd_mkwrite 585 586static inline pud_t pud_set_flags(pud_t pud, pudval_t set) 587{ 588 pudval_t v = native_pud_val(pud); 589 590 return native_make_pud(v | set); 591} 592 593static inline pud_t pud_clear_flags(pud_t pud, pudval_t clear) 594{ 595 pudval_t v = native_pud_val(pud); 596 597 return native_make_pud(v & ~clear); 598} 599 600/* See comments above mksaveddirty_shift() */ 601static inline pud_t pud_mksaveddirty(pud_t pud) 602{ 603 pudval_t v = native_pud_val(pud); 604 605 v = mksaveddirty_shift(v); 606 return native_make_pud(v); 607} 608 609/* See comments above mksaveddirty_shift() */ 610static inline pud_t pud_clear_saveddirty(pud_t pud) 611{ 612 pudval_t v = native_pud_val(pud); 613 614 v = clear_saveddirty_shift(v); 615 return native_make_pud(v); 616} 617 618static inline pud_t pud_mkold(pud_t pud) 619{ 620 return pud_clear_flags(pud, _PAGE_ACCESSED); 621} 622 623static inline pud_t pud_mkclean(pud_t pud) 624{ 625 return pud_clear_flags(pud, _PAGE_DIRTY_BITS); 626} 627 628static inline pud_t pud_wrprotect(pud_t pud) 629{ 630 pud = pud_clear_flags(pud, _PAGE_RW); 631 632 /* 633 * Blindly clearing _PAGE_RW might accidentally create 634 * a shadow stack PUD (RW=0, Dirty=1). Move the hardware 635 * dirty value to the software bit. 636 */ 637 return pud_mksaveddirty(pud); 638} 639 640static inline pud_t pud_mkdirty(pud_t pud) 641{ 642 pud = pud_set_flags(pud, _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 643 644 return pud_mksaveddirty(pud); 645} 646 647static inline pud_t pud_mkdevmap(pud_t pud) 648{ 649 return pud_set_flags(pud, _PAGE_DEVMAP); 650} 651 652static inline pud_t pud_mkhuge(pud_t pud) 653{ 654 return pud_set_flags(pud, _PAGE_PSE); 655} 656 657static inline pud_t pud_mkyoung(pud_t pud) 658{ 659 return pud_set_flags(pud, _PAGE_ACCESSED); 660} 661 662static inline pud_t pud_mkwrite(pud_t pud) 663{ 664 pud = pud_set_flags(pud, _PAGE_RW); 665 666 return pud_clear_saveddirty(pud); 667} 668 669#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 670static inline int pte_soft_dirty(pte_t pte) 671{ 672 return pte_flags(pte) & _PAGE_SOFT_DIRTY; 673} 674 675static inline int pmd_soft_dirty(pmd_t pmd) 676{ 677 return pmd_flags(pmd) & _PAGE_SOFT_DIRTY; 678} 679 680static inline int pud_soft_dirty(pud_t pud) 681{ 682 return pud_flags(pud) & _PAGE_SOFT_DIRTY; 683} 684 685static inline pte_t pte_mksoft_dirty(pte_t pte) 686{ 687 return pte_set_flags(pte, _PAGE_SOFT_DIRTY); 688} 689 690static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 691{ 692 return pmd_set_flags(pmd, _PAGE_SOFT_DIRTY); 693} 694 695static inline pud_t pud_mksoft_dirty(pud_t pud) 696{ 697 return pud_set_flags(pud, _PAGE_SOFT_DIRTY); 698} 699 700static inline pte_t pte_clear_soft_dirty(pte_t pte) 701{ 702 return pte_clear_flags(pte, _PAGE_SOFT_DIRTY); 703} 704 705static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 706{ 707 return pmd_clear_flags(pmd, _PAGE_SOFT_DIRTY); 708} 709 710static inline pud_t pud_clear_soft_dirty(pud_t pud) 711{ 712 return pud_clear_flags(pud, _PAGE_SOFT_DIRTY); 713} 714 715#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 716 717/* 718 * Mask out unsupported bits in a present pgprot. Non-present pgprots 719 * can use those bits for other purposes, so leave them be. 720 */ 721static inline pgprotval_t massage_pgprot(pgprot_t pgprot) 722{ 723 pgprotval_t protval = pgprot_val(pgprot); 724 725 if (protval & _PAGE_PRESENT) 726 protval &= __supported_pte_mask; 727 728 return protval; 729} 730 731static inline pgprotval_t check_pgprot(pgprot_t pgprot) 732{ 733 pgprotval_t massaged_val = massage_pgprot(pgprot); 734 735 /* mmdebug.h can not be included here because of dependencies */ 736#ifdef CONFIG_DEBUG_VM 737 WARN_ONCE(pgprot_val(pgprot) != massaged_val, 738 "attempted to set unsupported pgprot: %016llx " 739 "bits: %016llx supported: %016llx\n", 740 (u64)pgprot_val(pgprot), 741 (u64)pgprot_val(pgprot) ^ massaged_val, 742 (u64)__supported_pte_mask); 743#endif 744 745 return massaged_val; 746} 747 748static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot) 749{ 750 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 751 pfn ^= protnone_mask(pgprot_val(pgprot)); 752 pfn &= PTE_PFN_MASK; 753 return __pte(pfn | check_pgprot(pgprot)); 754} 755 756static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) 757{ 758 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 759 pfn ^= protnone_mask(pgprot_val(pgprot)); 760 pfn &= PHYSICAL_PMD_PAGE_MASK; 761 return __pmd(pfn | check_pgprot(pgprot)); 762} 763 764static inline pud_t pfn_pud(unsigned long page_nr, pgprot_t pgprot) 765{ 766 phys_addr_t pfn = (phys_addr_t)page_nr << PAGE_SHIFT; 767 pfn ^= protnone_mask(pgprot_val(pgprot)); 768 pfn &= PHYSICAL_PUD_PAGE_MASK; 769 return __pud(pfn | check_pgprot(pgprot)); 770} 771 772static inline pmd_t pmd_mkinvalid(pmd_t pmd) 773{ 774 return pfn_pmd(pmd_pfn(pmd), 775 __pgprot(pmd_flags(pmd) & ~(_PAGE_PRESENT|_PAGE_PROTNONE))); 776} 777 778static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask); 779 780static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 781{ 782 pteval_t val = pte_val(pte), oldval = val; 783 pte_t pte_result; 784 785 /* 786 * Chop off the NX bit (if present), and add the NX portion of 787 * the newprot (if present): 788 */ 789 val &= _PAGE_CHG_MASK; 790 val |= check_pgprot(newprot) & ~_PAGE_CHG_MASK; 791 val = flip_protnone_guard(oldval, val, PTE_PFN_MASK); 792 793 pte_result = __pte(val); 794 795 /* 796 * To avoid creating Write=0,Dirty=1 PTEs, pte_modify() needs to avoid: 797 * 1. Marking Write=0 PTEs Dirty=1 798 * 2. Marking Dirty=1 PTEs Write=0 799 * 800 * The first case cannot happen because the _PAGE_CHG_MASK will filter 801 * out any Dirty bit passed in newprot. Handle the second case by 802 * going through the mksaveddirty exercise. Only do this if the old 803 * value was Write=1 to avoid doing this on Shadow Stack PTEs. 804 */ 805 if (oldval & _PAGE_RW) 806 pte_result = pte_mksaveddirty(pte_result); 807 else 808 pte_result = pte_clear_saveddirty(pte_result); 809 810 return pte_result; 811} 812 813static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 814{ 815 pmdval_t val = pmd_val(pmd), oldval = val; 816 pmd_t pmd_result; 817 818 val &= (_HPAGE_CHG_MASK & ~_PAGE_DIRTY); 819 val |= check_pgprot(newprot) & ~_HPAGE_CHG_MASK; 820 val = flip_protnone_guard(oldval, val, PHYSICAL_PMD_PAGE_MASK); 821 822 pmd_result = __pmd(val); 823 824 /* 825 * To avoid creating Write=0,Dirty=1 PMDs, pte_modify() needs to avoid: 826 * 1. Marking Write=0 PMDs Dirty=1 827 * 2. Marking Dirty=1 PMDs Write=0 828 * 829 * The first case cannot happen because the _PAGE_CHG_MASK will filter 830 * out any Dirty bit passed in newprot. Handle the second case by 831 * going through the mksaveddirty exercise. Only do this if the old 832 * value was Write=1 to avoid doing this on Shadow Stack PTEs. 833 */ 834 if (oldval & _PAGE_RW) 835 pmd_result = pmd_mksaveddirty(pmd_result); 836 else 837 pmd_result = pmd_clear_saveddirty(pmd_result); 838 839 return pmd_result; 840} 841 842/* 843 * mprotect needs to preserve PAT and encryption bits when updating 844 * vm_page_prot 845 */ 846#define pgprot_modify pgprot_modify 847static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 848{ 849 pgprotval_t preservebits = pgprot_val(oldprot) & _PAGE_CHG_MASK; 850 pgprotval_t addbits = pgprot_val(newprot) & ~_PAGE_CHG_MASK; 851 return __pgprot(preservebits | addbits); 852} 853 854#define pte_pgprot(x) __pgprot(pte_flags(x)) 855#define pmd_pgprot(x) __pgprot(pmd_flags(x)) 856#define pud_pgprot(x) __pgprot(pud_flags(x)) 857#define p4d_pgprot(x) __pgprot(p4d_flags(x)) 858 859#define canon_pgprot(p) __pgprot(massage_pgprot(p)) 860 861static inline int is_new_memtype_allowed(u64 paddr, unsigned long size, 862 enum page_cache_mode pcm, 863 enum page_cache_mode new_pcm) 864{ 865 /* 866 * PAT type is always WB for untracked ranges, so no need to check. 867 */ 868 if (x86_platform.is_untracked_pat_range(paddr, paddr + size)) 869 return 1; 870 871 /* 872 * Certain new memtypes are not allowed with certain 873 * requested memtype: 874 * - request is uncached, return cannot be write-back 875 * - request is write-combine, return cannot be write-back 876 * - request is write-through, return cannot be write-back 877 * - request is write-through, return cannot be write-combine 878 */ 879 if ((pcm == _PAGE_CACHE_MODE_UC_MINUS && 880 new_pcm == _PAGE_CACHE_MODE_WB) || 881 (pcm == _PAGE_CACHE_MODE_WC && 882 new_pcm == _PAGE_CACHE_MODE_WB) || 883 (pcm == _PAGE_CACHE_MODE_WT && 884 new_pcm == _PAGE_CACHE_MODE_WB) || 885 (pcm == _PAGE_CACHE_MODE_WT && 886 new_pcm == _PAGE_CACHE_MODE_WC)) { 887 return 0; 888 } 889 890 return 1; 891} 892 893pmd_t *populate_extra_pmd(unsigned long vaddr); 894pte_t *populate_extra_pte(unsigned long vaddr); 895 896#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION 897pgd_t __pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd); 898 899/* 900 * Take a PGD location (pgdp) and a pgd value that needs to be set there. 901 * Populates the user and returns the resulting PGD that must be set in 902 * the kernel copy of the page tables. 903 */ 904static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd) 905{ 906 if (!static_cpu_has(X86_FEATURE_PTI)) 907 return pgd; 908 return __pti_set_user_pgtbl(pgdp, pgd); 909} 910#else /* CONFIG_MITIGATION_PAGE_TABLE_ISOLATION */ 911static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd) 912{ 913 return pgd; 914} 915#endif /* CONFIG_MITIGATION_PAGE_TABLE_ISOLATION */ 916 917#endif /* __ASSEMBLY__ */ 918 919 920#ifdef CONFIG_X86_32 921# include <asm/pgtable_32.h> 922#else 923# include <asm/pgtable_64.h> 924#endif 925 926#ifndef __ASSEMBLY__ 927#include <linux/mm_types.h> 928#include <linux/mmdebug.h> 929#include <linux/log2.h> 930#include <asm/fixmap.h> 931 932static inline int pte_none(pte_t pte) 933{ 934 return !(pte.pte & ~(_PAGE_KNL_ERRATUM_MASK)); 935} 936 937#define __HAVE_ARCH_PTE_SAME 938static inline int pte_same(pte_t a, pte_t b) 939{ 940 return a.pte == b.pte; 941} 942 943static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 944{ 945 if (__pte_needs_invert(pte_val(pte))) 946 return __pte(pte_val(pte) - (nr << PFN_PTE_SHIFT)); 947 return __pte(pte_val(pte) + (nr << PFN_PTE_SHIFT)); 948} 949#define pte_advance_pfn pte_advance_pfn 950 951static inline int pte_present(pte_t a) 952{ 953 return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE); 954} 955 956#ifdef CONFIG_ARCH_HAS_PTE_DEVMAP 957static inline int pte_devmap(pte_t a) 958{ 959 return (pte_flags(a) & _PAGE_DEVMAP) == _PAGE_DEVMAP; 960} 961#endif 962 963#define pte_accessible pte_accessible 964static inline bool pte_accessible(struct mm_struct *mm, pte_t a) 965{ 966 if (pte_flags(a) & _PAGE_PRESENT) 967 return true; 968 969 if ((pte_flags(a) & _PAGE_PROTNONE) && 970 atomic_read(&mm->tlb_flush_pending)) 971 return true; 972 973 return false; 974} 975 976static inline int pmd_present(pmd_t pmd) 977{ 978 /* 979 * Checking for _PAGE_PSE is needed too because 980 * split_huge_page will temporarily clear the present bit (but 981 * the _PAGE_PSE flag will remain set at all times while the 982 * _PAGE_PRESENT bit is clear). 983 */ 984 return pmd_flags(pmd) & (_PAGE_PRESENT | _PAGE_PROTNONE | _PAGE_PSE); 985} 986 987#ifdef CONFIG_NUMA_BALANCING 988/* 989 * These work without NUMA balancing but the kernel does not care. See the 990 * comment in include/linux/pgtable.h 991 */ 992static inline int pte_protnone(pte_t pte) 993{ 994 return (pte_flags(pte) & (_PAGE_PROTNONE | _PAGE_PRESENT)) 995 == _PAGE_PROTNONE; 996} 997 998static inline int pmd_protnone(pmd_t pmd) 999{ 1000 return (pmd_flags(pmd) & (_PAGE_PROTNONE | _PAGE_PRESENT)) 1001 == _PAGE_PROTNONE; 1002} 1003#endif /* CONFIG_NUMA_BALANCING */ 1004 1005static inline int pmd_none(pmd_t pmd) 1006{ 1007 /* Only check low word on 32-bit platforms, since it might be 1008 out of sync with upper half. */ 1009 unsigned long val = native_pmd_val(pmd); 1010 return (val & ~_PAGE_KNL_ERRATUM_MASK) == 0; 1011} 1012 1013static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1014{ 1015 return (unsigned long)__va(pmd_val(pmd) & pmd_pfn_mask(pmd)); 1016} 1017 1018/* 1019 * Currently stuck as a macro due to indirect forward reference to 1020 * linux/mmzone.h's __section_mem_map_addr() definition: 1021 */ 1022#define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1023 1024/* 1025 * Conversion functions: convert a page and protection to a page entry, 1026 * and a page entry and page directory to the page they refer to. 1027 * 1028 * (Currently stuck as a macro because of indirect forward reference 1029 * to linux/mm.h:page_to_nid()) 1030 */ 1031#define mk_pte(page, pgprot) \ 1032({ \ 1033 pgprot_t __pgprot = pgprot; \ 1034 \ 1035 WARN_ON_ONCE((pgprot_val(__pgprot) & (_PAGE_DIRTY | _PAGE_RW)) == \ 1036 _PAGE_DIRTY); \ 1037 pfn_pte(page_to_pfn(page), __pgprot); \ 1038}) 1039 1040static inline int pmd_bad(pmd_t pmd) 1041{ 1042 return (pmd_flags(pmd) & ~(_PAGE_USER | _PAGE_ACCESSED)) != 1043 (_KERNPG_TABLE & ~_PAGE_ACCESSED); 1044} 1045 1046static inline unsigned long pages_to_mb(unsigned long npg) 1047{ 1048 return npg >> (20 - PAGE_SHIFT); 1049} 1050 1051#if CONFIG_PGTABLE_LEVELS > 2 1052static inline int pud_none(pud_t pud) 1053{ 1054 return (native_pud_val(pud) & ~(_PAGE_KNL_ERRATUM_MASK)) == 0; 1055} 1056 1057static inline int pud_present(pud_t pud) 1058{ 1059 return pud_flags(pud) & _PAGE_PRESENT; 1060} 1061 1062static inline pmd_t *pud_pgtable(pud_t pud) 1063{ 1064 return (pmd_t *)__va(pud_val(pud) & pud_pfn_mask(pud)); 1065} 1066 1067/* 1068 * Currently stuck as a macro due to indirect forward reference to 1069 * linux/mmzone.h's __section_mem_map_addr() definition: 1070 */ 1071#define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1072 1073#define pud_leaf pud_leaf 1074static inline bool pud_leaf(pud_t pud) 1075{ 1076 return (pud_val(pud) & (_PAGE_PSE | _PAGE_PRESENT)) == 1077 (_PAGE_PSE | _PAGE_PRESENT); 1078} 1079 1080static inline int pud_bad(pud_t pud) 1081{ 1082 return (pud_flags(pud) & ~(_KERNPG_TABLE | _PAGE_USER)) != 0; 1083} 1084#endif /* CONFIG_PGTABLE_LEVELS > 2 */ 1085 1086#if CONFIG_PGTABLE_LEVELS > 3 1087static inline int p4d_none(p4d_t p4d) 1088{ 1089 return (native_p4d_val(p4d) & ~(_PAGE_KNL_ERRATUM_MASK)) == 0; 1090} 1091 1092static inline int p4d_present(p4d_t p4d) 1093{ 1094 return p4d_flags(p4d) & _PAGE_PRESENT; 1095} 1096 1097static inline pud_t *p4d_pgtable(p4d_t p4d) 1098{ 1099 return (pud_t *)__va(p4d_val(p4d) & p4d_pfn_mask(p4d)); 1100} 1101 1102/* 1103 * Currently stuck as a macro due to indirect forward reference to 1104 * linux/mmzone.h's __section_mem_map_addr() definition: 1105 */ 1106#define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1107 1108static inline int p4d_bad(p4d_t p4d) 1109{ 1110 unsigned long ignore_flags = _KERNPG_TABLE | _PAGE_USER; 1111 1112 if (IS_ENABLED(CONFIG_MITIGATION_PAGE_TABLE_ISOLATION)) 1113 ignore_flags |= _PAGE_NX; 1114 1115 return (p4d_flags(p4d) & ~ignore_flags) != 0; 1116} 1117#endif /* CONFIG_PGTABLE_LEVELS > 3 */ 1118 1119static inline unsigned long p4d_index(unsigned long address) 1120{ 1121 return (address >> P4D_SHIFT) & (PTRS_PER_P4D - 1); 1122} 1123 1124#if CONFIG_PGTABLE_LEVELS > 4 1125static inline int pgd_present(pgd_t pgd) 1126{ 1127 if (!pgtable_l5_enabled()) 1128 return 1; 1129 return pgd_flags(pgd) & _PAGE_PRESENT; 1130} 1131 1132static inline unsigned long pgd_page_vaddr(pgd_t pgd) 1133{ 1134 return (unsigned long)__va((unsigned long)pgd_val(pgd) & PTE_PFN_MASK); 1135} 1136 1137/* 1138 * Currently stuck as a macro due to indirect forward reference to 1139 * linux/mmzone.h's __section_mem_map_addr() definition: 1140 */ 1141#define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1142 1143/* to find an entry in a page-table-directory. */ 1144static inline p4d_t *p4d_offset(pgd_t *pgd, unsigned long address) 1145{ 1146 if (!pgtable_l5_enabled()) 1147 return (p4d_t *)pgd; 1148 return (p4d_t *)pgd_page_vaddr(*pgd) + p4d_index(address); 1149} 1150 1151static inline int pgd_bad(pgd_t pgd) 1152{ 1153 unsigned long ignore_flags = _PAGE_USER; 1154 1155 if (!pgtable_l5_enabled()) 1156 return 0; 1157 1158 if (IS_ENABLED(CONFIG_MITIGATION_PAGE_TABLE_ISOLATION)) 1159 ignore_flags |= _PAGE_NX; 1160 1161 return (pgd_flags(pgd) & ~ignore_flags) != _KERNPG_TABLE; 1162} 1163 1164static inline int pgd_none(pgd_t pgd) 1165{ 1166 if (!pgtable_l5_enabled()) 1167 return 0; 1168 /* 1169 * There is no need to do a workaround for the KNL stray 1170 * A/D bit erratum here. PGDs only point to page tables 1171 * except on 32-bit non-PAE which is not supported on 1172 * KNL. 1173 */ 1174 return !native_pgd_val(pgd); 1175} 1176#endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1177 1178#endif /* __ASSEMBLY__ */ 1179 1180#define KERNEL_PGD_BOUNDARY pgd_index(PAGE_OFFSET) 1181#define KERNEL_PGD_PTRS (PTRS_PER_PGD - KERNEL_PGD_BOUNDARY) 1182 1183#ifndef __ASSEMBLY__ 1184 1185extern int direct_gbpages; 1186void init_mem_mapping(void); 1187void early_alloc_pgt_buf(void); 1188void __init poking_init(void); 1189unsigned long init_memory_mapping(unsigned long start, 1190 unsigned long end, pgprot_t prot); 1191 1192#ifdef CONFIG_X86_64 1193extern pgd_t trampoline_pgd_entry; 1194#endif 1195 1196/* local pte updates need not use xchg for locking */ 1197static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep) 1198{ 1199 pte_t res = *ptep; 1200 1201 /* Pure native function needs no input for mm, addr */ 1202 native_pte_clear(NULL, 0, ptep); 1203 return res; 1204} 1205 1206static inline pmd_t native_local_pmdp_get_and_clear(pmd_t *pmdp) 1207{ 1208 pmd_t res = *pmdp; 1209 1210 native_pmd_clear(pmdp); 1211 return res; 1212} 1213 1214static inline pud_t native_local_pudp_get_and_clear(pud_t *pudp) 1215{ 1216 pud_t res = *pudp; 1217 1218 native_pud_clear(pudp); 1219 return res; 1220} 1221 1222static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1223 pmd_t *pmdp, pmd_t pmd) 1224{ 1225 page_table_check_pmd_set(mm, pmdp, pmd); 1226 set_pmd(pmdp, pmd); 1227} 1228 1229static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 1230 pud_t *pudp, pud_t pud) 1231{ 1232 page_table_check_pud_set(mm, pudp, pud); 1233 native_set_pud(pudp, pud); 1234} 1235 1236/* 1237 * We only update the dirty/accessed state if we set 1238 * the dirty bit by hand in the kernel, since the hardware 1239 * will do the accessed bit for us, and we don't want to 1240 * race with other CPU's that might be updating the dirty 1241 * bit at the same time. 1242 */ 1243struct vm_area_struct; 1244 1245#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1246extern int ptep_set_access_flags(struct vm_area_struct *vma, 1247 unsigned long address, pte_t *ptep, 1248 pte_t entry, int dirty); 1249 1250#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1251extern int ptep_test_and_clear_young(struct vm_area_struct *vma, 1252 unsigned long addr, pte_t *ptep); 1253 1254#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1255extern int ptep_clear_flush_young(struct vm_area_struct *vma, 1256 unsigned long address, pte_t *ptep); 1257 1258#define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1259static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, 1260 pte_t *ptep) 1261{ 1262 pte_t pte = native_ptep_get_and_clear(ptep); 1263 page_table_check_pte_clear(mm, pte); 1264 return pte; 1265} 1266 1267#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1268static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1269 unsigned long addr, pte_t *ptep, 1270 int full) 1271{ 1272 pte_t pte; 1273 if (full) { 1274 /* 1275 * Full address destruction in progress; paravirt does not 1276 * care about updates and native needs no locking 1277 */ 1278 pte = native_local_ptep_get_and_clear(ptep); 1279 page_table_check_pte_clear(mm, pte); 1280 } else { 1281 pte = ptep_get_and_clear(mm, addr, ptep); 1282 } 1283 return pte; 1284} 1285 1286#define __HAVE_ARCH_PTEP_SET_WRPROTECT 1287static inline void ptep_set_wrprotect(struct mm_struct *mm, 1288 unsigned long addr, pte_t *ptep) 1289{ 1290 /* 1291 * Avoid accidentally creating shadow stack PTEs 1292 * (Write=0,Dirty=1). Use cmpxchg() to prevent races with 1293 * the hardware setting Dirty=1. 1294 */ 1295 pte_t old_pte, new_pte; 1296 1297 old_pte = READ_ONCE(*ptep); 1298 do { 1299 new_pte = pte_wrprotect(old_pte); 1300 } while (!try_cmpxchg((long *)&ptep->pte, (long *)&old_pte, *(long *)&new_pte)); 1301} 1302 1303#define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 1304 1305#define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1306 1307#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1308extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1309 unsigned long address, pmd_t *pmdp, 1310 pmd_t entry, int dirty); 1311extern int pudp_set_access_flags(struct vm_area_struct *vma, 1312 unsigned long address, pud_t *pudp, 1313 pud_t entry, int dirty); 1314 1315#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1316extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1317 unsigned long addr, pmd_t *pmdp); 1318extern int pudp_test_and_clear_young(struct vm_area_struct *vma, 1319 unsigned long addr, pud_t *pudp); 1320 1321#define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1322extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 1323 unsigned long address, pmd_t *pmdp); 1324 1325 1326#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1327static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, unsigned long addr, 1328 pmd_t *pmdp) 1329{ 1330 pmd_t pmd = native_pmdp_get_and_clear(pmdp); 1331 1332 page_table_check_pmd_clear(mm, pmd); 1333 1334 return pmd; 1335} 1336 1337#define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 1338static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 1339 unsigned long addr, pud_t *pudp) 1340{ 1341 pud_t pud = native_pudp_get_and_clear(pudp); 1342 1343 page_table_check_pud_clear(mm, pud); 1344 1345 return pud; 1346} 1347 1348#define __HAVE_ARCH_PMDP_SET_WRPROTECT 1349static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1350 unsigned long addr, pmd_t *pmdp) 1351{ 1352 /* 1353 * Avoid accidentally creating shadow stack PTEs 1354 * (Write=0,Dirty=1). Use cmpxchg() to prevent races with 1355 * the hardware setting Dirty=1. 1356 */ 1357 pmd_t old_pmd, new_pmd; 1358 1359 old_pmd = READ_ONCE(*pmdp); 1360 do { 1361 new_pmd = pmd_wrprotect(old_pmd); 1362 } while (!try_cmpxchg((long *)pmdp, (long *)&old_pmd, *(long *)&new_pmd)); 1363} 1364 1365#ifndef pmdp_establish 1366#define pmdp_establish pmdp_establish 1367static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1368 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1369{ 1370 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 1371 if (IS_ENABLED(CONFIG_SMP)) { 1372 return xchg(pmdp, pmd); 1373 } else { 1374 pmd_t old = *pmdp; 1375 WRITE_ONCE(*pmdp, pmd); 1376 return old; 1377 } 1378} 1379#endif 1380 1381#define __HAVE_ARCH_PMDP_INVALIDATE_AD 1382extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, 1383 unsigned long address, pmd_t *pmdp); 1384 1385/* 1386 * Page table pages are page-aligned. The lower half of the top 1387 * level is used for userspace and the top half for the kernel. 1388 * 1389 * Returns true for parts of the PGD that map userspace and 1390 * false for the parts that map the kernel. 1391 */ 1392static inline bool pgdp_maps_userspace(void *__ptr) 1393{ 1394 unsigned long ptr = (unsigned long)__ptr; 1395 1396 return (((ptr & ~PAGE_MASK) / sizeof(pgd_t)) < PGD_KERNEL_START); 1397} 1398 1399#define pgd_leaf pgd_leaf 1400static inline bool pgd_leaf(pgd_t pgd) { return false; } 1401 1402#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION 1403/* 1404 * All top-level MITIGATION_PAGE_TABLE_ISOLATION page tables are order-1 pages 1405 * (8k-aligned and 8k in size). The kernel one is at the beginning 4k and 1406 * the user one is in the last 4k. To switch between them, you 1407 * just need to flip the 12th bit in their addresses. 1408 */ 1409#define PTI_PGTABLE_SWITCH_BIT PAGE_SHIFT 1410 1411/* 1412 * This generates better code than the inline assembly in 1413 * __set_bit(). 1414 */ 1415static inline void *ptr_set_bit(void *ptr, int bit) 1416{ 1417 unsigned long __ptr = (unsigned long)ptr; 1418 1419 __ptr |= BIT(bit); 1420 return (void *)__ptr; 1421} 1422static inline void *ptr_clear_bit(void *ptr, int bit) 1423{ 1424 unsigned long __ptr = (unsigned long)ptr; 1425 1426 __ptr &= ~BIT(bit); 1427 return (void *)__ptr; 1428} 1429 1430static inline pgd_t *kernel_to_user_pgdp(pgd_t *pgdp) 1431{ 1432 return ptr_set_bit(pgdp, PTI_PGTABLE_SWITCH_BIT); 1433} 1434 1435static inline pgd_t *user_to_kernel_pgdp(pgd_t *pgdp) 1436{ 1437 return ptr_clear_bit(pgdp, PTI_PGTABLE_SWITCH_BIT); 1438} 1439 1440static inline p4d_t *kernel_to_user_p4dp(p4d_t *p4dp) 1441{ 1442 return ptr_set_bit(p4dp, PTI_PGTABLE_SWITCH_BIT); 1443} 1444 1445static inline p4d_t *user_to_kernel_p4dp(p4d_t *p4dp) 1446{ 1447 return ptr_clear_bit(p4dp, PTI_PGTABLE_SWITCH_BIT); 1448} 1449#endif /* CONFIG_MITIGATION_PAGE_TABLE_ISOLATION */ 1450 1451/* 1452 * clone_pgd_range(pgd_t *dst, pgd_t *src, int count); 1453 * 1454 * dst - pointer to pgd range anywhere on a pgd page 1455 * src - "" 1456 * count - the number of pgds to copy. 1457 * 1458 * dst and src can be on the same page, but the range must not overlap, 1459 * and must not cross a page boundary. 1460 */ 1461static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count) 1462{ 1463 memcpy(dst, src, count * sizeof(pgd_t)); 1464#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION 1465 if (!static_cpu_has(X86_FEATURE_PTI)) 1466 return; 1467 /* Clone the user space pgd as well */ 1468 memcpy(kernel_to_user_pgdp(dst), kernel_to_user_pgdp(src), 1469 count * sizeof(pgd_t)); 1470#endif 1471} 1472 1473#define PTE_SHIFT ilog2(PTRS_PER_PTE) 1474static inline int page_level_shift(enum pg_level level) 1475{ 1476 return (PAGE_SHIFT - PTE_SHIFT) + level * PTE_SHIFT; 1477} 1478static inline unsigned long page_level_size(enum pg_level level) 1479{ 1480 return 1UL << page_level_shift(level); 1481} 1482static inline unsigned long page_level_mask(enum pg_level level) 1483{ 1484 return ~(page_level_size(level) - 1); 1485} 1486 1487/* 1488 * The x86 doesn't have any external MMU info: the kernel page 1489 * tables contain all the necessary information. 1490 */ 1491static inline void update_mmu_cache(struct vm_area_struct *vma, 1492 unsigned long addr, pte_t *ptep) 1493{ 1494} 1495static inline void update_mmu_cache_range(struct vm_fault *vmf, 1496 struct vm_area_struct *vma, unsigned long addr, 1497 pte_t *ptep, unsigned int nr) 1498{ 1499} 1500static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1501 unsigned long addr, pmd_t *pmd) 1502{ 1503} 1504static inline void update_mmu_cache_pud(struct vm_area_struct *vma, 1505 unsigned long addr, pud_t *pud) 1506{ 1507} 1508static inline pte_t pte_swp_mkexclusive(pte_t pte) 1509{ 1510 return pte_set_flags(pte, _PAGE_SWP_EXCLUSIVE); 1511} 1512 1513static inline int pte_swp_exclusive(pte_t pte) 1514{ 1515 return pte_flags(pte) & _PAGE_SWP_EXCLUSIVE; 1516} 1517 1518static inline pte_t pte_swp_clear_exclusive(pte_t pte) 1519{ 1520 return pte_clear_flags(pte, _PAGE_SWP_EXCLUSIVE); 1521} 1522 1523#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1524static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1525{ 1526 return pte_set_flags(pte, _PAGE_SWP_SOFT_DIRTY); 1527} 1528 1529static inline int pte_swp_soft_dirty(pte_t pte) 1530{ 1531 return pte_flags(pte) & _PAGE_SWP_SOFT_DIRTY; 1532} 1533 1534static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1535{ 1536 return pte_clear_flags(pte, _PAGE_SWP_SOFT_DIRTY); 1537} 1538 1539#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1540static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1541{ 1542 return pmd_set_flags(pmd, _PAGE_SWP_SOFT_DIRTY); 1543} 1544 1545static inline int pmd_swp_soft_dirty(pmd_t pmd) 1546{ 1547 return pmd_flags(pmd) & _PAGE_SWP_SOFT_DIRTY; 1548} 1549 1550static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1551{ 1552 return pmd_clear_flags(pmd, _PAGE_SWP_SOFT_DIRTY); 1553} 1554#endif 1555#endif 1556 1557#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 1558static inline pte_t pte_swp_mkuffd_wp(pte_t pte) 1559{ 1560 return pte_set_flags(pte, _PAGE_SWP_UFFD_WP); 1561} 1562 1563static inline int pte_swp_uffd_wp(pte_t pte) 1564{ 1565 return pte_flags(pte) & _PAGE_SWP_UFFD_WP; 1566} 1567 1568static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) 1569{ 1570 return pte_clear_flags(pte, _PAGE_SWP_UFFD_WP); 1571} 1572 1573static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd) 1574{ 1575 return pmd_set_flags(pmd, _PAGE_SWP_UFFD_WP); 1576} 1577 1578static inline int pmd_swp_uffd_wp(pmd_t pmd) 1579{ 1580 return pmd_flags(pmd) & _PAGE_SWP_UFFD_WP; 1581} 1582 1583static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd) 1584{ 1585 return pmd_clear_flags(pmd, _PAGE_SWP_UFFD_WP); 1586} 1587#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 1588 1589static inline u16 pte_flags_pkey(unsigned long pte_flags) 1590{ 1591#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 1592 /* ifdef to avoid doing 59-bit shift on 32-bit values */ 1593 return (pte_flags & _PAGE_PKEY_MASK) >> _PAGE_BIT_PKEY_BIT0; 1594#else 1595 return 0; 1596#endif 1597} 1598 1599static inline bool __pkru_allows_pkey(u16 pkey, bool write) 1600{ 1601 u32 pkru = read_pkru(); 1602 1603 if (!__pkru_allows_read(pkru, pkey)) 1604 return false; 1605 if (write && !__pkru_allows_write(pkru, pkey)) 1606 return false; 1607 1608 return true; 1609} 1610 1611/* 1612 * 'pteval' can come from a PTE, PMD or PUD. We only check 1613 * _PAGE_PRESENT, _PAGE_USER, and _PAGE_RW in here which are the 1614 * same value on all 3 types. 1615 */ 1616static inline bool __pte_access_permitted(unsigned long pteval, bool write) 1617{ 1618 unsigned long need_pte_bits = _PAGE_PRESENT|_PAGE_USER; 1619 1620 /* 1621 * Write=0,Dirty=1 PTEs are shadow stack, which the kernel 1622 * shouldn't generally allow access to, but since they 1623 * are already Write=0, the below logic covers both cases. 1624 */ 1625 if (write) 1626 need_pte_bits |= _PAGE_RW; 1627 1628 if ((pteval & need_pte_bits) != need_pte_bits) 1629 return 0; 1630 1631 return __pkru_allows_pkey(pte_flags_pkey(pteval), write); 1632} 1633 1634#define pte_access_permitted pte_access_permitted 1635static inline bool pte_access_permitted(pte_t pte, bool write) 1636{ 1637 return __pte_access_permitted(pte_val(pte), write); 1638} 1639 1640#define pmd_access_permitted pmd_access_permitted 1641static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1642{ 1643 return __pte_access_permitted(pmd_val(pmd), write); 1644} 1645 1646#define pud_access_permitted pud_access_permitted 1647static inline bool pud_access_permitted(pud_t pud, bool write) 1648{ 1649 return __pte_access_permitted(pud_val(pud), write); 1650} 1651 1652#define __HAVE_ARCH_PFN_MODIFY_ALLOWED 1 1653extern bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot); 1654 1655static inline bool arch_has_pfn_modify_check(void) 1656{ 1657 return boot_cpu_has_bug(X86_BUG_L1TF); 1658} 1659 1660#define arch_check_zapped_pte arch_check_zapped_pte 1661void arch_check_zapped_pte(struct vm_area_struct *vma, pte_t pte); 1662 1663#define arch_check_zapped_pmd arch_check_zapped_pmd 1664void arch_check_zapped_pmd(struct vm_area_struct *vma, pmd_t pmd); 1665 1666#ifdef CONFIG_XEN_PV 1667#define arch_has_hw_nonleaf_pmd_young arch_has_hw_nonleaf_pmd_young 1668static inline bool arch_has_hw_nonleaf_pmd_young(void) 1669{ 1670 return !cpu_feature_enabled(X86_FEATURE_XENPV); 1671} 1672#endif 1673 1674#ifdef CONFIG_PAGE_TABLE_CHECK 1675static inline bool pte_user_accessible_page(pte_t pte) 1676{ 1677 return (pte_val(pte) & _PAGE_PRESENT) && (pte_val(pte) & _PAGE_USER); 1678} 1679 1680static inline bool pmd_user_accessible_page(pmd_t pmd) 1681{ 1682 return pmd_leaf(pmd) && (pmd_val(pmd) & _PAGE_PRESENT) && (pmd_val(pmd) & _PAGE_USER); 1683} 1684 1685static inline bool pud_user_accessible_page(pud_t pud) 1686{ 1687 return pud_leaf(pud) && (pud_val(pud) & _PAGE_PRESENT) && (pud_val(pud) & _PAGE_USER); 1688} 1689#endif 1690 1691#ifdef CONFIG_X86_SGX 1692int arch_memory_failure(unsigned long pfn, int flags); 1693#define arch_memory_failure arch_memory_failure 1694 1695bool arch_is_platform_page(u64 paddr); 1696#define arch_is_platform_page arch_is_platform_page 1697#endif 1698 1699#endif /* __ASSEMBLY__ */ 1700 1701#endif /* _ASM_X86_PGTABLE_H */ 1702