1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_X86_MSR_INDEX_H 3#define _ASM_X86_MSR_INDEX_H 4 5#include <linux/bits.h> 6 7/* CPU model specific register (MSR) numbers. */ 8 9/* x86-64 specific MSRs */ 10#define MSR_EFER 0xc0000080 /* extended feature register */ 11#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 12#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 13#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 14#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 15#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 16#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 17#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 18#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 19 20/* EFER bits: */ 21#define _EFER_SCE 0 /* SYSCALL/SYSRET */ 22#define _EFER_LME 8 /* Long mode enable */ 23#define _EFER_LMA 10 /* Long mode active (read-only) */ 24#define _EFER_NX 11 /* No execute enable */ 25#define _EFER_SVME 12 /* Enable virtualization */ 26#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 27#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 28#define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ 29 30#define EFER_SCE (1<<_EFER_SCE) 31#define EFER_LME (1<<_EFER_LME) 32#define EFER_LMA (1<<_EFER_LMA) 33#define EFER_NX (1<<_EFER_NX) 34#define EFER_SVME (1<<_EFER_SVME) 35#define EFER_LMSLE (1<<_EFER_LMSLE) 36#define EFER_FFXSR (1<<_EFER_FFXSR) 37#define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) 38 39/* FRED MSRs */ 40#define MSR_IA32_FRED_RSP0 0x1cc /* Level 0 stack pointer */ 41#define MSR_IA32_FRED_RSP1 0x1cd /* Level 1 stack pointer */ 42#define MSR_IA32_FRED_RSP2 0x1ce /* Level 2 stack pointer */ 43#define MSR_IA32_FRED_RSP3 0x1cf /* Level 3 stack pointer */ 44#define MSR_IA32_FRED_STKLVLS 0x1d0 /* Exception stack levels */ 45#define MSR_IA32_FRED_SSP0 MSR_IA32_PL0_SSP /* Level 0 shadow stack pointer */ 46#define MSR_IA32_FRED_SSP1 0x1d1 /* Level 1 shadow stack pointer */ 47#define MSR_IA32_FRED_SSP2 0x1d2 /* Level 2 shadow stack pointer */ 48#define MSR_IA32_FRED_SSP3 0x1d3 /* Level 3 shadow stack pointer */ 49#define MSR_IA32_FRED_CONFIG 0x1d4 /* Entrypoint and interrupt stack level */ 50 51/* Intel MSRs. Some also available on other CPUs */ 52#define MSR_TEST_CTRL 0x00000033 53#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 54#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 55 56#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 57#define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 58#define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 59#define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 60#define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 61#define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 62#define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ 63#define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) 64#define SPEC_CTRL_BHI_DIS_S_SHIFT 10 /* Disable Branch History Injection behavior */ 65#define SPEC_CTRL_BHI_DIS_S BIT(SPEC_CTRL_BHI_DIS_S_SHIFT) 66 67/* A mask for bits which the kernel toggles when controlling mitigations */ 68#define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \ 69 | SPEC_CTRL_RRSBA_DIS_S \ 70 | SPEC_CTRL_BHI_DIS_S) 71 72#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 73#define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 74#define PRED_CMD_SBPB BIT(7) /* Selective Branch Prediction Barrier */ 75 76#define MSR_PPIN_CTL 0x0000004e 77#define MSR_PPIN 0x0000004f 78 79#define MSR_IA32_PERFCTR0 0x000000c1 80#define MSR_IA32_PERFCTR1 0x000000c2 81#define MSR_FSB_FREQ 0x000000cd 82#define MSR_PLATFORM_INFO 0x000000ce 83#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 84#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 85 86#define MSR_IA32_UMWAIT_CONTROL 0xe1 87#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 88#define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 89/* 90 * The time field is bit[31:2], but representing a 32bit value with 91 * bit[1:0] zero. 92 */ 93#define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 94 95/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 96#define MSR_IA32_CORE_CAPS 0x000000cf 97#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2 98#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT) 99#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 100#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 101 102#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 103#define NHM_C3_AUTO_DEMOTE (1UL << 25) 104#define NHM_C1_AUTO_DEMOTE (1UL << 26) 105#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 106#define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 107#define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 108 109#define MSR_MTRRcap 0x000000fe 110 111#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 112#define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 113#define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 114#define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ 115#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 116#define ARCH_CAP_SSB_NO BIT(4) /* 117 * Not susceptible to Speculative Store Bypass 118 * attack, so no Speculative Store Bypass 119 * control required. 120 */ 121#define ARCH_CAP_MDS_NO BIT(5) /* 122 * Not susceptible to 123 * Microarchitectural Data 124 * Sampling (MDS) vulnerabilities. 125 */ 126#define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 127 * The processor is not susceptible to a 128 * machine check error due to modifying the 129 * code page size along with either the 130 * physical address or cache type 131 * without TLB invalidation. 132 */ 133#define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 134#define ARCH_CAP_TAA_NO BIT(8) /* 135 * Not susceptible to 136 * TSX Async Abort (TAA) vulnerabilities. 137 */ 138#define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* 139 * Not susceptible to SBDR and SSDP 140 * variants of Processor MMIO stale data 141 * vulnerabilities. 142 */ 143#define ARCH_CAP_FBSDP_NO BIT(14) /* 144 * Not susceptible to FBSDP variant of 145 * Processor MMIO stale data 146 * vulnerabilities. 147 */ 148#define ARCH_CAP_PSDP_NO BIT(15) /* 149 * Not susceptible to PSDP variant of 150 * Processor MMIO stale data 151 * vulnerabilities. 152 */ 153#define ARCH_CAP_FB_CLEAR BIT(17) /* 154 * VERW clears CPU fill buffer 155 * even on MDS_NO CPUs. 156 */ 157#define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* 158 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] 159 * bit available to control VERW 160 * behavior. 161 */ 162#define ARCH_CAP_RRSBA BIT(19) /* 163 * Indicates RET may use predictors 164 * other than the RSB. With eIBRS 165 * enabled predictions in kernel mode 166 * are restricted to targets in 167 * kernel. 168 */ 169#define ARCH_CAP_BHI_NO BIT(20) /* 170 * CPU is not affected by Branch 171 * History Injection. 172 */ 173#define ARCH_CAP_XAPIC_DISABLE BIT(21) /* 174 * IA32_XAPIC_DISABLE_STATUS MSR 175 * supported 176 */ 177#define ARCH_CAP_PBRSB_NO BIT(24) /* 178 * Not susceptible to Post-Barrier 179 * Return Stack Buffer Predictions. 180 */ 181#define ARCH_CAP_GDS_CTRL BIT(25) /* 182 * CPU is vulnerable to Gather 183 * Data Sampling (GDS) and 184 * has controls for mitigation. 185 */ 186#define ARCH_CAP_GDS_NO BIT(26) /* 187 * CPU is not vulnerable to Gather 188 * Data Sampling (GDS). 189 */ 190#define ARCH_CAP_RFDS_NO BIT(27) /* 191 * Not susceptible to Register 192 * File Data Sampling. 193 */ 194#define ARCH_CAP_RFDS_CLEAR BIT(28) /* 195 * VERW clears CPU Register 196 * File. 197 */ 198 199#define MSR_IA32_FLUSH_CMD 0x0000010b 200#define L1D_FLUSH BIT(0) /* 201 * Writeback and invalidate the 202 * L1 data cache. 203 */ 204 205#define MSR_IA32_BBL_CR_CTL 0x00000119 206#define MSR_IA32_BBL_CR_CTL3 0x0000011e 207 208#define MSR_IA32_TSX_CTRL 0x00000122 209#define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 210#define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 211 212#define MSR_IA32_MCU_OPT_CTRL 0x00000123 213#define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ 214#define RTM_ALLOW BIT(1) /* TSX development mode */ 215#define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ 216#define GDS_MITG_DIS BIT(4) /* Disable GDS mitigation */ 217#define GDS_MITG_LOCKED BIT(5) /* GDS mitigation locked */ 218 219#define MSR_IA32_SYSENTER_CS 0x00000174 220#define MSR_IA32_SYSENTER_ESP 0x00000175 221#define MSR_IA32_SYSENTER_EIP 0x00000176 222 223#define MSR_IA32_MCG_CAP 0x00000179 224#define MSR_IA32_MCG_STATUS 0x0000017a 225#define MSR_IA32_MCG_CTL 0x0000017b 226#define MSR_ERROR_CONTROL 0x0000017f 227#define MSR_IA32_MCG_EXT_CTL 0x000004d0 228 229#define MSR_OFFCORE_RSP_0 0x000001a6 230#define MSR_OFFCORE_RSP_1 0x000001a7 231#define MSR_TURBO_RATIO_LIMIT 0x000001ad 232#define MSR_TURBO_RATIO_LIMIT1 0x000001ae 233#define MSR_TURBO_RATIO_LIMIT2 0x000001af 234 235#define MSR_SNOOP_RSP_0 0x00001328 236#define MSR_SNOOP_RSP_1 0x00001329 237 238#define MSR_LBR_SELECT 0x000001c8 239#define MSR_LBR_TOS 0x000001c9 240 241#define MSR_IA32_POWER_CTL 0x000001fc 242#define MSR_IA32_POWER_CTL_BIT_EE 19 243 244/* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ 245#define MSR_INTEGRITY_CAPS 0x000002d9 246#define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2 247#define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT) 248#define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 249#define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) 250#define MSR_INTEGRITY_CAPS_SAF_GEN_MASK GENMASK_ULL(10, 9) 251 252#define MSR_LBR_NHM_FROM 0x00000680 253#define MSR_LBR_NHM_TO 0x000006c0 254#define MSR_LBR_CORE_FROM 0x00000040 255#define MSR_LBR_CORE_TO 0x00000060 256 257#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 258#define LBR_INFO_MISPRED BIT_ULL(63) 259#define LBR_INFO_IN_TX BIT_ULL(62) 260#define LBR_INFO_ABORT BIT_ULL(61) 261#define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 262#define LBR_INFO_CYCLES 0xffff 263#define LBR_INFO_BR_TYPE_OFFSET 56 264#define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 265#define LBR_INFO_BR_CNTR_OFFSET 32 266#define LBR_INFO_BR_CNTR_NUM 4 267#define LBR_INFO_BR_CNTR_BITS 2 268#define LBR_INFO_BR_CNTR_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_BITS - 1, 0) 269#define LBR_INFO_BR_CNTR_FULL_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_NUM * LBR_INFO_BR_CNTR_BITS - 1, 0) 270 271#define MSR_ARCH_LBR_CTL 0x000014ce 272#define ARCH_LBR_CTL_LBREN BIT(0) 273#define ARCH_LBR_CTL_CPL_OFFSET 1 274#define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 275#define ARCH_LBR_CTL_STACK_OFFSET 3 276#define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 277#define ARCH_LBR_CTL_FILTER_OFFSET 16 278#define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 279#define MSR_ARCH_LBR_DEPTH 0x000014cf 280#define MSR_ARCH_LBR_FROM_0 0x00001500 281#define MSR_ARCH_LBR_TO_0 0x00001600 282#define MSR_ARCH_LBR_INFO_0 0x00001200 283 284#define MSR_IA32_PEBS_ENABLE 0x000003f1 285#define MSR_PEBS_DATA_CFG 0x000003f2 286#define MSR_IA32_DS_AREA 0x00000600 287#define MSR_IA32_PERF_CAPABILITIES 0x00000345 288#define PERF_CAP_METRICS_IDX 15 289#define PERF_CAP_PT_IDX 16 290 291#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 292#define PERF_CAP_PEBS_TRAP BIT_ULL(6) 293#define PERF_CAP_ARCH_REG BIT_ULL(7) 294#define PERF_CAP_PEBS_FORMAT 0xf00 295#define PERF_CAP_PEBS_BASELINE BIT_ULL(14) 296#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ 297 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) 298 299#define MSR_IA32_RTIT_CTL 0x00000570 300#define RTIT_CTL_TRACEEN BIT(0) 301#define RTIT_CTL_CYCLEACC BIT(1) 302#define RTIT_CTL_OS BIT(2) 303#define RTIT_CTL_USR BIT(3) 304#define RTIT_CTL_PWR_EVT_EN BIT(4) 305#define RTIT_CTL_FUP_ON_PTW BIT(5) 306#define RTIT_CTL_FABRIC_EN BIT(6) 307#define RTIT_CTL_CR3EN BIT(7) 308#define RTIT_CTL_TOPA BIT(8) 309#define RTIT_CTL_MTC_EN BIT(9) 310#define RTIT_CTL_TSC_EN BIT(10) 311#define RTIT_CTL_DISRETC BIT(11) 312#define RTIT_CTL_PTW_EN BIT(12) 313#define RTIT_CTL_BRANCH_EN BIT(13) 314#define RTIT_CTL_EVENT_EN BIT(31) 315#define RTIT_CTL_NOTNT BIT_ULL(55) 316#define RTIT_CTL_MTC_RANGE_OFFSET 14 317#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 318#define RTIT_CTL_CYC_THRESH_OFFSET 19 319#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 320#define RTIT_CTL_PSB_FREQ_OFFSET 24 321#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 322#define RTIT_CTL_ADDR0_OFFSET 32 323#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 324#define RTIT_CTL_ADDR1_OFFSET 36 325#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 326#define RTIT_CTL_ADDR2_OFFSET 40 327#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 328#define RTIT_CTL_ADDR3_OFFSET 44 329#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 330#define MSR_IA32_RTIT_STATUS 0x00000571 331#define RTIT_STATUS_FILTEREN BIT(0) 332#define RTIT_STATUS_CONTEXTEN BIT(1) 333#define RTIT_STATUS_TRIGGEREN BIT(2) 334#define RTIT_STATUS_BUFFOVF BIT(3) 335#define RTIT_STATUS_ERROR BIT(4) 336#define RTIT_STATUS_STOPPED BIT(5) 337#define RTIT_STATUS_BYTECNT_OFFSET 32 338#define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 339#define MSR_IA32_RTIT_ADDR0_A 0x00000580 340#define MSR_IA32_RTIT_ADDR0_B 0x00000581 341#define MSR_IA32_RTIT_ADDR1_A 0x00000582 342#define MSR_IA32_RTIT_ADDR1_B 0x00000583 343#define MSR_IA32_RTIT_ADDR2_A 0x00000584 344#define MSR_IA32_RTIT_ADDR2_B 0x00000585 345#define MSR_IA32_RTIT_ADDR3_A 0x00000586 346#define MSR_IA32_RTIT_ADDR3_B 0x00000587 347#define MSR_IA32_RTIT_CR3_MATCH 0x00000572 348#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 349#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 350 351#define MSR_MTRRfix64K_00000 0x00000250 352#define MSR_MTRRfix16K_80000 0x00000258 353#define MSR_MTRRfix16K_A0000 0x00000259 354#define MSR_MTRRfix4K_C0000 0x00000268 355#define MSR_MTRRfix4K_C8000 0x00000269 356#define MSR_MTRRfix4K_D0000 0x0000026a 357#define MSR_MTRRfix4K_D8000 0x0000026b 358#define MSR_MTRRfix4K_E0000 0x0000026c 359#define MSR_MTRRfix4K_E8000 0x0000026d 360#define MSR_MTRRfix4K_F0000 0x0000026e 361#define MSR_MTRRfix4K_F8000 0x0000026f 362#define MSR_MTRRdefType 0x000002ff 363 364#define MSR_IA32_CR_PAT 0x00000277 365 366#define MSR_IA32_DEBUGCTLMSR 0x000001d9 367#define MSR_IA32_LASTBRANCHFROMIP 0x000001db 368#define MSR_IA32_LASTBRANCHTOIP 0x000001dc 369#define MSR_IA32_LASTINTFROMIP 0x000001dd 370#define MSR_IA32_LASTINTTOIP 0x000001de 371 372#define MSR_IA32_PASID 0x00000d93 373#define MSR_IA32_PASID_VALID BIT_ULL(31) 374 375/* DEBUGCTLMSR bits (others vary by model): */ 376#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 377#define DEBUGCTLMSR_BTF_SHIFT 1 378#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 379#define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) 380#define DEBUGCTLMSR_TR (1UL << 6) 381#define DEBUGCTLMSR_BTS (1UL << 7) 382#define DEBUGCTLMSR_BTINT (1UL << 8) 383#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 384#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 385#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 386#define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 387#define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 388#define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 389 390#define MSR_PEBS_FRONTEND 0x000003f7 391 392#define MSR_IA32_MC0_CTL 0x00000400 393#define MSR_IA32_MC0_STATUS 0x00000401 394#define MSR_IA32_MC0_ADDR 0x00000402 395#define MSR_IA32_MC0_MISC 0x00000403 396 397/* C-state Residency Counters */ 398#define MSR_PKG_C3_RESIDENCY 0x000003f8 399#define MSR_PKG_C6_RESIDENCY 0x000003f9 400#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 401#define MSR_PKG_C7_RESIDENCY 0x000003fa 402#define MSR_CORE_C3_RESIDENCY 0x000003fc 403#define MSR_CORE_C6_RESIDENCY 0x000003fd 404#define MSR_CORE_C7_RESIDENCY 0x000003fe 405#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 406#define MSR_PKG_C2_RESIDENCY 0x0000060d 407#define MSR_PKG_C8_RESIDENCY 0x00000630 408#define MSR_PKG_C9_RESIDENCY 0x00000631 409#define MSR_PKG_C10_RESIDENCY 0x00000632 410 411/* Interrupt Response Limit */ 412#define MSR_PKGC3_IRTL 0x0000060a 413#define MSR_PKGC6_IRTL 0x0000060b 414#define MSR_PKGC7_IRTL 0x0000060c 415#define MSR_PKGC8_IRTL 0x00000633 416#define MSR_PKGC9_IRTL 0x00000634 417#define MSR_PKGC10_IRTL 0x00000635 418 419/* Run Time Average Power Limiting (RAPL) Interface */ 420 421#define MSR_VR_CURRENT_CONFIG 0x00000601 422#define MSR_RAPL_POWER_UNIT 0x00000606 423 424#define MSR_PKG_POWER_LIMIT 0x00000610 425#define MSR_PKG_ENERGY_STATUS 0x00000611 426#define MSR_PKG_PERF_STATUS 0x00000613 427#define MSR_PKG_POWER_INFO 0x00000614 428 429#define MSR_DRAM_POWER_LIMIT 0x00000618 430#define MSR_DRAM_ENERGY_STATUS 0x00000619 431#define MSR_DRAM_PERF_STATUS 0x0000061b 432#define MSR_DRAM_POWER_INFO 0x0000061c 433 434#define MSR_PP0_POWER_LIMIT 0x00000638 435#define MSR_PP0_ENERGY_STATUS 0x00000639 436#define MSR_PP0_POLICY 0x0000063a 437#define MSR_PP0_PERF_STATUS 0x0000063b 438 439#define MSR_PP1_POWER_LIMIT 0x00000640 440#define MSR_PP1_ENERGY_STATUS 0x00000641 441#define MSR_PP1_POLICY 0x00000642 442 443#define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 444#define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a 445#define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 446 447/* Config TDP MSRs */ 448#define MSR_CONFIG_TDP_NOMINAL 0x00000648 449#define MSR_CONFIG_TDP_LEVEL_1 0x00000649 450#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 451#define MSR_CONFIG_TDP_CONTROL 0x0000064B 452#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 453 454#define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 455#define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650 456 457#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 458#define MSR_PKG_ANY_CORE_C0_RES 0x00000659 459#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 460#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 461 462#define MSR_CORE_C1_RES 0x00000660 463#define MSR_MODULE_C6_RES_MS 0x00000664 464 465#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 466#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 467 468#define MSR_ATOM_CORE_RATIOS 0x0000066a 469#define MSR_ATOM_CORE_VIDS 0x0000066b 470#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 471#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 472 473#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 474#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 475#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 476 477/* Control-flow Enforcement Technology MSRs */ 478#define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ 479#define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ 480#define CET_SHSTK_EN BIT_ULL(0) 481#define CET_WRSS_EN BIT_ULL(1) 482#define CET_ENDBR_EN BIT_ULL(2) 483#define CET_LEG_IW_EN BIT_ULL(3) 484#define CET_NO_TRACK_EN BIT_ULL(4) 485#define CET_SUPPRESS_DISABLE BIT_ULL(5) 486#define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) 487#define CET_SUPPRESS BIT_ULL(10) 488#define CET_WAIT_ENDBR BIT_ULL(11) 489 490#define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ 491#define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ 492#define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ 493#define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ 494#define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ 495 496/* Hardware P state interface */ 497#define MSR_PPERF 0x0000064e 498#define MSR_PERF_LIMIT_REASONS 0x0000064f 499#define MSR_PM_ENABLE 0x00000770 500#define MSR_HWP_CAPABILITIES 0x00000771 501#define MSR_HWP_REQUEST_PKG 0x00000772 502#define MSR_HWP_INTERRUPT 0x00000773 503#define MSR_HWP_REQUEST 0x00000774 504#define MSR_HWP_STATUS 0x00000777 505 506/* CPUID.6.EAX */ 507#define HWP_BASE_BIT (1<<7) 508#define HWP_NOTIFICATIONS_BIT (1<<8) 509#define HWP_ACTIVITY_WINDOW_BIT (1<<9) 510#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 511#define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 512 513/* IA32_HWP_CAPABILITIES */ 514#define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 515#define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 516#define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 517#define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 518 519/* IA32_HWP_REQUEST */ 520#define HWP_MIN_PERF(x) (x & 0xff) 521#define HWP_MAX_PERF(x) ((x & 0xff) << 8) 522#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 523#define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 524#define HWP_EPP_PERFORMANCE 0x00 525#define HWP_EPP_BALANCE_PERFORMANCE 0x80 526#define HWP_EPP_BALANCE_POWERSAVE 0xC0 527#define HWP_EPP_POWERSAVE 0xFF 528#define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 529#define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 530 531/* IA32_HWP_STATUS */ 532#define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 533#define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 534 535/* IA32_HWP_INTERRUPT */ 536#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 537#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 538 539#define MSR_AMD64_MC0_MASK 0xc0010044 540 541#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 542#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 543#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 544#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 545 546#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 547 548/* These are consecutive and not in the normal 4er MCE bank block */ 549#define MSR_IA32_MC0_CTL2 0x00000280 550#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 551 552#define MSR_P6_PERFCTR0 0x000000c1 553#define MSR_P6_PERFCTR1 0x000000c2 554#define MSR_P6_EVNTSEL0 0x00000186 555#define MSR_P6_EVNTSEL1 0x00000187 556 557#define MSR_KNC_PERFCTR0 0x00000020 558#define MSR_KNC_PERFCTR1 0x00000021 559#define MSR_KNC_EVNTSEL0 0x00000028 560#define MSR_KNC_EVNTSEL1 0x00000029 561 562/* Alternative perfctr range with full access. */ 563#define MSR_IA32_PMC0 0x000004c1 564 565/* Auto-reload via MSR instead of DS area */ 566#define MSR_RELOAD_PMC0 0x000014c1 567#define MSR_RELOAD_FIXED_CTR0 0x00001309 568 569/* KeyID partitioning between MKTME and TDX */ 570#define MSR_IA32_MKTME_KEYID_PARTITIONING 0x00000087 571 572/* 573 * AMD64 MSRs. Not complete. See the architecture manual for a more 574 * complete list. 575 */ 576#define MSR_AMD64_PATCH_LEVEL 0x0000008b 577#define MSR_AMD64_TSC_RATIO 0xc0000104 578#define MSR_AMD64_NB_CFG 0xc001001f 579#define MSR_AMD64_PATCH_LOADER 0xc0010020 580#define MSR_AMD_PERF_CTL 0xc0010062 581#define MSR_AMD_PERF_STATUS 0xc0010063 582#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 583#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 584#define MSR_AMD64_OSVW_STATUS 0xc0010141 585#define MSR_AMD_PPIN_CTL 0xc00102f0 586#define MSR_AMD_PPIN 0xc00102f1 587#define MSR_AMD64_CPUID_FN_1 0xc0011004 588#define MSR_AMD64_LS_CFG 0xc0011020 589#define MSR_AMD64_DC_CFG 0xc0011022 590#define MSR_AMD64_TW_CFG 0xc0011023 591 592#define MSR_AMD64_DE_CFG 0xc0011029 593#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 594#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) 595#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9 596 597#define MSR_AMD64_BU_CFG2 0xc001102a 598#define MSR_AMD64_IBSFETCHCTL 0xc0011030 599#define MSR_AMD64_IBSFETCHLINAD 0xc0011031 600#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 601#define MSR_AMD64_IBSFETCH_REG_COUNT 3 602#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 603#define MSR_AMD64_IBSOPCTL 0xc0011033 604#define MSR_AMD64_IBSOPRIP 0xc0011034 605#define MSR_AMD64_IBSOPDATA 0xc0011035 606#define MSR_AMD64_IBSOPDATA2 0xc0011036 607#define MSR_AMD64_IBSOPDATA3 0xc0011037 608#define MSR_AMD64_IBSDCLINAD 0xc0011038 609#define MSR_AMD64_IBSDCPHYSAD 0xc0011039 610#define MSR_AMD64_IBSOP_REG_COUNT 7 611#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 612#define MSR_AMD64_IBSCTL 0xc001103a 613#define MSR_AMD64_IBSBRTARGET 0xc001103b 614#define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 615#define MSR_AMD64_IBSOPDATA4 0xc001103d 616#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 617#define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b 618#define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 619#define MSR_AMD64_SEV_ES_GHCB 0xc0010130 620#define MSR_AMD64_SEV 0xc0010131 621#define MSR_AMD64_SEV_ENABLED_BIT 0 622#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 623#define MSR_AMD64_SEV_ES_ENABLED_BIT 1 624#define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 625#define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 626#define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) 627#define MSR_AMD64_SNP_VTOM_BIT 3 628#define MSR_AMD64_SNP_VTOM BIT_ULL(MSR_AMD64_SNP_VTOM_BIT) 629#define MSR_AMD64_SNP_REFLECT_VC_BIT 4 630#define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(MSR_AMD64_SNP_REFLECT_VC_BIT) 631#define MSR_AMD64_SNP_RESTRICTED_INJ_BIT 5 632#define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(MSR_AMD64_SNP_RESTRICTED_INJ_BIT) 633#define MSR_AMD64_SNP_ALT_INJ_BIT 6 634#define MSR_AMD64_SNP_ALT_INJ BIT_ULL(MSR_AMD64_SNP_ALT_INJ_BIT) 635#define MSR_AMD64_SNP_DEBUG_SWAP_BIT 7 636#define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(MSR_AMD64_SNP_DEBUG_SWAP_BIT) 637#define MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT 8 638#define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT) 639#define MSR_AMD64_SNP_BTB_ISOLATION_BIT 9 640#define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(MSR_AMD64_SNP_BTB_ISOLATION_BIT) 641#define MSR_AMD64_SNP_VMPL_SSS_BIT 10 642#define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(MSR_AMD64_SNP_VMPL_SSS_BIT) 643#define MSR_AMD64_SNP_SECURE_TSC_BIT 11 644#define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(MSR_AMD64_SNP_SECURE_TSC_BIT) 645#define MSR_AMD64_SNP_VMGEXIT_PARAM_BIT 12 646#define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(MSR_AMD64_SNP_VMGEXIT_PARAM_BIT) 647#define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13) 648#define MSR_AMD64_SNP_IBS_VIRT_BIT 14 649#define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(MSR_AMD64_SNP_IBS_VIRT_BIT) 650#define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15) 651#define MSR_AMD64_SNP_VMSA_REG_PROT_BIT 16 652#define MSR_AMD64_SNP_VMSA_REG_PROT BIT_ULL(MSR_AMD64_SNP_VMSA_REG_PROT_BIT) 653#define MSR_AMD64_SNP_SMT_PROT_BIT 17 654#define MSR_AMD64_SNP_SMT_PROT BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT) 655#define MSR_AMD64_SNP_RESV_BIT 18 656#define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, MSR_AMD64_SNP_RESV_BIT) 657 658#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 659 660#define MSR_AMD64_RMP_BASE 0xc0010132 661#define MSR_AMD64_RMP_END 0xc0010133 662 663/* AMD Collaborative Processor Performance Control MSRs */ 664#define MSR_AMD_CPPC_CAP1 0xc00102b0 665#define MSR_AMD_CPPC_ENABLE 0xc00102b1 666#define MSR_AMD_CPPC_CAP2 0xc00102b2 667#define MSR_AMD_CPPC_REQ 0xc00102b3 668#define MSR_AMD_CPPC_STATUS 0xc00102b4 669 670#define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) 671#define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) 672#define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) 673#define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) 674 675#define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) 676#define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) 677#define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) 678#define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) 679 680/* AMD Performance Counter Global Status and Control MSRs */ 681#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 682#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 683#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 684 685/* AMD Last Branch Record MSRs */ 686#define MSR_AMD64_LBR_SELECT 0xc000010e 687 688/* Zen4 */ 689#define MSR_ZEN4_BP_CFG 0xc001102e 690#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5 691 692/* Fam 19h MSRs */ 693#define MSR_F19H_UMC_PERF_CTL 0xc0010800 694#define MSR_F19H_UMC_PERF_CTR 0xc0010801 695 696/* Zen 2 */ 697#define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 698#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) 699 700/* Fam 17h MSRs */ 701#define MSR_F17H_IRPERF 0xc00000e9 702 703/* Fam 16h MSRs */ 704#define MSR_F16H_L2I_PERF_CTL 0xc0010230 705#define MSR_F16H_L2I_PERF_CTR 0xc0010231 706#define MSR_F16H_DR1_ADDR_MASK 0xc0011019 707#define MSR_F16H_DR2_ADDR_MASK 0xc001101a 708#define MSR_F16H_DR3_ADDR_MASK 0xc001101b 709#define MSR_F16H_DR0_ADDR_MASK 0xc0011027 710 711/* Fam 15h MSRs */ 712#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 713#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 714#define MSR_F15H_PERF_CTL 0xc0010200 715#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 716#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 717#define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 718#define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 719#define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 720#define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 721 722#define MSR_F15H_PERF_CTR 0xc0010201 723#define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 724#define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 725#define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 726#define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 727#define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 728#define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 729 730#define MSR_F15H_NB_PERF_CTL 0xc0010240 731#define MSR_F15H_NB_PERF_CTR 0xc0010241 732#define MSR_F15H_PTSC 0xc0010280 733#define MSR_F15H_IC_CFG 0xc0011021 734#define MSR_F15H_EX_CFG 0xc001102c 735 736/* Fam 10h MSRs */ 737#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 738#define FAM10H_MMIO_CONF_ENABLE (1<<0) 739#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 740#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 741#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 742#define FAM10H_MMIO_CONF_BASE_SHIFT 20 743#define MSR_FAM10H_NODE_ID 0xc001100c 744 745/* K8 MSRs */ 746#define MSR_K8_TOP_MEM1 0xc001001a 747#define MSR_K8_TOP_MEM2 0xc001001d 748#define MSR_AMD64_SYSCFG 0xc0010010 749#define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 750#define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) 751#define MSR_AMD64_SYSCFG_SNP_EN_BIT 24 752#define MSR_AMD64_SYSCFG_SNP_EN BIT_ULL(MSR_AMD64_SYSCFG_SNP_EN_BIT) 753#define MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT 25 754#define MSR_AMD64_SYSCFG_SNP_VMPL_EN BIT_ULL(MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT) 755#define MSR_AMD64_SYSCFG_MFDM_BIT 19 756#define MSR_AMD64_SYSCFG_MFDM BIT_ULL(MSR_AMD64_SYSCFG_MFDM_BIT) 757 758#define MSR_K8_INT_PENDING_MSG 0xc0010055 759/* C1E active bits in int pending message */ 760#define K8_INTP_C1E_ACTIVE_MASK 0x18000000 761#define MSR_K8_TSEG_ADDR 0xc0010112 762#define MSR_K8_TSEG_MASK 0xc0010113 763#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 764#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 765#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 766 767/* K7 MSRs */ 768#define MSR_K7_EVNTSEL0 0xc0010000 769#define MSR_K7_PERFCTR0 0xc0010004 770#define MSR_K7_EVNTSEL1 0xc0010001 771#define MSR_K7_PERFCTR1 0xc0010005 772#define MSR_K7_EVNTSEL2 0xc0010002 773#define MSR_K7_PERFCTR2 0xc0010006 774#define MSR_K7_EVNTSEL3 0xc0010003 775#define MSR_K7_PERFCTR3 0xc0010007 776#define MSR_K7_CLK_CTL 0xc001001b 777#define MSR_K7_HWCR 0xc0010015 778#define MSR_K7_HWCR_SMMLOCK_BIT 0 779#define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 780#define MSR_K7_HWCR_IRPERF_EN_BIT 30 781#define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 782#define MSR_K7_FID_VID_CTL 0xc0010041 783#define MSR_K7_FID_VID_STATUS 0xc0010042 784 785/* K6 MSRs */ 786#define MSR_K6_WHCR 0xc0000082 787#define MSR_K6_UWCCR 0xc0000085 788#define MSR_K6_EPMR 0xc0000086 789#define MSR_K6_PSOR 0xc0000087 790#define MSR_K6_PFIR 0xc0000088 791 792/* Centaur-Hauls/IDT defined MSRs. */ 793#define MSR_IDT_FCR1 0x00000107 794#define MSR_IDT_FCR2 0x00000108 795#define MSR_IDT_FCR3 0x00000109 796#define MSR_IDT_FCR4 0x0000010a 797 798#define MSR_IDT_MCR0 0x00000110 799#define MSR_IDT_MCR1 0x00000111 800#define MSR_IDT_MCR2 0x00000112 801#define MSR_IDT_MCR3 0x00000113 802#define MSR_IDT_MCR4 0x00000114 803#define MSR_IDT_MCR5 0x00000115 804#define MSR_IDT_MCR6 0x00000116 805#define MSR_IDT_MCR7 0x00000117 806#define MSR_IDT_MCR_CTRL 0x00000120 807 808/* VIA Cyrix defined MSRs*/ 809#define MSR_VIA_FCR 0x00001107 810#define MSR_VIA_LONGHAUL 0x0000110a 811#define MSR_VIA_RNG 0x0000110b 812#define MSR_VIA_BCR2 0x00001147 813 814/* Transmeta defined MSRs */ 815#define MSR_TMTA_LONGRUN_CTRL 0x80868010 816#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 817#define MSR_TMTA_LRTI_READOUT 0x80868018 818#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 819 820/* Intel defined MSRs. */ 821#define MSR_IA32_P5_MC_ADDR 0x00000000 822#define MSR_IA32_P5_MC_TYPE 0x00000001 823#define MSR_IA32_TSC 0x00000010 824#define MSR_IA32_PLATFORM_ID 0x00000017 825#define MSR_IA32_EBL_CR_POWERON 0x0000002a 826#define MSR_EBC_FREQUENCY_ID 0x0000002c 827#define MSR_SMI_COUNT 0x00000034 828 829/* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 830#define MSR_IA32_FEAT_CTL 0x0000003a 831#define FEAT_CTL_LOCKED BIT(0) 832#define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 833#define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 834#define FEAT_CTL_SGX_LC_ENABLED BIT(17) 835#define FEAT_CTL_SGX_ENABLED BIT(18) 836#define FEAT_CTL_LMCE_ENABLED BIT(20) 837 838#define MSR_IA32_TSC_ADJUST 0x0000003b 839#define MSR_IA32_BNDCFGS 0x00000d90 840 841#define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 842 843#define MSR_IA32_XFD 0x000001c4 844#define MSR_IA32_XFD_ERR 0x000001c5 845#define MSR_IA32_XSS 0x00000da0 846 847#define MSR_IA32_APICBASE 0x0000001b 848#define MSR_IA32_APICBASE_BSP (1<<8) 849#define MSR_IA32_APICBASE_ENABLE (1<<11) 850#define MSR_IA32_APICBASE_BASE (0xfffff<<12) 851 852#define MSR_IA32_UCODE_WRITE 0x00000079 853#define MSR_IA32_UCODE_REV 0x0000008b 854 855/* Intel SGX Launch Enclave Public Key Hash MSRs */ 856#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 857#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 858#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 859#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 860 861#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 862#define MSR_IA32_SMBASE 0x0000009e 863 864#define MSR_IA32_PERF_STATUS 0x00000198 865#define MSR_IA32_PERF_CTL 0x00000199 866#define INTEL_PERF_CTL_MASK 0xffff 867 868/* AMD Branch Sampling configuration */ 869#define MSR_AMD_DBG_EXTN_CFG 0xc000010f 870#define MSR_AMD_SAMP_BR_FROM 0xc0010300 871 872#define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6) 873 874#define MSR_IA32_MPERF 0x000000e7 875#define MSR_IA32_APERF 0x000000e8 876 877#define MSR_IA32_THERM_CONTROL 0x0000019a 878#define MSR_IA32_THERM_INTERRUPT 0x0000019b 879 880#define THERM_INT_HIGH_ENABLE (1 << 0) 881#define THERM_INT_LOW_ENABLE (1 << 1) 882#define THERM_INT_PLN_ENABLE (1 << 24) 883 884#define MSR_IA32_THERM_STATUS 0x0000019c 885 886#define THERM_STATUS_PROCHOT (1 << 0) 887#define THERM_STATUS_POWER_LIMIT (1 << 10) 888 889#define MSR_THERM2_CTL 0x0000019d 890 891#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 892 893#define MSR_IA32_MISC_ENABLE 0x000001a0 894 895#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 896 897#define MSR_MISC_FEATURE_CONTROL 0x000001a4 898#define MSR_MISC_PWR_MGMT 0x000001aa 899 900#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 901#define ENERGY_PERF_BIAS_PERFORMANCE 0 902#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 903#define ENERGY_PERF_BIAS_NORMAL 6 904#define ENERGY_PERF_BIAS_NORMAL_POWERSAVE 7 905#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 906#define ENERGY_PERF_BIAS_POWERSAVE 15 907 908#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 909 910#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 911#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 912#define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) 913 914#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 915 916#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 917#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 918#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 919#define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) 920 921/* Thermal Thresholds Support */ 922#define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 923#define THERM_SHIFT_THRESHOLD0 8 924#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 925#define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 926#define THERM_SHIFT_THRESHOLD1 16 927#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 928#define THERM_STATUS_THRESHOLD0 (1 << 6) 929#define THERM_LOG_THRESHOLD0 (1 << 7) 930#define THERM_STATUS_THRESHOLD1 (1 << 8) 931#define THERM_LOG_THRESHOLD1 (1 << 9) 932 933/* MISC_ENABLE bits: architectural */ 934#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 935#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 936#define MSR_IA32_MISC_ENABLE_TCC_BIT 1 937#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 938#define MSR_IA32_MISC_ENABLE_EMON_BIT 7 939#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 940#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 941#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 942#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 943#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 944#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 945#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 946#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 947#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 948#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 949#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 950#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 951#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 952#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 953#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 954 955/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 956#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 957#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 958#define MSR_IA32_MISC_ENABLE_TM1_BIT 3 959#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 960#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 961#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 962#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 963#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 964#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 965#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 966#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 967#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 968#define MSR_IA32_MISC_ENABLE_FERR_BIT 10 969#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 970#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 971#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 972#define MSR_IA32_MISC_ENABLE_TM2_BIT 13 973#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 974#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 975#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 976#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 977#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 978#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 979#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 980#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 981#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 982#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 983#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 984#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 985#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 986 987/* MISC_FEATURES_ENABLES non-architectural features */ 988#define MSR_MISC_FEATURES_ENABLES 0x00000140 989 990#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 991#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 992#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 993 994#define MSR_IA32_TSC_DEADLINE 0x000006E0 995 996 997#define MSR_TSX_FORCE_ABORT 0x0000010F 998 999#define MSR_TFA_RTM_FORCE_ABORT_BIT 0 1000#define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 1001#define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 1002#define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) 1003#define MSR_TFA_SDV_ENABLE_RTM_BIT 2 1004#define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) 1005 1006/* P4/Xeon+ specific */ 1007#define MSR_IA32_MCG_EAX 0x00000180 1008#define MSR_IA32_MCG_EBX 0x00000181 1009#define MSR_IA32_MCG_ECX 0x00000182 1010#define MSR_IA32_MCG_EDX 0x00000183 1011#define MSR_IA32_MCG_ESI 0x00000184 1012#define MSR_IA32_MCG_EDI 0x00000185 1013#define MSR_IA32_MCG_EBP 0x00000186 1014#define MSR_IA32_MCG_ESP 0x00000187 1015#define MSR_IA32_MCG_EFLAGS 0x00000188 1016#define MSR_IA32_MCG_EIP 0x00000189 1017#define MSR_IA32_MCG_RESERVED 0x0000018a 1018 1019/* Pentium IV performance counter MSRs */ 1020#define MSR_P4_BPU_PERFCTR0 0x00000300 1021#define MSR_P4_BPU_PERFCTR1 0x00000301 1022#define MSR_P4_BPU_PERFCTR2 0x00000302 1023#define MSR_P4_BPU_PERFCTR3 0x00000303 1024#define MSR_P4_MS_PERFCTR0 0x00000304 1025#define MSR_P4_MS_PERFCTR1 0x00000305 1026#define MSR_P4_MS_PERFCTR2 0x00000306 1027#define MSR_P4_MS_PERFCTR3 0x00000307 1028#define MSR_P4_FLAME_PERFCTR0 0x00000308 1029#define MSR_P4_FLAME_PERFCTR1 0x00000309 1030#define MSR_P4_FLAME_PERFCTR2 0x0000030a 1031#define MSR_P4_FLAME_PERFCTR3 0x0000030b 1032#define MSR_P4_IQ_PERFCTR0 0x0000030c 1033#define MSR_P4_IQ_PERFCTR1 0x0000030d 1034#define MSR_P4_IQ_PERFCTR2 0x0000030e 1035#define MSR_P4_IQ_PERFCTR3 0x0000030f 1036#define MSR_P4_IQ_PERFCTR4 0x00000310 1037#define MSR_P4_IQ_PERFCTR5 0x00000311 1038#define MSR_P4_BPU_CCCR0 0x00000360 1039#define MSR_P4_BPU_CCCR1 0x00000361 1040#define MSR_P4_BPU_CCCR2 0x00000362 1041#define MSR_P4_BPU_CCCR3 0x00000363 1042#define MSR_P4_MS_CCCR0 0x00000364 1043#define MSR_P4_MS_CCCR1 0x00000365 1044#define MSR_P4_MS_CCCR2 0x00000366 1045#define MSR_P4_MS_CCCR3 0x00000367 1046#define MSR_P4_FLAME_CCCR0 0x00000368 1047#define MSR_P4_FLAME_CCCR1 0x00000369 1048#define MSR_P4_FLAME_CCCR2 0x0000036a 1049#define MSR_P4_FLAME_CCCR3 0x0000036b 1050#define MSR_P4_IQ_CCCR0 0x0000036c 1051#define MSR_P4_IQ_CCCR1 0x0000036d 1052#define MSR_P4_IQ_CCCR2 0x0000036e 1053#define MSR_P4_IQ_CCCR3 0x0000036f 1054#define MSR_P4_IQ_CCCR4 0x00000370 1055#define MSR_P4_IQ_CCCR5 0x00000371 1056#define MSR_P4_ALF_ESCR0 0x000003ca 1057#define MSR_P4_ALF_ESCR1 0x000003cb 1058#define MSR_P4_BPU_ESCR0 0x000003b2 1059#define MSR_P4_BPU_ESCR1 0x000003b3 1060#define MSR_P4_BSU_ESCR0 0x000003a0 1061#define MSR_P4_BSU_ESCR1 0x000003a1 1062#define MSR_P4_CRU_ESCR0 0x000003b8 1063#define MSR_P4_CRU_ESCR1 0x000003b9 1064#define MSR_P4_CRU_ESCR2 0x000003cc 1065#define MSR_P4_CRU_ESCR3 0x000003cd 1066#define MSR_P4_CRU_ESCR4 0x000003e0 1067#define MSR_P4_CRU_ESCR5 0x000003e1 1068#define MSR_P4_DAC_ESCR0 0x000003a8 1069#define MSR_P4_DAC_ESCR1 0x000003a9 1070#define MSR_P4_FIRM_ESCR0 0x000003a4 1071#define MSR_P4_FIRM_ESCR1 0x000003a5 1072#define MSR_P4_FLAME_ESCR0 0x000003a6 1073#define MSR_P4_FLAME_ESCR1 0x000003a7 1074#define MSR_P4_FSB_ESCR0 0x000003a2 1075#define MSR_P4_FSB_ESCR1 0x000003a3 1076#define MSR_P4_IQ_ESCR0 0x000003ba 1077#define MSR_P4_IQ_ESCR1 0x000003bb 1078#define MSR_P4_IS_ESCR0 0x000003b4 1079#define MSR_P4_IS_ESCR1 0x000003b5 1080#define MSR_P4_ITLB_ESCR0 0x000003b6 1081#define MSR_P4_ITLB_ESCR1 0x000003b7 1082#define MSR_P4_IX_ESCR0 0x000003c8 1083#define MSR_P4_IX_ESCR1 0x000003c9 1084#define MSR_P4_MOB_ESCR0 0x000003aa 1085#define MSR_P4_MOB_ESCR1 0x000003ab 1086#define MSR_P4_MS_ESCR0 0x000003c0 1087#define MSR_P4_MS_ESCR1 0x000003c1 1088#define MSR_P4_PMH_ESCR0 0x000003ac 1089#define MSR_P4_PMH_ESCR1 0x000003ad 1090#define MSR_P4_RAT_ESCR0 0x000003bc 1091#define MSR_P4_RAT_ESCR1 0x000003bd 1092#define MSR_P4_SAAT_ESCR0 0x000003ae 1093#define MSR_P4_SAAT_ESCR1 0x000003af 1094#define MSR_P4_SSU_ESCR0 0x000003be 1095#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 1096 1097#define MSR_P4_TBPU_ESCR0 0x000003c2 1098#define MSR_P4_TBPU_ESCR1 0x000003c3 1099#define MSR_P4_TC_ESCR0 0x000003c4 1100#define MSR_P4_TC_ESCR1 0x000003c5 1101#define MSR_P4_U2L_ESCR0 0x000003b0 1102#define MSR_P4_U2L_ESCR1 0x000003b1 1103 1104#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 1105 1106/* Intel Core-based CPU performance counters */ 1107#define MSR_CORE_PERF_FIXED_CTR0 0x00000309 1108#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 1109#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 1110#define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 1111#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 1112#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 1113#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 1114#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 1115 1116#define MSR_PERF_METRICS 0x00000329 1117 1118/* PERF_GLOBAL_OVF_CTL bits */ 1119#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 1120#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 1121#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 1122#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 1123#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 1124#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 1125 1126/* Geode defined MSRs */ 1127#define MSR_GEODE_BUSCONT_CONF0 0x00001900 1128 1129/* Intel VT MSRs */ 1130#define MSR_IA32_VMX_BASIC 0x00000480 1131#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 1132#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 1133#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 1134#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 1135#define MSR_IA32_VMX_MISC 0x00000485 1136#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 1137#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 1138#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 1139#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 1140#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 1141#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 1142#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 1143#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 1144#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 1145#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 1146#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 1147#define MSR_IA32_VMX_VMFUNC 0x00000491 1148#define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 1149 1150/* VMX_BASIC bits and bitmasks */ 1151#define VMX_BASIC_VMCS_SIZE_SHIFT 32 1152#define VMX_BASIC_TRUE_CTLS (1ULL << 55) 1153#define VMX_BASIC_64 0x0001000000000000LLU 1154#define VMX_BASIC_MEM_TYPE_SHIFT 50 1155#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 1156#define VMX_BASIC_MEM_TYPE_WB 6LLU 1157#define VMX_BASIC_INOUT 0x0040000000000000LLU 1158 1159/* Resctrl MSRs: */ 1160/* - Intel: */ 1161#define MSR_IA32_L3_QOS_CFG 0xc81 1162#define MSR_IA32_L2_QOS_CFG 0xc82 1163#define MSR_IA32_QM_EVTSEL 0xc8d 1164#define MSR_IA32_QM_CTR 0xc8e 1165#define MSR_IA32_PQR_ASSOC 0xc8f 1166#define MSR_IA32_L3_CBM_BASE 0xc90 1167#define MSR_IA32_L2_CBM_BASE 0xd10 1168#define MSR_IA32_MBA_THRTL_BASE 0xd50 1169 1170/* - AMD: */ 1171#define MSR_IA32_MBA_BW_BASE 0xc0000200 1172#define MSR_IA32_SMBA_BW_BASE 0xc0000280 1173#define MSR_IA32_EVT_CFG_BASE 0xc0000400 1174 1175/* MSR_IA32_VMX_MISC bits */ 1176#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 1177#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 1178#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 1179 1180/* AMD-V MSRs */ 1181#define MSR_VM_CR 0xc0010114 1182#define MSR_VM_IGNNE 0xc0010115 1183#define MSR_VM_HSAVE_PA 0xc0010117 1184 1185#define SVM_VM_CR_VALID_MASK 0x001fULL 1186#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL 1187#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL 1188 1189/* Hardware Feedback Interface */ 1190#define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 1191#define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 1192 1193/* x2APIC locked status */ 1194#define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD 1195#define LEGACY_XAPIC_DISABLED BIT(0) /* 1196 * x2APIC mode is locked and 1197 * disabling x2APIC will cause 1198 * a #GP 1199 */ 1200 1201#endif /* _ASM_X86_MSR_INDEX_H */ 1202