1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2009. SUSE Linux Products GmbH. All rights reserved. 4 * 5 * Authors: 6 * Alexander Graf <agraf@suse.de> 7 * Kevin Wolf <mail@kevin-wolf.de> 8 * Paul Mackerras <paulus@samba.org> 9 * 10 * Description: 11 * Functions relating to running KVM on Book 3S processors where 12 * we don't have access to hypervisor mode, and we run the guest 13 * in problem state (user mode). 14 * 15 * This file is derived from arch/powerpc/kvm/44x.c, 16 * by Hollis Blanchard <hollisb@us.ibm.com>. 17 */ 18 19#include <linux/kvm_host.h> 20#include <linux/export.h> 21#include <linux/err.h> 22#include <linux/slab.h> 23 24#include <asm/reg.h> 25#include <asm/cputable.h> 26#include <asm/cacheflush.h> 27#include <linux/uaccess.h> 28#include <asm/interrupt.h> 29#include <asm/io.h> 30#include <asm/kvm_ppc.h> 31#include <asm/kvm_book3s.h> 32#include <asm/mmu_context.h> 33#include <asm/switch_to.h> 34#include <asm/firmware.h> 35#include <asm/setup.h> 36#include <linux/gfp.h> 37#include <linux/sched.h> 38#include <linux/vmalloc.h> 39#include <linux/highmem.h> 40#include <linux/module.h> 41#include <linux/miscdevice.h> 42#include <asm/asm-prototypes.h> 43#include <asm/tm.h> 44 45#include "book3s.h" 46 47#define CREATE_TRACE_POINTS 48#include "trace_pr.h" 49 50/* #define EXIT_DEBUG */ 51/* #define DEBUG_EXT */ 52 53static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, 54 ulong msr); 55#ifdef CONFIG_PPC_BOOK3S_64 56static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac); 57#endif 58 59/* Some compatibility defines */ 60#ifdef CONFIG_PPC_BOOK3S_32 61#define MSR_USER32 MSR_USER 62#define MSR_USER64 MSR_USER 63#define HW_PAGE_SIZE PAGE_SIZE 64#define HPTE_R_M _PAGE_COHERENT 65#endif 66 67static bool kvmppc_is_split_real(struct kvm_vcpu *vcpu) 68{ 69 ulong msr = kvmppc_get_msr(vcpu); 70 return (msr & (MSR_IR|MSR_DR)) == MSR_DR; 71} 72 73static void kvmppc_fixup_split_real(struct kvm_vcpu *vcpu) 74{ 75 ulong msr = kvmppc_get_msr(vcpu); 76 ulong pc = kvmppc_get_pc(vcpu); 77 78 /* We are in DR only split real mode */ 79 if ((msr & (MSR_IR|MSR_DR)) != MSR_DR) 80 return; 81 82 /* We have not fixed up the guest already */ 83 if (vcpu->arch.hflags & BOOK3S_HFLAG_SPLIT_HACK) 84 return; 85 86 /* The code is in fixupable address space */ 87 if (pc & SPLIT_HACK_MASK) 88 return; 89 90 vcpu->arch.hflags |= BOOK3S_HFLAG_SPLIT_HACK; 91 kvmppc_set_pc(vcpu, pc | SPLIT_HACK_OFFS); 92} 93 94static void kvmppc_unfixup_split_real(struct kvm_vcpu *vcpu) 95{ 96 if (vcpu->arch.hflags & BOOK3S_HFLAG_SPLIT_HACK) { 97 ulong pc = kvmppc_get_pc(vcpu); 98 ulong lr = kvmppc_get_lr(vcpu); 99 if ((pc & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS) 100 kvmppc_set_pc(vcpu, pc & ~SPLIT_HACK_MASK); 101 if ((lr & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS) 102 kvmppc_set_lr(vcpu, lr & ~SPLIT_HACK_MASK); 103 vcpu->arch.hflags &= ~BOOK3S_HFLAG_SPLIT_HACK; 104 } 105} 106 107static void kvmppc_inject_interrupt_pr(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) 108{ 109 unsigned long msr, pc, new_msr, new_pc; 110 111 kvmppc_unfixup_split_real(vcpu); 112 113 msr = kvmppc_get_msr(vcpu); 114 pc = kvmppc_get_pc(vcpu); 115 new_msr = vcpu->arch.intr_msr; 116 new_pc = to_book3s(vcpu)->hior + vec; 117 118#ifdef CONFIG_PPC_BOOK3S_64 119 /* If transactional, change to suspend mode on IRQ delivery */ 120 if (MSR_TM_TRANSACTIONAL(msr)) 121 new_msr |= MSR_TS_S; 122 else 123 new_msr |= msr & MSR_TS_MASK; 124#endif 125 126 kvmppc_set_srr0(vcpu, pc); 127 kvmppc_set_srr1(vcpu, (msr & SRR1_MSR_BITS) | srr1_flags); 128 kvmppc_set_pc(vcpu, new_pc); 129 kvmppc_set_msr(vcpu, new_msr); 130} 131 132static void kvmppc_core_vcpu_load_pr(struct kvm_vcpu *vcpu, int cpu) 133{ 134#ifdef CONFIG_PPC_BOOK3S_64 135 struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); 136 memcpy(svcpu->slb, to_book3s(vcpu)->slb_shadow, sizeof(svcpu->slb)); 137 svcpu->slb_max = to_book3s(vcpu)->slb_shadow_max; 138 svcpu->in_use = 0; 139 svcpu_put(svcpu); 140 141 /* Disable AIL if supported */ 142 if (cpu_has_feature(CPU_FTR_HVMODE)) { 143 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 144 mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~LPCR_AIL); 145 if (cpu_has_feature(CPU_FTR_ARCH_300) && (current->thread.fscr & FSCR_SCV)) 146 mtspr(SPRN_FSCR, mfspr(SPRN_FSCR) & ~FSCR_SCV); 147 } 148#endif 149 150 vcpu->cpu = smp_processor_id(); 151#ifdef CONFIG_PPC_BOOK3S_32 152 current->thread.kvm_shadow_vcpu = vcpu->arch.shadow_vcpu; 153#endif 154 155 if (kvmppc_is_split_real(vcpu)) 156 kvmppc_fixup_split_real(vcpu); 157 158 kvmppc_restore_tm_pr(vcpu); 159} 160 161static void kvmppc_core_vcpu_put_pr(struct kvm_vcpu *vcpu) 162{ 163#ifdef CONFIG_PPC_BOOK3S_64 164 struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); 165 if (svcpu->in_use) { 166 kvmppc_copy_from_svcpu(vcpu); 167 } 168 memcpy(to_book3s(vcpu)->slb_shadow, svcpu->slb, sizeof(svcpu->slb)); 169 to_book3s(vcpu)->slb_shadow_max = svcpu->slb_max; 170 svcpu_put(svcpu); 171 172 /* Enable AIL if supported */ 173 if (cpu_has_feature(CPU_FTR_HVMODE)) { 174 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 175 mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_AIL_3); 176 if (cpu_has_feature(CPU_FTR_ARCH_300) && (current->thread.fscr & FSCR_SCV)) 177 mtspr(SPRN_FSCR, mfspr(SPRN_FSCR) | FSCR_SCV); 178 } 179#endif 180 181 if (kvmppc_is_split_real(vcpu)) 182 kvmppc_unfixup_split_real(vcpu); 183 184 kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX); 185 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 186 kvmppc_save_tm_pr(vcpu); 187 188 vcpu->cpu = -1; 189} 190 191/* Copy data needed by real-mode code from vcpu to shadow vcpu */ 192void kvmppc_copy_to_svcpu(struct kvm_vcpu *vcpu) 193{ 194 struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); 195 196 svcpu->gpr[0] = vcpu->arch.regs.gpr[0]; 197 svcpu->gpr[1] = vcpu->arch.regs.gpr[1]; 198 svcpu->gpr[2] = vcpu->arch.regs.gpr[2]; 199 svcpu->gpr[3] = vcpu->arch.regs.gpr[3]; 200 svcpu->gpr[4] = vcpu->arch.regs.gpr[4]; 201 svcpu->gpr[5] = vcpu->arch.regs.gpr[5]; 202 svcpu->gpr[6] = vcpu->arch.regs.gpr[6]; 203 svcpu->gpr[7] = vcpu->arch.regs.gpr[7]; 204 svcpu->gpr[8] = vcpu->arch.regs.gpr[8]; 205 svcpu->gpr[9] = vcpu->arch.regs.gpr[9]; 206 svcpu->gpr[10] = vcpu->arch.regs.gpr[10]; 207 svcpu->gpr[11] = vcpu->arch.regs.gpr[11]; 208 svcpu->gpr[12] = vcpu->arch.regs.gpr[12]; 209 svcpu->gpr[13] = vcpu->arch.regs.gpr[13]; 210 svcpu->cr = vcpu->arch.regs.ccr; 211 svcpu->xer = vcpu->arch.regs.xer; 212 svcpu->ctr = vcpu->arch.regs.ctr; 213 svcpu->lr = vcpu->arch.regs.link; 214 svcpu->pc = vcpu->arch.regs.nip; 215#ifdef CONFIG_PPC_BOOK3S_64 216 svcpu->shadow_fscr = vcpu->arch.shadow_fscr; 217#endif 218 /* 219 * Now also save the current time base value. We use this 220 * to find the guest purr and spurr value. 221 */ 222 vcpu->arch.entry_tb = get_tb(); 223 vcpu->arch.entry_vtb = get_vtb(); 224 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 225 vcpu->arch.entry_ic = mfspr(SPRN_IC); 226 svcpu->in_use = true; 227 228 svcpu_put(svcpu); 229} 230 231static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu) 232{ 233 ulong guest_msr = kvmppc_get_msr(vcpu); 234 ulong smsr = guest_msr; 235 236 /* Guest MSR values */ 237#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 238 smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE | 239 MSR_TM | MSR_TS_MASK; 240#else 241 smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE; 242#endif 243 /* Process MSR values */ 244 smsr |= MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_PR | MSR_EE; 245 /* External providers the guest reserved */ 246 smsr |= (guest_msr & vcpu->arch.guest_owned_ext); 247 /* 64-bit Process MSR values */ 248#ifdef CONFIG_PPC_BOOK3S_64 249 smsr |= MSR_HV; 250#endif 251#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 252 /* 253 * in guest privileged state, we want to fail all TM transactions. 254 * So disable MSR TM bit so that all tbegin. will be able to be 255 * trapped into host. 256 */ 257 if (!(guest_msr & MSR_PR)) 258 smsr &= ~MSR_TM; 259#endif 260 vcpu->arch.shadow_msr = smsr; 261} 262 263/* Copy data touched by real-mode code from shadow vcpu back to vcpu */ 264void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu) 265{ 266 struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); 267#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 268 ulong old_msr; 269#endif 270 271 /* 272 * Maybe we were already preempted and synced the svcpu from 273 * our preempt notifiers. Don't bother touching this svcpu then. 274 */ 275 if (!svcpu->in_use) 276 goto out; 277 278 vcpu->arch.regs.gpr[0] = svcpu->gpr[0]; 279 vcpu->arch.regs.gpr[1] = svcpu->gpr[1]; 280 vcpu->arch.regs.gpr[2] = svcpu->gpr[2]; 281 vcpu->arch.regs.gpr[3] = svcpu->gpr[3]; 282 vcpu->arch.regs.gpr[4] = svcpu->gpr[4]; 283 vcpu->arch.regs.gpr[5] = svcpu->gpr[5]; 284 vcpu->arch.regs.gpr[6] = svcpu->gpr[6]; 285 vcpu->arch.regs.gpr[7] = svcpu->gpr[7]; 286 vcpu->arch.regs.gpr[8] = svcpu->gpr[8]; 287 vcpu->arch.regs.gpr[9] = svcpu->gpr[9]; 288 vcpu->arch.regs.gpr[10] = svcpu->gpr[10]; 289 vcpu->arch.regs.gpr[11] = svcpu->gpr[11]; 290 vcpu->arch.regs.gpr[12] = svcpu->gpr[12]; 291 vcpu->arch.regs.gpr[13] = svcpu->gpr[13]; 292 vcpu->arch.regs.ccr = svcpu->cr; 293 vcpu->arch.regs.xer = svcpu->xer; 294 vcpu->arch.regs.ctr = svcpu->ctr; 295 vcpu->arch.regs.link = svcpu->lr; 296 vcpu->arch.regs.nip = svcpu->pc; 297 vcpu->arch.shadow_srr1 = svcpu->shadow_srr1; 298 vcpu->arch.fault_dar = svcpu->fault_dar; 299 vcpu->arch.fault_dsisr = svcpu->fault_dsisr; 300 vcpu->arch.last_inst = svcpu->last_inst; 301#ifdef CONFIG_PPC_BOOK3S_64 302 vcpu->arch.shadow_fscr = svcpu->shadow_fscr; 303#endif 304 /* 305 * Update purr and spurr using time base on exit. 306 */ 307 vcpu->arch.purr += get_tb() - vcpu->arch.entry_tb; 308 vcpu->arch.spurr += get_tb() - vcpu->arch.entry_tb; 309 to_book3s(vcpu)->vtb += get_vtb() - vcpu->arch.entry_vtb; 310 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 311 vcpu->arch.ic += mfspr(SPRN_IC) - vcpu->arch.entry_ic; 312 313#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 314 /* 315 * Unlike other MSR bits, MSR[TS]bits can be changed at guest without 316 * notifying host: 317 * modified by unprivileged instructions like "tbegin"/"tend"/ 318 * "tresume"/"tsuspend" in PR KVM guest. 319 * 320 * It is necessary to sync here to calculate a correct shadow_msr. 321 * 322 * privileged guest's tbegin will be failed at present. So we 323 * only take care of problem state guest. 324 */ 325 old_msr = kvmppc_get_msr(vcpu); 326 if (unlikely((old_msr & MSR_PR) && 327 (vcpu->arch.shadow_srr1 & (MSR_TS_MASK)) != 328 (old_msr & (MSR_TS_MASK)))) { 329 old_msr &= ~(MSR_TS_MASK); 330 old_msr |= (vcpu->arch.shadow_srr1 & (MSR_TS_MASK)); 331 kvmppc_set_msr_fast(vcpu, old_msr); 332 kvmppc_recalc_shadow_msr(vcpu); 333 } 334#endif 335 336 svcpu->in_use = false; 337 338out: 339 svcpu_put(svcpu); 340} 341 342#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 343void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu) 344{ 345 tm_enable(); 346 vcpu->arch.tfhar = mfspr(SPRN_TFHAR); 347 vcpu->arch.texasr = mfspr(SPRN_TEXASR); 348 vcpu->arch.tfiar = mfspr(SPRN_TFIAR); 349 tm_disable(); 350} 351 352void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) 353{ 354 tm_enable(); 355 mtspr(SPRN_TFHAR, vcpu->arch.tfhar); 356 mtspr(SPRN_TEXASR, vcpu->arch.texasr); 357 mtspr(SPRN_TFIAR, vcpu->arch.tfiar); 358 tm_disable(); 359} 360 361/* loadup math bits which is enabled at kvmppc_get_msr() but not enabled at 362 * hardware. 363 */ 364static void kvmppc_handle_lost_math_exts(struct kvm_vcpu *vcpu) 365{ 366 ulong exit_nr; 367 ulong ext_diff = (kvmppc_get_msr(vcpu) & ~vcpu->arch.guest_owned_ext) & 368 (MSR_FP | MSR_VEC | MSR_VSX); 369 370 if (!ext_diff) 371 return; 372 373 if (ext_diff == MSR_FP) 374 exit_nr = BOOK3S_INTERRUPT_FP_UNAVAIL; 375 else if (ext_diff == MSR_VEC) 376 exit_nr = BOOK3S_INTERRUPT_ALTIVEC; 377 else 378 exit_nr = BOOK3S_INTERRUPT_VSX; 379 380 kvmppc_handle_ext(vcpu, exit_nr, ext_diff); 381} 382 383void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu) 384{ 385 if (!(MSR_TM_ACTIVE(kvmppc_get_msr(vcpu)))) { 386 kvmppc_save_tm_sprs(vcpu); 387 return; 388 } 389 390 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 391 kvmppc_giveup_ext(vcpu, MSR_VSX); 392 393 preempt_disable(); 394 _kvmppc_save_tm_pr(vcpu, mfmsr()); 395 preempt_enable(); 396} 397 398void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu) 399{ 400 if (!MSR_TM_ACTIVE(kvmppc_get_msr(vcpu))) { 401 kvmppc_restore_tm_sprs(vcpu); 402 if (kvmppc_get_msr(vcpu) & MSR_TM) { 403 kvmppc_handle_lost_math_exts(vcpu); 404 if (vcpu->arch.fscr & FSCR_TAR) 405 kvmppc_handle_fac(vcpu, FSCR_TAR_LG); 406 } 407 return; 408 } 409 410 preempt_disable(); 411 _kvmppc_restore_tm_pr(vcpu, kvmppc_get_msr(vcpu)); 412 preempt_enable(); 413 414 if (kvmppc_get_msr(vcpu) & MSR_TM) { 415 kvmppc_handle_lost_math_exts(vcpu); 416 if (vcpu->arch.fscr & FSCR_TAR) 417 kvmppc_handle_fac(vcpu, FSCR_TAR_LG); 418 } 419} 420#endif 421 422static int kvmppc_core_check_requests_pr(struct kvm_vcpu *vcpu) 423{ 424 int r = 1; /* Indicate we want to get back into the guest */ 425 426 /* We misuse TLB_FLUSH to indicate that we want to clear 427 all shadow cache entries */ 428 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 429 kvmppc_mmu_pte_flush(vcpu, 0, 0); 430 431 return r; 432} 433 434/************* MMU Notifiers *************/ 435static bool do_kvm_unmap_gfn(struct kvm *kvm, struct kvm_gfn_range *range) 436{ 437 unsigned long i; 438 struct kvm_vcpu *vcpu; 439 440 kvm_for_each_vcpu(i, vcpu, kvm) 441 kvmppc_mmu_pte_pflush(vcpu, range->start << PAGE_SHIFT, 442 range->end << PAGE_SHIFT); 443 444 return false; 445} 446 447static bool kvm_unmap_gfn_range_pr(struct kvm *kvm, struct kvm_gfn_range *range) 448{ 449 return do_kvm_unmap_gfn(kvm, range); 450} 451 452static bool kvm_age_gfn_pr(struct kvm *kvm, struct kvm_gfn_range *range) 453{ 454 /* XXX could be more clever ;) */ 455 return false; 456} 457 458static bool kvm_test_age_gfn_pr(struct kvm *kvm, struct kvm_gfn_range *range) 459{ 460 /* XXX could be more clever ;) */ 461 return false; 462} 463 464/*****************************************/ 465 466static void kvmppc_set_msr_pr(struct kvm_vcpu *vcpu, u64 msr) 467{ 468 ulong old_msr; 469 470 /* For PAPR guest, make sure MSR reflects guest mode */ 471 if (vcpu->arch.papr_enabled) 472 msr = (msr & ~MSR_HV) | MSR_ME; 473 474#ifdef EXIT_DEBUG 475 printk(KERN_INFO "KVM: Set MSR to 0x%llx\n", msr); 476#endif 477 478#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 479 /* We should never target guest MSR to TS=10 && PR=0, 480 * since we always fail transaction for guest privilege 481 * state. 482 */ 483 if (!(msr & MSR_PR) && MSR_TM_TRANSACTIONAL(msr)) 484 kvmppc_emulate_tabort(vcpu, 485 TM_CAUSE_KVM_FAC_UNAV | TM_CAUSE_PERSISTENT); 486#endif 487 488 old_msr = kvmppc_get_msr(vcpu); 489 msr &= to_book3s(vcpu)->msr_mask; 490 kvmppc_set_msr_fast(vcpu, msr); 491 kvmppc_recalc_shadow_msr(vcpu); 492 493 if (msr & MSR_POW) { 494 if (!vcpu->arch.pending_exceptions) { 495 kvm_vcpu_halt(vcpu); 496 vcpu->stat.generic.halt_wakeup++; 497 498 /* Unset POW bit after we woke up */ 499 msr &= ~MSR_POW; 500 kvmppc_set_msr_fast(vcpu, msr); 501 } 502 } 503 504 if (kvmppc_is_split_real(vcpu)) 505 kvmppc_fixup_split_real(vcpu); 506 else 507 kvmppc_unfixup_split_real(vcpu); 508 509 if ((kvmppc_get_msr(vcpu) & (MSR_PR|MSR_IR|MSR_DR)) != 510 (old_msr & (MSR_PR|MSR_IR|MSR_DR))) { 511 kvmppc_mmu_flush_segments(vcpu); 512 kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)); 513 514 /* Preload magic page segment when in kernel mode */ 515 if (!(msr & MSR_PR) && vcpu->arch.magic_page_pa) { 516 struct kvm_vcpu_arch *a = &vcpu->arch; 517 518 if (msr & MSR_DR) 519 kvmppc_mmu_map_segment(vcpu, a->magic_page_ea); 520 else 521 kvmppc_mmu_map_segment(vcpu, a->magic_page_pa); 522 } 523 } 524 525 /* 526 * When switching from 32 to 64-bit, we may have a stale 32-bit 527 * magic page around, we need to flush it. Typically 32-bit magic 528 * page will be instantiated when calling into RTAS. Note: We 529 * assume that such transition only happens while in kernel mode, 530 * ie, we never transition from user 32-bit to kernel 64-bit with 531 * a 32-bit magic page around. 532 */ 533 if (vcpu->arch.magic_page_pa && 534 !(old_msr & MSR_PR) && !(old_msr & MSR_SF) && (msr & MSR_SF)) { 535 /* going from RTAS to normal kernel code */ 536 kvmppc_mmu_pte_flush(vcpu, (uint32_t)vcpu->arch.magic_page_pa, 537 ~0xFFFUL); 538 } 539 540 /* Preload FPU if it's enabled */ 541 if (kvmppc_get_msr(vcpu) & MSR_FP) 542 kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP); 543 544#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 545 if (kvmppc_get_msr(vcpu) & MSR_TM) 546 kvmppc_handle_lost_math_exts(vcpu); 547#endif 548} 549 550static void kvmppc_set_pvr_pr(struct kvm_vcpu *vcpu, u32 pvr) 551{ 552 u32 host_pvr; 553 554 vcpu->arch.hflags &= ~BOOK3S_HFLAG_SLB; 555 vcpu->arch.pvr = pvr; 556#ifdef CONFIG_PPC_BOOK3S_64 557 if ((pvr >= 0x330000) && (pvr < 0x70330000)) { 558 kvmppc_mmu_book3s_64_init(vcpu); 559 if (!to_book3s(vcpu)->hior_explicit) 560 to_book3s(vcpu)->hior = 0xfff00000; 561 to_book3s(vcpu)->msr_mask = 0xffffffffffffffffULL; 562 vcpu->arch.cpu_type = KVM_CPU_3S_64; 563 } else 564#endif 565 { 566 kvmppc_mmu_book3s_32_init(vcpu); 567 if (!to_book3s(vcpu)->hior_explicit) 568 to_book3s(vcpu)->hior = 0; 569 to_book3s(vcpu)->msr_mask = 0xffffffffULL; 570 vcpu->arch.cpu_type = KVM_CPU_3S_32; 571 } 572 573 kvmppc_sanity_check(vcpu); 574 575 /* If we are in hypervisor level on 970, we can tell the CPU to 576 * treat DCBZ as 32 bytes store */ 577 vcpu->arch.hflags &= ~BOOK3S_HFLAG_DCBZ32; 578 if (vcpu->arch.mmu.is_dcbz32(vcpu) && (mfmsr() & MSR_HV) && 579 !strcmp(cur_cpu_spec->platform, "ppc970")) 580 vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; 581 582 /* Cell performs badly if MSR_FEx are set. So let's hope nobody 583 really needs them in a VM on Cell and force disable them. */ 584 if (!strcmp(cur_cpu_spec->platform, "ppc-cell-be")) 585 to_book3s(vcpu)->msr_mask &= ~(MSR_FE0 | MSR_FE1); 586 587 /* 588 * If they're asking for POWER6 or later, set the flag 589 * indicating that we can do multiple large page sizes 590 * and 1TB segments. 591 * Also set the flag that indicates that tlbie has the large 592 * page bit in the RB operand instead of the instruction. 593 */ 594 switch (PVR_VER(pvr)) { 595 case PVR_POWER6: 596 case PVR_POWER7: 597 case PVR_POWER7p: 598 case PVR_POWER8: 599 case PVR_POWER8E: 600 case PVR_POWER8NVL: 601 case PVR_HX_C2000: 602 case PVR_POWER9: 603 vcpu->arch.hflags |= BOOK3S_HFLAG_MULTI_PGSIZE | 604 BOOK3S_HFLAG_NEW_TLBIE; 605 break; 606 } 607 608#ifdef CONFIG_PPC_BOOK3S_32 609 /* 32 bit Book3S always has 32 byte dcbz */ 610 vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; 611#endif 612 613 /* On some CPUs we can execute paired single operations natively */ 614 asm ( "mfpvr %0" : "=r"(host_pvr)); 615 switch (host_pvr) { 616 case 0x00080200: /* lonestar 2.0 */ 617 case 0x00088202: /* lonestar 2.2 */ 618 case 0x70000100: /* gekko 1.0 */ 619 case 0x00080100: /* gekko 2.0 */ 620 case 0x00083203: /* gekko 2.3a */ 621 case 0x00083213: /* gekko 2.3b */ 622 case 0x00083204: /* gekko 2.4 */ 623 case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */ 624 case 0x00087200: /* broadway */ 625 vcpu->arch.hflags |= BOOK3S_HFLAG_NATIVE_PS; 626 /* Enable HID2.PSE - in case we need it later */ 627 mtspr(SPRN_HID2_GEKKO, mfspr(SPRN_HID2_GEKKO) | (1 << 29)); 628 } 629} 630 631/* Book3s_32 CPUs always have 32 bytes cache line size, which Linux assumes. To 632 * make Book3s_32 Linux work on Book3s_64, we have to make sure we trap dcbz to 633 * emulate 32 bytes dcbz length. 634 * 635 * The Book3s_64 inventors also realized this case and implemented a special bit 636 * in the HID5 register, which is a hypervisor ressource. Thus we can't use it. 637 * 638 * My approach here is to patch the dcbz instruction on executing pages. 639 */ 640static void kvmppc_patch_dcbz(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte) 641{ 642 struct page *hpage; 643 u64 hpage_offset; 644 u32 *page; 645 int i; 646 647 hpage = gfn_to_page(vcpu->kvm, pte->raddr >> PAGE_SHIFT); 648 if (is_error_page(hpage)) 649 return; 650 651 hpage_offset = pte->raddr & ~PAGE_MASK; 652 hpage_offset &= ~0xFFFULL; 653 hpage_offset /= 4; 654 655 get_page(hpage); 656 page = kmap_atomic(hpage); 657 658 /* patch dcbz into reserved instruction, so we trap */ 659 for (i=hpage_offset; i < hpage_offset + (HW_PAGE_SIZE / 4); i++) 660 if ((be32_to_cpu(page[i]) & 0xff0007ff) == INS_DCBZ) 661 page[i] &= cpu_to_be32(0xfffffff7); 662 663 kunmap_atomic(page); 664 put_page(hpage); 665} 666 667static bool kvmppc_visible_gpa(struct kvm_vcpu *vcpu, gpa_t gpa) 668{ 669 ulong mp_pa = vcpu->arch.magic_page_pa; 670 671 if (!(kvmppc_get_msr(vcpu) & MSR_SF)) 672 mp_pa = (uint32_t)mp_pa; 673 674 gpa &= ~0xFFFULL; 675 if (unlikely(mp_pa) && unlikely((mp_pa & KVM_PAM) == (gpa & KVM_PAM))) { 676 return true; 677 } 678 679 return kvm_is_visible_gfn(vcpu->kvm, gpa >> PAGE_SHIFT); 680} 681 682static int kvmppc_handle_pagefault(struct kvm_vcpu *vcpu, 683 ulong eaddr, int vec) 684{ 685 bool data = (vec == BOOK3S_INTERRUPT_DATA_STORAGE); 686 bool iswrite = false; 687 int r = RESUME_GUEST; 688 int relocated; 689 int page_found = 0; 690 struct kvmppc_pte pte = { 0 }; 691 bool dr = (kvmppc_get_msr(vcpu) & MSR_DR) ? true : false; 692 bool ir = (kvmppc_get_msr(vcpu) & MSR_IR) ? true : false; 693 u64 vsid; 694 695 relocated = data ? dr : ir; 696 if (data && (vcpu->arch.fault_dsisr & DSISR_ISSTORE)) 697 iswrite = true; 698 699 /* Resolve real address if translation turned on */ 700 if (relocated) { 701 page_found = vcpu->arch.mmu.xlate(vcpu, eaddr, &pte, data, iswrite); 702 } else { 703 pte.may_execute = true; 704 pte.may_read = true; 705 pte.may_write = true; 706 pte.raddr = eaddr & KVM_PAM; 707 pte.eaddr = eaddr; 708 pte.vpage = eaddr >> 12; 709 pte.page_size = MMU_PAGE_64K; 710 pte.wimg = HPTE_R_M; 711 } 712 713 switch (kvmppc_get_msr(vcpu) & (MSR_DR|MSR_IR)) { 714 case 0: 715 pte.vpage |= ((u64)VSID_REAL << (SID_SHIFT - 12)); 716 break; 717 case MSR_DR: 718 if (!data && 719 (vcpu->arch.hflags & BOOK3S_HFLAG_SPLIT_HACK) && 720 ((pte.raddr & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS)) 721 pte.raddr &= ~SPLIT_HACK_MASK; 722 fallthrough; 723 case MSR_IR: 724 vcpu->arch.mmu.esid_to_vsid(vcpu, eaddr >> SID_SHIFT, &vsid); 725 726 if ((kvmppc_get_msr(vcpu) & (MSR_DR|MSR_IR)) == MSR_DR) 727 pte.vpage |= ((u64)VSID_REAL_DR << (SID_SHIFT - 12)); 728 else 729 pte.vpage |= ((u64)VSID_REAL_IR << (SID_SHIFT - 12)); 730 pte.vpage |= vsid; 731 732 if (vsid == -1) 733 page_found = -EINVAL; 734 break; 735 } 736 737 if (vcpu->arch.mmu.is_dcbz32(vcpu) && 738 (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) { 739 /* 740 * If we do the dcbz hack, we have to NX on every execution, 741 * so we can patch the executing code. This renders our guest 742 * NX-less. 743 */ 744 pte.may_execute = !data; 745 } 746 747 if (page_found == -ENOENT || page_found == -EPERM) { 748 /* Page not found in guest PTE entries, or protection fault */ 749 u64 flags; 750 751 if (page_found == -EPERM) 752 flags = DSISR_PROTFAULT; 753 else 754 flags = DSISR_NOHPTE; 755 if (data) { 756 flags |= vcpu->arch.fault_dsisr & DSISR_ISSTORE; 757 kvmppc_core_queue_data_storage(vcpu, 0, eaddr, flags); 758 } else { 759 kvmppc_core_queue_inst_storage(vcpu, flags); 760 } 761 } else if (page_found == -EINVAL) { 762 /* Page not found in guest SLB */ 763 kvmppc_set_dar(vcpu, kvmppc_get_fault_dar(vcpu)); 764 kvmppc_book3s_queue_irqprio(vcpu, vec + 0x80); 765 } else if (kvmppc_visible_gpa(vcpu, pte.raddr)) { 766 if (data && !(vcpu->arch.fault_dsisr & DSISR_NOHPTE)) { 767 /* 768 * There is already a host HPTE there, presumably 769 * a read-only one for a page the guest thinks 770 * is writable, so get rid of it first. 771 */ 772 kvmppc_mmu_unmap_page(vcpu, &pte); 773 } 774 /* The guest's PTE is not mapped yet. Map on the host */ 775 if (kvmppc_mmu_map_page(vcpu, &pte, iswrite) == -EIO) { 776 /* Exit KVM if mapping failed */ 777 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 778 return RESUME_HOST; 779 } 780 if (data) 781 vcpu->stat.sp_storage++; 782 else if (vcpu->arch.mmu.is_dcbz32(vcpu) && 783 (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) 784 kvmppc_patch_dcbz(vcpu, &pte); 785 } else { 786 /* MMIO */ 787 vcpu->stat.mmio_exits++; 788 vcpu->arch.paddr_accessed = pte.raddr; 789 vcpu->arch.vaddr_accessed = pte.eaddr; 790 r = kvmppc_emulate_mmio(vcpu); 791 if ( r == RESUME_HOST_NV ) 792 r = RESUME_HOST; 793 } 794 795 return r; 796} 797 798/* Give up external provider (FPU, Altivec, VSX) */ 799void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr) 800{ 801 struct thread_struct *t = ¤t->thread; 802 803 /* 804 * VSX instructions can access FP and vector registers, so if 805 * we are giving up VSX, make sure we give up FP and VMX as well. 806 */ 807 if (msr & MSR_VSX) 808 msr |= MSR_FP | MSR_VEC; 809 810 msr &= vcpu->arch.guest_owned_ext; 811 if (!msr) 812 return; 813 814#ifdef DEBUG_EXT 815 printk(KERN_INFO "Giving up ext 0x%lx\n", msr); 816#endif 817 818 if (msr & MSR_FP) { 819 /* 820 * Note that on CPUs with VSX, giveup_fpu stores 821 * both the traditional FP registers and the added VSX 822 * registers into thread.fp_state.fpr[]. 823 */ 824 if (t->regs->msr & MSR_FP) 825 giveup_fpu(current); 826 t->fp_save_area = NULL; 827 } 828 829#ifdef CONFIG_ALTIVEC 830 if (msr & MSR_VEC) { 831 if (current->thread.regs->msr & MSR_VEC) 832 giveup_altivec(current); 833 t->vr_save_area = NULL; 834 } 835#endif 836 837 vcpu->arch.guest_owned_ext &= ~(msr | MSR_VSX); 838 kvmppc_recalc_shadow_msr(vcpu); 839} 840 841/* Give up facility (TAR / EBB / DSCR) */ 842void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac) 843{ 844#ifdef CONFIG_PPC_BOOK3S_64 845 if (!(vcpu->arch.shadow_fscr & (1ULL << fac))) { 846 /* Facility not available to the guest, ignore giveup request*/ 847 return; 848 } 849 850 switch (fac) { 851 case FSCR_TAR_LG: 852 vcpu->arch.tar = mfspr(SPRN_TAR); 853 mtspr(SPRN_TAR, current->thread.tar); 854 vcpu->arch.shadow_fscr &= ~FSCR_TAR; 855 break; 856 } 857#endif 858} 859 860/* Handle external providers (FPU, Altivec, VSX) */ 861static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr, 862 ulong msr) 863{ 864 struct thread_struct *t = ¤t->thread; 865 866 /* When we have paired singles, we emulate in software */ 867 if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) 868 return RESUME_GUEST; 869 870 if (!(kvmppc_get_msr(vcpu) & msr)) { 871 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 872 return RESUME_GUEST; 873 } 874 875 if (msr == MSR_VSX) { 876 /* No VSX? Give an illegal instruction interrupt */ 877#ifdef CONFIG_VSX 878 if (!cpu_has_feature(CPU_FTR_VSX)) 879#endif 880 { 881 kvmppc_core_queue_program(vcpu, SRR1_PROGILL); 882 return RESUME_GUEST; 883 } 884 885 /* 886 * We have to load up all the FP and VMX registers before 887 * we can let the guest use VSX instructions. 888 */ 889 msr = MSR_FP | MSR_VEC | MSR_VSX; 890 } 891 892 /* See if we already own all the ext(s) needed */ 893 msr &= ~vcpu->arch.guest_owned_ext; 894 if (!msr) 895 return RESUME_GUEST; 896 897#ifdef DEBUG_EXT 898 printk(KERN_INFO "Loading up ext 0x%lx\n", msr); 899#endif 900 901 if (msr & MSR_FP) { 902 preempt_disable(); 903 enable_kernel_fp(); 904 load_fp_state(&vcpu->arch.fp); 905 disable_kernel_fp(); 906 t->fp_save_area = &vcpu->arch.fp; 907 preempt_enable(); 908 } 909 910 if (msr & MSR_VEC) { 911#ifdef CONFIG_ALTIVEC 912 preempt_disable(); 913 enable_kernel_altivec(); 914 load_vr_state(&vcpu->arch.vr); 915 disable_kernel_altivec(); 916 t->vr_save_area = &vcpu->arch.vr; 917 preempt_enable(); 918#endif 919 } 920 921 t->regs->msr |= msr; 922 vcpu->arch.guest_owned_ext |= msr; 923 kvmppc_recalc_shadow_msr(vcpu); 924 925 return RESUME_GUEST; 926} 927 928/* 929 * Kernel code using FP or VMX could have flushed guest state to 930 * the thread_struct; if so, get it back now. 931 */ 932static void kvmppc_handle_lost_ext(struct kvm_vcpu *vcpu) 933{ 934 unsigned long lost_ext; 935 936 lost_ext = vcpu->arch.guest_owned_ext & ~current->thread.regs->msr; 937 if (!lost_ext) 938 return; 939 940 if (lost_ext & MSR_FP) { 941 preempt_disable(); 942 enable_kernel_fp(); 943 load_fp_state(&vcpu->arch.fp); 944 disable_kernel_fp(); 945 preempt_enable(); 946 } 947#ifdef CONFIG_ALTIVEC 948 if (lost_ext & MSR_VEC) { 949 preempt_disable(); 950 enable_kernel_altivec(); 951 load_vr_state(&vcpu->arch.vr); 952 disable_kernel_altivec(); 953 preempt_enable(); 954 } 955#endif 956 current->thread.regs->msr |= lost_ext; 957} 958 959#ifdef CONFIG_PPC_BOOK3S_64 960 961void kvmppc_trigger_fac_interrupt(struct kvm_vcpu *vcpu, ulong fac) 962{ 963 /* Inject the Interrupt Cause field and trigger a guest interrupt */ 964 vcpu->arch.fscr &= ~(0xffULL << 56); 965 vcpu->arch.fscr |= (fac << 56); 966 kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_FAC_UNAVAIL); 967} 968 969static void kvmppc_emulate_fac(struct kvm_vcpu *vcpu, ulong fac) 970{ 971 enum emulation_result er = EMULATE_FAIL; 972 973 if (!(kvmppc_get_msr(vcpu) & MSR_PR)) 974 er = kvmppc_emulate_instruction(vcpu); 975 976 if ((er != EMULATE_DONE) && (er != EMULATE_AGAIN)) { 977 /* Couldn't emulate, trigger interrupt in guest */ 978 kvmppc_trigger_fac_interrupt(vcpu, fac); 979 } 980} 981 982/* Enable facilities (TAR, EBB, DSCR) for the guest */ 983static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac) 984{ 985 bool guest_fac_enabled; 986 BUG_ON(!cpu_has_feature(CPU_FTR_ARCH_207S)); 987 988 /* 989 * Not every facility is enabled by FSCR bits, check whether the 990 * guest has this facility enabled at all. 991 */ 992 switch (fac) { 993 case FSCR_TAR_LG: 994 case FSCR_EBB_LG: 995 guest_fac_enabled = (vcpu->arch.fscr & (1ULL << fac)); 996 break; 997 case FSCR_TM_LG: 998 guest_fac_enabled = kvmppc_get_msr(vcpu) & MSR_TM; 999 break; 1000 default: 1001 guest_fac_enabled = false; 1002 break; 1003 } 1004 1005 if (!guest_fac_enabled) { 1006 /* Facility not enabled by the guest */ 1007 kvmppc_trigger_fac_interrupt(vcpu, fac); 1008 return RESUME_GUEST; 1009 } 1010 1011 switch (fac) { 1012 case FSCR_TAR_LG: 1013 /* TAR switching isn't lazy in Linux yet */ 1014 current->thread.tar = mfspr(SPRN_TAR); 1015 mtspr(SPRN_TAR, vcpu->arch.tar); 1016 vcpu->arch.shadow_fscr |= FSCR_TAR; 1017 break; 1018 default: 1019 kvmppc_emulate_fac(vcpu, fac); 1020 break; 1021 } 1022 1023#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1024 /* Since we disabled MSR_TM at privilege state, the mfspr instruction 1025 * for TM spr can trigger TM fac unavailable. In this case, the 1026 * emulation is handled by kvmppc_emulate_fac(), which invokes 1027 * kvmppc_emulate_mfspr() finally. But note the mfspr can include 1028 * RT for NV registers. So it need to restore those NV reg to reflect 1029 * the update. 1030 */ 1031 if ((fac == FSCR_TM_LG) && !(kvmppc_get_msr(vcpu) & MSR_PR)) 1032 return RESUME_GUEST_NV; 1033#endif 1034 1035 return RESUME_GUEST; 1036} 1037 1038void kvmppc_set_fscr(struct kvm_vcpu *vcpu, u64 fscr) 1039{ 1040 if (fscr & FSCR_SCV) 1041 fscr &= ~FSCR_SCV; /* SCV must not be enabled */ 1042 /* Prohibit prefixed instructions for now */ 1043 fscr &= ~FSCR_PREFIX; 1044 if ((vcpu->arch.fscr & FSCR_TAR) && !(fscr & FSCR_TAR)) { 1045 /* TAR got dropped, drop it in shadow too */ 1046 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 1047 } else if (!(vcpu->arch.fscr & FSCR_TAR) && (fscr & FSCR_TAR)) { 1048 vcpu->arch.fscr = fscr; 1049 kvmppc_handle_fac(vcpu, FSCR_TAR_LG); 1050 return; 1051 } 1052 1053 vcpu->arch.fscr = fscr; 1054} 1055#endif 1056 1057static void kvmppc_setup_debug(struct kvm_vcpu *vcpu) 1058{ 1059 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 1060 u64 msr = kvmppc_get_msr(vcpu); 1061 1062 kvmppc_set_msr(vcpu, msr | MSR_SE); 1063 } 1064} 1065 1066static void kvmppc_clear_debug(struct kvm_vcpu *vcpu) 1067{ 1068 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 1069 u64 msr = kvmppc_get_msr(vcpu); 1070 1071 kvmppc_set_msr(vcpu, msr & ~MSR_SE); 1072 } 1073} 1074 1075static int kvmppc_exit_pr_progint(struct kvm_vcpu *vcpu, unsigned int exit_nr) 1076{ 1077 enum emulation_result er; 1078 ulong flags; 1079 ppc_inst_t last_inst; 1080 int emul, r; 1081 1082 /* 1083 * shadow_srr1 only contains valid flags if we came here via a program 1084 * exception. The other exceptions (emulation assist, FP unavailable, 1085 * etc.) do not provide flags in SRR1, so use an illegal-instruction 1086 * exception when injecting a program interrupt into the guest. 1087 */ 1088 if (exit_nr == BOOK3S_INTERRUPT_PROGRAM) 1089 flags = vcpu->arch.shadow_srr1 & 0x1f0000ull; 1090 else 1091 flags = SRR1_PROGILL; 1092 1093 emul = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst); 1094 if (emul != EMULATE_DONE) 1095 return RESUME_GUEST; 1096 1097 if (kvmppc_get_msr(vcpu) & MSR_PR) { 1098#ifdef EXIT_DEBUG 1099 pr_info("Userspace triggered 0x700 exception at\n 0x%lx (0x%x)\n", 1100 kvmppc_get_pc(vcpu), ppc_inst_val(last_inst)); 1101#endif 1102 if ((ppc_inst_val(last_inst) & 0xff0007ff) != (INS_DCBZ & 0xfffffff7)) { 1103 kvmppc_core_queue_program(vcpu, flags); 1104 return RESUME_GUEST; 1105 } 1106 } 1107 1108 vcpu->stat.emulated_inst_exits++; 1109 er = kvmppc_emulate_instruction(vcpu); 1110 switch (er) { 1111 case EMULATE_DONE: 1112 r = RESUME_GUEST_NV; 1113 break; 1114 case EMULATE_AGAIN: 1115 r = RESUME_GUEST; 1116 break; 1117 case EMULATE_FAIL: 1118 pr_crit("%s: emulation at %lx failed (%08x)\n", 1119 __func__, kvmppc_get_pc(vcpu), ppc_inst_val(last_inst)); 1120 kvmppc_core_queue_program(vcpu, flags); 1121 r = RESUME_GUEST; 1122 break; 1123 case EMULATE_DO_MMIO: 1124 vcpu->run->exit_reason = KVM_EXIT_MMIO; 1125 r = RESUME_HOST_NV; 1126 break; 1127 case EMULATE_EXIT_USER: 1128 r = RESUME_HOST_NV; 1129 break; 1130 default: 1131 BUG(); 1132 } 1133 1134 return r; 1135} 1136 1137int kvmppc_handle_exit_pr(struct kvm_vcpu *vcpu, unsigned int exit_nr) 1138{ 1139 struct kvm_run *run = vcpu->run; 1140 int r = RESUME_HOST; 1141 int s; 1142 1143 vcpu->stat.sum_exits++; 1144 1145 run->exit_reason = KVM_EXIT_UNKNOWN; 1146 run->ready_for_interrupt_injection = 1; 1147 1148 /* We get here with MSR.EE=1 */ 1149 1150 trace_kvm_exit(exit_nr, vcpu); 1151 guest_exit(); 1152 1153 switch (exit_nr) { 1154 case BOOK3S_INTERRUPT_INST_STORAGE: 1155 { 1156 ulong shadow_srr1 = vcpu->arch.shadow_srr1; 1157 vcpu->stat.pf_instruc++; 1158 1159 if (kvmppc_is_split_real(vcpu)) 1160 kvmppc_fixup_split_real(vcpu); 1161 1162#ifdef CONFIG_PPC_BOOK3S_32 1163 /* We set segments as unused segments when invalidating them. So 1164 * treat the respective fault as segment fault. */ 1165 { 1166 struct kvmppc_book3s_shadow_vcpu *svcpu; 1167 u32 sr; 1168 1169 svcpu = svcpu_get(vcpu); 1170 sr = svcpu->sr[kvmppc_get_pc(vcpu) >> SID_SHIFT]; 1171 svcpu_put(svcpu); 1172 if (sr == SR_INVALID) { 1173 kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)); 1174 r = RESUME_GUEST; 1175 break; 1176 } 1177 } 1178#endif 1179 1180 /* only care about PTEG not found errors, but leave NX alone */ 1181 if (shadow_srr1 & 0x40000000) { 1182 int idx = srcu_read_lock(&vcpu->kvm->srcu); 1183 r = kvmppc_handle_pagefault(vcpu, kvmppc_get_pc(vcpu), exit_nr); 1184 srcu_read_unlock(&vcpu->kvm->srcu, idx); 1185 vcpu->stat.sp_instruc++; 1186 } else if (vcpu->arch.mmu.is_dcbz32(vcpu) && 1187 (!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) { 1188 /* 1189 * XXX If we do the dcbz hack we use the NX bit to flush&patch the page, 1190 * so we can't use the NX bit inside the guest. Let's cross our fingers, 1191 * that no guest that needs the dcbz hack does NX. 1192 */ 1193 kvmppc_mmu_pte_flush(vcpu, kvmppc_get_pc(vcpu), ~0xFFFUL); 1194 r = RESUME_GUEST; 1195 } else { 1196 kvmppc_core_queue_inst_storage(vcpu, 1197 shadow_srr1 & 0x58000000); 1198 r = RESUME_GUEST; 1199 } 1200 break; 1201 } 1202 case BOOK3S_INTERRUPT_DATA_STORAGE: 1203 { 1204 ulong dar = kvmppc_get_fault_dar(vcpu); 1205 u32 fault_dsisr = vcpu->arch.fault_dsisr; 1206 vcpu->stat.pf_storage++; 1207 1208#ifdef CONFIG_PPC_BOOK3S_32 1209 /* We set segments as unused segments when invalidating them. So 1210 * treat the respective fault as segment fault. */ 1211 { 1212 struct kvmppc_book3s_shadow_vcpu *svcpu; 1213 u32 sr; 1214 1215 svcpu = svcpu_get(vcpu); 1216 sr = svcpu->sr[dar >> SID_SHIFT]; 1217 svcpu_put(svcpu); 1218 if (sr == SR_INVALID) { 1219 kvmppc_mmu_map_segment(vcpu, dar); 1220 r = RESUME_GUEST; 1221 break; 1222 } 1223 } 1224#endif 1225 1226 /* 1227 * We need to handle missing shadow PTEs, and 1228 * protection faults due to us mapping a page read-only 1229 * when the guest thinks it is writable. 1230 */ 1231 if (fault_dsisr & (DSISR_NOHPTE | DSISR_PROTFAULT)) { 1232 int idx = srcu_read_lock(&vcpu->kvm->srcu); 1233 r = kvmppc_handle_pagefault(vcpu, dar, exit_nr); 1234 srcu_read_unlock(&vcpu->kvm->srcu, idx); 1235 } else { 1236 kvmppc_core_queue_data_storage(vcpu, 0, dar, fault_dsisr); 1237 r = RESUME_GUEST; 1238 } 1239 break; 1240 } 1241 case BOOK3S_INTERRUPT_DATA_SEGMENT: 1242 if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_fault_dar(vcpu)) < 0) { 1243 kvmppc_set_dar(vcpu, kvmppc_get_fault_dar(vcpu)); 1244 kvmppc_book3s_queue_irqprio(vcpu, 1245 BOOK3S_INTERRUPT_DATA_SEGMENT); 1246 } 1247 r = RESUME_GUEST; 1248 break; 1249 case BOOK3S_INTERRUPT_INST_SEGMENT: 1250 if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)) < 0) { 1251 kvmppc_book3s_queue_irqprio(vcpu, 1252 BOOK3S_INTERRUPT_INST_SEGMENT); 1253 } 1254 r = RESUME_GUEST; 1255 break; 1256 /* We're good on these - the host merely wanted to get our attention */ 1257 case BOOK3S_INTERRUPT_DECREMENTER: 1258 case BOOK3S_INTERRUPT_HV_DECREMENTER: 1259 case BOOK3S_INTERRUPT_DOORBELL: 1260 case BOOK3S_INTERRUPT_H_DOORBELL: 1261 vcpu->stat.dec_exits++; 1262 r = RESUME_GUEST; 1263 break; 1264 case BOOK3S_INTERRUPT_EXTERNAL: 1265 case BOOK3S_INTERRUPT_EXTERNAL_HV: 1266 case BOOK3S_INTERRUPT_H_VIRT: 1267 vcpu->stat.ext_intr_exits++; 1268 r = RESUME_GUEST; 1269 break; 1270 case BOOK3S_INTERRUPT_HMI: 1271 case BOOK3S_INTERRUPT_PERFMON: 1272 case BOOK3S_INTERRUPT_SYSTEM_RESET: 1273 r = RESUME_GUEST; 1274 break; 1275 case BOOK3S_INTERRUPT_PROGRAM: 1276 case BOOK3S_INTERRUPT_H_EMUL_ASSIST: 1277 r = kvmppc_exit_pr_progint(vcpu, exit_nr); 1278 break; 1279 case BOOK3S_INTERRUPT_SYSCALL: 1280 { 1281 ppc_inst_t last_sc; 1282 int emul; 1283 1284 /* Get last sc for papr */ 1285 if (vcpu->arch.papr_enabled) { 1286 /* The sc instruction points SRR0 to the next inst */ 1287 emul = kvmppc_get_last_inst(vcpu, INST_SC, &last_sc); 1288 if (emul != EMULATE_DONE) { 1289 kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) - 4); 1290 r = RESUME_GUEST; 1291 break; 1292 } 1293 } 1294 1295 if (vcpu->arch.papr_enabled && 1296 (ppc_inst_val(last_sc) == 0x44000022) && 1297 !(kvmppc_get_msr(vcpu) & MSR_PR)) { 1298 /* SC 1 papr hypercalls */ 1299 ulong cmd = kvmppc_get_gpr(vcpu, 3); 1300 int i; 1301 1302#ifdef CONFIG_PPC_BOOK3S_64 1303 if (kvmppc_h_pr(vcpu, cmd) == EMULATE_DONE) { 1304 r = RESUME_GUEST; 1305 break; 1306 } 1307#endif 1308 1309 run->papr_hcall.nr = cmd; 1310 for (i = 0; i < 9; ++i) { 1311 ulong gpr = kvmppc_get_gpr(vcpu, 4 + i); 1312 run->papr_hcall.args[i] = gpr; 1313 } 1314 run->exit_reason = KVM_EXIT_PAPR_HCALL; 1315 vcpu->arch.hcall_needed = 1; 1316 r = RESUME_HOST; 1317 } else if (vcpu->arch.osi_enabled && 1318 (((u32)kvmppc_get_gpr(vcpu, 3)) == OSI_SC_MAGIC_R3) && 1319 (((u32)kvmppc_get_gpr(vcpu, 4)) == OSI_SC_MAGIC_R4)) { 1320 /* MOL hypercalls */ 1321 u64 *gprs = run->osi.gprs; 1322 int i; 1323 1324 run->exit_reason = KVM_EXIT_OSI; 1325 for (i = 0; i < 32; i++) 1326 gprs[i] = kvmppc_get_gpr(vcpu, i); 1327 vcpu->arch.osi_needed = 1; 1328 r = RESUME_HOST_NV; 1329 } else if (!(kvmppc_get_msr(vcpu) & MSR_PR) && 1330 (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) { 1331 /* KVM PV hypercalls */ 1332 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu)); 1333 r = RESUME_GUEST; 1334 } else { 1335 /* Guest syscalls */ 1336 vcpu->stat.syscall_exits++; 1337 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 1338 r = RESUME_GUEST; 1339 } 1340 break; 1341 } 1342 case BOOK3S_INTERRUPT_FP_UNAVAIL: 1343 case BOOK3S_INTERRUPT_ALTIVEC: 1344 case BOOK3S_INTERRUPT_VSX: 1345 { 1346 int ext_msr = 0; 1347 int emul; 1348 ppc_inst_t last_inst; 1349 1350 if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) { 1351 /* Do paired single instruction emulation */ 1352 emul = kvmppc_get_last_inst(vcpu, INST_GENERIC, 1353 &last_inst); 1354 if (emul == EMULATE_DONE) 1355 r = kvmppc_exit_pr_progint(vcpu, exit_nr); 1356 else 1357 r = RESUME_GUEST; 1358 1359 break; 1360 } 1361 1362 /* Enable external provider */ 1363 switch (exit_nr) { 1364 case BOOK3S_INTERRUPT_FP_UNAVAIL: 1365 ext_msr = MSR_FP; 1366 break; 1367 1368 case BOOK3S_INTERRUPT_ALTIVEC: 1369 ext_msr = MSR_VEC; 1370 break; 1371 1372 case BOOK3S_INTERRUPT_VSX: 1373 ext_msr = MSR_VSX; 1374 break; 1375 } 1376 1377 r = kvmppc_handle_ext(vcpu, exit_nr, ext_msr); 1378 break; 1379 } 1380 case BOOK3S_INTERRUPT_ALIGNMENT: 1381 { 1382 ppc_inst_t last_inst; 1383 int emul = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst); 1384 1385 if (emul == EMULATE_DONE) { 1386 u32 dsisr; 1387 u64 dar; 1388 1389 dsisr = kvmppc_alignment_dsisr(vcpu, ppc_inst_val(last_inst)); 1390 dar = kvmppc_alignment_dar(vcpu, ppc_inst_val(last_inst)); 1391 1392 kvmppc_set_dsisr(vcpu, dsisr); 1393 kvmppc_set_dar(vcpu, dar); 1394 1395 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 1396 } 1397 r = RESUME_GUEST; 1398 break; 1399 } 1400#ifdef CONFIG_PPC_BOOK3S_64 1401 case BOOK3S_INTERRUPT_FAC_UNAVAIL: 1402 r = kvmppc_handle_fac(vcpu, vcpu->arch.shadow_fscr >> 56); 1403 break; 1404#endif 1405 case BOOK3S_INTERRUPT_MACHINE_CHECK: 1406 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 1407 r = RESUME_GUEST; 1408 break; 1409 case BOOK3S_INTERRUPT_TRACE: 1410 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 1411 run->exit_reason = KVM_EXIT_DEBUG; 1412 r = RESUME_HOST; 1413 } else { 1414 kvmppc_book3s_queue_irqprio(vcpu, exit_nr); 1415 r = RESUME_GUEST; 1416 } 1417 break; 1418 default: 1419 { 1420 ulong shadow_srr1 = vcpu->arch.shadow_srr1; 1421 /* Ugh - bork here! What did we get? */ 1422 printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | msr=0x%lx\n", 1423 exit_nr, kvmppc_get_pc(vcpu), shadow_srr1); 1424 r = RESUME_HOST; 1425 BUG(); 1426 break; 1427 } 1428 } 1429 1430 if (!(r & RESUME_HOST)) { 1431 /* To avoid clobbering exit_reason, only check for signals if 1432 * we aren't already exiting to userspace for some other 1433 * reason. */ 1434 1435 /* 1436 * Interrupts could be timers for the guest which we have to 1437 * inject again, so let's postpone them until we're in the guest 1438 * and if we really did time things so badly, then we just exit 1439 * again due to a host external interrupt. 1440 */ 1441 s = kvmppc_prepare_to_enter(vcpu); 1442 if (s <= 0) 1443 r = s; 1444 else { 1445 /* interrupts now hard-disabled */ 1446 kvmppc_fix_ee_before_entry(); 1447 } 1448 1449 kvmppc_handle_lost_ext(vcpu); 1450 } 1451 1452 trace_kvm_book3s_reenter(r, vcpu); 1453 1454 return r; 1455} 1456 1457static int kvm_arch_vcpu_ioctl_get_sregs_pr(struct kvm_vcpu *vcpu, 1458 struct kvm_sregs *sregs) 1459{ 1460 struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); 1461 int i; 1462 1463 sregs->pvr = vcpu->arch.pvr; 1464 1465 sregs->u.s.sdr1 = to_book3s(vcpu)->sdr1; 1466 if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) { 1467 for (i = 0; i < 64; i++) { 1468 sregs->u.s.ppc64.slb[i].slbe = vcpu->arch.slb[i].orige | i; 1469 sregs->u.s.ppc64.slb[i].slbv = vcpu->arch.slb[i].origv; 1470 } 1471 } else { 1472 for (i = 0; i < 16; i++) 1473 sregs->u.s.ppc32.sr[i] = kvmppc_get_sr(vcpu, i); 1474 1475 for (i = 0; i < 8; i++) { 1476 sregs->u.s.ppc32.ibat[i] = vcpu3s->ibat[i].raw; 1477 sregs->u.s.ppc32.dbat[i] = vcpu3s->dbat[i].raw; 1478 } 1479 } 1480 1481 return 0; 1482} 1483 1484static int kvm_arch_vcpu_ioctl_set_sregs_pr(struct kvm_vcpu *vcpu, 1485 struct kvm_sregs *sregs) 1486{ 1487 struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu); 1488 int i; 1489 1490 kvmppc_set_pvr_pr(vcpu, sregs->pvr); 1491 1492 vcpu3s->sdr1 = sregs->u.s.sdr1; 1493#ifdef CONFIG_PPC_BOOK3S_64 1494 if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) { 1495 /* Flush all SLB entries */ 1496 vcpu->arch.mmu.slbmte(vcpu, 0, 0); 1497 vcpu->arch.mmu.slbia(vcpu); 1498 1499 for (i = 0; i < 64; i++) { 1500 u64 rb = sregs->u.s.ppc64.slb[i].slbe; 1501 u64 rs = sregs->u.s.ppc64.slb[i].slbv; 1502 1503 if (rb & SLB_ESID_V) 1504 vcpu->arch.mmu.slbmte(vcpu, rs, rb); 1505 } 1506 } else 1507#endif 1508 { 1509 for (i = 0; i < 16; i++) { 1510 vcpu->arch.mmu.mtsrin(vcpu, i, sregs->u.s.ppc32.sr[i]); 1511 } 1512 for (i = 0; i < 8; i++) { 1513 kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), false, 1514 (u32)sregs->u.s.ppc32.ibat[i]); 1515 kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), true, 1516 (u32)(sregs->u.s.ppc32.ibat[i] >> 32)); 1517 kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), false, 1518 (u32)sregs->u.s.ppc32.dbat[i]); 1519 kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), true, 1520 (u32)(sregs->u.s.ppc32.dbat[i] >> 32)); 1521 } 1522 } 1523 1524 /* Flush the MMU after messing with the segments */ 1525 kvmppc_mmu_pte_flush(vcpu, 0, 0); 1526 1527 return 0; 1528} 1529 1530static int kvmppc_get_one_reg_pr(struct kvm_vcpu *vcpu, u64 id, 1531 union kvmppc_one_reg *val) 1532{ 1533 int r = 0; 1534 1535 switch (id) { 1536 case KVM_REG_PPC_DEBUG_INST: 1537 *val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT); 1538 break; 1539 case KVM_REG_PPC_HIOR: 1540 *val = get_reg_val(id, to_book3s(vcpu)->hior); 1541 break; 1542 case KVM_REG_PPC_VTB: 1543 *val = get_reg_val(id, to_book3s(vcpu)->vtb); 1544 break; 1545 case KVM_REG_PPC_LPCR: 1546 case KVM_REG_PPC_LPCR_64: 1547 /* 1548 * We are only interested in the LPCR_ILE bit 1549 */ 1550 if (vcpu->arch.intr_msr & MSR_LE) 1551 *val = get_reg_val(id, LPCR_ILE); 1552 else 1553 *val = get_reg_val(id, 0); 1554 break; 1555#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1556 case KVM_REG_PPC_TFHAR: 1557 *val = get_reg_val(id, vcpu->arch.tfhar); 1558 break; 1559 case KVM_REG_PPC_TFIAR: 1560 *val = get_reg_val(id, vcpu->arch.tfiar); 1561 break; 1562 case KVM_REG_PPC_TEXASR: 1563 *val = get_reg_val(id, vcpu->arch.texasr); 1564 break; 1565 case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31: 1566 *val = get_reg_val(id, 1567 vcpu->arch.gpr_tm[id-KVM_REG_PPC_TM_GPR0]); 1568 break; 1569 case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63: 1570 { 1571 int i, j; 1572 1573 i = id - KVM_REG_PPC_TM_VSR0; 1574 if (i < 32) 1575 for (j = 0; j < TS_FPRWIDTH; j++) 1576 val->vsxval[j] = vcpu->arch.fp_tm.fpr[i][j]; 1577 else { 1578 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1579 val->vval = vcpu->arch.vr_tm.vr[i-32]; 1580 else 1581 r = -ENXIO; 1582 } 1583 break; 1584 } 1585 case KVM_REG_PPC_TM_CR: 1586 *val = get_reg_val(id, vcpu->arch.cr_tm); 1587 break; 1588 case KVM_REG_PPC_TM_XER: 1589 *val = get_reg_val(id, vcpu->arch.xer_tm); 1590 break; 1591 case KVM_REG_PPC_TM_LR: 1592 *val = get_reg_val(id, vcpu->arch.lr_tm); 1593 break; 1594 case KVM_REG_PPC_TM_CTR: 1595 *val = get_reg_val(id, vcpu->arch.ctr_tm); 1596 break; 1597 case KVM_REG_PPC_TM_FPSCR: 1598 *val = get_reg_val(id, vcpu->arch.fp_tm.fpscr); 1599 break; 1600 case KVM_REG_PPC_TM_AMR: 1601 *val = get_reg_val(id, vcpu->arch.amr_tm); 1602 break; 1603 case KVM_REG_PPC_TM_PPR: 1604 *val = get_reg_val(id, vcpu->arch.ppr_tm); 1605 break; 1606 case KVM_REG_PPC_TM_VRSAVE: 1607 *val = get_reg_val(id, vcpu->arch.vrsave_tm); 1608 break; 1609 case KVM_REG_PPC_TM_VSCR: 1610 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1611 *val = get_reg_val(id, vcpu->arch.vr_tm.vscr.u[3]); 1612 else 1613 r = -ENXIO; 1614 break; 1615 case KVM_REG_PPC_TM_DSCR: 1616 *val = get_reg_val(id, vcpu->arch.dscr_tm); 1617 break; 1618 case KVM_REG_PPC_TM_TAR: 1619 *val = get_reg_val(id, vcpu->arch.tar_tm); 1620 break; 1621#endif 1622 default: 1623 r = -EINVAL; 1624 break; 1625 } 1626 1627 return r; 1628} 1629 1630static void kvmppc_set_lpcr_pr(struct kvm_vcpu *vcpu, u64 new_lpcr) 1631{ 1632 if (new_lpcr & LPCR_ILE) 1633 vcpu->arch.intr_msr |= MSR_LE; 1634 else 1635 vcpu->arch.intr_msr &= ~MSR_LE; 1636} 1637 1638static int kvmppc_set_one_reg_pr(struct kvm_vcpu *vcpu, u64 id, 1639 union kvmppc_one_reg *val) 1640{ 1641 int r = 0; 1642 1643 switch (id) { 1644 case KVM_REG_PPC_HIOR: 1645 to_book3s(vcpu)->hior = set_reg_val(id, *val); 1646 to_book3s(vcpu)->hior_explicit = true; 1647 break; 1648 case KVM_REG_PPC_VTB: 1649 to_book3s(vcpu)->vtb = set_reg_val(id, *val); 1650 break; 1651 case KVM_REG_PPC_LPCR: 1652 case KVM_REG_PPC_LPCR_64: 1653 kvmppc_set_lpcr_pr(vcpu, set_reg_val(id, *val)); 1654 break; 1655#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1656 case KVM_REG_PPC_TFHAR: 1657 vcpu->arch.tfhar = set_reg_val(id, *val); 1658 break; 1659 case KVM_REG_PPC_TFIAR: 1660 vcpu->arch.tfiar = set_reg_val(id, *val); 1661 break; 1662 case KVM_REG_PPC_TEXASR: 1663 vcpu->arch.texasr = set_reg_val(id, *val); 1664 break; 1665 case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31: 1666 vcpu->arch.gpr_tm[id - KVM_REG_PPC_TM_GPR0] = 1667 set_reg_val(id, *val); 1668 break; 1669 case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63: 1670 { 1671 int i, j; 1672 1673 i = id - KVM_REG_PPC_TM_VSR0; 1674 if (i < 32) 1675 for (j = 0; j < TS_FPRWIDTH; j++) 1676 vcpu->arch.fp_tm.fpr[i][j] = val->vsxval[j]; 1677 else 1678 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1679 vcpu->arch.vr_tm.vr[i-32] = val->vval; 1680 else 1681 r = -ENXIO; 1682 break; 1683 } 1684 case KVM_REG_PPC_TM_CR: 1685 vcpu->arch.cr_tm = set_reg_val(id, *val); 1686 break; 1687 case KVM_REG_PPC_TM_XER: 1688 vcpu->arch.xer_tm = set_reg_val(id, *val); 1689 break; 1690 case KVM_REG_PPC_TM_LR: 1691 vcpu->arch.lr_tm = set_reg_val(id, *val); 1692 break; 1693 case KVM_REG_PPC_TM_CTR: 1694 vcpu->arch.ctr_tm = set_reg_val(id, *val); 1695 break; 1696 case KVM_REG_PPC_TM_FPSCR: 1697 vcpu->arch.fp_tm.fpscr = set_reg_val(id, *val); 1698 break; 1699 case KVM_REG_PPC_TM_AMR: 1700 vcpu->arch.amr_tm = set_reg_val(id, *val); 1701 break; 1702 case KVM_REG_PPC_TM_PPR: 1703 vcpu->arch.ppr_tm = set_reg_val(id, *val); 1704 break; 1705 case KVM_REG_PPC_TM_VRSAVE: 1706 vcpu->arch.vrsave_tm = set_reg_val(id, *val); 1707 break; 1708 case KVM_REG_PPC_TM_VSCR: 1709 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 1710 vcpu->arch.vr.vscr.u[3] = set_reg_val(id, *val); 1711 else 1712 r = -ENXIO; 1713 break; 1714 case KVM_REG_PPC_TM_DSCR: 1715 vcpu->arch.dscr_tm = set_reg_val(id, *val); 1716 break; 1717 case KVM_REG_PPC_TM_TAR: 1718 vcpu->arch.tar_tm = set_reg_val(id, *val); 1719 break; 1720#endif 1721 default: 1722 r = -EINVAL; 1723 break; 1724 } 1725 1726 return r; 1727} 1728 1729static int kvmppc_core_vcpu_create_pr(struct kvm_vcpu *vcpu) 1730{ 1731 struct kvmppc_vcpu_book3s *vcpu_book3s; 1732 unsigned long p; 1733 int err; 1734 1735 err = -ENOMEM; 1736 1737 vcpu_book3s = vzalloc(sizeof(struct kvmppc_vcpu_book3s)); 1738 if (!vcpu_book3s) 1739 goto out; 1740 vcpu->arch.book3s = vcpu_book3s; 1741 1742#ifdef CONFIG_KVM_BOOK3S_32_HANDLER 1743 vcpu->arch.shadow_vcpu = 1744 kzalloc(sizeof(*vcpu->arch.shadow_vcpu), GFP_KERNEL); 1745 if (!vcpu->arch.shadow_vcpu) 1746 goto free_vcpu3s; 1747#endif 1748 1749 p = __get_free_page(GFP_KERNEL|__GFP_ZERO); 1750 if (!p) 1751 goto free_shadow_vcpu; 1752 vcpu->arch.shared = (void *)p; 1753#ifdef CONFIG_PPC_BOOK3S_64 1754 /* Always start the shared struct in native endian mode */ 1755#ifdef __BIG_ENDIAN__ 1756 vcpu->arch.shared_big_endian = true; 1757#else 1758 vcpu->arch.shared_big_endian = false; 1759#endif 1760 1761 /* 1762 * Default to the same as the host if we're on sufficiently 1763 * recent machine that we have 1TB segments; 1764 * otherwise default to PPC970FX. 1765 */ 1766 vcpu->arch.pvr = 0x3C0301; 1767 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 1768 vcpu->arch.pvr = mfspr(SPRN_PVR); 1769 vcpu->arch.intr_msr = MSR_SF; 1770#else 1771 /* default to book3s_32 (750) */ 1772 vcpu->arch.pvr = 0x84202; 1773 vcpu->arch.intr_msr = 0; 1774#endif 1775 kvmppc_set_pvr_pr(vcpu, vcpu->arch.pvr); 1776 vcpu->arch.slb_nr = 64; 1777 1778 vcpu->arch.shadow_msr = MSR_USER64 & ~MSR_LE; 1779 1780 err = kvmppc_mmu_init_pr(vcpu); 1781 if (err < 0) 1782 goto free_shared_page; 1783 1784 return 0; 1785 1786free_shared_page: 1787 free_page((unsigned long)vcpu->arch.shared); 1788free_shadow_vcpu: 1789#ifdef CONFIG_KVM_BOOK3S_32_HANDLER 1790 kfree(vcpu->arch.shadow_vcpu); 1791free_vcpu3s: 1792#endif 1793 vfree(vcpu_book3s); 1794out: 1795 return err; 1796} 1797 1798static void kvmppc_core_vcpu_free_pr(struct kvm_vcpu *vcpu) 1799{ 1800 struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); 1801 1802 kvmppc_mmu_destroy_pr(vcpu); 1803 free_page((unsigned long)vcpu->arch.shared & PAGE_MASK); 1804#ifdef CONFIG_KVM_BOOK3S_32_HANDLER 1805 kfree(vcpu->arch.shadow_vcpu); 1806#endif 1807 vfree(vcpu_book3s); 1808} 1809 1810static int kvmppc_vcpu_run_pr(struct kvm_vcpu *vcpu) 1811{ 1812 int ret; 1813 1814 /* Check if we can run the vcpu at all */ 1815 if (!vcpu->arch.sane) { 1816 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1817 ret = -EINVAL; 1818 goto out; 1819 } 1820 1821 kvmppc_setup_debug(vcpu); 1822 1823 /* 1824 * Interrupts could be timers for the guest which we have to inject 1825 * again, so let's postpone them until we're in the guest and if we 1826 * really did time things so badly, then we just exit again due to 1827 * a host external interrupt. 1828 */ 1829 ret = kvmppc_prepare_to_enter(vcpu); 1830 if (ret <= 0) 1831 goto out; 1832 /* interrupts now hard-disabled */ 1833 1834 /* Save FPU, Altivec and VSX state */ 1835 giveup_all(current); 1836 1837 /* Preload FPU if it's enabled */ 1838 if (kvmppc_get_msr(vcpu) & MSR_FP) 1839 kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP); 1840 1841 kvmppc_fix_ee_before_entry(); 1842 1843 ret = __kvmppc_vcpu_run(vcpu); 1844 1845 kvmppc_clear_debug(vcpu); 1846 1847 /* No need for guest_exit. It's done in handle_exit. 1848 We also get here with interrupts enabled. */ 1849 1850 /* Make sure we save the guest FPU/Altivec/VSX state */ 1851 kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX); 1852 1853 /* Make sure we save the guest TAR/EBB/DSCR state */ 1854 kvmppc_giveup_fac(vcpu, FSCR_TAR_LG); 1855 1856 srr_regs_clobbered(); 1857out: 1858 vcpu->mode = OUTSIDE_GUEST_MODE; 1859 return ret; 1860} 1861 1862/* 1863 * Get (and clear) the dirty memory log for a memory slot. 1864 */ 1865static int kvm_vm_ioctl_get_dirty_log_pr(struct kvm *kvm, 1866 struct kvm_dirty_log *log) 1867{ 1868 struct kvm_memory_slot *memslot; 1869 struct kvm_vcpu *vcpu; 1870 ulong ga, ga_end; 1871 int is_dirty = 0; 1872 int r; 1873 unsigned long n; 1874 1875 mutex_lock(&kvm->slots_lock); 1876 1877 r = kvm_get_dirty_log(kvm, log, &is_dirty, &memslot); 1878 if (r) 1879 goto out; 1880 1881 /* If nothing is dirty, don't bother messing with page tables. */ 1882 if (is_dirty) { 1883 ga = memslot->base_gfn << PAGE_SHIFT; 1884 ga_end = ga + (memslot->npages << PAGE_SHIFT); 1885 1886 kvm_for_each_vcpu(n, vcpu, kvm) 1887 kvmppc_mmu_pte_pflush(vcpu, ga, ga_end); 1888 1889 n = kvm_dirty_bitmap_bytes(memslot); 1890 memset(memslot->dirty_bitmap, 0, n); 1891 } 1892 1893 r = 0; 1894out: 1895 mutex_unlock(&kvm->slots_lock); 1896 return r; 1897} 1898 1899static void kvmppc_core_flush_memslot_pr(struct kvm *kvm, 1900 struct kvm_memory_slot *memslot) 1901{ 1902 return; 1903} 1904 1905static int kvmppc_core_prepare_memory_region_pr(struct kvm *kvm, 1906 const struct kvm_memory_slot *old, 1907 struct kvm_memory_slot *new, 1908 enum kvm_mr_change change) 1909{ 1910 return 0; 1911} 1912 1913static void kvmppc_core_commit_memory_region_pr(struct kvm *kvm, 1914 struct kvm_memory_slot *old, 1915 const struct kvm_memory_slot *new, 1916 enum kvm_mr_change change) 1917{ 1918 return; 1919} 1920 1921static void kvmppc_core_free_memslot_pr(struct kvm_memory_slot *slot) 1922{ 1923 return; 1924} 1925 1926#ifdef CONFIG_PPC64 1927static int kvm_vm_ioctl_get_smmu_info_pr(struct kvm *kvm, 1928 struct kvm_ppc_smmu_info *info) 1929{ 1930 long int i; 1931 struct kvm_vcpu *vcpu; 1932 1933 info->flags = 0; 1934 1935 /* SLB is always 64 entries */ 1936 info->slb_size = 64; 1937 1938 /* Standard 4k base page size segment */ 1939 info->sps[0].page_shift = 12; 1940 info->sps[0].slb_enc = 0; 1941 info->sps[0].enc[0].page_shift = 12; 1942 info->sps[0].enc[0].pte_enc = 0; 1943 1944 /* 1945 * 64k large page size. 1946 * We only want to put this in if the CPUs we're emulating 1947 * support it, but unfortunately we don't have a vcpu easily 1948 * to hand here to test. Just pick the first vcpu, and if 1949 * that doesn't exist yet, report the minimum capability, 1950 * i.e., no 64k pages. 1951 * 1T segment support goes along with 64k pages. 1952 */ 1953 i = 1; 1954 vcpu = kvm_get_vcpu(kvm, 0); 1955 if (vcpu && (vcpu->arch.hflags & BOOK3S_HFLAG_MULTI_PGSIZE)) { 1956 info->flags = KVM_PPC_1T_SEGMENTS; 1957 info->sps[i].page_shift = 16; 1958 info->sps[i].slb_enc = SLB_VSID_L | SLB_VSID_LP_01; 1959 info->sps[i].enc[0].page_shift = 16; 1960 info->sps[i].enc[0].pte_enc = 1; 1961 ++i; 1962 } 1963 1964 /* Standard 16M large page size segment */ 1965 info->sps[i].page_shift = 24; 1966 info->sps[i].slb_enc = SLB_VSID_L; 1967 info->sps[i].enc[0].page_shift = 24; 1968 info->sps[i].enc[0].pte_enc = 0; 1969 1970 return 0; 1971} 1972 1973static int kvm_configure_mmu_pr(struct kvm *kvm, struct kvm_ppc_mmuv3_cfg *cfg) 1974{ 1975 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 1976 return -ENODEV; 1977 /* Require flags and process table base and size to all be zero. */ 1978 if (cfg->flags || cfg->process_table) 1979 return -EINVAL; 1980 return 0; 1981} 1982 1983#else 1984static int kvm_vm_ioctl_get_smmu_info_pr(struct kvm *kvm, 1985 struct kvm_ppc_smmu_info *info) 1986{ 1987 /* We should not get called */ 1988 BUG(); 1989 return 0; 1990} 1991#endif /* CONFIG_PPC64 */ 1992 1993static unsigned int kvm_global_user_count = 0; 1994static DEFINE_SPINLOCK(kvm_global_user_count_lock); 1995 1996static int kvmppc_core_init_vm_pr(struct kvm *kvm) 1997{ 1998 mutex_init(&kvm->arch.hpt_mutex); 1999 2000#ifdef CONFIG_PPC_BOOK3S_64 2001 /* Start out with the default set of hcalls enabled */ 2002 kvmppc_pr_init_default_hcalls(kvm); 2003#endif 2004 2005 if (firmware_has_feature(FW_FEATURE_SET_MODE)) { 2006 spin_lock(&kvm_global_user_count_lock); 2007 if (++kvm_global_user_count == 1) 2008 pseries_disable_reloc_on_exc(); 2009 spin_unlock(&kvm_global_user_count_lock); 2010 } 2011 return 0; 2012} 2013 2014static void kvmppc_core_destroy_vm_pr(struct kvm *kvm) 2015{ 2016#ifdef CONFIG_PPC64 2017 WARN_ON(!list_empty(&kvm->arch.spapr_tce_tables)); 2018#endif 2019 2020 if (firmware_has_feature(FW_FEATURE_SET_MODE)) { 2021 spin_lock(&kvm_global_user_count_lock); 2022 BUG_ON(kvm_global_user_count == 0); 2023 if (--kvm_global_user_count == 0) 2024 pseries_enable_reloc_on_exc(); 2025 spin_unlock(&kvm_global_user_count_lock); 2026 } 2027} 2028 2029static int kvmppc_core_check_processor_compat_pr(void) 2030{ 2031 /* 2032 * PR KVM can work on POWER9 inside a guest partition 2033 * running in HPT mode. It can't work if we are using 2034 * radix translation (because radix provides no way for 2035 * a process to have unique translations in quadrant 3). 2036 */ 2037 if (cpu_has_feature(CPU_FTR_ARCH_300) && radix_enabled()) 2038 return -EIO; 2039 return 0; 2040} 2041 2042static int kvm_arch_vm_ioctl_pr(struct file *filp, 2043 unsigned int ioctl, unsigned long arg) 2044{ 2045 return -ENOTTY; 2046} 2047 2048static struct kvmppc_ops kvm_ops_pr = { 2049 .get_sregs = kvm_arch_vcpu_ioctl_get_sregs_pr, 2050 .set_sregs = kvm_arch_vcpu_ioctl_set_sregs_pr, 2051 .get_one_reg = kvmppc_get_one_reg_pr, 2052 .set_one_reg = kvmppc_set_one_reg_pr, 2053 .vcpu_load = kvmppc_core_vcpu_load_pr, 2054 .vcpu_put = kvmppc_core_vcpu_put_pr, 2055 .inject_interrupt = kvmppc_inject_interrupt_pr, 2056 .set_msr = kvmppc_set_msr_pr, 2057 .vcpu_run = kvmppc_vcpu_run_pr, 2058 .vcpu_create = kvmppc_core_vcpu_create_pr, 2059 .vcpu_free = kvmppc_core_vcpu_free_pr, 2060 .check_requests = kvmppc_core_check_requests_pr, 2061 .get_dirty_log = kvm_vm_ioctl_get_dirty_log_pr, 2062 .flush_memslot = kvmppc_core_flush_memslot_pr, 2063 .prepare_memory_region = kvmppc_core_prepare_memory_region_pr, 2064 .commit_memory_region = kvmppc_core_commit_memory_region_pr, 2065 .unmap_gfn_range = kvm_unmap_gfn_range_pr, 2066 .age_gfn = kvm_age_gfn_pr, 2067 .test_age_gfn = kvm_test_age_gfn_pr, 2068 .free_memslot = kvmppc_core_free_memslot_pr, 2069 .init_vm = kvmppc_core_init_vm_pr, 2070 .destroy_vm = kvmppc_core_destroy_vm_pr, 2071 .get_smmu_info = kvm_vm_ioctl_get_smmu_info_pr, 2072 .emulate_op = kvmppc_core_emulate_op_pr, 2073 .emulate_mtspr = kvmppc_core_emulate_mtspr_pr, 2074 .emulate_mfspr = kvmppc_core_emulate_mfspr_pr, 2075 .fast_vcpu_kick = kvm_vcpu_kick, 2076 .arch_vm_ioctl = kvm_arch_vm_ioctl_pr, 2077#ifdef CONFIG_PPC_BOOK3S_64 2078 .hcall_implemented = kvmppc_hcall_impl_pr, 2079 .configure_mmu = kvm_configure_mmu_pr, 2080#endif 2081 .giveup_ext = kvmppc_giveup_ext, 2082}; 2083 2084 2085int kvmppc_book3s_init_pr(void) 2086{ 2087 int r; 2088 2089 r = kvmppc_core_check_processor_compat_pr(); 2090 if (r < 0) 2091 return r; 2092 2093 kvm_ops_pr.owner = THIS_MODULE; 2094 kvmppc_pr_ops = &kvm_ops_pr; 2095 2096 r = kvmppc_mmu_hpte_sysinit(); 2097 return r; 2098} 2099 2100void kvmppc_book3s_exit_pr(void) 2101{ 2102 kvmppc_pr_ops = NULL; 2103 kvmppc_mmu_hpte_sysexit(); 2104} 2105 2106/* 2107 * We only support separate modules for book3s 64 2108 */ 2109#ifdef CONFIG_PPC_BOOK3S_64 2110 2111module_init(kvmppc_book3s_init_pr); 2112module_exit(kvmppc_book3s_exit_pr); 2113 2114MODULE_LICENSE("GPL"); 2115MODULE_ALIAS_MISCDEV(KVM_MINOR); 2116MODULE_ALIAS("devname:kvm"); 2117#endif 2118