1Binding for TI mux clock.
2
3This binding uses the common clock binding[1].  It assumes a
4register-mapped multiplexer with multiple input clock signals or
5parents, one of which can be selected as output.  This clock does not
6gate or adjust the parent rate via a divider or multiplier.
7
8By default the "clocks" property lists the parents in the same order
9as they are programmed into the register.  E.g:
10
11	clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
12
13results in programming the register as follows:
14
15register value		selected parent clock
160			foo_clock
171			bar_clock
182			baz_clock
19
20Some clock controller IPs do not allow a value of zero to be programmed
21into the register, instead indexing begins at 1.  The optional property
22"index-starts-at-one" modified the scheme as follows:
23
24register value		selected clock parent
251			foo_clock
262			bar_clock
273			baz_clock
28
29The binding must provide the register to control the mux. Optionally
30the number of bits to shift the control field in the register can be
31supplied. If the shift value is missing it is the same as supplying
32a zero shift.
33
34[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
35
36Required properties:
37- compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
38- #clock-cells : from common clock binding; shall be set to 0.
39- clocks : link phandles of parent clocks
40- reg : register offset for register controlling adjustable mux
41
42Optional properties:
43- clock-output-names : from common clock binding.
44- ti,bit-shift : number of bits to shift the bit-mask, defaults to
45  0 if not present
46- ti,index-starts-at-one : valid input select programming starts at 1, not
47  zero
48- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
49  not supported by the composite-mux-clock subtype
50- ti,latch-bit : latch the mux value to HW, only needed if the register
51  access requires this. As an example, dra7x DPLL_GMAC H14 muxing
52  implements such behavior.
53
54Examples:
55
56sys_clkin_ck: sys_clkin_ck@4a306110 {
57	#clock-cells = <0>;
58	compatible = "ti,mux-clock";
59	clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
60	reg = <0x0110>;
61	ti,index-starts-at-one;
62};
63
64abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
65	#clock-cells = <0>;
66	compatible = "ti,mux-clock";
67	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
68	ti,bit-shift = <24>;
69	reg = <0x0108>;
70};
71
72mcbsp5_mux_fck: mcbsp5_mux_fck {
73	#clock-cells = <0>;
74	compatible = "ti,composite-mux-clock";
75	clocks = <&core_96m_fck>, <&mcbsp_clks>;
76	ti,bit-shift = <4>;
77	reg = <0x02d8>;
78};
79