1/*
2 * Copyright 2021-2022 Haiku, Inc. All rights reserved.
3 * Released under the terms of the MIT License.
4 */
5
6#include <asm_defs.h>
7#include <kernel/arch/arm64/arm_registers.h>
8
9	.text
10
11/* Based on 12.1 The Translation Lookaside Buffer
12 * ARM DEN0024A (ID050815)
13 */
14FUNCTION(_arch_mmu_invalidate_tlb_all):
15    dsb st /* ensure write has completed*/
16//  cmp	x0, 3
17//  b.eq	el3
18	cmp	x0, 2
19	b.eq   el2
20	cmp	x0, 1
21	b.eq   el1
22
23el3:
24	tlbi alle3
25	dsb sy
26	isb
27	ret
28el2:
29	tlbi alle2
30	dsb sy
31	isb
32	ret
33el1:
34	tlbi vmalle1
35	dsb sy
36	isb
37	ret
38FUNCTION_END(_arch_mmu_invalidate_tlb_all)
39
40
41/* Based on Example 11-3 Cleaning to Point of Coherency
42 * ARM DEN0024A (ID050815)
43 */
44FUNCTION(_arch_cache_clean_poc):
45    MRS X0, CLIDR_EL1
46    AND W3, W0, #0x07000000    // Get 2 x Level of Coherence
47    LSR W3, W3, #23
48    CBZ W3, Finished
49    MOV W10, #0    // W10 = 2 x cache level
50    MOV W8, #1    //    W8 = constant 0b1
51Loop1:
52    ADD W2, W10, W10, LSR #1    // Calculate 3 x cache level
53    LSR W1, W0, W2    // extract 3-bit cache type for this level
54    AND W1, W1, #0x7
55    CMP W1, #2
56    B.LT Skip    // No data or unified cache at this level
57    MSR CSSELR_EL1, X10    //    Select this cache level
58    ISB    //    Synchronize change of CSSELR
59    MRS X1, CCSIDR_EL1    //    Read CCSIDR
60    AND W2, W1, #7    //    W2 = log2(linelen)-4
61    ADD W2, W2, #4    //    W2 = log2(linelen)
62    UBFX W4, W1, #3, #10    //  W4 = max way number, right aligned
63    CLZ W5, W4    /* W5 = 32-log2(ways), bit position of way in DC operand */
64    LSL W9, W4, W5 /* W9 = max way number, aligned to position in DC operand */
65    LSL W16, W8, W5 // W16 = amount to decrement way number per iteration
66Loop2:
67    UBFX W7, W1, #13, #15 // W7 = max set number, right aligned
68    LSL W7, W7, W2    /* W7 = max set number, aligned to position in DC operand */
69    LSL W17, W8, W2    // W17 = amount to decrement set number per iteration
70Loop3:
71    ORR W11, W10, W9 // W11 = combine way number and cache number...
72    ORR W11, W11, W7 // ... and set number for DC operand
73    DC CSW, X11    // Do data cache clean by set and way
74    SUBS W7, W7, W17 // Decrement set number
75    B.GE Loop3
76    SUBS X9, X9, X16 // Decrement way number
77    B.GE Loop2
78Skip:
79    ADD W10, W10, #2 // Increment 2 x cache level
80    CMP W3, W10
81    DSB  sy  /* Ensure completion of previous cache maintenance operation */
82    B.GT Loop1
83Finished:
84    ret
85FUNCTION_END(_arch_cache_clean_poc)
86