1/*-
2 * Copyright (c) 2017 Kevin Lo <kevlo@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD$");
29
30#include "opt_wlan.h"
31
32#include <sys/param.h>
33#include <sys/lock.h>
34#include <sys/mutex.h>
35#include <sys/mbuf.h>
36#include <sys/kernel.h>
37#include <sys/socket.h>
38#include <sys/systm.h>
39#include <sys/malloc.h>
40#include <sys/queue.h>
41#include <sys/taskqueue.h>
42#include <sys/bus.h>
43#include <sys/endian.h>
44#include <sys/linker.h>
45
46#include <net/if.h>
47#include <net/ethernet.h>
48#include <net/if_media.h>
49
50#include <net80211/ieee80211_var.h>
51#include <net80211/ieee80211_radiotap.h>
52
53#include <dev/rtwn/if_rtwnreg.h>
54#include <dev/rtwn/if_rtwnvar.h>
55
56#include <dev/rtwn/if_rtwn_debug.h>
57#include <dev/rtwn/if_rtwn_ridx.h>
58#include <dev/rtwn/if_rtwn_rx.h>
59
60#include <dev/rtwn/rtl8192c/r92c.h>
61
62#include <dev/rtwn/rtl8192e/r92e.h>
63#include <dev/rtwn/rtl8192e/r92e_reg.h>
64#include <dev/rtwn/rtl8192e/r92e_var.h>
65
66static int
67r92e_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c)
68{
69	uint8_t chan;
70	int group;
71
72	chan = rtwn_chan2centieee(c);
73	if (IEEE80211_IS_CHAN_2GHZ(c)) {
74		if (chan <= 2)			group = 0;
75		else if (chan <= 5)		group = 1;
76		else if (chan <= 8)		group = 2;
77		else if (chan <= 11)		group = 3;
78		else if (chan <= 14)		group = 4;
79		else {
80			KASSERT(0, ("wrong 2GHz channel %d!\n", chan));
81			return (-1);
82		}
83	} else {
84		KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags));
85		return (-1);
86	}
87
88	return (group);
89}
90
91static void
92r92e_get_txpower(struct rtwn_softc *sc, int chain, struct ieee80211_channel *c,
93    uint8_t power[RTWN_RIDX_COUNT])
94{
95	struct r92e_softc *rs = sc->sc_priv;
96	int i, ridx, group, max_mcs;
97
98	/* Determine channel group. */
99	group = r92e_get_power_group(sc, c);
100	if (group == -1) {	/* shouldn't happen */
101		device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__);
102		return;
103	}
104
105	max_mcs = RTWN_RIDX_HT_MCS(sc->ntxchains * 8 - 1);
106
107	/* XXX regulatory */
108	/* XXX net80211 regulatory */
109
110	for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++)
111		power[ridx] = rs->cck_tx_pwr[chain][group];
112	for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++)
113		power[ridx] = rs->ht40_tx_pwr_2g[chain][group];
114
115	for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++)
116		power[ridx] += rs->ofdm_tx_pwr_diff_2g[chain][0];
117
118	for (i = 0; i < sc->ntxchains; i++) {
119		uint8_t min_mcs;
120		uint8_t pwr_diff;
121
122		if (IEEE80211_IS_CHAN_HT40(c))
123			pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i];
124		else
125			pwr_diff = rs->bw20_tx_pwr_diff_2g[chain][i];
126
127		min_mcs = RTWN_RIDX_HT_MCS(i * 8);
128		for (ridx = min_mcs; ridx <= max_mcs; ridx++)
129			power[ridx] += pwr_diff;
130	}
131
132	/* Apply max limit. */
133	for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) {
134		if (power[ridx] > R92C_MAX_TX_PWR)
135			power[ridx] = R92C_MAX_TX_PWR;
136	}
137
138#ifdef RTWN_DEBUG
139	if (sc->sc_debug & RTWN_DEBUG_TXPWR) {
140		/* Dump per-rate Tx power values. */
141		printf("Tx power for chain %d:\n", chain);
142		for (ridx = RTWN_RIDX_CCK1; ridx < RTWN_RIDX_COUNT; ridx++)
143			printf("Rate %d = %u\n", ridx, power[ridx]);
144	}
145#endif
146}
147
148static void
149r92e_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c)
150{
151	uint8_t power[RTWN_RIDX_COUNT];
152	int i;
153
154	for (i = 0; i < sc->ntxchains; i++) {
155		memset(power, 0, sizeof(power));
156		/* Compute per-rate Tx power values. */
157		r92e_get_txpower(sc, i, c, power);
158		/* Write per-rate Tx power values to hardware. */
159		r92c_write_txpower(sc, i, power);
160	}
161}
162
163static void
164r92e_set_bw40(struct rtwn_softc *sc, uint8_t chan, int prichlo)
165{
166	int i;
167
168	rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x100, 0x80);
169	rtwn_write_1(sc, R12A_DATA_SEC,
170	    prichlo ? R12A_DATA_SEC_PRIM_DOWN_20 : R12A_DATA_SEC_PRIM_UP_20);
171
172	rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_40MHZ);
173	rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, 0, R92C_RFMOD_40MHZ);
174
175	/* Select 40MHz bandwidth. */
176	for (i = 0; i < sc->nrxchains; i++)
177		rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW,
178		    R88E_RF_CHNLBW_BW20, 0x400);
179
180	/* Set CCK side band. */
181	rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM,
182	    R92C_CCK0_SYSTEM_CCK_SIDEBAND, (prichlo ? 0 : 1) << 4);
183
184	rtwn_bb_setbits(sc, R92C_OFDM1_LSTF, 0x0c00, (prichlo ? 1 : 2) << 10);
185
186	rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2,
187	    R92C_FPGA0_ANAPARAM2_CBW20, 0);
188
189	rtwn_bb_setbits(sc, 0x818, 0x0c000000, (prichlo ? 2 : 1) << 26);
190}
191
192static void
193r92e_set_bw20(struct rtwn_softc *sc, uint8_t chan)
194{
195	int i;
196
197	rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0);
198	rtwn_write_1(sc, R12A_DATA_SEC, R12A_DATA_SEC_NO_EXT);
199
200	rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, R92C_RFMOD_40MHZ, 0);
201	rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, R92C_RFMOD_40MHZ, 0);
202
203	/* Select 20MHz bandwidth. */
204	for (i = 0; i < sc->nrxchains; i++)
205		rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW,
206		    R88E_RF_CHNLBW_BW20, 0xc00);
207
208	rtwn_bb_setbits(sc, R92C_OFDM0_TXPSEUDONOISEWGT, 0xc0000000, 0);
209}
210
211void
212r92e_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c)
213{
214	struct r92e_softc *rs = sc->sc_priv;
215	u_int chan;
216	int i;
217
218	chan = rtwn_chan2centieee(c);
219
220	for (i = 0; i < sc->nrxchains; i++) {
221		rtwn_rf_write(sc, i, R92C_RF_CHNLBW,
222		    RW(rs->rf_chnlbw[0], R92C_RF_CHNLBW_CHNL, chan));
223	}
224
225	if (IEEE80211_IS_CHAN_HT40(c))
226		r92e_set_bw40(sc, chan, IEEE80211_IS_CHAN_HT40U(c));
227	else
228		r92e_set_bw20(sc, chan);
229
230	/* Set Tx power for this new channel. */
231	r92e_set_txpower(sc, c);
232}
233