1/*-
2 * SPDX-License-Identifier: ISC
3 *
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2006 Atheros Communications, Inc.
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 * $FreeBSD: releng/12.0/sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c 326695 2017-12-08 15:57:29Z pfg $
20 */
21#include "opt_ah.h"
22
23#include "ah.h"
24#include "ah_internal.h"
25
26#include "ar5211/ar5211.h"
27#include "ar5211/ar5211reg.h"
28
29/*
30 * Checks to see if an interrupt is pending on our NIC
31 *
32 * Returns: TRUE    if an interrupt is pending
33 *          FALSE   if not
34 */
35HAL_BOOL
36ar5211IsInterruptPending(struct ath_hal *ah)
37{
38	return OS_REG_READ(ah, AR_INTPEND) != 0;
39}
40
41/*
42 * Reads the Interrupt Status Register value from the NIC, thus deasserting
43 * the interrupt line, and returns both the masked and unmasked mapped ISR
44 * values.  The value returned is mapped to abstract the hw-specific bit
45 * locations in the Interrupt Status Register.
46 *
47 * Returns: A hardware-abstracted bitmap of all non-masked-out
48 *          interrupts pending, as well as an unmasked value
49 */
50HAL_BOOL
51ar5211GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
52{
53	uint32_t isr;
54
55	isr = OS_REG_READ(ah, AR_ISR_RAC);
56	if (isr == 0xffffffff) {
57		*masked = 0;
58		return AH_FALSE;
59	}
60
61	*masked = isr & HAL_INT_COMMON;
62
63	if (isr & AR_ISR_HIUERR)
64		*masked |= HAL_INT_FATAL;
65	if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
66		*masked |= HAL_INT_RX;
67	if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL))
68		*masked |= HAL_INT_TX;
69	/*
70	 * Receive overrun is usually non-fatal on Oahu/Spirit.
71	 * BUT on some parts rx could fail and the chip must be reset.
72	 * So we force a hardware reset in all cases.
73	 */
74	if ((isr & AR_ISR_RXORN) && AH_PRIVATE(ah)->ah_rxornIsFatal) {
75		HALDEBUG(ah, HAL_DEBUG_ANY,
76		    "%s: receive FIFO overrun interrupt\n", __func__);
77		*masked |= HAL_INT_FATAL;
78	}
79
80	/*
81	 * On fatal errors collect ISR state for debugging.
82	 */
83	if (*masked & HAL_INT_FATAL) {
84		AH_PRIVATE(ah)->ah_fatalState[0] = isr;
85		AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S);
86		AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S);
87		AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S);
88		AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(ah, AR_ISR_S3_S);
89		AH_PRIVATE(ah)->ah_fatalState[5] = OS_REG_READ(ah, AR_ISR_S4_S);
90		HALDEBUG(ah, HAL_DEBUG_ANY,
91		    "%s: fatal error, ISR_RAC=0x%x ISR_S2_S=0x%x\n",
92		    __func__, isr, AH_PRIVATE(ah)->ah_fatalState[3]);
93	}
94	return AH_TRUE;
95}
96
97HAL_INT
98ar5211GetInterrupts(struct ath_hal *ah)
99{
100	return AH5211(ah)->ah_maskReg;
101}
102
103/*
104 * Atomically enables NIC interrupts.  Interrupts are passed in
105 * via the enumerated bitmask in ints.
106 */
107HAL_INT
108ar5211SetInterrupts(struct ath_hal *ah, HAL_INT ints)
109{
110	struct ath_hal_5211 *ahp = AH5211(ah);
111	uint32_t omask = ahp->ah_maskReg;
112	uint32_t mask;
113
114	HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
115	    __func__, omask, ints);
116
117	/*
118	 * Disable interrupts here before reading & modifying
119	 * the mask so that the ISR does not modify the mask
120	 * out from under us.
121	 */
122	if (omask & HAL_INT_GLOBAL) {
123		HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
124		OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
125		/* XXX??? */
126		(void) OS_REG_READ(ah, AR_IER);	/* flush write to HW */
127	}
128
129	mask = ints & HAL_INT_COMMON;
130	if (ints & HAL_INT_TX) {
131		if (ahp->ah_txOkInterruptMask)
132			mask |= AR_IMR_TXOK;
133		if (ahp->ah_txErrInterruptMask)
134			mask |= AR_IMR_TXERR;
135		if (ahp->ah_txDescInterruptMask)
136			mask |= AR_IMR_TXDESC;
137		if (ahp->ah_txEolInterruptMask)
138			mask |= AR_IMR_TXEOL;
139	}
140	if (ints & HAL_INT_RX)
141		mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC;
142	if (ints & HAL_INT_FATAL) {
143		/*
144		 * NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2
145		 *     so enabling HIUERR enables delivery.
146		 */
147		mask |= AR_IMR_HIUERR;
148	}
149
150	/* Write the new IMR and store off our SW copy. */
151	HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
152	OS_REG_WRITE(ah, AR_IMR, mask);
153	ahp->ah_maskReg = ints;
154
155	/* Re-enable interrupts as appropriate. */
156	if (ints & HAL_INT_GLOBAL) {
157		HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
158		OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
159	}
160
161	return omask;
162}
163