1 2/*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 16 * redistribution must be conditioned upon including a substantially 17 * similar Disclaimer requirement for further binary redistribution. 18 * 19 * NO WARRANTY 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 23 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 24 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 28 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGES. 31 * 32 * $FreeBSD: releng/12.0/sys/dev/ath/ah_osdep.h 326255 2017-11-27 14:52:40Z pfg $ 33 */ 34#ifndef _ATH_AH_OSDEP_H_ 35#define _ATH_AH_OSDEP_H_ 36/* 37 * Atheros Hardware Access Layer (HAL) OS Dependent Definitions. 38 */ 39#include <sys/cdefs.h> 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/endian.h> 43#include <sys/linker_set.h> 44 45#include <machine/bus.h> 46 47/* 48 * Bus i/o type definitions. 49 */ 50typedef void *HAL_SOFTC; 51typedef bus_space_tag_t HAL_BUS_TAG; 52typedef bus_space_handle_t HAL_BUS_HANDLE; 53 54/* 55 * Although the underlying hardware may support 64 bit DMA, the 56 * current Atheros hardware only supports 32 bit addressing. 57 */ 58typedef uint32_t HAL_DMA_ADDR; 59 60/* 61 * Linker set writearounds for chip and RF backend registration. 62 */ 63#define OS_DATA_SET(set, item) DATA_SET(set, item) 64#define OS_SET_DECLARE(set, ptype) SET_DECLARE(set, ptype) 65#define OS_SET_FOREACH(pvar, set) SET_FOREACH(pvar, set) 66 67/* 68 * Delay n microseconds. 69 */ 70#define OS_DELAY(_n) DELAY(_n) 71 72#define OS_INLINE __inline 73#define OS_MEMZERO(_a, _n) bzero((_a), (_n)) 74#define OS_MEMCPY(_d, _s, _n) memcpy(_d,_s,_n) 75#define OS_MEMCMP(_a, _b, _l) memcmp((_a), (_b), (_l)) 76 77#define abs(_a) __builtin_abs(_a) 78 79struct ath_hal; 80 81/* 82 * The hardware registers are native little-endian byte order. 83 * Big-endian hosts are handled by enabling hardware byte-swap 84 * of register reads and writes at reset. But the PCI clock 85 * domain registers are not byte swapped! Thus, on big-endian 86 * platforms we have to explicitly byte-swap those registers. 87 * OS_REG_UNSWAPPED identifies the registers that need special handling. 88 * 89 * This is not currently used by the FreeBSD HAL osdep code; the HAL 90 * currently does not configure hardware byteswapping for register space 91 * accesses and instead does it through the FreeBSD bus space code. 92 */ 93#if _BYTE_ORDER == _BIG_ENDIAN 94#define OS_REG_UNSWAPPED(_reg) \ 95 (((_reg) >= 0x4000 && (_reg) < 0x5000) || \ 96 ((_reg) >= 0x7000 && (_reg) < 0x8000)) 97#else /* _BYTE_ORDER == _LITTLE_ENDIAN */ 98#define OS_REG_UNSWAPPED(_reg) (0) 99#endif /* _BYTE_ORDER */ 100 101/* 102 * For USB/SDIO support (where access latencies are quite high); 103 * some write accesses may be buffered and then flushed when 104 * either a read is done, or an explicit flush is done. 105 * 106 * These are simply placeholders for now. 107 */ 108#define OS_REG_WRITE_BUFFER_ENABLE(_ah) \ 109 do { } while (0) 110#define OS_REG_WRITE_BUFFER_DISABLE(_ah) \ 111 do { } while (0) 112#define OS_REG_WRITE_BUFFER_FLUSH(_ah) \ 113 do { } while (0) 114 115/* 116 * Read and write barriers. Some platforms require more strongly ordered 117 * operations and unfortunately most of the HAL is written assuming everything 118 * is either an x86 or the bus layer will do the barriers for you. 119 * 120 * Read barriers should occur before each read, and write barriers 121 * occur after each write. 122 * 123 * Later on for SDIO/USB parts we will methodize this and make them no-ops; 124 * register accesses will go via USB commands. 125 */ 126#define OS_BUS_BARRIER_READ BUS_SPACE_BARRIER_READ 127#define OS_BUS_BARRIER_WRITE BUS_SPACE_BARRIER_WRITE 128#define OS_BUS_BARRIER_RW \ 129 (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 130#define OS_BUS_BARRIER(_ah, _start, _len, _t) \ 131 bus_space_barrier((bus_space_tag_t)(_ah)->ah_st, \ 132 (bus_space_handle_t)(_ah)->ah_sh, (_start), (_len), (_t)) 133#define OS_BUS_BARRIER_REG(_ah, _reg, _t) \ 134 OS_BUS_BARRIER((_ah), (_reg), 4, (_t)) 135 136/* 137 * Register read/write operations are handled through 138 * platform-dependent routines. 139 */ 140#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val) 141#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg) 142 143extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val); 144extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg); 145 146#ifdef AH_DEBUG_ALQ 147extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value); 148#else 149#define OS_MARK(_ah, _id, _v) 150#endif 151 152#endif /* _ATH_AH_OSDEP_H_ */ 153