1/* 2 * Copyright 2004-2015 Haiku, Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Jérôme Duval, jerome.duval@free.fr 7 * Marcus Overhagen, marcus@overhagen.de 8 * Jérôme Lévêque, leveque.jerome@gmail.com 9 */ 10 11 12#ifndef _ICE1712_REG_H_ 13#define _ICE1712_REG_H_ 14 15//PCI Interface and Configuration Registers (Page 3.1) 16//Table 3.1 17#define PCI_VENDOR_ID 0x00 //2 bytes 18#define PCI_DEVICE_ID 0x02 //2 bytes 19#define PCI_COMMAND 0x04 //2 bytes 20#define PCI_DEVICE_STATUS 0x06 //2 bytes 21#define PCI_REVISION_ID 0x08 //1 byte 22#define PCI_CLASS_CODE 0x0A //2 bytes 23#define PCI_LATENCY_TIMER 0x0D //1 byte 24#define PCI_HEADER_TYPE 0x0E //1 byte 25#define PCI_BIST 0x0F //1 byte 26#define PCI_CONTROLLER_BASE_AD 0x10 //4 bytes 27#define PCI_DDMA_BASE_AD 0x14 //4 bytes 28#define PCI_DMA_BASE_AD 0x18 //4 bytes 29#define PCI_MULTI_BASE_AD 0x1C //4 bytes 30#define PCI_SUB_VENDOR_ID 0x2C //2 bytes 31#define PCI_SUB_SYSTEM_ID 0x2E //2 bytes 32#define PCI_CAPABILITY_POINTER 0x34 //4 bytes 33#define PCI_INT_PIN_LINE 0x3C //2 bytes 34#define PCI_LATENCY_GRANT 0x3E //2 bytes 35#define PCI_LEGACY_AUDIO_CONTROL 0x40 //2 bytes 36#define PCI_LEGACY_CONF_CONTROL 0x42 //2 bytes 37#define PCI_HARD_CONF_CONTROL 0x60 //4 bytes 38#define PCI_CAPABILITY_ID 0x80 //1 byte 39#define PCI_NEXT_ITEM_POINTER 0x81 //1 byte 40#define PCI_POWER_CAPABILITY 0x82 //2 bytes 41#define PCI_POWER_CONTROL_STATUS 0x84 //2 bytes 42#define PCI_PMCSR_EXT_DATA 0x86 //2 bytes 43 44//CCSxx Controller Register Map (Page 4.3) 45//Table 4.2 46#define CCS_CONTROL_STATUS 0x00 //1 byte 47#define CCS_INTERRUPT_MASK 0x01 //1 byte 48#define CCS_INTERRUPT_STATUS 0x02 //1 byte 49#define CCS_CCI_INDEX 0x03 //1 byte 50#define CCS_CCI_DATA 0x04 //1 byte 51#define CCS_NMI_STATUS_1 0x05 //1 byte 52#define CCS_NMI_DATA 0x06 //1 byte 53#define CCS_NMI_INDEX 0x07 //1 byte 54#define CCS_CONS_AC97_INDEX 0x08 //1 byte 55#define CCS_CONS_AC97_COMMAND_STATUS 0x09 //1 byte 56#define CCS_CONS_AC97_DATA 0x0A //2 bytes 57#define CCS_MIDI_1_DATA 0x0C //1 byte 58#define CCS_MIDI_1_COMMAND_STATUS 0x0D //1 byte 59#define CCS_NMI_STATUS_2 0x0E //1 byte 60#define CCS_GAME_PORT 0x0F //1 byte 61#define CCS_I2C_DEV_ADDRESS 0x10 //1 byte 62#define CCS_I2C_BYTE_ADDRESS 0x11 //1 byte 63#define CCS_I2C_DATA 0x12 //1 byte 64#define CCS_I2C_CONTROL_STATUS 0x13 //1 byte 65#define CCS_CONS_DMA_BASE_ADDRESS 0x14 //4 bytes 66#define CCS_CONS_DMA_COUNT_ADDRESS 0x18 //2 bytes 67#define CCS_SERR_SHADOW 0x1B //1 byte 68#define CCS_MIDI_2_DATA 0x1C //1 byte 69#define CCS_MIDI_2_COMMAND_STATUS 0x1D //1 byte 70#define CCS_TIMER 0x1E //2 bytes 71 72//Controller Indexed Register (Page 4.12) 73#define CCI_PB_TERM_COUNT_HI 0x00 //1 byte 74#define CCI_PB_TERM_COUNT_LO 0x01 //1 byte 75#define CCI_PB_CONTROL 0x02 //1 byte 76#define CCI_PB_LEFT_VOLUME 0x03 //1 byte 77#define CCI_PB_RIGHT_VOLUME 0x04 //1 byte 78#define CCI_SOFT_VOLUME 0x05 //1 byte 79#define CCI_PB_SAMPLING_RATE_LO 0x06 //1 byte 80#define CCI_PB_SAMPLING_RATE_MI 0x07 //1 byte 81#define CCI_PB_SAMPLING_RATE_HI 0x08 //1 byte 82#define CCI_REC_TERM_COUNT_HI 0x10 //1 byte 83#define CCI_REC_TERM_COUNT_LO 0x11 //1 byte 84#define CCI_REC_CONTROL 0x12 //1 byte 85#define CCI_GPIO_DATA 0x20 //1 byte 86#define CCI_GPIO_WRITE_MASK 0x21 //1 byte 87#define CCI_GPIO_DIRECTION_CONTROL 0x22 //1 byte 88#define CCI_CONS_POWER_DOWN 0x30 //1 byte 89#define CCI_MULTI_POWER_DOWN 0x31 //1 byte 90 91//Consumer Section DMA Channel Registers (Page 4.20) 92//Table 4.4 93#define DS_DMA_INT_MASK 0x00 //2 bytes 94#define DS_DMA_INT_STATUS 0x02 //2 bytes 95#define DS_CHANNEL_DATA 0x04 //4 bytes 96#define DS_CHANNEL_INDEX 0x08 //1 byte 97 98//Professional Multi-Track Control Registers (Page 4.24) 99//Table 4.7 100#define MT_DMA_INT_MASK_STATUS 0x00 //1 byte 101#define MT_SAMPLING_RATE_SELECT 0x01 //1 byte 102#define MT_I2S_DATA_FORMAT 0x02 //1 byte 103#define MT_PROF_AC97_INDEX 0x04 //1 byte 104#define MT_PROF_AC97_COMMAND_STATUS 0x05 //1 byte 105#define MT_PROF_AC97_DATA 0x06 //2 bytes 106#define MT_PROF_PB_DMA_BASE_ADDRESS 0x10 //4 bytes 107#define MT_PROF_PB_DMA_COUNT_ADDRESS 0x14 //2 bytes 108#define MT_PROF_PB_DMA_TERM_COUNT 0x16 //2 bytes 109#define MT_PROF_PB_CONTROL 0x18 //1 byte 110#define MT_PROF_REC_DMA_BASE_ADDRESS 0x20 //4 bytes 111#define MT_PROF_REC_DMA_COUNT_ADDRESS 0x24 //2 bytes 112#define MT_PROF_REC_DMA_TERM_COUNT 0x26 //2 bytes 113#define MT_PROF_REC_CONTROL 0x28 //1 byte 114#define MT_ROUTING_CONTROL_PSDOUT 0x30 //2 bytes 115#define MT_ROUTING_CONTROL_SPDOUT 0x32 //2 bytes 116#define MT_CAPTURED_DATA 0x34 //4 bytes 117#define MT_LR_VOLUME_CONTROL 0x38 //2 bytes 118#define MT_VOLUME_CONTROL_CHANNEL_INDEX 0x3A //1 byte 119#define MT_VOLUME_CONTROL_RATE 0x3B //1 byte 120#define MT_MIXER_MONITOR_RETURN 0x3C //1 byte 121#define MT_PEAK_METER_INDEX 0x3E //1 byte 122#define MT_PEAK_METER_DATA 0x3F //1 byte 123 124#define I2C_EEPROM_ADDRESS_READ 0xA0 //1010 0000 125#define I2C_EEPROM_ADDRESS_WRITE 0xA1 //1010 0001 126 127#define SPDIF_STEREO_IN 0x02 //0000 0010 128#define SPDIF_STEREO_OUT 0x01 //0000 0001 129 130#endif 131