1/* 2 * Copyright 2005-2013, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Jan-Rixt Van Hoye 7 * Salvatore Benedetto <salvatore.benedetto@gmail.com> 8 * Michael Lotz <mmlr@mlotz.ch> 9 * Siarzhuk Zharski <imker@gmx.li> 10 */ 11 12#ifndef OHCI_HARDWARE_H 13#define OHCI_HARDWARE_H 14 15// -------------------------------- 16// The OHCI registers 17// -------------------------------- 18 19// -------------------------------- 20// Revision register (section 7.1.1) 21// -------------------------------- 22 23#define OHCI_REVISION 0x00 24#define OHCI_REVISION_LOW(rev) ((rev) & 0x0f) 25#define OHCI_REVISION_HIGH(rev) (((rev) >> 4) & 0x03) 26#define OHCI_REVISION_LEGACY(rev) ((rev) & 0x10) 27 28// -------------------------------- 29// Control register (section 7.1.2) 30// -------------------------------- 31 32#define OHCI_CONTROL 0x04 33#define OHCI_CONTROL_BULK_SERVICE_RATIO_MASK 0x00000003 34#define OHCI_CONTROL_BULK_RATIO_1_1 0x00000000 35#define OHCI_CONTROL_BULK_RATIO_1_2 0x00000001 36#define OHCI_CONTROL_BULK_RATIO_1_3 0x00000002 37#define OHCI_CONTROL_BULK_RATIO_1_4 0x00000003 38#define OHCI_PERIODIC_LIST_ENABLE 0x00000004 39#define OHCI_ISOCHRONOUS_ENABLE 0x00000008 40#define OHCI_CONTROL_LIST_ENABLE 0x00000010 41#define OHCI_BULK_LIST_ENABLE 0x00000020 42#define OHCI_HC_FUNCTIONAL_STATE_MASK 0x000000c0 43#define OHCI_HC_FUNCTIONAL_STATE_RESET 0x00000000 44#define OHCI_HC_FUNCTIONAL_STATE_RESUME 0x00000040 45#define OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL 0x00000080 46#define OHCI_HC_FUNCTIONAL_STATE_SUSPEND 0x000000c0 47#define OHCI_INTERRUPT_ROUTING 0x00000100 48#define OHCI_REMOTE_WAKEUP_CONNECTED 0x00000200 49#define OHCI_REMORE_WAKEUP_ENABLED 0x00000400 50 51// -------------------------------- 52// Command status register (section 7.1.3) 53// -------------------------------- 54 55#define OHCI_COMMAND_STATUS 0x08 56#define OHCI_HOST_CONTROLLER_RESET 0x00000001 57#define OHCI_CONTROL_LIST_FILLED 0x00000002 58#define OHCI_BULK_LIST_FILLED 0x00000004 59#define OHCI_OWNERSHIP_CHANGE_REQUEST 0x00000008 60#define OHCI_SCHEDULING_OVERRUN_COUNT_MASK 0x00030000 61 62// -------------------------------- 63// Interrupt status register (section 7.1.4) 64// -------------------------------- 65 66#define OHCI_INTERRUPT_STATUS 0x0c 67#define OHCI_SCHEDULING_OVERRUN 0x00000001 68#define OHCI_WRITEBACK_DONE_HEAD 0x00000002 69#define OHCI_START_OF_FRAME 0x00000004 70#define OHCI_RESUME_DETECTED 0x00000008 71#define OHCI_UNRECOVERABLE_ERROR 0x00000010 72#define OHCI_FRAME_NUMBER_OVERFLOW 0x00000020 73#define OHCI_ROOT_HUB_STATUS_CHANGE 0x00000040 74#define OHCI_OWNERSHIP_CHANGE 0x40000000 75#define OHCI_MASTER_INTERRUPT_ENABLE 0x80000000 76 77// -------------------------------- 78// Interupt enable register (section 7.1.5) 79// -------------------------------- 80 81#define OHCI_INTERRUPT_ENABLE 0x10 82 83// -------------------------------- 84// Interupt disable register (section 7.1.6) 85// -------------------------------- 86 87#define OHCI_INTERRUPT_DISABLE 0x14 88 89// ------------------------------------- 90// Memory Pointer Partition (section 7.2) 91// ------------------------------------- 92 93// -------------------------------- 94// HCCA register (section 7.2.1) 95// -------------------------------- 96 97#define OHCI_HCCA 0x18 98 99// -------------------------------- 100// Period current ED register (section 7.2.2) 101// -------------------------------- 102 103#define OHCI_PERIOD_CURRENT_ED 0x1c 104 105// -------------------------------- 106// Control head ED register (section 7.2.3) 107// -------------------------------- 108 109#define OHCI_CONTROL_HEAD_ED 0x20 110 111// -------------------------------- 112// Current control ED register (section 7.2.4) 113// -------------------------------- 114 115#define OHCI_CONTROL_CURRENT_ED 0x24 116 117// -------------------------------- 118// Bulk head ED register (section 7.2.5) 119// -------------------------------- 120 121#define OHCI_BULK_HEAD_ED 0x28 122 123// -------------------------------- 124// Current bulk ED register (section 7.2.6) 125// -------------------------------- 126 127#define OHCI_BULK_CURRENT_ED 0x2c 128 129// -------------------------------- 130// Done head register (section 7.2.7) 131// -------------------------------- 132 133#define OHCI_DONE_HEAD 0x30 134 135// -------------------------------- 136// Frame Counter partition (section 7.3) 137// -------------------------------- 138 139// -------------------------------- 140// Frame interval register (section 7.3.1) 141// -------------------------------- 142 143#define OHCI_FRAME_INTERVAL 0x34 144#define OHCI_GET_INTERVAL_VALUE(s) ((s) & 0x3fff) 145#define OHCI_GET_FS_LARGEST_DATA_PACKET(s) (((s) >> 16) & 0x7fff) 146#define OHCI_FRAME_INTERVAL_TOGGLE 0x80000000 147 148// -------------------------------- 149// Frame remaining register (section 7.3.2) 150// -------------------------------- 151 152#define OHCI_FRAME_REMAINING 0x38 153 154// -------------------------------- 155// Frame number register (section 7.3.3) 156// -------------------------------- 157 158#define OHCI_FRAME_NUMBER 0x3c 159 160// -------------------------------- 161// Periodic start register (section 7.3.4) 162// -------------------------------- 163 164#define OHCI_PERIODIC_START 0x40 165 166// -------------------------------- 167// Low Speed (LS) treshold register (section 7.3.5) 168// -------------------------------- 169 170#define OHCI_LOW_SPEED_THRESHOLD 0x44 171 172// -------------------------------- 173// Root Hub Partition (section 7.4) 174// -------------------------------- 175 176// -------------------------------- 177// Root Hub Descriptor A register (section 7.4.1) 178// -------------------------------- 179 180#define OHCI_RH_DESCRIPTOR_A 0x48 181#define OHCI_RH_GET_PORT_COUNT(s) ((s) & 0xff) 182#define OHCI_RH_POWER_SWITCHING_MODE 0x0100 183#define OHCI_RH_NO_POWER_SWITCHING 0x0200 184#define OHCI_RH_DEVICE_TYPE 0x0400 185#define OHCI_RH_OVER_CURRENT_PROTECTION_MODE 0x0800 186#define OHCI_RH_NO_OVER_CURRENT_PROTECTION 0x1000 187#define OHCI_RH_GET_POWER_ON_TO_POWER_GOOD_TIME(s) ((s) >> 24) 188 189// -------------------------------- 190// Root Hub Descriptor B register (section 7.4.2) 191// -------------------------------- 192 193#define OHCI_RH_DESCRIPTOR_B 0x4c 194 195// -------------------------------- 196// Root Hub status register (section 7.4.3) 197// -------------------------------- 198 199#define OHCI_RH_STATUS 0x50 200#define OHCI_RH_LOCAL_POWER_STATUS 0x00000001 201#define OHCI_RH_OVER_CURRENT_INDICATOR 0x00000002 202#define OHCI_RH_DEVICE_REMOTE_WAKEUP_ENABLE 0x00008000 203#define OHCI_RH_LOCAL_POWER_STATUS_CHANGE 0x00010000 204#define OHCI_RH_OVER_CURRENT_INDICATOR_CHANGE 0x00020000 205#define OHCI_RH_CLEAR_REMOTE_WAKEUP_ENABLE 0x80000000 206 207// -------------------------------- 208// Root Hub port status (n) register (section 7.4.4) 209// -------------------------------- 210 211#define OHCI_RH_PORT_STATUS(n) (0x54 + (n) * 4)// 0 based indexing 212#define OHCI_RH_PORTSTATUS_CCS 0x00000001 // Current Connection Status 213#define OHCI_RH_PORTSTATUS_PES 0x00000002 // Port Enable Status 214#define OHCI_RH_PORTSTATUS_PSS 0x00000004 // Port Suspend Status 215#define OHCI_RH_PORTSTATUS_POCI 0x00000008 // Port Overcurrent Indicator 216#define OHCI_RH_PORTSTATUS_PRS 0x00000010 // Port Reset Status 217#define OHCI_RH_PORTSTATUS_PPS 0x00000100 // Port Power Status 218#define OHCI_RH_PORTSTATUS_LSDA 0x00000200 // Low Speed Device Attached 219#define OHCI_RH_PORTSTATUS_CSC 0x00010000 // Connection Status Change 220#define OHCI_RH_PORTSTATUS_PESC 0x00020000 // Port Enable Status Change 221#define OHCI_RH_PORTSTATUS_PSSC 0x00040000 // Port Suspend Status change 222#define OHCI_RH_PORTSTATUS_OCIC 0x00080000 // Port Overcurrent Change 223#define OHCI_RH_PORTSTATUS_PRSC 0x00100000 // Port Reset Status Change 224 225// -------------------------------- 226// Enable List 227// -------------------------------- 228 229#define OHCI_ENABLE_LIST (OHCI_PERIODIC_LIST_ENABLE \ 230 | OHCI_ISOCHRONOUS_ENABLE \ 231 | OHCI_CONTROL_LIST_ENABLE \ 232 | OHCI_BULK_LIST_ENABLE) 233 234// -------------------------------- 235// All interupts 236// -------------------------------- 237 238#define OHCI_ALL_INTERRUPTS (OHCI_SCHEDULING_OVERRUN \ 239 | OHCI_WRITEBACK_DONE_HEAD \ 240 | OHCI_START_OF_FRAME \ 241 | OHCI_RESUME_DETECTED \ 242 | OHCI_UNRECOVERABLE_ERROR \ 243 | OHCI_FRAME_NUMBER_OVERFLOW \ 244 | OHCI_ROOT_HUB_STATUS_CHANGE \ 245 | OHCI_OWNERSHIP_CHANGE) 246 247// -------------------------------- 248// All normal interupts 249// -------------------------------- 250 251#define OHCI_NORMAL_INTERRUPTS (OHCI_SCHEDULING_OVERRUN \ 252 | OHCI_WRITEBACK_DONE_HEAD \ 253 | OHCI_RESUME_DETECTED \ 254 | OHCI_UNRECOVERABLE_ERROR \ 255 | OHCI_ROOT_HUB_STATUS_CHANGE) 256 257// -------------------------------- 258// FSMPS 259// -------------------------------- 260 261#define OHCI_FSMPS(i) (((i - 210) * 6 / 7) << 16) 262 263// -------------------------------- 264// Periodic 265// -------------------------------- 266 267#define OHCI_PERIODIC(i) ((i) * 9 / 10) 268 269// -------------------------------- 270// HCCA structure (section 4.4) 271// 256 bytes aligned 272// -------------------------------- 273 274#define OHCI_NUMBER_OF_INTERRUPTS 32 275#define OHCI_STATIC_ENDPOINT_COUNT 6 276#define OHCI_BIGGEST_INTERVAL 32 277 278typedef struct { 279 uint32 interrupt_table[OHCI_NUMBER_OF_INTERRUPTS]; 280 uint32 current_frame_number; 281 uint32 done_head; 282 // The following is 120 instead of 116 because the spec 283 // only specifies 252 bytes 284 uint8 reserved_for_hc[120]; 285} ohci_hcca; 286 287#define OHCI_DONE_INTERRUPTS 1 288#define OHCI_HCCA_SIZE 256 289#define OHCI_HCCA_ALIGN 256 290#define OHCI_PAGE_SIZE 0x1000 291#define OHCI_PAGE(x) ((x) &~ 0xfff) 292#define OHCI_PAGE_OFFSET(x) ((x) & 0xfff) 293 294// -------------------------------- 295// Endpoint descriptor structure (section 4.2) 296// -------------------------------- 297 298typedef struct { 299 // Hardware part 300 uint32 flags; // Flags field 301 uint32 tail_physical_descriptor; // Queue tail physical pointer 302 uint32 head_physical_descriptor; // Queue head physical pointer 303 uint32 next_physical_endpoint; // Physical pointer to the next endpoint 304 // Software part 305 uint32 physical_address; // Physical pointer to this address 306 void *tail_logical_descriptor; // Queue tail logical pointer 307 void *next_logical_endpoint; // Logical pointer to the next endpoint 308 mutex *lock; // Protects tail changes and checks 309} ohci_endpoint_descriptor; 310 311#define OHCI_ENDPOINT_ADDRESS_MASK 0x0000007f 312#define OHCI_ENDPOINT_GET_DEVICE_ADDRESS(s) ((s) & 0x7f) 313#define OHCI_ENDPOINT_SET_DEVICE_ADDRESS(s) (s) 314#define OHCI_ENDPOINT_GET_ENDPOINT_NUMBER(s) (((s) >> 7) & 0xf) 315#define OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(s) ((s) << 7) 316#define OHCI_ENDPOINT_DIRECTION_MASK 0x00001800 317#define OHCI_ENDPOINT_DIRECTION_DESCRIPTOR 0x00000000 318#define OHCI_ENDPOINT_DIRECTION_OUT 0x00000800 319#define OHCI_ENDPOINT_DIRECTION_IN 0x00001000 320#define OHCI_ENDPOINT_LOW_SPEED 0x00002000 321#define OHCI_ENDPOINT_FULL_SPEED 0x00000000 322#define OHCI_ENDPOINT_SKIP 0x00004000 323#define OHCI_ENDPOINT_GENERAL_FORMAT 0x00000000 324#define OHCI_ENDPOINT_ISOCHRONOUS_FORMAT 0x00008000 325#define OHCI_ENDPOINT_MAX_PACKET_SIZE_MASK (0x7ff << 16) 326#define OHCI_ENDPOINT_GET_MAX_PACKET_SIZE(s) (((s) >> 16) & 0x07ff) 327#define OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(s) ((s) << 16) 328#define OHCI_ENDPOINT_HALTED 0x00000001 329#define OHCI_ENDPOINT_TOGGLE_CARRY 0x00000002 330#define OHCI_ENDPOINT_HEAD_MASK 0xfffffffc 331 332 333// -------------------------------- 334// General transfer descriptor structure (section 4.3.1) 335// -------------------------------- 336 337typedef struct { 338 // Hardware part 16 bytes 339 uint32 flags; // Flags field 340 uint32 buffer_physical; // Physical buffer pointer 341 uint32 next_physical_descriptor; // Physical pointer next descriptor 342 uint32 last_physical_byte_address; // Physical pointer to buffer end 343 // Software part 344 uint32 physical_address; // Physical address of this descriptor 345 size_t buffer_size; // Size of the buffer 346 void *buffer_logical; // Logical pointer to the buffer 347 void *next_logical_descriptor; // Logical pointer next descriptor 348} ohci_general_td; 349 350#define OHCI_TD_BUFFER_ROUNDING 0x00040000 351#define OHCI_TD_DIRECTION_PID_MASK 0x00180000 352#define OHCI_TD_DIRECTION_PID_SETUP 0x00000000 353#define OHCI_TD_DIRECTION_PID_OUT 0x00080000 354#define OHCI_TD_DIRECTION_PID_IN 0x00100000 355#define OHCI_TD_GET_DELAY_INTERRUPT(x) (((x) >> 21) & 7) 356#define OHCI_TD_SET_DELAY_INTERRUPT(x) ((x) << 21) 357#define OHCI_TD_INTERRUPT_MASK 0x00e00000 358#define OHCI_TD_TOGGLE_CARRY 0x00000000 359#define OHCI_TD_TOGGLE_0 0x02000000 360#define OHCI_TD_TOGGLE_1 0x03000000 361#define OHCI_TD_TOGGLE_MASK 0x03000000 362#define OHCI_TD_GET_ERROR_COUNT(x) (((x) >> 26) & 3) 363#define OHCI_TD_GET_CONDITION_CODE(x) ((x) >> 28) 364#define OHCI_TD_SET_CONDITION_CODE(x) ((x) << 28) 365#define OHCI_TD_CONDITION_CODE_MASK 0xf0000000 366 367#define OHCI_TD_INTERRUPT_IMMEDIATE 0x00 368#define OHCI_TD_INTERRUPT_NONE 0x07 369 370#define OHCI_TD_CONDITION_NO_ERROR 0x00 371#define OHCI_TD_CONDITION_CRC_ERROR 0x01 372#define OHCI_TD_CONDITION_BIT_STUFFING 0x02 373#define OHCI_TD_CONDITION_TOGGLE_MISMATCH 0x03 374#define OHCI_TD_CONDITION_STALL 0x04 375#define OHCI_TD_CONDITION_NO_RESPONSE 0x05 376#define OHCI_TD_CONDITION_PID_CHECK_FAILURE 0x06 377#define OHCI_TD_CONDITION_UNEXPECTED_PID 0x07 378#define OHCI_TD_CONDITION_DATA_OVERRUN 0x08 379#define OHCI_TD_CONDITION_DATA_UNDERRUN 0x09 380#define OHCI_TD_CONDITION_BUFFER_OVERRUN 0x0c 381#define OHCI_TD_CONDITION_BUFFER_UNDERRUN 0x0d 382#define OHCI_TD_CONDITION_NOT_ACCESSED 0x0f 383 384#define OHCI_GENERAL_TD_ALIGN 16 385 386// -------------------------------- 387// Isochronous transfer descriptor structure (section 4.3.2) 388// -------------------------------- 389 390#define OHCI_ITD_NOFFSET 8 391typedef struct { 392 // Hardware part 32 byte 393 uint32 flags; 394 uint32 buffer_page_byte_0; // Physical page number of byte 0 395 uint32 next_physical_descriptor; // Next isochronous transfer descriptor 396 uint32 last_byte_address; // Physical buffer end 397 uint16 offset[OHCI_ITD_NOFFSET]; // Buffer offsets 398 // Software part 399 uint32 physical_address; // Physical address of this descriptor 400 size_t buffer_size; // Size of the buffer 401 void *buffer_logical; // Logical pointer to the buffer 402 void *next_logical_descriptor; // Logical pointer next descriptor 403 void *next_done_descriptor; // Used for collision in the hash table 404} ohci_isochronous_td; 405 406#define OHCI_ITD_GET_STARTING_FRAME(x) ((x) & 0x0000ffff) 407#define OHCI_ITD_SET_STARTING_FRAME(x) ((x) & 0xffff) 408#define OHCI_ITD_GET_DELAY_INTERRUPT(x) (((x) >> 21) & 7) 409#define OHCI_ITD_SET_DELAY_INTERRUPT(x) ((x) << 21) 410#define OHCI_ITD_INTERRUPT_MASK 0x00e00000 411#define OHCI_ITD_GET_FRAME_COUNT(x) ((((x) >> 24) & 7) + 1) 412#define OHCI_ITD_SET_FRAME_COUNT(x) (((x) - 1) << 24) 413#define OHCI_ITD_GET_CONDITION_CODE(x) ((x) >> 28) 414#define OHCI_ITD_SET_CONDITION_CODE(x) ((x) << 28) 415#define OHCI_ITD_CONDITION_CODE_MASK 0xf0000000 416 417#define OHCI_ITD_OFFSET_IDX(x) (x) 418 419#define OHCI_ITD_INTERRUPT_IMMEDIATE 0x00 420#define OHCI_ITD_INTERRUPT_NONE 0x07 421 422#define OHCI_ITD_CONDITION_NO_ERROR 0x00 423#define OHCI_ITD_CONDITION_CRC_ERROR 0x01 424#define OHCI_ITD_CONDITION_BIT_STUFFING 0x02 425#define OHCI_ITD_CONDITION_TOGGLE_MISMATCH 0x03 426#define OHCI_ITD_CONDITION_STALL 0x04 427#define OHCI_ITD_CONDITION_NO_RESPONSE 0x05 428#define OHCI_ITD_CONDITION_PID_CHECK_FAILURE 0x06 429#define OHCI_ITD_CONDITION_UNEXPECTED_PID 0x07 430#define OHCI_ITD_CONDITION_DATA_OVERRUN 0x08 431#define OHCI_ITD_CONDITION_DATA_UNDERRUN 0x09 432#define OHCI_ITD_CONDITION_BUFFER_OVERRUN 0x0c 433#define OHCI_ITD_CONDITION_BUFFER_UNDERRUN 0x0d 434#define OHCI_ITD_CONDITION_NOT_ACCESSED 0x0f 435 436// TO FIX 437#define itd_pswn itd_offset // Packet Status Word 438#define OHCI_ITD_PAGE_SELECT 0x00001000 439#define OHCI_ITD_MK_OFFS(len) (0xe000 | ((len) & 0x1fff)) 440#define OHCI_ITD_GET_BUFFER_LENGTH(x) ((x) & 0xfff) 441#define OHCI_ITD_GET_BUFFER_CONDITION_CODE(x) ((x) >> 12) 442 443#define OHCI_ISOCHRONOUS_TD_ALIGN 32 444 445// Number of frames 446#define NUMBER_OF_FRAMES 1024 447#define MAX_AVAILABLE_BANDWIDTH 900 // Microseconds 448 449// -------------------------------- 450// Completion Codes (section 4.3.3) 451// -------------------------------- 452 453#define OHCI_NO_ERROR 0 454#define OHCI_CRC 1 455#define OHCI_BIT_STUFFING 2 456#define OHCI_DATA_TOGGLE_MISMATCH 3 457#define OHCI_STALL 4 458#define OHCI_DEVICE_NOT_RESPONDING 5 459#define OHCI_PID_CHECK_FAILURE 6 460#define OHCI_UNEXPECTED_PID 7 461#define OHCI_DATA_OVERRUN 8 462#define OHCI_DATA_UNDERRUN 9 463#define OHCI_BUFFER_OVERRUN 12 464#define OHCI_BUFFER_UNDERRUN 13 465#define OHCI_NOT_ACCESSED 15 466 467// -------------------------------- 468// Some delay needed when changing 469// certain registers. 470// -------------------------------- 471 472#define OHCI_ENABLE_POWER_DELAY 5000 473#define OHCI_READ_DESC_DELAY 5000 474 475// Maximum port count set by OHCI 476#define OHCI_MAX_PORT_COUNT 15 477 478#endif // OHCI_HARDWARE_H 479