1/* 2 * Copyright 2020, J��r��me Duval, jerome.duval@gmail.com. 3 * 4 * Distributed under the terms of the MIT License. 5 */ 6#ifndef _PCH_I2C_HARDWARE_H 7#define _PCH_I2C_HARDWARE_H 8 9 10#define PCH_IC_CON 0x00 11#define PCH_IC_CON_MASTER 0x1 12#define PCH_IC_CON_SPEED_STD 0x2 13#define PCH_IC_CON_SPEED_FAST 0x4 14#define PCH_IC_CON_SPEED_HIGH 0x6 15#define PCH_IC_CON_10BIT_ADDR_MASTER 0x10 16#define PCH_IC_CON_RESTART_EN 0x20 17#define PCH_IC_CON_SLAVE_DISABLE 0x40 18#define PCH_IC_CON_TX_EMPTY_CTRL 0x100 19#define PCH_IC_TAR 0x04 20#define PCH_IC_HS_MADDR 0x08 21#define PCH_IC_DATA_CMD 0x10 22#define PCH_IC_DATA_CMD_READ (1 << 8) 23#define PCH_IC_DATA_CMD_STOP (1 << 9) 24#define PCH_IC_DATA_CMD_RESTART (1 << 10) 25#define PCH_IC_SS_SCL_HCNT 0x14 26#define PCH_IC_SS_SCL_LCNT 0x18 27#define PCH_IC_FS_SCL_HCNT 0x1c 28#define PCH_IC_FS_SCL_LCNT 0x20 29#define PCH_IC_HS_SCL_HCNT 0x24 30#define PCH_IC_HS_SCL_LCNT 0x28 31#define PCH_IC_INTR_STAT 0x2c 32#define PCH_IC_INTR_STAT_RX_UNDER (1 << 0) 33#define PCH_IC_INTR_STAT_RX_OVER (1 << 1) 34#define PCH_IC_INTR_STAT_RX_FULL (1 << 2) 35#define PCH_IC_INTR_STAT_TX_OVER (1 << 3) 36#define PCH_IC_INTR_STAT_TX_EMPTY (1 << 4) 37#define PCH_IC_INTR_STAT_RD_REQ (1 << 5) 38#define PCH_IC_INTR_STAT_TX_ABRT (1 << 6) 39#define PCH_IC_INTR_STAT_RX_DONE (1 << 7) 40#define PCH_IC_INTR_STAT_ACTIVITY (1 << 8) 41#define PCH_IC_INTR_STAT_STOP_DET (1 << 9) 42#define PCH_IC_INTR_STAT_START_DET (1 << 10) 43#define PCH_IC_INTR_STAT_GEN_CALL (1 << 11) 44#define PCH_IC_INTR_STAT_MST_ON_HOLD (1 << 13) 45 46#define PCH_IC_INTR_MASK 0x30 47#define PCH_IC_RAW_INTR_STAT 0x34 48#define PCH_IC_RX_TL 0x38 49#define PCH_IC_TX_TL 0x3c 50#define PCH_IC_CLR_INTR 0x40 51#define PCH_IC_CLR_RX_UNDER 0x44 52#define PCH_IC_CLR_RX_OVER 0x48 53#define PCH_IC_CLR_TX_OVER 0x4c 54#define PCH_IC_CLR_RD_REQ 0x50 55#define PCH_IC_CLR_TX_ABRT 0x54 56#define PCH_IC_CLR_RX_DONE 0x58 57#define PCH_IC_CLR_ACTIVITY 0x5c 58#define PCH_IC_CLR_STOP_DET 0x60 59#define PCH_IC_CLR_START_DET 0x64 60#define PCH_IC_CLR_GEN_CALL 0x68 61#define PCH_IC_ENABLE 0x6c 62#define PCH_IC_STATUS 0x70 63#define PCH_IC_STATUS_ACTIVITY 0x1 64#define PCH_IC_TXFLR 0x74 65#define PCH_IC_RXFLR 0x78 66#define PCH_IC_SDA_HOLD 0x7c 67#define PCH_IC_TX_ABRT_SOURCE 0x80 68#define PCH_IC_DMA_CR 0x88 69#define PCH_IC_DMA_TDLR 0x8c 70#define PCH_IC_DMA_RDLR 0x90 71#define PCH_IC_ACK_GENERAL_CALL 0x98 72#define PCH_IC_ENABLE_STATUS 0x9c 73#define PCH_IC_FS_SPKLEN 0xa0 74#define PCH_IC_CLR_RESTRART_DET 0xa8 75#define PCH_IC_COMP_PARAM1 0xf4 76#define PCH_IC_COMP_PARAM1_RX(x) (1 + (((x) >> 8) & 0xff)) 77#define PCH_IC_COMP_PARAM1_TX(x) (1 + (((x) >> 16) & 0xff)) 78#define PCH_IC_COMP_VERSION 0xf8 79#define PCH_IC_COMP_VERSION_MIN 0x3131312a 80 81#define PCH_SUP_RESETS 0x204 82#define PCH_SUP_RESETS_FUNC 0x3 83#define PCH_SUP_RESETS_IDMA 0x4 84#define PCH_SUP_ACTIVELTR_VALUE 0x210 85#define PCH_SUP_IDLELTR_VALUE 0x214 86#define PCH_SUP_TX_ACK_COUNT 0x218 87#define PCH_SUP_RX_BYTE_COUNT 0x21c 88#define PCH_SUP_TX_COMPLETE_INTR_STAT 0x220 89#define PCH_SUP_TX_COMPLETE_INTR_CLR 0x224 90#define PCH_SUP_SW_SCRATCH_0 0x228 91#define PCH_SUP_SW_SCRATCH_1 0x22c 92#define PCH_SUP_SW_SCRATCH_2 0x230 93#define PCH_SUP_SW_SCRATCH_3 0x234 94#define PCH_SUP_CLOCK_GATE 0x238 95#define PCH_SUP_REMAP_ADDR_LO 0x240 96#define PCH_SUP_REMAP_ADDR_HI 0x244 97#define PCH_SUP_DEVIDLE_CONTROL 0x24c 98#define PCH_SUP_CAPABLITIES 0x2fc 99#define PCH_SUP_CAPABLITIES_TYPE_MASK 0xf 100#define PCH_SUP_CAPABLITIES_TYPE_SHIFT 4 101 102 103#endif // _PCH_I2C_HARDWARE_H 104