1/* CTRC functionality */ 2/* Author: 3 Rudolf Cornelissen 11/2002-9/2005 4*/ 5 6#define MODULE_BIT 0x00040000 7 8#include "std.h" 9 10/*Adjust passed parameters to a valid mode line*/ 11status_t eng_crtc_validate_timing( 12 uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, 13 uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt 14) 15{ 16/* horizontal */ 17 /* make all parameters multiples of 8 */ 18 *hd_e &= 0xfff8; 19 *hs_s &= 0xfff8; 20 *hs_e &= 0xfff8; 21 *ht &= 0xfff8; 22 23 /* confine to required number of bits, taking logic into account */ 24 if (*hd_e > ((0x00ff - 2) << 3)) *hd_e = ((0x00ff - 2) << 3); 25 if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3); 26 if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3); 27 if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3); 28 29 /* NOTE: keep horizontal timing at multiples of 8! */ 30 /* confine to a reasonable width */ 31 if (*hd_e < 640) *hd_e = 640; 32 /* assuming all VIA unichrome cards to have same max. constraint.. */ 33 //fixme: checkout correct max... 34 if (*hd_e > 1600) *hd_e = 1600; 35 36 /* if hor. total does not leave room for a sensible sync pulse, increase it! */ 37 if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); 38 39 /* if hor. total does not adhere to max. blanking pulse width, decrease it! */ 40 if (*ht > (*hd_e + 0x3f8)) *ht = (*hd_e + 0x3f8); 41 42 /* make sure sync pulse is not during display */ 43 if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8); 44 if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8); 45 46 /* correct sync pulse if it is too long: 47 * there are only 5 bits available to save this in the card registers! */ 48 if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8); 49 50/*vertical*/ 51 /* confine to required number of bits, taking logic into account */ 52 if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); 53 if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); 54 if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; 55 if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2); 56 57 /* confine to a reasonable height */ 58 if (*vd_e < 480) *vd_e = 480; 59 /* assuming all VIA unichrome cards to have same max. constraint.. */ 60 //fixme: checkout correct max... 61 if (*vd_e > 1200) *vd_e = 1200; 62 63 /*if vertical total does not leave room for a sync pulse, increase it!*/ 64 if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); 65 66 /* if vert. total does not adhere to max. blanking pulse width, decrease it! */ 67 if (*vt > (*vd_e + 0xff)) *vt = (*vd_e + 0xff); 68 69 /* make sure sync pulse is not during display */ 70 if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1); 71 if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1); 72 73 /* correct sync pulse if it is too long: 74 * there are only 4 bits available to save this in the card registers! */ 75 if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f); 76 77 return B_OK; 78} 79 80/*set a mode line - inputs are in pixels*/ 81status_t eng_crtc_set_timing(display_mode target) 82{ 83 uint16 fifolimit = 0; 84 uint8 temp; 85 86 uint32 htotal; /*total horizontal total VCLKs*/ 87 uint32 hdisp_e; /*end of horizontal display (begins at 0)*/ 88 uint32 hsync_s; /*begin of horizontal sync pulse*/ 89 uint32 hsync_e; /*end of horizontal sync pulse*/ 90 uint32 hblnk_s; /*begin horizontal blanking*/ 91 uint32 hblnk_e; /*end horizontal blanking*/ 92 93 uint32 vtotal; /*total vertical total scanlines*/ 94 uint32 vdisp_e; /*end of vertical display*/ 95 uint32 vsync_s; /*begin of vertical sync pulse*/ 96 uint32 vsync_e; /*end of vertical sync pulse*/ 97 uint32 vblnk_s; /*begin vertical blanking*/ 98 uint32 vblnk_e; /*end vertical blanking*/ 99 100 uint32 linecomp; /*split screen and vdisp_e interrupt*/ 101 102 LOG(4,("CRTC: setting timing\n")); 103 104 /* setup tuned internal modeline for flatpanel if connected and active */ 105 /* notes: 106 * - the CRTC modeline must end earlier than the panel modeline to keep correct 107 * sync going; 108 * - if the CRTC modeline ends too soon, pixelnoise will occur in 8 (or so) pixel 109 * wide horizontal stripes. This can be observed earliest on fullscreen overlay, 110 * and if it gets worse, also normal desktop output will suffer. The stripes 111 * are mainly visible at the left of the screen, over the entire screen height. */ 112 if (0)//si->ps.tmds1_active) 113 { 114 LOG(2,("CRTC: DFP active: tuning modeline\n")); 115 116 /* horizontal timing */ 117 target.timing.h_sync_start = 118 ((uint16)((si->ps.p1_timing.h_sync_start / ((float)si->ps.p1_timing.h_display)) * 119 target.timing.h_display)) & 0xfff8; 120 121 target.timing.h_sync_end = 122 ((uint16)((si->ps.p1_timing.h_sync_end / ((float)si->ps.p1_timing.h_display)) * 123 target.timing.h_display)) & 0xfff8; 124 125 target.timing.h_total = 126 (((uint16)((si->ps.p1_timing.h_total / ((float)si->ps.p1_timing.h_display)) * 127 target.timing.h_display)) & 0xfff8) - 8; 128 129 /* in native mode the CRTC needs some extra time to keep synced correctly; 130 * OTOH the overlay unit distorts if we reserve too much time! */ 131 if (target.timing.h_display == si->ps.p1_timing.h_display) 132 { 133 /* NV11 timing has different constraints than later cards */ 134 if (si->ps.card_type == NV11) 135 target.timing.h_total -= 56; 136 else 137 /* confirmed NV34 with 1680x1050 panel */ 138 target.timing.h_total -= 32; 139 } 140 141 if (target.timing.h_sync_start == target.timing.h_display) 142 target.timing.h_sync_start += 8; 143 if (target.timing.h_sync_end == target.timing.h_total) 144 target.timing.h_sync_end -= 8; 145 146 /* vertical timing */ 147 target.timing.v_sync_start = 148 ((uint16)((si->ps.p1_timing.v_sync_start / ((float)si->ps.p1_timing.v_display)) * 149 target.timing.v_display)); 150 151 target.timing.v_sync_end = 152 ((uint16)((si->ps.p1_timing.v_sync_end / ((float)si->ps.p1_timing.v_display)) * 153 target.timing.v_display)); 154 155 target.timing.v_total = 156 ((uint16)((si->ps.p1_timing.v_total / ((float)si->ps.p1_timing.v_display)) * 157 target.timing.v_display)) - 1; 158 159 if (target.timing.v_sync_start == target.timing.v_display) 160 target.timing.v_sync_start += 1; 161 if (target.timing.v_sync_end == target.timing.v_total) 162 target.timing.v_sync_end -= 1; 163 164 /* disable GPU scaling testmode so automatic scaling will be done */ 165 DACW(FP_DEBUG1, 0); 166 } 167 168 /* Modify parameters as required by standard VGA */ 169 htotal = ((target.timing.h_total >> 3) - 5); 170 hdisp_e = ((target.timing.h_display >> 3) - 1); 171 hblnk_s = hdisp_e; 172 hblnk_e = (htotal + 4);//0; 173 hsync_s = (target.timing.h_sync_start >> 3); 174 hsync_e = (target.timing.h_sync_end >> 3); 175 176 vtotal = target.timing.v_total - 2; 177 vdisp_e = target.timing.v_display - 1; 178 vblnk_s = vdisp_e; 179 vblnk_e = (vtotal + 1); 180 vsync_s = target.timing.v_sync_start;//-1; 181 vsync_e = target.timing.v_sync_end;//-1; 182 183 /* prevent memory adress counter from being reset (linecomp may not occur). 184 * set all bits, otherwise distortion stripes may appear onscreen (VIA) */ 185 linecomp = 0xffff; 186 187 /* Note for laptop and DVI flatpanels: 188 * CRTC timing has a seperate set of registers from flatpanel timing. 189 * The flatpanel timing registers have scaling registers that are used to match 190 * these two modelines. */ 191 { 192 LOG(4,("CRTC: Setting full timing...\n")); 193 194 /* log the mode that will be set */ 195 LOG(2,("CRTC:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e)); 196 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e)); 197 198 /* actually program the card! */ 199 /* unlock CRTC registers at index 0-7 */ 200 CRTCW(VSYNCE, (CRTCR(VSYNCE) & 0x7f)); 201 /* horizontal standard VGA regs */ 202 CRTCW(HTOTAL, (htotal & 0xff)); 203 CRTCW(HDISPE, (hdisp_e & 0xff)); 204 CRTCW(HBLANKS, (hblnk_s & 0xff)); 205 /* also unlock vertical retrace registers in advance */ 206 CRTCW(HBLANKE, ((hblnk_e & 0x1f) | 0x80)); 207 CRTCW(HSYNCS, (hsync_s & 0xff)); 208 CRTCW(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2))); 209 210 /* vertical standard VGA regs */ 211 CRTCW(VTOTAL, (vtotal & 0xff)); 212 CRTCW(OVERFLOW, 213 ( 214 ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) | 215 ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) | 216 ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) | 217 ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x0100) >> (8 - 4)) 218 )); 219 CRTCW(PRROWSCN, 0x00); /* not used */ 220 CRTCW(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x0200) >> (9 - 6)))); 221 CRTCW(VSYNCS, (vsync_s & 0xff)); 222 CRTCW(VSYNCE, ((CRTCR(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); 223 CRTCW(VDISPE, (vdisp_e & 0xff)); 224 CRTCW(VBLANKS, (vblnk_s & 0xff)); 225 CRTCW(VBLANKE, (vblnk_e & 0xff)); 226 CRTCW(LINECOMP, (linecomp & 0xff)); 227 228 /* horizontal extended regs */ 229 CRTCW(HTIMEXT1, (CRTCR(HTIMEXT1) & 0xc8) | 230 ( 231 ((linecomp & 0x1c00) >> (10 - 0)) | 232 ((hblnk_e & 0x040) >> (6 - 5)) | 233 ((hsync_s & 0x100) >> (8 - 4)) 234 )); 235 CRTCW(HTIMEXT2, (CRTCR(HTIMEXT2) & 0xf7) | ((htotal & 0x100) >> (8 - 3))); 236 237 /* vertical extended regs */ 238 CRTCW(VTIMEXT_PIT, (CRTCR(VTIMEXT_PIT) & 0xe0) | 239 ( 240 ((vtotal & 0x400) >> (10 - 0)) | 241 ((vsync_s & 0x400) >> (10 - 1)) | 242 ((vdisp_e & 0x400) >> (10 - 2)) | 243 ((vblnk_s & 0x400) >> (10 - 3)) | 244 ((linecomp & 0x2000) >> (13 - 4)) 245 )); 246 247 /* setup HSYNC & VSYNC polarity */ 248 LOG(2,("CRTC: sync polarity: ")); 249 temp = ENG_REG8(RG8_MISCR); 250 if (target.timing.flags & B_POSITIVE_HSYNC) 251 { 252 LOG(2,("H:pos ")); 253 temp &= ~0x40; 254 } 255 else 256 { 257 LOG(2,("H:neg ")); 258 temp |= 0x40; 259 } 260 if (target.timing.flags & B_POSITIVE_VSYNC) 261 { 262 LOG(2,("V:pos ")); 263 temp &= ~0x80; 264 } 265 else 266 { 267 LOG(2,("V:neg ")); 268 temp |= 0x80; 269 } 270 ENG_REG8(RG8_MISCW) = temp; 271 272 LOG(2,(", MISC reg readback: $%02x\n", ENG_REG8(RG8_MISCR))); 273 274 /* setup CRTC FIFO depth, method 'extrapolated' from VBE BIOS behaviour */ 275 switch (target.space) 276 { 277 case B_CMAP8: 278 fifolimit = 0x0001; 279 break; 280 case B_RGB15_LITTLE: 281 case B_RGB16_LITTLE: 282 fifolimit = 0x0002; 283 break; 284 case B_RGB24_LITTLE: 285 fifolimit = 0x0003; 286 break; 287 case B_RGB32_LITTLE: 288 fifolimit = 0x0004; 289 break; 290 } 291 fifolimit *= target.timing.h_display; 292 fifolimit >>= 4; 293 fifolimit += 4; 294 SEQW(FETCHCNTLO, (fifolimit & 0x00fe)); 295 SEQW(FETCHCNTHI, (((SEQR(FETCHCNTHI)) & 0xfc) | ((fifolimit & 0x0300) >> 8))); 296 } 297 298 /* always disable interlaced operation */ 299 /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */ 300// CRTCW(INTERLACE, 0xff); 301 302 /* disable CRTC slaved mode unless a panel is in use */ 303 // fixme: this kills TVout when it was in use... 304// if (!si->ps.tmds1_active) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x7f)); 305 306 /* setup flatpanel if connected and active */ 307 if (0)//si->ps.tmds1_active) 308 { 309 uint32 iscale_x, iscale_y; 310 311 /* calculate inverse scaling factors used by hardware in 20.12 format */ 312 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p1_timing.h_display); 313 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p1_timing.v_display); 314 315 /* unblock flatpanel timing programming (or something like that..) */ 316 CRTCW(FP_HTIMING, 0); 317 CRTCW(FP_VTIMING, 0); 318 LOG(2,("CRTC: FP_HTIMING reg readback: $%02x\n", CRTCR(FP_HTIMING))); 319 LOG(2,("CRTC: FP_VTIMING reg readback: $%02x\n", CRTCR(FP_VTIMING))); 320 321 /* enable full width visibility on flatpanel */ 322 DACW(FP_HVALID_S, 0); 323 DACW(FP_HVALID_E, (si->ps.p1_timing.h_display - 1)); 324 /* enable full height visibility on flatpanel */ 325 DACW(FP_VVALID_S, 0); 326 DACW(FP_VVALID_E, (si->ps.p1_timing.v_display - 1)); 327 328 /* nVidia cards support upscaling except on ??? */ 329 /* NV11 cards can upscale after all! */ 330 if (0)//si->ps.card_type == NV11) 331 { 332 /* disable last fetched line limiting */ 333 DACW(FP_DEBUG2, 0x00000000); 334 /* inform panel to scale if needed */ 335 if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12))) 336 { 337 LOG(2,("CRTC: DFP needs to do scaling\n")); 338 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) | 0x00000100)); 339 } 340 else 341 { 342 LOG(2,("CRTC: no scaling for DFP needed\n")); 343 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); 344 } 345 } 346 else 347 { 348 float dm_aspect; 349 350 LOG(2,("CRTC: GPU scales for DFP if needed\n")); 351 352 /* calculate display mode aspect */ 353 dm_aspect = (target.timing.h_display / ((float)target.timing.v_display)); 354 355 /* limit last fetched line if vertical scaling is done */ 356 if (iscale_y != (1 << 12)) 357 DACW(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16))); 358 else 359 DACW(FP_DEBUG2, 0x00000000); 360 361 /* inform panel not to scale */ 362 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); 363 364 /* GPU scaling is automatically setup by hardware, so only modify this 365 * scalingfactor for non 4:3 (1.33) aspect panels; 366 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */ 367 368 /* correct for widescreen panels relative to mode... 369 * (so if panel is more widescreen than mode being set) */ 370 /* BTW: known widescreen panels: 371 * 1280 x 800 (1.60), 372 * 1440 x 900 (1.60), 373 * 1680 x 1050 (1.60), 374 * 1920 x 1200 (1.60). */ 375 /* known 4:3 aspect non-standard resolution panels: 376 * 1400 x 1050 (1.33). */ 377 /* NOTE: 378 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 379 if ((iscale_x != (1 << 12)) && (si->ps.panel1_aspect > (dm_aspect + 0.10))) 380 { 381 uint16 diff; 382 383 LOG(2,("CRTC: (relative) widescreen panel: tuning horizontal scaling\n")); 384 385 /* X-scaling should be the same as Y-scaling */ 386 iscale_x = iscale_y; 387 /* enable testmode (b12) and program modified X-scaling factor */ 388 DACW(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12))); 389 /* center/cut-off left and right side of screen */ 390 diff = ((si->ps.p1_timing.h_display - 391 (target.timing.h_display * ((1 << 12) / ((float)iscale_x)))) 392 / 2); 393 DACW(FP_HVALID_S, diff); 394 DACW(FP_HVALID_E, ((si->ps.p1_timing.h_display - diff) - 1)); 395 } 396 /* correct for portrait panels... */ 397 /* NOTE: 398 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 399 if ((iscale_y != (1 << 12)) && (si->ps.panel1_aspect < (dm_aspect - 0.10))) 400 { 401 LOG(2,("CRTC: (relative) portrait panel: should tune vertical scaling\n")); 402 /* fixme: implement if this kind of portrait panels exist on nVidia... */ 403 } 404 } 405 406 /* do some logging.. */ 407 LOG(2,("CRTC: FP_HVALID_S reg readback: $%08x\n", DACR(FP_HVALID_S))); 408 LOG(2,("CRTC: FP_HVALID_E reg readback: $%08x\n", DACR(FP_HVALID_E))); 409 LOG(2,("CRTC: FP_VVALID_S reg readback: $%08x\n", DACR(FP_VVALID_S))); 410 LOG(2,("CRTC: FP_VVALID_E reg readback: $%08x\n", DACR(FP_VVALID_E))); 411 LOG(2,("CRTC: FP_DEBUG0 reg readback: $%08x\n", DACR(FP_DEBUG0))); 412 LOG(2,("CRTC: FP_DEBUG1 reg readback: $%08x\n", DACR(FP_DEBUG1))); 413 LOG(2,("CRTC: FP_DEBUG2 reg readback: $%08x\n", DACR(FP_DEBUG2))); 414 LOG(2,("CRTC: FP_DEBUG3 reg readback: $%08x\n", DACR(FP_DEBUG3))); 415 LOG(2,("CRTC: FP_TG_CTRL reg readback: $%08x\n", DACR(FP_TG_CTRL))); 416 } 417 418 return B_OK; 419} 420 421status_t eng_crtc_depth(int mode) 422{ 423 uint8 genctrl = 0; 424 425 /* set VCLK scaling */ 426 /* genctrl bit use: 427 b7: %0 = PAL is 6-bit wide (on b0-5) 428 %1 = PAL is 8-bit wide 429 Note: 430 3123Ax chips only support 6-bits. If we support that chip, 431 update PAL programming! 432 b6: ? 433 b5: %0 = distortions (stripes) only (tested 8-bit mode) 434 %1 = OK 435 b4: %0 = 15-bit color in 2 bytes/pixel mode; 436 %1 = 16-bit color in 2 bytes/pixel mode. 437 b3-2:%00 = 1 byte /pixel; 438 %01 = 2 bytes/pixel; 439 %10 = 3 bytes/pixel; (assumed) 440 %11 = 4 bytes/pixel. 441 b1: %0 = 4 bits/pixel; 442 %1 = b3-2 scheme above. 443 b0: ? 444 */ 445 switch(mode) 446 { 447 case BPP8: 448 /* indexed mode */ 449 genctrl = 0xa2; //%1010 0010 450 break; 451 case BPP15: 452 /* direct mode */ 453 genctrl = 0xa6; //%1010 0110 454 break; 455 case BPP16: 456 /* direct mode */ 457 genctrl = 0xb6; //%1011 0110 458 break; 459 case BPP24: 460 /* direct mode */ 461 //fixme? this is a guess.. 462 genctrl = 0xaa; //%1010 1010 463 break; 464 case BPP32: 465 /* direct mode */ 466 genctrl = 0xae; //%1010 1110 467 break; 468 } 469 /* setup bytes per pixel, and direct/indirect mode */ 470 SEQW(COLDEPTH, genctrl); 471 472 return B_OK; 473} 474 475status_t eng_crtc_dpms(bool display, bool h, bool v) 476{ 477 uint8 temp; 478 479 LOG(4,("CRTC: setting DPMS: ")); 480 481 /* start synchronous reset: required before turning screen off! */ 482 SEQW(RESET, 0x01); 483 484 /* turn screen off */ 485 temp = SEQR(CLKMODE); 486 if (display) 487 { 488 SEQW(CLKMODE, (temp & ~0x20)); 489 490 /* end synchronous reset if display should be enabled */ 491 SEQW(RESET, 0x03); 492 493 //'safe mode' test! feedback needed with this 'setting'! 494 if (0)//si->ps.tmds1_active) 495 { 496 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) 497 * internal transmitters... */ 498 /* note: 499 * the powerbits in this register are hardwired to the DVI connectors, 500 * instead of to the DACs! (confirmed NV34) */ 501 //fixme... 502 DACW(FP_DEBUG0, (DACR(FP_DEBUG0) & 0xcfffffff)); 503 /* ... and powerup external TMDS transmitter if it exists */ 504 /* (confirmed OK on NV28 and NV34) */ 505 CRTCW(0x59, (CRTCR(0x59) | 0x01)); 506 } 507 508 LOG(4,("display on, ")); 509 } 510 else 511 { 512 SEQW(CLKMODE, (temp | 0x20)); 513 514 //'safe mode' test! feedback needed with this 'setting'! 515 if (0)//si->ps.tmds1_active) 516 { 517 /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink) 518 * internal transmitters... */ 519 /* note: 520 * the powerbits in this register are hardwired to the DVI connectors, 521 * instead of to the DACs! (confirmed NV34) */ 522 //fixme... 523 DACW(FP_DEBUG0, (DACR(FP_DEBUG0) | 0x30000000)); 524 /* ... and powerdown external TMDS transmitter if it exists */ 525 /* (confirmed OK on NV28 and NV34) */ 526 CRTCW(0x59, (CRTCR(0x59) & 0xfe)); 527 } 528 529 LOG(4,("display off, ")); 530 } 531 532 if (h) 533 { 534 CRTCW(HTIMEXT2, (CRTCR(HTIMEXT2) & 0xef)); 535 LOG(4,("hsync enabled, ")); 536 } 537 else 538 { 539 CRTCW(HTIMEXT2, (CRTCR(HTIMEXT2) | 0x10)); 540 LOG(4,("hsync disabled, ")); 541 } 542 if (v) 543 { 544 CRTCW(HTIMEXT2, (CRTCR(HTIMEXT2) & 0xdf)); 545 LOG(4,("vsync enabled\n")); 546 } 547 else 548 { 549 CRTCW(HTIMEXT2, (CRTCR(HTIMEXT2) | 0x20)); 550 LOG(4,("vsync disabled\n")); 551 } 552 553 return B_OK; 554} 555 556status_t eng_crtc_dpms_fetch(bool *display, bool *h, bool *v) 557{ 558 *display = !(SEQR(CLKMODE) & 0x20); 559 *h = !(CRTCR(HTIMEXT2) & 0x10); 560 *v = !(CRTCR(HTIMEXT2) & 0x20); 561 562 LOG(4,("CTRC: fetched DPMS state: ")); 563 if (*display) LOG(4,("display on, ")); 564 else LOG(4,("display off, ")); 565 if (*h) LOG(4,("hsync enabled, ")); 566 else LOG(4,("hsync disabled, ")); 567 if (*v) LOG(4,("vsync enabled\n")); 568 else LOG(4,("vsync disabled\n")); 569 570 return B_OK; 571} 572 573status_t eng_crtc_set_display_pitch() 574{ 575 uint16 offset; 576 577 LOG(4,("CRTC: setting card pitch (offset between lines)\n")); 578 579 /* figure out offset value hardware needs */ 580 offset = si->fbc.bytes_per_row >> 3; 581 582 LOG(2,("CRTC: offset register set to: $%04x\n", offset)); 583 584 /* program the card */ 585 CRTCW(PITCHL, (offset & 0x00ff)); 586 CRTCW(VTIMEXT_PIT, (((CRTCR(VTIMEXT_PIT)) & 0x1f) | ((offset & 0x0700) >> 3))); 587 588 return B_OK; 589} 590 591status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp) 592{ 593 LOG(4,("CRTC: setting card RAM to be displayed bpp %d\n", bpp)); 594 595 LOG(2,("CRTC: startadd: $%08x\n", startadd)); 596 LOG(2,("CRTC: frameRAM: $%08x\n", si->framebuffer)); 597 LOG(2,("CRTC: framebuffer: $%08x\n", si->fbc.frame_buffer)); 598 599 /* VIA: upto 32Mb RAM can be adressed */ 600 601 /* set standard registers */ 602 /* (VIA: startadress in 64bit words (b3 - b16): checked CLE266) */ 603 CRTCW(FBSTADDL, ((startadd & 0x000001f8) >> 1)); 604 CRTCW(FBSTADDH, ((startadd & 0x0001fe00) >> 9)); 605 /* set extended bits: (b17-24) */ 606 CRTCW(FBSTADDE, ((startadd & 0x01fe0000) >> 17)); 607 608 /* VIA doesn't support pixelpanning (checked CLE266). */ 609 610 return B_OK; 611} 612 613status_t eng_crtc_cursor_init() 614{ 615 int i; 616 uint32 * fb; 617 /* cursor bitmap will be stored at the start of the framebuffer */ 618 const uint32 curadd = 0; 619 620 /* background is white */ 621 CRTCDW(CURSOR_BG, 0xffffffff); 622 /* foreground is black */ 623 CRTCDW(CURSOR_FG, 0x00000000); 624 /* set cursor bitmap adress */ 625 CRTCDW(CURSOR_MODE, (curadd & 0xfffffffc)); 626 627 /* clear cursor (via cursor uses 4kb max) */ 628 fb = (uint32 *) si->framebuffer + curadd; 629 for (i = 0; i < (4096/4); i += 2) 630 { 631 fb[i + 0] = 0x00000000; 632 fb[i + 1] = 0xffffffff; 633 } 634 635 /* activate hardware cursor */ 636 eng_crtc_cursor_show(); 637 638 return B_OK; 639} 640 641status_t eng_crtc_cursor_show() 642{ 643 LOG(4,("CRTC: enabling cursor\n")); 644 /* b1 = 0 shows a 64x64 pixel map, b1 = 1 shows a 32x32 pixel map; 645 * b0 = 0 disables the cursor, b0 = 1 enables the cursor. */ 646 CRTCDW(CURSOR_MODE, (CRTCDR(CURSOR_MODE) | 0x00000003)); 647 648 return B_OK; 649} 650 651status_t eng_crtc_cursor_hide() 652{ 653 LOG(4,("CRTC: disabling cursor\n")); 654 CRTCDW(CURSOR_MODE, (CRTCDR(CURSOR_MODE) & 0xfffffffc)); 655 656 return B_OK; 657} 658 659/*set up cursor shape*/ 660status_t eng_crtc_cursor_define(uint8* andMask,uint8* xorMask) 661{ 662 int y; 663 uint8 *cursor; 664 665 /* get a pointer to the cursor */ 666 cursor = (uint8*) si->framebuffer; 667 668 /* pixmap is 4 bytes per row, two rows form pixeldata for one pixel in height */ 669 for (y = 0; y < 16; y++) 670 { 671 cursor[0 + (y * 8)] = *xorMask++; 672 cursor[1 + (y * 8)] = *xorMask++; 673 cursor[4 + (y * 8)] = *andMask++; 674 cursor[5 + (y * 8)] = *andMask++; 675 } 676 677 return B_OK; 678// 679/* for (y = 0; y < 1; y++)//hele hoogte invert 680 { 681 cursor[0 + (y*4)] = 0xff;//linker helft invert 682 cursor[0 + (1*4)] = 0xff;//rechter helft invert 683//invert = %11 684//black = %00 685 686// cursor[0 + (y * 4)] = *xorMask++; 687// cursor[32 + (y * 4)] = *xorMask++; 688// cursor[64 + (y * 4)] = *xorMask++; 689// cursor[96 + (y * 4)] = *xorMask++; 690 } 691*/ 692} 693 694/* position the cursor */ 695status_t eng_crtc_cursor_position(uint16 x, uint16 y) 696{ 697 /* set cursor origin, b1-7 = Y offset; b17-23 = X offset 698 * (? linux seems non-consistent) */ 699 CRTCDW(CURSOR_ORG, 0x00000000); 700 /* update cursorposition */ 701 CRTCDW(CURSOR_POS, (((x & 0x07ff) << 16) | (y & 0x07ff))); 702 703 return B_OK; 704} 705