1/*
2	Copyright (c) 2002-04, Thomas Kurschel
3
4
5	Part of Radeon accelerant
6
7	Header file explicitely for display mode changes
8*/
9
10#ifndef _SET_MODE_H
11#define _SET_MODE_H
12
13// PLL divider values
14typedef struct {
15	uint32 post_code;			// code for post divider
16	uint32 post;				// value of post divider
17	uint32 extra_post_code;		// code for extra post divider
18	uint32 extra_post;			// value of extra post divider
19	uint32 ref;					// reference divider
20	uint32 feedback;			// feedback divider
21	uint32 freq;				// resulting frequency
22} pll_dividers;
23
24
25// TV-timing
26typedef struct {
27	uint32 freq;				// TV sub carrier frequency x12
28	uint16 h_total;
29	uint16 h_sync_len;
30	uint16 h_genclk_delay;
31	uint16 h_setup_delay;
32	uint16 h_active_delay;
33	uint16 h_active_len;
34	uint16 v_total;
35	uint16 v_active_lines;
36	uint16 v_field_total;
37	uint16 v_fields;
38	uint16 f_total;
39	uint16 frame_size_adjust;
40	uint32 scale;
41} tv_timing;
42
43
44// TV-Out parameters
45typedef struct {
46	uint16 y_accum_init;
47	uint16 uv_accum_init;
48	uint16 uv_inc;
49	uint16 h_inc;
50	uint32 tv_clocks_to_active;
51
52	uint16 f_restart;
53	uint16 v_restart;
54	uint16 h_restart;
55	bool mode888;
56
57	uint16 y_saw_tooth_slope;
58	uint16 y_saw_tooth_amp;
59	uint16 y_rise_accum_init;
60	uint16 y_fall_accum_init;
61	bool y_coeff_enable;
62	uint8 y_coeff_value;
63
64	pll_dividers	tv_dividers;
65	pll_dividers	crt_dividers;
66
67	tv_timing		timing;
68} impactv_params;
69
70
71// CRTC register content (for mode change)
72typedef struct {
73	uint32		crtc_h_total_disp;
74	uint32		crtc_h_sync_strt_wid;
75	uint32		crtc_v_total_disp;
76	uint32		crtc_v_sync_strt_wid;
77	uint32		crtc_pitch;
78	uint32		crtc_gen_cntl;
79	uint32		crtc_offset_cntl;
80} crtc_regs;
81
82
83// PLL register content (for mode change)
84typedef struct {
85	uint32 		ppll_div_3;
86	uint32		ppll_ref_div;
87	uint32		htotal_cntl;
88
89	// pure information
90	uint32		dot_clock_freq;	// in 10 kHz
91	uint32		pll_output_freq;// in 10 kHz
92	int			feedback_div;
93	int			post_div;
94} pll_regs;
95
96
97// Flat Panel register content (for mode change)
98typedef struct {
99	uint32		fp_gen_cntl;
100	uint32		fp_panel_cntl;
101	uint32		lvds_gen_cntl;
102	uint32		tmds_pll_cntl;
103	uint32		tmds_trans_cntl;
104	uint32		fp_h_sync_strt_wid;
105	uint32		fp_v_sync_strt_wid;
106	uint32		fp2_gen_cntl;
107
108	uint32		fp2_h_sync_strt_wid;
109	uint32		fp2_v_sync_strt_wid;
110
111	// RMX registers
112	uint32		fp_horz_stretch;
113	uint32		fp_vert_stretch;
114
115	// Bios values used by Mobility Asics
116	uint32		bios_4_scratch;
117	uint32		bios_5_scratch;
118	uint32		bios_6_scratch;
119} fp_regs;
120
121
122#define RADEON_TV_TIMING_SIZE 32
123#define RADEON_TV_UPSAMP_COEFF_NUM (5*3)
124
125
126// ImpacTV-Out regs (for mode change)
127typedef struct {
128	uint32		tv_ftotal;
129	uint32		tv_vscaler_cntl1;
130	uint32		tv_y_saw_tooth_cntl;
131	uint32		tv_y_fall_cntl;
132	uint32		tv_y_rise_cntl;
133	uint32		tv_vscaler_cntl2;
134	uint32 		tv_hrestart;
135	uint32 		tv_vrestart;
136	uint32 		tv_frestart;
137	uint32		tv_tv_pll_cntl;
138	uint32 		tv_crt_pll_cntl;
139	uint32		tv_clock_sel_cntl;
140	uint32 		tv_clkout_cntl;
141	uint32		tv_htotal;
142	uint32 		tv_hsize;
143	uint32		tv_hdisp;
144	uint32		tv_hstart;
145	uint32		tv_vtotal;
146	uint32		tv_vdisp;
147	uint32		tv_sync_size;
148	uint32		tv_timing_cntl;
149	uint32		tv_modulator_cntl1;
150	uint32		tv_modulator_cntl2;
151	uint32		tv_data_delay_a;
152	uint32		tv_data_delay_b;
153	uint32		tv_frame_lock_cntl;
154	uint32		tv_pll_cntl1;
155	uint32		tv_rgb_cntl;
156	uint32		tv_pre_dac_mux_cntl;
157	uint32		tv_master_cntl;
158	uint32		tv_dac_cntl;
159	uint32		tv_uv_adr;
160	uint32		tv_pll_fine_cntl;
161	uint32		tv_gain_limit_settings;
162	uint32		tv_linear_gain_settings;
163	uint32		tv_upsamp_and_gain_cntl;
164	uint32		tv_crc_cntl;
165
166	uint16		tv_hor_timing[RADEON_TV_TIMING_SIZE];
167	uint16		tv_vert_timing[RADEON_TV_TIMING_SIZE];
168
169	uint32		tv_upsample_filter_coeff[RADEON_TV_UPSAMP_COEFF_NUM];
170} impactv_regs;
171
172
173// Monitor Signal Routing regs (for mode change)
174// (they collide with many other *_regs, so take
175// care to set only the bits really used for routing)
176typedef struct {
177	// DAC registers
178	uint32		dac_cntl2;
179	uint32		dac_cntl;
180	uint32		tv_master_cntl;
181	uint32		tv_dac_cntl;
182	bool		skip_tv_dac;	// if true, don't write tv_dac_cntl
183
184	// Display path registers
185	uint32		disp_hw_debug;
186	uint32		disp_output_cntl;
187	uint32		disp_tv_out_cntl;
188
189	// CRTC registers
190	uint32		crtc_ext_cntl;
191	uint32		crtc2_gen_cntl;
192
193	// PLL regs
194	uint32		vclk_ecp_cntl;
195	uint32		pixclks_cntl;
196
197	// GP IO-pad
198	uint32		gpiopad_a;
199
200	// flat panel registers
201	uint32		fp_gen_cntl;
202	uint32		fp2_gen_cntl;
203} routing_regs;
204
205
206// crtc.c
207uint16 Radeon_GetHSyncFudge( crtc_info *crtc, int datatype );
208void Radeon_CalcCRTCRegisters( accelerator_info *ai, crtc_info *crtc,
209	display_mode *mode, crtc_regs *values );
210void Radeon_ProgramCRTCRegisters( accelerator_info *ai, int crtc_idx,
211	crtc_regs *values );
212
213
214// pll.c
215void Radeon_CalcCRTPLLDividers( const general_pll_info *general_pll, const display_mode *mode, pll_dividers *dividers );
216void Radeon_CalcPLLRegisters( const display_mode *mode, const pll_dividers *dividers, pll_regs *values );
217void Radeon_ProgramPLL( accelerator_info *ai, int crtc_idx, pll_regs *values );
218void Radeon_CalcPLLDividers( const pll_info *pll, uint32 freq, uint fixed_post_div, pll_dividers *dividers );
219void Radeon_MatchCRTPLL(
220	const pll_info *pll,
221	uint32 tv_v_total, uint32 tv_h_total, uint32 tv_frame_size_adjust, uint32 freq,
222	const display_mode *mode, uint32 max_v_tweak, uint32 max_h_tweak,
223	uint32 max_frame_rate_drift, uint32 fixed_post_div,
224	pll_dividers *dividers,
225	display_mode *tweaked_mode );
226void Radeon_GetTVPLLConfiguration( const general_pll_info *general_pll, pll_info *pll,
227	bool internal_encoder );
228void Radeon_GetTVCRTPLLConfiguration( const general_pll_info *general_pll, pll_info *pll,
229	bool internal_tv_encoder );
230
231
232// flat_panel.c
233void Radeon_ReadRMXRegisters( accelerator_info *ai, fp_regs *values );
234void Radeon_CalcRMXRegisters( fp_info *flatpanel, display_mode *mode, bool use_rmx, fp_regs *values );
235void Radeon_ProgramRMXRegisters( accelerator_info *ai, fp_regs *values );
236
237void Radeon_ReadFPRegisters( accelerator_info *ai, fp_regs *values );
238void Radeon_CalcFPRegisters( accelerator_info *ai, crtc_info *crtc,
239	fp_info *fp_port, crtc_regs *crtc_values, fp_regs *values );
240void Radeon_ProgramFPRegisters( accelerator_info *ai, crtc_info *crtc,
241	fp_info *fp_port, fp_regs *values );
242
243
244// monitor_routing.h
245void Radeon_ReadMonitorRoutingRegs(
246	accelerator_info *ai, routing_regs *values );
247void Radeon_CalcMonitorRouting(
248	accelerator_info *ai, const impactv_params *tv_parameters, routing_regs *values );
249void Radeon_ProgramMonitorRouting(
250	accelerator_info *ai, routing_regs *values );
251void Radeon_SetupDefaultMonitorRouting(
252	accelerator_info *ai, int whished_num_heads, bool use_laptop_panel );
253
254
255// impactv.c
256
257typedef void (*impactv_write_FIFO) (
258	accelerator_info *ai, uint16 addr, uint32 value );
259typedef uint32 (*impactv_read_FIFO) (
260	accelerator_info *ai, uint16 addr );
261
262void Radeon_CalcImpacTVParams(
263	const general_pll_info *general_pll, impactv_params *params,
264	tv_standard_e tv_format, bool internal_encoder,
265	const display_mode *mode, display_mode *tweaked_mode );
266void Radeon_CalcImpacTVRegisters(
267	accelerator_info *ai, display_mode *mode,
268	impactv_params *params, impactv_regs *values, int crtc_idx,
269	bool internal_encoder, tv_standard_e tv_format, display_device_e display_device );
270void Radeon_ImpacTVwriteHorTimingTable(
271	accelerator_info *ai, impactv_write_FIFO write, impactv_regs *values, bool internal_encoder );
272void Radeon_ImpacTVwriteVertTimingTable(
273	accelerator_info *ai, impactv_write_FIFO write, impactv_regs *values );
274
275
276// theatre_out.c
277void Radeon_TheatreProgramTVRegisters( accelerator_info *ai, impactv_regs *values );
278void Radeon_TheatreReadTVRegisters( accelerator_info *ai, impactv_regs *values );
279uint32 Radeon_TheatreReadFIFO( accelerator_info *ai, uint16 addr );
280void Radeon_TheatreWriteFIFO( accelerator_info *ai, uint16 addr, uint32 value );
281
282// internal_tv_out.c
283void Radeon_InternalTVOutProgramRegisters( accelerator_info *ai, impactv_regs *values );
284void Radeon_InternalTVOutReadRegisters( accelerator_info *ai, impactv_regs *values );
285
286
287#endif
288