1/* 2 Copyright (c) 2003, Thomas Kurschel 3 4 5 Part of Radeon driver 6 7 TV-Out registers 8*/ 9 10#ifndef _TV_OUT_REGS_H 11#define _TV_OUT_REGS_H 12 13#define RADEON_TV_MASTER_CNTL 0x0800 14# define RADEON_TV_MASTER_CNTL_TV_ASYNC_RST (1 << 0) 15# define RADEON_TV_MASTER_CNTL_CRT_ASYNC_RST (1 << 1) 16# define RADEON_TV_MASTER_CNTL_RESTART_PHASE_FIX (1 << 3) 17# define RADEON_TV_MASTER_CNTL_TV_FIFO_ASYNC_RST (1 << 4) 18# define RADEON_TV_MASTER_CNTL_VIN_ASYNC_RST (1 << 5) 19# define RADEON_TV_MASTER_CNTL_AUD_ASYNC_RST (1 << 6) 20# define RADEON_TV_MASTER_CNTL_DVS_ASYNC_RST (1 << 7) 21# define RADEON_TV_MASTER_CNTL_CRT_FIFO_CE_EN (1 << 9) 22# define RADEON_TV_MASTER_CNTL_TV_FIFO_CE_EN (1 << 10) 23# define RADEON_TV_MASTER_CNTL_RE_SYNC_NOW_SEL_MASK (3 << 14) 24# define RADEON_TV_MASTER_CNTL_TVCLK_ALWAYS_ONb (1 << 30) 25# define RADEON_TV_MASTER_CNTL_TV_ON (1 << 31) 26 27#define RADEON_TV_RGB_CNTL 0x0804 28# define RADEON_TV_RGB_CNTL_RGB_SRC_SEL_SHIFT 8 29# define RADEON_TV_RGB_CNTL_RGB_DITHER_EN (1 << 5) 30# define RADEON_TV_RGB_CNTL_UVRAM_READ_MARGIN_SHIFT 16 31# define RADEON_TV_RGB_CNTL_FIFORAM_FIFOMACRO_READ_MARGIN_SHIFT 20 32 33#define RADEON_TV_HTOTAL 0x080c 34#define RADEON_TV_HDISP 0x0810 35#define RADEON_TV_HSTART 0x0818 36#define RADEON_TV_VTOTAL 0x0820 37#define RADEON_TV_VDISP 0x0824 38#define RADEON_TV_FTOTAL 0x082c 39#define RADEON_TV_FRESTART 0x0834 40#define RADEON_TV_HRESTART 0x0838 41#define RADEON_TV_VRESTART 0x083c 42 43#define RADEON_TV_HOST_READ_DATA 0x0840 44#define RADEON_TV_HOST_WRITE_DATA 0x0844 45#define RADEON_TV_HOST_RD_WT_CNTL 0x0848 46# define RADEON_TV_HOST_RD_WT_CNTL_RD (1 << 12) 47# define RADEON_TV_HOST_RD_WT_CNTL_RD_ACK (1 << 13) 48# define RADEON_TV_HOST_RD_WT_CNTL_WT (1 << 14) 49# define RADEON_TV_HOST_RD_WT_CNTL_WT_ACK (1 << 15) 50 51 52#define RADEON_TV_VSCALER_CNTL1 0x084c 53# define RADEON_TV_VSCALER_CNTL1_UV_INC_SHIFT 0 54# define RADEON_TV_VSCALER_CNTL1_UV_INC_MASK 0x0000ffff 55# define RADEON_TV_VSCALER_CNTL1_UV_THINNER_SHIFT 16 56# define RADEON_TV_VSCALER_CNTL1_UV_THINNER_MASK 0x003f0000 57# define RADEON_TV_VSCALER_CNTL1_Y_W_EN (1 << 24) 58# define RADEON_TV_VSCALER_CNTL1_Y_DEL_W_SIG_SHIFT 26 59# define RADEON_TV_VSCALER_CNTL1_RESTART_FIELD (1 << 29) 60 61 62#define RADEON_TV_TIMING_CNTL 0x0850 63# define RADEON_TV_TIMING_CNTL_UV_OUTPUT_POST_SCALE_SHIFT 24 64 65#define RADEON_TV_VSCALER_CNTL2 0x0854 66# define RADEON_TV_VSCALER_CNTL2_DITHER_MODE (1 << 0) 67# define RADEON_TV_VSCALER_CNTL2_Y_OUTPUT_DITHER_EN (1 << 1) 68# define RADEON_TV_VSCALER_CNTL2_UV_OUTPUT_DITHER_EN (1 << 2) 69# define RADEON_TV_VSCALER_CNTL2_UV_TO_BUF_DITHER_EN (1 << 3) 70# define RADEON_TV_VSCALER_CNTL2_UV_ACCUM_INIT_SHIFT 24 71 72#define RADEON_TV_Y_FALL_CNTL 0x0858 73# define RADEON_TV_Y_FALL_CNTL_Y_FALL_PING_PONG (1 << 16) 74# define RADEON_TV_Y_FALL_CNTL_Y_COEFF_EN (1 << 17) 75# define RADEON_TV_Y_FALL_CNTL_Y_COEFF_VALUE_SHIFT 24 76 77#define RADEON_TV_Y_RISE_CNTL 0x085c 78# define RADEON_TV_Y_RISE_CNTL_Y_RISE_PING_PONG (1 << 16) 79 80#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860 81# define RADEON_TV_Y_SAW_TOOTH_CNTL_SLOPE_SHIFT 16 82 83#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864 84#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868 85#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c 86 87#define RADEON_TV_MODULATOR_CNTL1 0x0870 88# define RADEON_TV_MODULATOR_CNTL1_YFLT_EN (1 << 2) 89# define RADEON_TV_MODULATOR_CNTL1_UVFLT_EN (1 << 3) 90# define RADEON_TV_MODULATOR_CNTL1_ALT_PHASE_EN (1 << 6) 91# define RADEON_TV_MODULATOR_CNTL1_SYNC_TIP_LEVEL (1 << 7) 92# define RADEON_TV_MODULATOR_CNTL1_SET_UP_LEVEL_SHIFT 8 93# define RADEON_TV_MODULATOR_CNTL1_SET_UP_LEVEL_MASK 0x00007f00 94# define RADEON_TV_MODULATOR_CNTL1_BLANK_LEVEL_SHIFT 16 95# define RADEON_TV_MODULATOR_CNTL1_BLANK_LEVEL_MASK 0x007f0000 96# define RADEON_TV_MODULATOR_CNTL1_SLEW_RATE_LIMIT (1 << 23) 97# define RADEON_TV_MODULATOR_CNTL1_CY_FILT_BLEND_SHIFT 28 98 99#define RADEON_TV_MODULATOR_CNTL2 0x0874 100# define TV_MODULATOR_CNTL2_U_BURST_LEVEL_MASK 0x1ff 101# define TV_MODULATOR_CNTL2_V_BURST_LEVEL_MASK 0x1ff 102# define TV_MODULATOR_CNTL2_V_BURST_LEVEL_SHIFT 16 103 104#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 105# define RADEON_TV_PRE_DAC_MUX_CNTL_Y_RED_EN (1 << 0) 106# define RADEON_TV_PRE_DAC_MUX_CNTL_C_GRN_EN (1 << 1) 107# define RADEON_TV_PRE_DAC_MUX_CNTL_CMP_BLU_EN (1 << 2) 108# define RADEON_TV_PRE_DAC_MUX_CNTL_DAC_DITHER_EN (1 << 3) 109# define RADEON_TV_PRE_DAC_MUX_CNTL_RED_MX_SHIFT 4 110# define RADEON_TV_PRE_DAC_MUX_CNTL_GRN_MX_SHIFT 8 111# define RADEON_TV_PRE_DAC_MUX_CNTL_BLU_MX_SHIFT 12 112# define RADEON_TV_MUX_FORCE_DAC_DATA 6 113# define RADEON_TV_PRE_DAC_MUX_CNTL_FORCE_DAC_DATA_SHIFT 16 114 115#define RADEON_TV_DAC_CNTL 0x088c 116# define RADEON_TV_DAC_CNTL_NBLANK (1 << 0) 117# define RADEON_TV_DAC_CNTL_NHOLD (1 << 1) 118# define RADEON_TV_DAC_CNTL_PEDESTAL (1 << 2) 119# define RADEON_TV_DAC_CNTL_DASLEEP (1 << 3) // Theatre only 120# define RADEON_TV_DAC_CNTL_DETECT (1 << 4) 121# define RADEON_TV_DAC_CNTL_CMPOUT (1 << 5) 122# define RADEON_TV_DAC_CNTL_BGSLEEP (1 << 6) 123# define RADEON_TV_DAC_CNTL_STD_PAL (0 << 8) 124# define RADEON_TV_DAC_CNTL_STD_NTSC (1 << 8) 125# define RADEON_TV_DAC_CNTL_STD_PS2 (2 << 8) 126# define RADEON_TV_DAC_CNTL_STD_RS343 (3 << 8) 127# define RADEON_TV_DAC_CNTL_BGADJ_SHIFT 16 128# define RADEON_TV_DAC_CNTL_DACADJ_SHIFT 20 129# define RADEON_TV_DAC_CNTL_RDACPD (1 << 24) 130# define RADEON_TV_DAC_CNTL_GDACPD (1 << 25) 131# define RADEON_TV_DAC_CNTL_BDACPD (1 << 26) 132# define RADEON_TV_DAC_CNTL_RDACDET (1 << 29) 133# define RADEON_TV_DAC_CNTL_GDACDET (1 << 30) 134# define RADEON_TV_DAC_CNTL_BDACDET (1 << 31) 135 136#define RADEON_TV_CRC_CNTL 0x0890 137 138#define RADEON_TV_UV_ADR 0x08ac 139# define RADEON_TV_UV_ADR_MAX_UV_ADR_MASK 0x000000ff 140# define RADEON_TV_UV_ADR_MAX_UV_ADR_SHIFT 0 141# define RADEON_TV_UV_ADR_TABLE1_BOT_ADR_MASK 0x0000ff00 142# define RADEON_TV_UV_ADR_TABLE1_BOT_ADR_SHIFT 8 143# define RADEON_TV_UV_ADR_TABLE3_TOP_ADR_MASK 0x00ff0000 144# define RADEON_TV_UV_ADR_TABLE3_TOP_ADR_SHIFT 16 145# define RADEON_TV_UV_ADR_HCODE_TABLE_SEL_MASK 0x06000000 146# define RADEON_TV_UV_ADR_HCODE_TABLE_SEL_SHIFT 25 147# define RADEON_TV_UV_ADR_VCODE_TABLE_SEL_MASK 0x18000000 148# define RADEON_TV_UV_ADR_VCODE_TABLE_SEL_SHIFT 27 149#define RADEON_TV_MAX_FIFO_ADDR 0x1a7 150#define RADEON_TV_MAX_FIFO_ADDR_INTERN 0x1ff 151 152 153#define RADEON_TV_PLL_FINE_CNTL 0x20 154 155#define RADEON_TV_PLL_CNTL 0x21 156# define RADEON_TV_PLL_CNTL_TV_M0_LO_MASK 0xff 157# define RADEON_TV_PLL_CNTL_TV_N0_LO_MASK 0x1ff 158# define RADEON_TV_PLL_CNTL_TV_N0_LO_SHIFT 8 159# define RADEON_TV_PLL_CNTL_TV_M0_LO_BITS 8 160# define RADEON_TV_PLL_CNTL_TV_M0_HI_SHIFT 18 161# define RADEON_TV_PLL_CNTL_TV_N0_LO_BITS 9 162# define RADEON_TV_PLL_CNTL_TV_N0_HI_SHIFT 21 163# define RADEON_TV_PLL_CNTL_TV_SLIP_EN (1 << 23) 164# define RADEON_TV_PLL_CNTL_TV_P_SHIFT 24 165# define RADEON_TV_PLL_CNTL_TV_DTO_EN (1 << 28) 166 167# define RADEON_TV_CRT_PLL_CNTL_M0_LO_MASK 0xff 168# define RADEON_TV_CRT_PLL_CNTL_N0_LO_MASK 0x1ff 169# define RADEON_TV_CRT_PLL_CNTL_N0_LO_SHIFT 8 170# define RADEON_TV_CRT_PLL_CNTL_M0_LO_BITS 8 171# define RADEON_TV_CRT_PLL_CNTL_M0_HI_SHIFT 18 172# define RADEON_TV_CRT_PLL_CNTL_N0_LO_BITS 9 173# define RADEON_TV_CRT_PLL_CNTL_N0_HI_SHIFT 21 174# define RADEON_TV_CRT_PLL_CNTL_CLKBY2 (1 << 25) 175 176 177#define RADEON_TV_PLL_CNTL1 0x22 178# define RADEON_TV_PLL_CNTL1_TVPCP_SHIFT 8 179# define RADEON_TV_PLL_CNTL1_TVPVG_SHIFT 11 180# define RADEON_TV_PLL_CNTL1_TVPDC_SHIFT 14 181# define RADEON_TV_PLL_CNTL1_TVCLK_SRC_SEL_CPUCLK (0 << 30) 182# define RADEON_TV_PLL_CNTL1_TVCLK_SRC_SEL_TVPLLCLK (1 << 30) 183# define RADEON_TV_PLL_CNTL1_TVPLL_TEST (1 << 31) 184 185 186# define RADEON_TV_CLOCK_SEL_CNTL_BYTCLK_SHIFT 2 187# define RADEON_TV_CLOCK_SEL_CNTL_BYTCLKD_SHIFT 8 188 189#endif 190