1/* 2 Copyright (c) 2002, Thomas Kurschel 3 4 5 Part of Radeon driver 6 7 Unsorted list of remaining Radeon registers 8*/ 9 10 11#ifndef _RADEON_REGS_H 12#define _RADEON_REGS_H 13 14 15#define RADEON_AMCGPIO_A_REG 0x01a0 16#define RADEON_AMCGPIO_EN_REG 0x01a8 17#define RADEON_AMCGPIO_MASK 0x0194 18#define RADEON_AMCGPIO_Y_REG 0x01a4 19#define RADEON_ATTRDR 0x03c1 /* VGA */ 20#define RADEON_ATTRDW 0x03c0 /* VGA */ 21#define RADEON_ATTRX 0x03c0 /* VGA */ 22#define RADEON_AUX_SC_CNTL 0x1660 23# define RADEON_AUX1_SC_EN (1 << 0) 24# define RADEON_AUX1_SC_MODE_OR (0 << 1) 25# define RADEON_AUX1_SC_MODE_NAND (1 << 1) 26# define RADEON_AUX2_SC_EN (1 << 2) 27# define RADEON_AUX2_SC_MODE_OR (0 << 3) 28# define RADEON_AUX2_SC_MODE_NAND (1 << 3) 29# define RADEON_AUX3_SC_EN (1 << 4) 30# define RADEON_AUX3_SC_MODE_OR (0 << 5) 31# define RADEON_AUX3_SC_MODE_NAND (1 << 5) 32#define RADEON_AUX1_SC_BOTTOM 0x1670 33#define RADEON_AUX1_SC_LEFT 0x1664 34#define RADEON_AUX1_SC_RIGHT 0x1668 35#define RADEON_AUX1_SC_TOP 0x166c 36#define RADEON_AUX2_SC_BOTTOM 0x1680 37#define RADEON_AUX2_SC_LEFT 0x1674 38#define RADEON_AUX2_SC_RIGHT 0x1678 39#define RADEON_AUX2_SC_TOP 0x167c 40#define RADEON_AUX3_SC_BOTTOM 0x1690 41#define RADEON_AUX3_SC_LEFT 0x1684 42#define RADEON_AUX3_SC_RIGHT 0x1688 43#define RADEON_AUX3_SC_TOP 0x168c 44#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8 45#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc 46 47 48#define RADEON_CLR_CMP_CLR_3D 0x1a24 49#define RADEON_CLR_CMP_CLR_DST 0x15c8 50#define RADEON_CLR_CMP_CLR_SRC 0x15c4 51#define RADEON_CLR_CMP_CNTL 0x15c0 52# define RADEON_SRC_CMP_EQ_COLOR (4 << 0) 53# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0) 54# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24) 55#define RADEON_CLR_CMP_MASK 0x15cc 56# define RADEON_CLR_CMP_MSK 0xffffffff 57#define RADEON_CLR_CMP_MASK_3D 0x1A28 58#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c 59#define RADEON_CONFIG_APER_0_BASE 0x0100 60#define RADEON_CONFIG_APER_1_BASE 0x0104 61#define RADEON_CONFIG_APER_SIZE 0x0108 62#define RADEON_CONFIG_BONDS 0x00e8 63#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114 64#define RADEON_CONFIG_REG_1_BASE 0x010c 65#define RADEON_CONFIG_REG_APER_SIZE 0x0110 66#define RADEON_CONFIG_XSTRAP 0x00e4 67#define RADEON_CONSTANT_COLOR_C 0x1d34 68# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff 69# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff 70# define RADEON_CONSTANT_COLOR_ZERO 0x00000000 71#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ 72#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ 73 74#define RADEON_TV_DAC_CNTL 0x088c 75# define RADEON_TV_DAC_STD_MASK 0x0300 76# define RADEON_TV_DAC_RDACPD (1 << 24) 77# define RADEON_TV_DAC_GDACPD (1 << 25) 78# define RADEON_TV_DAC_BDACPD (1 << 26) 79 80#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820 81#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824 82#define RADEON_DISP_MISC_CNTL 0x0d00 83# define RADEON_SOFT_RESET_GRPH_PP (1 << 0) 84 85 86#define RADEON_DST_BRES_DEC 0x1630 87#define RADEON_DST_BRES_ERR 0x1628 88#define RADEON_DST_BRES_INC 0x162c 89#define RADEON_DST_BRES_LNTH 0x1634 90#define RADEON_DST_BRES_LNTH_SUB 0x1638 91#define RADEON_DST_HEIGHT 0x1410 92#define RADEON_DST_HEIGHT_WIDTH 0x143c 93#define RADEON_DST_HEIGHT_WIDTH_8 0x158c 94#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4 95#define RADEON_DST_HEIGHT_Y 0x15a0 96#define RADEON_DST_OFFSET 0x1404 97#define RADEON_DST_PITCH 0x1408 98#define RADEON_DST_PITCH_OFFSET_C 0x1c80 99# define RADEON_PITCH_SHIFT 21 100# define RADEON_DST_TILE_LINEAR (0 << 30) 101# define RADEON_DST_TILE_MACRO (1 << 30) 102# define RADEON_DST_TILE_MICRO (2 << 30) 103# define RADEON_DST_TILE_BOTH (3 << 30) 104#define RADEON_DST_WIDTH 0x140c 105#define RADEON_DST_WIDTH_HEIGHT 0x1598 106#define RADEON_DST_WIDTH_X 0x1588 107#define RADEON_DST_WIDTH_X_INCY 0x159c 108#define RADEON_DST_X 0x141c 109#define RADEON_DST_X_SUB 0x15a4 110#define RADEON_DST_X_Y 0x1594 111#define RADEON_DST_Y 0x1420 112#define RADEON_DST_Y_SUB 0x15a8 113#define RADEON_DST_Y_X 0x1438 114 115#define RADEON_FLUSH_1 0x1704 116#define RADEON_FLUSH_2 0x1708 117#define RADEON_FLUSH_3 0x170c 118#define RADEON_FLUSH_4 0x1710 119#define RADEON_FLUSH_5 0x1714 120#define RADEON_FLUSH_6 0x1718 121#define RADEON_FLUSH_7 0x171c 122#define RADEON_FOG_3D_TABLE_START 0x1810 123#define RADEON_FOG_3D_TABLE_END 0x1814 124#define RADEON_FOG_3D_TABLE_DENSITY 0x181c 125#define RADEON_FOG_TABLE_INDEX 0x1a14 126#define RADEON_FOG_TABLE_DATA 0x1a18 127 128#define RADEON_GENENB 0x03c3 /* VGA */ 129#define RADEON_GENFC_RD 0x03ca /* VGA */ 130#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ 131#define RADEON_GENMO_RD 0x03cc /* VGA */ 132#define RADEON_GENMO_WT 0x03c2 /* VGA */ 133#define RADEON_GENS0 0x03c2 /* VGA */ 134#define RADEON_GENS1 0x03da /* VGA, 0x03ba */ 135 136#define RADEON_GRPH8_DATA 0x03cf /* VGA */ 137#define RADEON_GRPH8_IDX 0x03ce /* VGA */ 138#define RADEON_GUI_DEBUG0 0x16a0 139#define RADEON_GUI_DEBUG1 0x16a4 140#define RADEON_GUI_DEBUG2 0x16a8 141#define RADEON_GUI_DEBUG3 0x16ac 142#define RADEON_GUI_DEBUG4 0x16b0 143#define RADEON_GUI_DEBUG5 0x16b4 144#define RADEON_GUI_DEBUG6 0x16b8 145#define RADEON_GUI_SCRATCH_REG0 0x15e0 146#define RADEON_GUI_SCRATCH_REG1 0x15e4 147#define RADEON_GUI_SCRATCH_REG2 0x15e8 148#define RADEON_GUI_SCRATCH_REG3 0x15ec 149#define RADEON_GUI_SCRATCH_REG4 0x15f0 150#define RADEON_GUI_SCRATCH_REG5 0x15f4 151#define RADEON_HOST_DATA0 0x17c0 152#define RADEON_HOST_DATA1 0x17c4 153#define RADEON_HOST_DATA2 0x17c8 154#define RADEON_HOST_DATA3 0x17cc 155#define RADEON_HOST_DATA4 0x17d0 156#define RADEON_HOST_DATA5 0x17d4 157#define RADEON_HOST_DATA6 0x17d8 158#define RADEON_HOST_DATA7 0x17dc 159#define RADEON_HOST_DATA_LAST 0x17e0 160#define RADEON_HW_DEBUG 0x0128 161#define RADEON_HW_DEBUG2 0x011c 162 163#define RADEON_I2C_CNTL_1 0x0094 164 165#define RADEON_LEAD_BRES_DEC 0x1608 166#define RADEON_LEAD_BRES_LNTH 0x161c 167#define RADEON_LEAD_BRES_LNTH_SUB 0x1624 168#define RADEON_LVDS_PLL_CNTL 0x02d4 169 170# define RADEON_HSYNC_DELAY_SHIFT 28 171# define RADEON_HSYNC_DELAY_MASK (0xf << 28) 172 173#define RADEON_MDGPIO_A_REG 0x01ac 174#define RADEON_MDGPIO_EN_REG 0x01b0 175#define RADEON_MDGPIO_MASK 0x0198 176#define RADEON_MDGPIO_Y_REG 0x01b4 177 178#define RADEON_MEM_STR_CNTL 0x0150 179#define RADEON_MEM_VGA_RP_SEL 0x003c 180#define RADEON_MEM_VGA_WP_SEL 0x0038 181#define RADEON_MM_INDEX 0x0000 182#define RADEON_MPLL_CNTL 0x000e /* PLL */ 183#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ 184#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ 185 186#define RADEON_N_VIF_COUNT 0x0248 187 188#define RADEON_PCI_GART_PAGE 0x017c 189#define RADEON_PLANE_3D_MASK_C 0x1d44 190#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */ 191 192#define RADEON_SC_BOTTOM 0x164c 193#define RADEON_SC_BOTTOM_RIGHT 0x16f0 194#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c 195#define RADEON_SC_LEFT 0x1640 196#define RADEON_SC_RIGHT 0x1644 197#define RADEON_SC_TOP 0x1648 198#define RADEON_SC_TOP_LEFT 0x16ec 199#define RADEON_SC_TOP_LEFT_C 0x1c88 200# define RADEON_SC_SIGN_MASK_LO 0x8000 201# define RADEON_SC_SIGN_MASK_HI 0x80000000 202#define RADEON_SEQ8_DATA 0x03c5 /* VGA */ 203#define RADEON_SEQ8_IDX 0x03c4 /* VGA */ 204#define RADEON_SNAPSHOT_F_COUNT 0x0244 205#define RADEON_SNAPSHOT_VH_COUNTS 0x0240 206#define RADEON_SNAPSHOT_VIF_COUNT 0x024c 207#define RADEON_SRC_OFFSET 0x15ac 208#define RADEON_SRC_PITCH 0x15b0 209#define RADEON_SRC_SC_BOTTOM 0x165c 210#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4 211#define RADEON_SRC_SC_RIGHT 0x1654 212#define RADEON_SRC_X 0x1414 213#define RADEON_SRC_X_Y 0x1590 214#define RADEON_SRC_Y 0x1418 215#define RADEON_SRC_Y_X 0x1434 216#define RADEON_SURFACE_CNTL 0x0b00 217# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 218# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) 219# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) 220#define RADEON_SURFACE0_INFO 0x0b0c 221#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 222#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 223#define RADEON_SURFACE1_INFO 0x0b1c 224#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 225#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 226#define RADEON_SURFACE2_INFO 0x0b2c 227#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 228#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 229#define RADEON_SURFACE3_INFO 0x0b3c 230#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 231#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 232#define RADEON_SURFACE4_INFO 0x0b4c 233#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 234#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 235#define RADEON_SURFACE5_INFO 0x0b5c 236#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 237#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 238#define RADEON_SURFACE6_INFO 0x0b6c 239#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 240#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 241#define RADEON_SURFACE7_INFO 0x0b7c 242#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 243#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 244#define RADEON_SW_SEMAPHORE 0x013c 245 246#define RADEON_TMDS_CRC 0x02a0 247#define RADEON_TRAIL_BRES_DEC 0x1614 248#define RADEON_TRAIL_BRES_ERR 0x160c 249#define RADEON_TRAIL_BRES_INC 0x1610 250#define RADEON_TRAIL_X 0x1618 251#define RADEON_TRAIL_X_SUB 0x1620 252 253#define RADEON_VGA_DDA_CONFIG 0x02e8 // Rage 128 reg 254#define RADEON_VGA_DDA_ON_OFF 0x02ec 255#define RADEON_VID_BUFFER_CONTROL 0x0900 256#define RADEON_VIDEOMUX_CNTL 0x0190 257 258#define RADEON_OVR_CLR 0x0230 259#define RADEON_OVR_WID_LEFT_RIGHT 0x0234 260#define RADEON_OVR_WID_TOP_BOTTOM 0x0238 261 262 263#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ 264#define RADEON_XCLK_CNTL 0x000d /* PLL */ 265#define RADEON_XDLL_CNTL 0x000c /* PLL */ 266#define RADEON_XPLL_CNTL 0x000b /* PLL */ 267 268 269#endif 270 271