1/* 2 Copyright (c) 2002, Thomas Kurschel 3 4 5 Part of Radeon driver 6 7 PLL registers 8*/ 9 10#ifndef _PLL_REG_H 11#define _PLL_REG_H 12 13// mmio registers 14#define RADEON_CLOCK_CNTL_DATA 0x000c 15#define RADEON_CLOCK_CNTL_INDEX 0x0008 16# define RADEON_PLL_WR_EN (1 << 7) 17# define RADEON_PLL_DIV_SEL_MASK (3 << 8) 18# define RADEON_PLL_DIV_SEL_DIV0 (0 << 8) 19# define RADEON_PLL_DIV_SEL_DIV1 (1 << 8) 20# define RADEON_PLL_DIV_SEL_DIV2 (2 << 8) 21# define RADEON_PLL_DIV_SEL_DIV3 (3 << 8) 22#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ 23# define RADEON_SCLK_DYN_START_CNTL (1 << 15) 24 25// PLL Power management registers 26#define RADEON_CLK_PWRMGT_CNTL 0x0014 27# define RADEON_ENGIN_DYNCLK_MODE (1 << 12) 28# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13) 29# define RADEON_ACTIVE_HILO_LAT_SHIFT 13 30# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12) 31# define RADEON_DYN_STOP_MODE_MASK (7 << 21) 32#define RADEON_PLL_PWRMGT_CNTL 0x0015 33# define RADEON_TCL_BYPASS_DISABLE (1 << 20) 34 35// indirect PLL registers 36#define RADEON_CLK_PIN_CNTL 0x0001 37#define RADEON_PPLL_CNTL 0x0002 38# define RADEON_PPLL_RESET (1 << 0) 39# define RADEON_PPLL_SLEEP (1 << 1) 40# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16) 41# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 42# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) 43#define RADEON_PPLL_REF_DIV 0x0003 44# define RADEON_PPLL_REF_DIV_MASK 0x03ff 45# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 46# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 47# define RADEON_PPLL_REF_DIV_ACC_SHIFT 18 48# define RADEON_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) 49#define RADEON_PPLL_DIV_0 0x0004 50#define RADEON_PPLL_DIV_1 0x0005 51#define RADEON_PPLL_DIV_2 0x0006 52#define RADEON_PPLL_DIV_3 0x0007 53# define RADEON_PPLL_FB3_DIV_MASK 0x07ff 54# define RADEON_PPLL_POST3_DIV_MASK 0x00070000 55#define RADEON_VCLK_ECP_CNTL 0x0008 56# define RADEON_VCLK_SRC_SEL_MASK (3 << 0) 57# define RADEON_VCLK_SRC_CPU_CLK (0 << 0) 58# define RADEON_VCLK_SRC_PSCAN_CLK (1 << 0) 59# define RADEON_VCLK_SRC_BYTE_CLK (2 << 0) 60# define RADEON_VCLK_SRC_PPLL_CLK (3 << 0) 61# define RADEON_PIXCLK_ALWAYS_ONb (1 << 6) // negated 62# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1 << 7) // negated 63# define RADEON_ECP_DIV_SHIFT 8 64# define RADEON_ECP_DIV_MASK (3 << 8) 65# define RADEON_ECP_DIV_VCLK (0 << 8) 66# define RADEON_ECP_DIV_VCLK_2 (1 << 8) 67# define RADEON_VCLK_ECP_CNTL_BYTE_CLK_POST_DIV_SHIFT 16 68# define RADEON_VCLK_ECP_CNTL_BYTE_CLK_POST_DIV_MASK (3 << 16) 69# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) 70 71#define RADEON_HTOTAL_CNTL 0x0009 72#define RADEON_SCLK_CNTL 0x000d /* PLL */ 73# define RADEON_SCLK_SRC_SEL_MASK 0x0007 74# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 75# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 76# define RADEON_SCLK_FORCEON_MASK 0xffff8000 77# define RADEON_SCLK_FORCE_DISP2 (1<<15) 78# define RADEON_SCLK_FORCE_CP (1<<16) 79# define RADEON_SCLK_FORCE_HDP (1<<17) 80# define RADEON_SCLK_FORCE_DISP1 (1<<18) 81# define RADEON_SCLK_FORCE_TOP (1<<19) 82# define RADEON_SCLK_FORCE_E2 (1<<20) 83# define RADEON_SCLK_FORCE_SE (1<<21) 84# define RADEON_SCLK_FORCE_IDCT (1<<22) 85# define RADEON_SCLK_FORCE_VIP (1<<23) 86# define RADEON_SCLK_FORCE_RE (1<<24) 87# define RADEON_SCLK_FORCE_PB (1<<25) 88# define RADEON_SCLK_FORCE_TAM (1<<26) 89# define RADEON_SCLK_FORCE_TDM (1<<27) 90# define RADEON_SCLK_FORCE_RB (1<<28) 91# define RADEON_SCLK_FORCE_TV_SCLK (1<<29) 92# define RADEON_SCLK_FORCE_SUBPIC (1<<30) 93# define RADEON_SCLK_FORCE_OV0 (1<<31) 94# define R300_SCLK_FORCE_VAP (1<<21) 95# define R300_SCLK_FORCE_SR (1<<25) 96# define R300_SCLK_FORCE_PX (1<<26) 97# define R300_SCLK_FORCE_TX (1<<27) 98# define R300_SCLK_FORCE_US (1<<28) 99# define R300_SCLK_FORCE_SU (1<<30) 100#define R300_SCLK_CNTL2 0x1e /* PLL */ 101# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10) 102# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11) 103# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12) 104# define R300_SCLK_FORCE_TCL (1<<13) 105# define R300_SCLK_FORCE_CBA (1<<14) 106# define R300_SCLK_FORCE_GA (1<<15) 107#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ 108# define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007 109# define RADEON_SCLK_MORE_FORCEON 0x0700 110#define RADEON_MCLK_CNTL 0x0012 111# define RADEON_FORCEON_MCLKA (1 << 16) 112# define RADEON_FORCEON_MCLKB (1 << 17) 113# define RADEON_FORCEON_YCLKA (1 << 18) 114# define RADEON_FORCEON_YCLKB (1 << 19) 115# define RADEON_FORCEON_MC (1 << 20) 116# define RADEON_FORCEON_AIC (1 << 21) 117# define R300_DISABLE_MC_MCLKA (1 << 21) 118# define R300_DISABLE_MC_MCLKB (1 << 21) 119#define RADEON_MCLK_MISC 0x001f /* PLL */ 120# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1<<12) 121# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1<<13) 122# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) 123# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) 124#define RADEON_P2PLL_CNTL 0x002a 125# define RADEON_P2PLL_RESET (1 << 0) 126# define RADEON_P2PLL_SLEEP (1 << 1) 127# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) 128# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 129# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) 130#define RADEON_P2PLL_REF_DIV 0x002B 131# define RADEON_P2PLL_REF_DIV_MASK 0x03ff 132# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 133# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 134#define RADEON_P2PLL_DIV_0 0x002c 135# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff 136# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 137#define RADEON_PIXCLKS_CNTL 0x0002d 138# define RADEON_PIX2CLK_SRC_SEL_MASK (3 << 0) 139# define RADEON_PIX2CLK_SRC_SEL_CPU_CLK (0 << 0) 140# define RADEON_PIX2CLK_SRC_SEL_PSCAN_CLK (1 << 0) 141# define RADEON_PIX2CLK_SRC_SEL_P2PLL_CLK (3 << 0) 142# define RADEON_PIXCLK_TV_SRC_SEL_MASK (1 << 8) 143# define RADEON_PIXCLK_TV_SRC_SEL_PIXCLK (0 << 8) 144# define RADEON_PIXCLK_TV_SRC_SEL_PIX2CLK (1 << 8) 145# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 146# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) 147# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) 148# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) 149# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) 150# define R300_DVOCLK_ALWAYS_ONb (1 << 10) 151# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11) 152# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12) 153# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13) 154# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) 155# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) 156# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) 157# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) 158# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) 159# define R300_P2G2CLK_ALWAYS_ONb (1 << 18) 160# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) 161# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) 162#define RADEON_HTOTAL2_CNTL 0x002e 163 164 165#endif 166