1/* 2 Copyright (c) 2002, Thomas Kurschel 3 4 5 Part of Radeon driver 6 7 Config registers (most are in PCI configuration space) 8*/ 9 10#ifndef _CONFIG_REGS_H 11#define _CONFIG_REGS_H 12 13// mmio registers 14#define RADEON_CONFIG_APER_0_BASE 0x0100 15#define RADEON_CONFIG_APER_1_BASE 0x0104 16#define RADEON_CONFIG_APER_SIZE 0x0108 17 18#define RADEON_CONFIG_CNTL 0x00e0 19# define RADEON_CFG_ATI_REV_A11 (0 << 16) 20# define RADEON_CFG_ATI_REV_A12 (1 << 16) 21# define RADEON_CFG_ATI_REV_A13 (2 << 16) 22# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) 23#define RADEON_CFG_ATI_REV_ID_SHIFT 16 24#define RADEON_CONFIG_MEMSIZE 0x00f8 25# define RADEON_CONFIG_MEMSIZE_MASK 0x1ff00000 26 27// following registers can be accessed via PCI configuration space too 28// (PCI-configuration-space-add + 0xf00 = MMIO-address) 29#define RADEON_VENDOR_ID 0x0f00 30#define RADEON_DEVICE_ID 0x0f02 31#define RADEON_COMMAND 0x0f04 32#define RADEON_STATUS 0x0f06 33#define RADEON_REVISION_ID 0x0f08 34#define RADEON_REGPROG_INF 0x0f09 35#define RADEON_SUB_CLASS 0x0f0a 36#define RADEON_BASE_CODE 0x0f0b 37#define RADEON_CACHE_LINE 0x0f0c 38#define RADEON_LATENCY 0x0f0d 39#define RADEON_HEADER 0x0f0e 40#define RADEON_BIST 0x0f0f 41#define RADEON_MEM_BASE 0x0f10 42#define RADEON_IO_BASE 0x0f14 43#define RADEON_REG_BASE 0x0f18 44#define RADEON_ADAPTER_ID 0x0f2c //mirror of AADPER_ID_W 45#define RADEON_BIOS_ROM 0x0f30 46#define RADEON_CAPABILITIES_PTR 0x0f34 47#define RADEON_INTERRUPT_LINE 0x0f3c 48#define RADEON_INTERRUPT_PIN 0x0f3d 49#define RADEON_MIN_GRANT 0x0f3e 50#define RADEON_MAX_LATENCY 0x0f3f 51#define RADEON_ADAPTER_ID_W 0x0f4c 52#define RADEON_CAPABILITIES_ID 0x0f50 53 54#define RADEON_PMI_CAP_ID 0x0f50 55#define RADEON_PMI_NXT_CAP_PTR 0x0f51 56#define RADEON_PMI_PMC_REG 0x0f52 57#define RADEON_PMI_STATUS 0x0f54 58#define RADEON_PMI_DATA 0x0f57 59 60#define RADEON_AGP_CAP_ID 0x0f58 61#define RADEON_AGP_STATUS 0x0f5c 62#define RADEON_AGP_COMMAND 0x0f60 63 64 65#endif 66